Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	22802067	1			T23	12		T20	2		T21	30
all_values[1]	22802067	1			T23	12		T20	2		T21	30
all_values[2]	22802067	1			T23	12		T20	2		T21	30
all_values[3]	22802067	1			T23	12		T20	2		T21	30
all_values[4]	22802067	1			T23	12		T20	2		T21	30
all_values[5]	22802067	1			T23	12		T20	2		T21	30
all_values[6]	22802067	1			T23	12		T20	2		T21	30
all_values[7]	22802067	1			T23	12		T20	2		T21	30
all_values[8]	22802067	1			T23	12		T20	2		T21	30
all_values[9]	22802067	1			T23	12		T20	2		T21	30
all_values[10]	22802067	1			T23	12		T20	2		T21	30
all_values[11]	22802067	1			T23	12		T20	2		T21	30
all_values[12]	22802067	1			T23	12		T20	2		T21	30
all_values[13]	22802067	1			T23	12		T20	2		T21	30
all_values[14]	22802067	1			T23	12		T20	2		T21	30
all_values[15]	22802067	1			T23	12		T20	2		T21	30
all_values[16]	22802067	1			T23	12		T20	2		T21	30
all_values[17]	22802067	1			T23	12		T20	2		T21	30
all_values[18]	22802067	1			T23	12		T20	2		T21	30
all_values[19]	22802067	1			T23	12		T20	2		T21	30
all_values[20]	22802067	1			T23	12		T20	2		T21	30
all_values[21]	22802067	1			T23	12		T20	2		T21	30
all_values[22]	22802067	1			T23	12		T20	2		T21	30
all_values[23]	22802067	1			T23	12		T20	2		T21	30
all_values[24]	22802067	1			T23	12		T20	2		T21	30
all_values[25]	22802067	1			T23	12		T20	2		T21	30
all_values[26]	22802067	1			T23	12		T20	2		T21	30
all_values[27]	22802067	1			T23	12		T20	2		T21	30
all_values[28]	22802067	1			T23	12		T20	2		T21	30
all_values[29]	22802067	1			T23	12		T20	2		T21	30
all_values[30]	22802067	1			T23	12		T20	2		T21	30
all_values[31]	22802067	1			T23	12		T20	2		T21	30

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

401596952

1

T23

216

T20

47

T21

537

auto[1]

328069192

1

T23

168

T20

17

T21

423

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133715250

1

T23

281

T20

43

T21

568

auto[1]

595950894

1

T23

103

T20

21

T21

392

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721279781

1

T23

344

T20

64

T21

821

auto[1]

8386363

1

T23

40

T21

139

T22

97

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3215641	1			T23	3		T20	2		T21	17
all_values[0]	auto[0]	auto[0]	auto[1]	9193914	1			T23	4		T11	5		T13	1
all_values[0]	auto[0]	auto[1]	auto[0]	952336	1			T23	1		T21	7		T22	5
all_values[0]	auto[0]	auto[1]	auto[1]	9178390	1			T23	2		T21	4		T22	7
all_values[0]	auto[1]	auto[0]	auto[1]	131029	1			T21	1		T22	2		T13	2
all_values[0]	auto[1]	auto[1]	auto[1]	130757	1			T23	2		T21	1		T72	1
all_values[1]	auto[0]	auto[0]	auto[0]	3223308	1			T23	7		T20	1		T21	8
all_values[1]	auto[0]	auto[0]	auto[1]	9215557	1			T21	5		T11	5		T14	2
all_values[1]	auto[0]	auto[1]	auto[0]	947374	1			T23	5		T21	7		T22	4
all_values[1]	auto[0]	auto[1]	auto[1]	9153714	1			T20	1		T21	8		T22	4
all_values[1]	auto[1]	auto[0]	auto[1]	131863	1			T21	1		T22	1		T72	3
all_values[1]	auto[1]	auto[1]	auto[1]	130251	1			T21	1		T22	3		T13	1
all_values[2]	auto[0]	auto[0]	auto[0]	3218071	1			T23	3		T20	1		T21	9
all_values[2]	auto[0]	auto[0]	auto[1]	9172595	1			T23	1		T21	8		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	955413	1			T23	4		T21	2		T22	7
all_values[2]	auto[0]	auto[1]	auto[1]	9193891	1			T23	3		T20	1		T21	6
all_values[2]	auto[1]	auto[0]	auto[1]	130850	1			T23	1		T21	3		T22	2
all_values[2]	auto[1]	auto[1]	auto[1]	131247	1			T21	2		T22	1		T72	4
all_values[3]	auto[0]	auto[0]	auto[0]	3221198	1			T23	4		T20	1		T21	11
all_values[3]	auto[0]	auto[0]	auto[1]	9176002	1			T23	3		T21	3		T22	7
all_values[3]	auto[0]	auto[1]	auto[0]	954437	1			T23	3		T21	14		T22	6
all_values[3]	auto[0]	auto[1]	auto[1]	9188052	1			T20	1		T1	1		T13	3
all_values[3]	auto[1]	auto[0]	auto[1]	131830	1			T23	2		T21	2		T22	2
all_values[3]	auto[1]	auto[1]	auto[1]	130548	1			T13	1		T72	4		T97	3
all_values[4]	auto[0]	auto[0]	auto[0]	3234550	1			T23	2		T20	1		T21	10
all_values[4]	auto[0]	auto[0]	auto[1]	9207936	1			T21	7		T22	1		T1	1
all_values[4]	auto[0]	auto[1]	auto[0]	945106	1			T23	3		T20	1		T21	6
all_values[4]	auto[0]	auto[1]	auto[1]	9151846	1			T23	4		T21	1		T22	2
all_values[4]	auto[1]	auto[0]	auto[1]	131641	1			T21	6		T22	1		T13	1
all_values[4]	auto[1]	auto[1]	auto[1]	130988	1			T23	3		T22	2		T72	1
all_values[5]	auto[0]	auto[0]	auto[0]	3226315	1			T23	5		T20	2		T21	6
all_values[5]	auto[0]	auto[0]	auto[1]	9209038	1			T21	12		T22	1		T1	1
all_values[5]	auto[0]	auto[1]	auto[0]	948691	1			T23	7		T21	4		T22	5
all_values[5]	auto[0]	auto[1]	auto[1]	9155875	1			T21	4		T1	1		T11	1
all_values[5]	auto[1]	auto[0]	auto[1]	131607	1			T21	3		T22	2		T13	1
all_values[5]	auto[1]	auto[1]	auto[1]	130541	1			T21	1		T72	3		T97	4
all_values[6]	auto[0]	auto[0]	auto[0]	3232396	1			T23	6		T20	1		T21	4
all_values[6]	auto[0]	auto[0]	auto[1]	9251823	1			T20	1		T21	6		T22	4
all_values[6]	auto[0]	auto[1]	auto[0]	955222	1			T23	2		T21	11		T22	4
all_values[6]	auto[0]	auto[1]	auto[1]	9100042	1			T23	2		T21	3		T11	1
all_values[6]	auto[1]	auto[0]	auto[1]	131937	1			T23	1		T21	3		T22	1
all_values[6]	auto[1]	auto[1]	auto[1]	130647	1			T23	1		T21	3		T22	1
all_values[7]	auto[0]	auto[0]	auto[0]	3220872	1			T23	7		T20	1		T21	9
all_values[7]	auto[0]	auto[0]	auto[1]	9176024	1			T20	1		T21	4		T22	7
all_values[7]	auto[0]	auto[1]	auto[0]	946873	1			T23	5		T21	10		T22	2
all_values[7]	auto[0]	auto[1]	auto[1]	9196441	1			T21	2		T22	2		T11	2
all_values[7]	auto[1]	auto[0]	auto[1]	131774	1			T21	3		T22	2		T13	2
all_values[7]	auto[1]	auto[1]	auto[1]	130083	1			T21	2		T22	1		T72	1
all_values[8]	auto[0]	auto[0]	auto[0]	3231812	1			T23	7		T20	1		T21	17
all_values[8]	auto[0]	auto[0]	auto[1]	9145945	1			T23	1		T20	1		T21	5
all_values[8]	auto[0]	auto[1]	auto[0]	954076	1			T23	3		T21	4		T22	2
all_values[8]	auto[0]	auto[1]	auto[1]	9207981	1			T21	1		T22	5		T14	2
all_values[8]	auto[1]	auto[0]	auto[1]	130991	1			T23	1		T21	2		T22	2
all_values[8]	auto[1]	auto[1]	auto[1]	131262	1			T21	1		T22	2		T72	1
all_values[9]	auto[0]	auto[0]	auto[0]	3221602	1			T23	7		T20	2		T21	12
all_values[9]	auto[0]	auto[0]	auto[1]	9231727	1			T21	3		T11	5		T13	1
all_values[9]	auto[0]	auto[1]	auto[0]	948192	1			T23	5		T21	7		T22	2
all_values[9]	auto[0]	auto[1]	auto[1]	9138654	1			T21	5		T22	2		T1	1
all_values[9]	auto[1]	auto[0]	auto[1]	131479	1			T21	2		T22	1		T13	2
all_values[9]	auto[1]	auto[1]	auto[1]	130413	1			T21	1		T22	1		T72	2
all_values[10]	auto[0]	auto[0]	auto[0]	3223528	1			T23	2		T20	1		T21	20
all_values[10]	auto[0]	auto[0]	auto[1]	9148277	1			T22	2		T11	6		T13	4
all_values[10]	auto[0]	auto[1]	auto[0]	954123	1			T23	10		T20	1		T21	8
all_values[10]	auto[0]	auto[1]	auto[1]	9214243	1			T1	1		T11	1		T13	4
all_values[10]	auto[1]	auto[0]	auto[1]	131571	1			T22	3		T13	2		T72	5
all_values[10]	auto[1]	auto[1]	auto[1]	130325	1			T21	2		T22	1		T72	2
all_values[11]	auto[0]	auto[0]	auto[0]	3226915	1			T23	7		T20	1		T21	14
all_values[11]	auto[0]	auto[0]	auto[1]	9215292	1			T21	5		T22	3		T11	8
all_values[11]	auto[0]	auto[1]	auto[0]	964902	1			T23	3		T20	1		T21	6
all_values[11]	auto[0]	auto[1]	auto[1]	9132577	1			T23	1		T22	6		T1	1
all_values[11]	auto[1]	auto[0]	auto[1]	131601	1			T21	5		T22	1		T72	2
all_values[11]	auto[1]	auto[1]	auto[1]	130780	1			T23	1		T22	1		T72	4
all_values[12]	auto[0]	auto[0]	auto[0]	3222088	1			T23	5		T20	1		T21	8
all_values[12]	auto[0]	auto[0]	auto[1]	9173302	1			T23	1		T21	1		T22	1
all_values[12]	auto[0]	auto[1]	auto[0]	953074	1			T23	5		T21	4		T22	3
all_values[12]	auto[0]	auto[1]	auto[1]	9191780	1			T20	1		T21	11		T22	8
all_values[12]	auto[1]	auto[0]	auto[1]	131361	1			T23	1		T21	1		T22	1
all_values[12]	auto[1]	auto[1]	auto[1]	130462	1			T21	5		T22	2		T72	4
all_values[13]	auto[0]	auto[0]	auto[0]	3216622	1			T23	6		T20	1		T21	7
all_values[13]	auto[0]	auto[0]	auto[1]	9204855	1			T22	4		T11	9		T14	4
all_values[13]	auto[0]	auto[1]	auto[0]	961082	1			T23	4		T21	14		T22	2
all_values[13]	auto[0]	auto[1]	auto[1]	9157543	1			T23	1		T20	1		T21	6
all_values[13]	auto[1]	auto[0]	auto[1]	130973	1			T23	1		T22	3		T72	2
all_values[13]	auto[1]	auto[1]	auto[1]	130992	1			T21	3		T22	2		T13	1
all_values[14]	auto[0]	auto[0]	auto[0]	3217256	1			T23	6		T20	1		T21	11
all_values[14]	auto[0]	auto[0]	auto[1]	9192992	1			T21	6		T22	1		T11	7
all_values[14]	auto[0]	auto[1]	auto[0]	949215	1			T23	1		T21	7		T22	3
all_values[14]	auto[0]	auto[1]	auto[1]	9180250	1			T23	3		T20	1		T21	3
all_values[14]	auto[1]	auto[0]	auto[1]	131493	1			T23	1		T21	3		T22	3
all_values[14]	auto[1]	auto[1]	auto[1]	130861	1			T23	1		T80	2		T97	2
all_values[15]	auto[0]	auto[0]	auto[0]	3219411	1			T23	7		T20	1		T21	12
all_values[15]	auto[0]	auto[0]	auto[1]	9204237	1			T20	1		T21	7		T22	11
all_values[15]	auto[0]	auto[1]	auto[0]	950285	1			T23	5		T21	7		T22	2
all_values[15]	auto[0]	auto[1]	auto[1]	9166625	1			T22	2		T1	1		T11	1
all_values[15]	auto[1]	auto[0]	auto[1]	130755	1			T21	4		T22	2		T13	2
all_values[15]	auto[1]	auto[1]	auto[1]	130754	1			T22	1		T72	2		T80	2
all_values[16]	auto[0]	auto[0]	auto[0]	3223374	1			T23	3		T20	1		T21	15
all_values[16]	auto[0]	auto[0]	auto[1]	9186609	1			T23	3		T20	1		T21	3
all_values[16]	auto[0]	auto[1]	auto[0]	950657	1			T23	1		T21	6		T22	1
all_values[16]	auto[0]	auto[1]	auto[1]	9179468	1			T23	3		T21	2		T22	10
all_values[16]	auto[1]	auto[0]	auto[1]	131378	1			T23	1		T21	4		T22	1
all_values[16]	auto[1]	auto[1]	auto[1]	130581	1			T23	1		T22	4		T72	1
all_values[17]	auto[0]	auto[0]	auto[0]	3220691	1			T23	4		T20	1		T21	13
all_values[17]	auto[0]	auto[0]	auto[1]	9230331	1			T22	1		T11	5		T14	1
all_values[17]	auto[0]	auto[1]	auto[0]	955046	1			T23	8		T21	14		T22	5
all_values[17]	auto[0]	auto[1]	auto[1]	9134046	1			T20	1		T22	1		T1	2
all_values[17]	auto[1]	auto[0]	auto[1]	131310	1			T21	2		T22	1		T72	1
all_values[17]	auto[1]	auto[1]	auto[1]	130643	1			T21	1		T22	1		T72	3
all_values[18]	auto[0]	auto[0]	auto[0]	3219539	1			T23	3		T20	1		T21	13
all_values[18]	auto[0]	auto[0]	auto[1]	9183631	1			T23	1		T21	3		T22	3
all_values[18]	auto[0]	auto[1]	auto[0]	969017	1			T23	1		T21	9		T22	2
all_values[18]	auto[0]	auto[1]	auto[1]	9168034	1			T23	6		T20	1		T21	1
all_values[18]	auto[1]	auto[0]	auto[1]	131789	1			T23	1		T21	1		T22	1
all_values[18]	auto[1]	auto[1]	auto[1]	130057	1			T21	3		T22	4		T13	1
all_values[19]	auto[0]	auto[0]	auto[0]	3240381	1			T23	5		T20	1		T21	9
all_values[19]	auto[0]	auto[0]	auto[1]	9235481	1			T23	1		T20	1		T21	7
all_values[19]	auto[0]	auto[1]	auto[0]	946262	1			T23	5		T21	4		T22	17
all_values[19]	auto[0]	auto[1]	auto[1]	9118303	1			T21	4		T22	1		T1	1
all_values[19]	auto[1]	auto[0]	auto[1]	130573	1			T23	1		T21	4		T22	1
all_values[19]	auto[1]	auto[1]	auto[1]	131067	1			T21	2		T13	1		T72	1
all_values[20]	auto[0]	auto[0]	auto[0]	3223950	1			T23	4		T20	1		T21	9
all_values[20]	auto[0]	auto[0]	auto[1]	9173774	1			T23	2		T20	1		T21	3
all_values[20]	auto[0]	auto[1]	auto[0]	958947	1			T23	3		T21	10		T22	7
all_values[20]	auto[0]	auto[1]	auto[1]	9183176	1			T21	4		T22	3		T1	1
all_values[20]	auto[1]	auto[0]	auto[1]	131006	1			T23	1		T21	3		T22	1
all_values[20]	auto[1]	auto[1]	auto[1]	131214	1			T23	2		T21	1		T22	2
all_values[21]	auto[0]	auto[0]	auto[0]	3227840	1			T23	4		T20	1		T21	12
all_values[21]	auto[0]	auto[0]	auto[1]	9181442	1			T23	2		T20	1		T21	6
all_values[21]	auto[0]	auto[1]	auto[0]	953934	1			T23	4		T21	5		T22	9
all_values[21]	auto[0]	auto[1]	auto[1]	9177197	1			T21	1		T22	2		T1	1
all_values[21]	auto[1]	auto[0]	auto[1]	131386	1			T23	1		T21	5		T22	3
all_values[21]	auto[1]	auto[1]	auto[1]	130268	1			T23	1		T21	1		T22	1
all_values[22]	auto[0]	auto[0]	auto[0]	3230893	1			T23	10		T20	2		T21	4
all_values[22]	auto[0]	auto[0]	auto[1]	9164288	1			T23	1		T21	9		T22	3
all_values[22]	auto[0]	auto[1]	auto[0]	961099	1			T21	12		T22	7		T11	4
all_values[22]	auto[0]	auto[1]	auto[1]	9183845	1			T21	2		T22	2		T1	1
all_values[22]	auto[1]	auto[0]	auto[1]	131071	1			T23	1		T21	3		T22	1
all_values[22]	auto[1]	auto[1]	auto[1]	130871	1			T80	1		T81	1		T97	1
all_values[23]	auto[0]	auto[0]	auto[0]	3238135	1			T23	2		T20	1		T21	5
all_values[23]	auto[0]	auto[0]	auto[1]	9200326	1			T20	1		T21	6		T22	4
all_values[23]	auto[0]	auto[1]	auto[0]	961570	1			T23	8		T21	4		T11	3
all_values[23]	auto[0]	auto[1]	auto[1]	9139326	1			T23	1		T21	10		T22	4
all_values[23]	auto[1]	auto[0]	auto[1]	131318	1			T21	3		T22	2		T13	3
all_values[23]	auto[1]	auto[1]	auto[1]	131392	1			T23	1		T21	2		T22	2
all_values[24]	auto[0]	auto[0]	auto[0]	3221112	1			T23	6		T20	1		T21	4
all_values[24]	auto[0]	auto[0]	auto[1]	9182149	1			T23	2		T21	6		T22	1
all_values[24]	auto[0]	auto[1]	auto[0]	943272	1			T23	1		T20	1		T21	10
all_values[24]	auto[0]	auto[1]	auto[1]	9193174	1			T23	1		T21	3		T22	1
all_values[24]	auto[1]	auto[0]	auto[1]	131579	1			T23	1		T21	3		T13	1
all_values[24]	auto[1]	auto[1]	auto[1]	130781	1			T23	1		T21	4		T22	1
all_values[25]	auto[0]	auto[0]	auto[0]	3227365	1			T23	2		T20	1		T21	3
all_values[25]	auto[0]	auto[0]	auto[1]	9156913	1			T21	7		T22	1		T1	1
all_values[25]	auto[0]	auto[1]	auto[0]	969779	1			T23	8		T21	11		T22	9
all_values[25]	auto[0]	auto[1]	auto[1]	9186052	1			T23	1		T20	1		T21	5
all_values[25]	auto[1]	auto[0]	auto[1]	131725	1			T21	1		T13	1		T72	1
all_values[25]	auto[1]	auto[1]	auto[1]	130233	1			T23	1		T21	3		T22	3
all_values[26]	auto[0]	auto[0]	auto[0]	3224060	1			T23	4		T20	1		T21	6
all_values[26]	auto[0]	auto[0]	auto[1]	9164490	1			T23	3		T21	4		T22	6
all_values[26]	auto[0]	auto[1]	auto[0]	944131	1			T23	3		T21	5		T22	1
all_values[26]	auto[0]	auto[1]	auto[1]	9207425	1			T20	1		T21	9		T1	1
all_values[26]	auto[1]	auto[0]	auto[1]	131406	1			T23	2		T21	2		T22	3
all_values[26]	auto[1]	auto[1]	auto[1]	130555	1			T21	4		T22	1		T13	1
all_values[27]	auto[0]	auto[0]	auto[0]	3225639	1			T23	9		T20	2		T21	8
all_values[27]	auto[0]	auto[0]	auto[1]	9187861	1			T23	1		T21	6		T22	6
all_values[27]	auto[0]	auto[1]	auto[0]	952144	1			T23	1		T21	11		T22	6
all_values[27]	auto[0]	auto[1]	auto[1]	9174942	1			T21	1		T22	1		T11	1
all_values[27]	auto[1]	auto[0]	auto[1]	131052	1			T21	3		T22	3		T13	2
all_values[27]	auto[1]	auto[1]	auto[1]	130429	1			T23	1		T21	1		T22	1
all_values[28]	auto[0]	auto[0]	auto[0]	3236326	1			T23	7		T20	1		T21	7
all_values[28]	auto[0]	auto[0]	auto[1]	9177541	1			T23	1		T21	2		T22	5
all_values[28]	auto[0]	auto[1]	auto[0]	942524	1			T23	3		T20	1		T21	8
all_values[28]	auto[0]	auto[1]	auto[1]	9183799	1			T21	7		T22	2		T1	1
all_values[28]	auto[1]	auto[0]	auto[1]	131182	1			T23	1		T21	3		T22	2
all_values[28]	auto[1]	auto[1]	auto[1]	130695	1			T21	3		T22	2		T72	2
all_values[29]	auto[0]	auto[0]	auto[0]	3228319	1			T23	6		T20	1		T21	4
all_values[29]	auto[0]	auto[0]	auto[1]	9225384	1			T21	1		T22	2		T11	5
all_values[29]	auto[0]	auto[1]	auto[0]	951346	1			T23	3		T21	12		T22	8
all_values[29]	auto[0]	auto[1]	auto[1]	9134591	1			T23	1		T20	1		T21	5
all_values[29]	auto[1]	auto[0]	auto[1]	131287	1			T23	1		T21	2		T22	2
all_values[29]	auto[1]	auto[1]	auto[1]	131140	1			T23	1		T21	6		T22	1
all_values[30]	auto[0]	auto[0]	auto[0]	3220480	1			T23	9		T20	1		T21	10
all_values[30]	auto[0]	auto[0]	auto[1]	9198038	1			T23	1		T21	3		T22	1
all_values[30]	auto[0]	auto[1]	auto[0]	951338	1			T21	10		T22	2		T11	2
all_values[30]	auto[0]	auto[1]	auto[1]	9169350	1			T20	1		T21	2		T1	1
all_values[30]	auto[1]	auto[0]	auto[1]	132008	1			T23	2		T21	3		T13	1
all_values[30]	auto[1]	auto[1]	auto[1]	130853	1			T21	2		T22	2		T13	1
all_values[31]	auto[0]	auto[0]	auto[0]	3225050	1			T23	3		T20	2		T21	14
all_values[31]	auto[0]	auto[0]	auto[1]	9220075	1			T23	1		T21	5		T22	6
all_values[31]	auto[0]	auto[1]	auto[0]	959044	1			T23	1		T21	8		T22	1
all_values[31]	auto[0]	auto[1]	auto[1]	9136050	1			T23	5		T22	3		T1	1
all_values[31]	auto[1]	auto[0]	auto[1]	131539	1			T23	1		T21	2		T22	4
all_values[31]	auto[1]	auto[1]	auto[1]	130309	1			T23	1		T21	1		T13	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal