Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[1]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[2]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[3]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[4]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[5]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[6]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[7]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[8]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[9]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[10]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[11]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[12]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[13]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[14]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[15]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[16]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[17]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[18]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[19]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[20]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[21]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[22]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[23]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[24]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[25]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[26]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[27]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[28]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[29]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[30]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[31]	22477655	1			T23	1		T20	2		T21	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443653948

1

T23

32

T20

64

T21

32

auto[1]

275631012

1

T38

4523

T39

7930

T40

4176

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571242452

1

T23

32

T20

64

T21

32

auto[1]

148042508

1

T38

7723

T39

10127

T40

6364

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

527510794

1

T23

32

T20

64

T21

32

auto[1]

191774166

1

T38

8018

T39

10007

T40

6542

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	8394272	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5755890	1			T38	24		T39	85		T40	37
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2325070	1			T38	113		T39	156		T40	114
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	3128998	1			T38	124		T39	139		T40	98
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	555885	1			T48	46		T50	190		T51	144
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2317540	1			T38	140		T39	152		T40	118
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	8405927	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5760051	1			T38	15		T39	91		T40	31
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2323389	1			T38	134		T39	198		T40	91
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	3125235	1			T38	101		T39	122		T40	130
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	558619	1			T48	34		T50	178		T51	148
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2304434	1			T38	130		T39	154		T40	98
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	8404129	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5755599	1			T38	24		T39	89		T40	31
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2333001	1			T38	117		T39	156		T40	88
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	3124789	1			T38	140		T39	159		T40	131
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	555958	1			T48	42		T50	200		T51	158
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2304179	1			T38	116		T39	184		T40	88
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	8410789	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5741359	1			T38	20		T39	93		T40	28
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2326844	1			T38	142		T39	151		T40	92
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	3132033	1			T38	122		T39	186		T40	115
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	557891	1			T48	38		T50	162		T51	134
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2308739	1			T38	122		T39	142		T40	92
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	8410902	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5756503	1			T38	15		T39	91		T40	31
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2319725	1			T38	132		T39	157		T40	94
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	3130273	1			T38	124		T39	156		T40	105
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	556678	1			T48	38		T50	186		T51	140
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2303574	1			T38	104		T39	152		T40	118
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	8412409	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5750012	1			T38	26		T39	96		T40	31
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2328577	1			T38	94		T39	154		T40	91
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	3120143	1			T38	154		T39	164		T40	94
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	557389	1			T48	41		T50	223		T51	138
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2309125	1			T38	114		T39	147		T40	106
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	8408664	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5757896	1			T38	23		T39	81		T40	31
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2327088	1			T38	116		T39	163		T40	106
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	3118329	1			T38	119		T39	114		T40	93
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	556975	1			T48	38		T50	196		T51	152
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2308703	1			T38	108		T39	202		T40	118
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	8403040	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5749215	1			T38	26		T39	81		T40	30
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2328054	1			T38	98		T39	120		T40	93
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	3132366	1			T38	165		T39	212		T40	132
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	560597	1			T48	23		T50	172		T51	143
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2304383	1			T38	114		T39	172		T40	84
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	8408303	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5740351	1			T38	21		T39	87		T40	25
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2327938	1			T38	147		T39	130		T40	84
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	3133102	1			T38	90		T39	165		T40	111
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	558994	1			T48	36		T50	240		T51	153
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2308967	1			T38	102		T39	170		T40	96
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	8396064	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5757476	1			T38	14		T39	103		T40	28
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2325016	1			T38	122		T39	141		T40	120
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	3129090	1			T38	141		T39	156		T40	103
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	559566	1			T48	42		T50	185		T51	138
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2310443	1			T38	118		T39	168		T40	76
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	8399965	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5750368	1			T38	20		T39	85		T40	32
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2319546	1			T38	117		T39	164		T40	76
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	3140709	1			T38	156		T39	155		T40	122
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	558935	1			T48	30		T50	184		T51	140
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2308132	1			T38	116		T39	144		T40	129
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	8408004	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5752395	1			T38	22		T39	91		T40	29
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2329810	1			T38	132		T39	158		T40	88
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	3121144	1			T38	102		T39	142		T40	107
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	559384	1			T48	46		T50	174		T51	125
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2306918	1			T38	109		T39	166		T40	88
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	8414787	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5743057	1			T38	19		T39	102		T40	28
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2330206	1			T38	122		T39	190		T40	94
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	3127865	1			T38	114		T39	169		T40	96
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	558343	1			T48	37		T50	190		T51	170
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2303397	1			T38	130		T39	114		T40	75
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	8414028	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5748230	1			T38	19		T39	86		T40	32
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2320770	1			T38	132		T39	170		T40	100
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	3125276	1			T38	103		T39	109		T40	96
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	556008	1			T48	34		T50	176		T51	171
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2313343	1			T38	112		T39	190		T40	124
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	8395364	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5751147	1			T38	19		T39	110		T40	26
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2329683	1			T38	136		T39	150		T40	90
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	3131276	1			T38	148		T39	153		T40	89
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	561428	1			T48	47		T50	184		T51	135
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2308757	1			T38	108		T39	162		T40	110
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	8405948	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5751234	1			T38	21		T39	90		T40	31
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2327023	1			T38	118		T39	177		T40	90
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	3126232	1			T38	133		T39	160		T40	97
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	558753	1			T48	24		T50	188		T51	171
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2308465	1			T38	162		T39	152		T40	106
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	8409546	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5748696	1			T38	18		T39	95		T40	31
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2322955	1			T38	119		T39	171		T40	118
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	3138836	1			T38	138		T39	126		T40	105
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	557531	1			T48	46		T50	192		T51	151
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2300091	1			T38	126		T39	162		T40	102
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	8418146	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5755224	1			T38	22		T39	83		T40	33
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2318062	1			T38	117		T39	154		T40	120
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	3131027	1			T38	144		T39	178		T40	92
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	559360	1			T48	46		T50	215		T51	115
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2295836	1			T38	116		T39	158		T40	100
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	8404066	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5754393	1			T38	16		T39	89		T40	32
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2319910	1			T38	98		T39	168		T40	102
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	3131971	1			T38	140		T39	151		T40	101
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	559798	1			T48	24		T50	214		T51	146
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2307517	1			T38	119		T39	164		T40	106
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	8423341	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5744755	1			T38	17		T39	98		T40	30
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2318996	1			T38	110		T39	162		T40	80
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	3136983	1			T38	130		T39	158		T40	108
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	559014	1			T48	22		T50	143		T51	156
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2294566	1			T38	102		T39	170		T40	104
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	8409536	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5753941	1			T38	18		T39	89		T40	28
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2321874	1			T38	126		T39	182		T40	98
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	3137314	1			T38	116		T39	148		T40	98
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	557733	1			T48	48		T50	187		T51	147
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2297257	1			T38	119		T39	115		T40	130
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	8393338	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5768624	1			T38	25		T39	85		T40	34
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2325361	1			T38	80		T39	162		T40	102
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	3133497	1			T38	174		T39	134		T40	105
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	559300	1			T48	37		T50	182		T51	172
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2297535	1			T38	149		T39	138		T40	74
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	8422172	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5744622	1			T38	23		T39	103		T40	29
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2318697	1			T38	136		T39	164		T40	95
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	3131643	1			T38	91		T39	166		T40	94
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	557725	1			T48	40		T50	180		T51	126
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2302796	1			T38	116		T39	177		T40	110
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	8410882	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5764366	1			T38	22		T39	83		T40	31
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2321783	1			T38	166		T39	115		T40	94
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3131785	1			T38	100		T39	202		T40	128
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	554161	1			T48	43		T50	196		T51	159
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2294678	1			T38	115		T39	138		T40	83
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	8417837	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5755557	1			T38	24		T39	80		T40	26
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2313916	1			T38	112		T39	173		T40	88
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	3132503	1			T38	119		T39	148		T40	102
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	559360	1			T48	28		T50	174		T51	150
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2298482	1			T38	136		T39	176		T40	117
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	8417500	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5747751	1			T38	19		T39	85		T40	30
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2314195	1			T38	92		T39	142		T40	96
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	3142677	1			T38	154		T39	153		T40	116
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	560229	1			T48	32		T50	186		T51	129
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2295303	1			T38	121		T39	154		T40	76
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	8420184	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5750157	1			T38	17		T39	85		T40	22
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2313543	1			T38	120		T39	202		T40	91
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	3136453	1			T38	122		T39	145		T40	94
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	557472	1			T48	50		T50	175		T51	140
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2299846	1			T38	149		T39	146		T40	94
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	8418476	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5748551	1			T38	18		T39	83		T40	31
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2325560	1			T38	158		T39	108		T40	129
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	3127620	1			T38	109		T39	178		T40	92
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	558715	1			T48	34		T50	182		T51	172
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2298733	1			T38	130		T39	161		T40	80
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	8415381	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5750567	1			T38	16		T39	94		T40	31
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2312627	1			T38	94		T39	158		T40	99
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	3138319	1			T38	153		T39	125		T40	94
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	559993	1			T48	38		T50	200		T51	166
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2300768	1			T38	110		T39	142		T40	126
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	8412634	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5754501	1			T38	17		T39	85		T40	28
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2324749	1			T38	102		T39	165		T40	96
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	3125900	1			T38	148		T39	168		T40	88
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	557427	1			T48	32		T50	198		T51	160
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2302444	1			T38	119		T39	172		T40	116
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	8414968	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5748383	1			T38	21		T39	88		T40	32
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2315840	1			T38	115		T39	170		T40	102
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	3140772	1			T38	130		T39	152		T40	84
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	559569	1			T48	26		T50	176		T51	130
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2298123	1			T38	126		T39	139		T40	95
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	8422186	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5743112	1			T38	16		T39	94		T40	28
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2324215	1			T38	120		T39	146		T40	124
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	3132977	1			T38	128		T39	164		T40	103
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	559754	1			T48	46		T50	168		T51	164
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2295411	1			T38	128		T39	167		T40	80

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal