Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[1]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[2]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[3]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[4]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[5]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[6]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[7]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[8]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[9]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[10]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[11]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[12]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[13]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[14]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[15]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[16]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[17]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[18]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[19]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[20]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[21]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[22]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[23]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[24]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[25]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[26]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[27]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[28]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[29]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[30]	22477655	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[31]	22477655	1			T23	1		T20	2		T21	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443653948

1

T23

32

T20

64

T21

32

auto[1]

275631012

1

T38

4523

T39

7930

T40

4176

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443645289

1

T23

32

T20

56

T21

32

auto[1]

275639671

1

T20

8

T1

23

T11

152

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	13434260	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	413788	1			T38	36		T39	41		T40	28
bins_for_gpio_bits[0]	auto[1]	auto[0]	414080	1			T11	3		T14	3		T15	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	8215527	1			T38	128		T39	196		T40	127
bins_for_gpio_bits[1]	auto[0]	auto[0]	13441865	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	412404	1			T38	29		T39	39		T40	27
bins_for_gpio_bits[1]	auto[1]	auto[0]	412686	1			T1	1		T11	5		T14	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	8210700	1			T38	116		T39	206		T40	102
bins_for_gpio_bits[2]	auto[0]	auto[0]	13448833	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	412803	1			T38	28		T39	38		T40	25
bins_for_gpio_bits[2]	auto[1]	auto[0]	413086	1			T20	1		T1	1		T11	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	8202933	1			T38	112		T39	235		T40	94
bins_for_gpio_bits[3]	auto[0]	auto[0]	13456380	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	413036	1			T38	34		T39	39		T40	24
bins_for_gpio_bits[3]	auto[1]	auto[0]	413286	1			T1	1		T11	4		T14	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	8194953	1			T38	108		T39	196		T40	96
bins_for_gpio_bits[4]	auto[0]	auto[0]	13448592	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	412032	1			T38	26		T39	37		T40	31
bins_for_gpio_bits[4]	auto[1]	auto[0]	412308	1			T11	6		T14	3		T15	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	8204723	1			T38	93		T39	206		T40	118
bins_for_gpio_bits[5]	auto[0]	auto[0]	13448075	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	412759	1			T38	27		T39	37		T40	28
bins_for_gpio_bits[5]	auto[1]	auto[0]	413054	1			T1	1		T11	2		T15	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	8203767	1			T38	113		T39	206		T40	109
bins_for_gpio_bits[6]	auto[0]	auto[0]	13441101	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	412712	1			T38	22		T39	42		T40	28
bins_for_gpio_bits[6]	auto[1]	auto[0]	412980	1			T11	5		T14	2		T15	6
bins_for_gpio_bits[6]	auto[1]	auto[1]	8210862	1			T38	109		T39	241		T40	121
bins_for_gpio_bits[7]	auto[0]	auto[0]	13450296	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	412860	1			T38	33		T39	36		T40	22
bins_for_gpio_bits[7]	auto[1]	auto[0]	413164	1			T1	1		T11	2		T15	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	8201335	1			T38	107		T39	217		T40	92
bins_for_gpio_bits[8]	auto[0]	auto[0]	13455574	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	413494	1			T38	28		T39	35		T40	26
bins_for_gpio_bits[8]	auto[1]	auto[0]	413769	1			T11	4		T15	7		T36	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	8194818	1			T38	95		T39	222		T40	95
bins_for_gpio_bits[9]	auto[0]	auto[0]	13437223	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	412677	1			T38	32		T39	40		T40	25
bins_for_gpio_bits[9]	auto[1]	auto[0]	412947	1			T11	3		T14	2		T15	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	8214808	1			T38	100		T39	231		T40	79
bins_for_gpio_bits[10]	auto[0]	auto[0]	13447204	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	412741	1			T38	33		T39	38		T40	34
bins_for_gpio_bits[10]	auto[1]	auto[0]	413016	1			T1	1		T11	8		T14	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	8204694	1			T38	103		T39	191		T40	127
bins_for_gpio_bits[11]	auto[0]	auto[0]	13446926	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	411762	1			T38	24		T39	36		T40	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	412032	1			T11	8		T14	3		T15	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	8206935	1			T38	107		T39	221		T40	93
bins_for_gpio_bits[12]	auto[0]	auto[0]	13460077	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	412483	1			T38	28		T39	36		T40	20
bins_for_gpio_bits[12]	auto[1]	auto[0]	412781	1			T20	1		T1	1		T11	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	8192314	1			T38	121		T39	180		T40	83
bins_for_gpio_bits[13]	auto[0]	auto[0]	13446707	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	413096	1			T38	26		T39	42		T40	29
bins_for_gpio_bits[13]	auto[1]	auto[0]	413367	1			T20	1		T11	5		T14	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	8204485	1			T38	105		T39	234		T40	127
bins_for_gpio_bits[14]	auto[0]	auto[0]	13443610	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	412462	1			T38	30		T39	40		T40	26
bins_for_gpio_bits[14]	auto[1]	auto[0]	412713	1			T11	4		T14	2		T15	6
bins_for_gpio_bits[14]	auto[1]	auto[1]	8208870	1			T38	97		T39	232		T40	110
bins_for_gpio_bits[15]	auto[0]	auto[0]	13446046	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	412887	1			T38	32		T39	44		T40	28
bins_for_gpio_bits[15]	auto[1]	auto[0]	413157	1			T1	1		T11	4		T14	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	8205565	1			T38	151		T39	198		T40	109
bins_for_gpio_bits[16]	auto[0]	auto[0]	13457359	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	413705	1			T38	34		T39	40		T40	27
bins_for_gpio_bits[16]	auto[1]	auto[0]	413978	1			T20	1		T1	2		T11	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	8192613	1			T38	110		T39	217		T40	106
bins_for_gpio_bits[17]	auto[0]	auto[0]	13454571	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	412424	1			T38	32		T39	47		T40	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	412664	1			T1	1		T11	5		T15	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	8197996	1			T38	106		T39	194		T40	108
bins_for_gpio_bits[18]	auto[0]	auto[0]	13442744	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	412909	1			T38	27		T39	41		T40	28
bins_for_gpio_bits[18]	auto[1]	auto[0]	413203	1			T11	8		T14	5		T15	9
bins_for_gpio_bits[18]	auto[1]	auto[1]	8208799	1			T38	108		T39	212		T40	110
bins_for_gpio_bits[19]	auto[0]	auto[0]	13466372	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	412648	1			T38	26		T39	40		T40	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	412948	1			T1	2		T11	9		T14	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	8185687	1			T38	93		T39	228		T40	110
bins_for_gpio_bits[20]	auto[0]	auto[0]	13455778	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	412698	1			T38	28		T39	32		T40	24
bins_for_gpio_bits[20]	auto[1]	auto[0]	412946	1			T20	1		T1	2		T11	5
bins_for_gpio_bits[20]	auto[1]	auto[1]	8196233	1			T38	109		T39	172		T40	134
bins_for_gpio_bits[21]	auto[0]	auto[0]	13438569	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	413377	1			T38	33		T39	36		T40	21
bins_for_gpio_bits[21]	auto[1]	auto[0]	413627	1			T20	1		T1	1		T11	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	8212082	1			T38	141		T39	187		T40	87
bins_for_gpio_bits[22]	auto[0]	auto[0]	13458725	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	413527	1			T38	32		T39	43		T40	25
bins_for_gpio_bits[22]	auto[1]	auto[0]	413787	1			T1	1		T11	3		T14	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	8191616	1			T38	107		T39	237		T40	114
bins_for_gpio_bits[23]	auto[0]	auto[0]	13451769	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	412395	1			T38	32		T39	35		T40	19
bins_for_gpio_bits[23]	auto[1]	auto[0]	412681	1			T11	4		T14	4		T15	8
bins_for_gpio_bits[23]	auto[1]	auto[1]	8200810	1			T38	105		T39	186		T40	95
bins_for_gpio_bits[24]	auto[0]	auto[0]	13452000	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	411981	1			T38	33		T39	47		T40	24
bins_for_gpio_bits[24]	auto[1]	auto[0]	412256	1			T1	1		T11	1		T15	4
bins_for_gpio_bits[24]	auto[1]	auto[1]	8201418	1			T38	127		T39	209		T40	119
bins_for_gpio_bits[25]	auto[0]	auto[0]	13461263	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	412834	1			T38	28		T39	37		T40	22
bins_for_gpio_bits[25]	auto[1]	auto[0]	413109	1			T1	1		T11	4		T14	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	8190449	1			T38	112		T39	202		T40	84
bins_for_gpio_bits[26]	auto[0]	auto[0]	13457098	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	412818	1			T38	33		T39	43		T40	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	413082	1			T20	1		T1	1		T11	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	8194657	1			T38	133		T39	188		T40	94
bins_for_gpio_bits[27]	auto[0]	auto[0]	13458653	1			T23	1		T20	1		T21	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	412755	1			T38	34		T39	38		T40	21
bins_for_gpio_bits[27]	auto[1]	auto[0]	413003	1			T20	1		T1	1		T11	4
bins_for_gpio_bits[27]	auto[1]	auto[1]	8193244	1			T38	114		T39	206		T40	90
bins_for_gpio_bits[28]	auto[0]	auto[0]	13453547	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	412559	1			T38	25		T39	39		T40	31
bins_for_gpio_bits[28]	auto[1]	auto[0]	412780	1			T1	1		T11	3		T14	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	8198769	1			T38	101		T39	197		T40	126
bins_for_gpio_bits[29]	auto[0]	auto[0]	13450383	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	412620	1			T38	28		T39	43		T40	29
bins_for_gpio_bits[29]	auto[1]	auto[0]	412900	1			T1	1		T11	5		T15	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	8201752	1			T38	108		T39	214		T40	115
bins_for_gpio_bits[30]	auto[0]	auto[0]	13458185	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	413144	1			T38	29		T39	36		T40	22
bins_for_gpio_bits[30]	auto[1]	auto[0]	413395	1			T11	4		T14	1		T15	3
bins_for_gpio_bits[30]	auto[1]	auto[1]	8192931	1			T38	118		T39	191		T40	105
bins_for_gpio_bits[31]	auto[0]	auto[0]	13467002	1			T23	1		T20	2		T21	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	412112	1			T38	30		T39	39		T40	25
bins_for_gpio_bits[31]	auto[1]	auto[0]	412376	1			T11	9		T14	3		T15	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	8186165	1			T38	114		T39	222		T40	83