Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12540584 |
1 |
|
|
T23 |
7 |
|
T20 |
2 |
|
T21 |
18 |
| auto[1] |
10261483 |
1 |
|
|
T23 |
5 |
|
T21 |
12 |
|
T22 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21482133 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1319934 |
1 |
|
|
T74 |
2 |
|
T91 |
4 |
|
T95 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12577326 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10224741 |
1 |
|
|
T11 |
8 |
|
T14 |
4 |
|
T15 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4464477 |
1 |
|
|
T11 |
8 |
|
T14 |
3 |
|
T15 |
5 |
| auto[1] |
auto[0] |
auto[1] |
662848 |
1 |
|
|
T74 |
2 |
|
T91 |
4 |
|
T95 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4440330 |
1 |
|
|
T14 |
1 |
|
T15 |
4 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
657086 |
1 |
|
|
T95 |
2 |
|
T47 |
2800 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12570728 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
14 |
| auto[1] |
10231339 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21464531 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1337536 |
1 |
|
|
T89 |
1 |
|
T90 |
1 |
|
T92 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12457791 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10344276 |
1 |
|
|
T1 |
2 |
|
T11 |
4 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4505047 |
1 |
|
|
T1 |
2 |
|
T11 |
3 |
|
T14 |
2 |
| auto[1] |
auto[0] |
auto[1] |
668553 |
1 |
|
|
T92 |
1 |
|
T47 |
2969 |
|
T98 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4501693 |
1 |
|
|
T11 |
1 |
|
T15 |
6 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
668983 |
1 |
|
|
T89 |
1 |
|
T90 |
1 |
|
T95 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12503376 |
1 |
|
|
T23 |
2 |
|
T20 |
1 |
|
T21 |
20 |
| auto[1] |
10298691 |
1 |
|
|
T23 |
10 |
|
T20 |
1 |
|
T21 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21476262 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1325805 |
1 |
|
|
T2 |
1 |
|
T74 |
2 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12530067 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10272000 |
1 |
|
|
T11 |
9 |
|
T14 |
3 |
|
T15 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4467674 |
1 |
|
|
T11 |
8 |
|
T14 |
1 |
|
T15 |
6 |
| auto[1] |
auto[0] |
auto[1] |
661584 |
1 |
|
|
T89 |
2 |
|
T47 |
2856 |
|
T98 |
7 |
| auto[1] |
auto[1] |
auto[0] |
4478521 |
1 |
|
|
T11 |
1 |
|
T14 |
2 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
664221 |
1 |
|
|
T2 |
1 |
|
T74 |
2 |
|
T75 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12573808 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
24 |
| auto[1] |
10228259 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21478640 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1323427 |
1 |
|
|
T74 |
3 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12542316 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10259751 |
1 |
|
|
T11 |
4 |
|
T14 |
3 |
|
T15 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4485935 |
1 |
|
|
T11 |
3 |
|
T14 |
3 |
|
T15 |
6 |
| auto[1] |
auto[0] |
auto[1] |
665355 |
1 |
|
|
T74 |
3 |
|
T89 |
2 |
|
T90 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4450389 |
1 |
|
|
T11 |
1 |
|
T15 |
6 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
658072 |
1 |
|
|
T5 |
1 |
|
T8 |
1 |
|
T90 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12526751 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
10 |
| auto[1] |
10275316 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21482491 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1319576 |
1 |
|
|
T74 |
1 |
|
T75 |
1 |
|
T88 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12573911 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10228156 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T14 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4462771 |
1 |
|
|
T11 |
5 |
|
T14 |
2 |
|
T15 |
7 |
| auto[1] |
auto[0] |
auto[1] |
661771 |
1 |
|
|
T74 |
1 |
|
T90 |
2 |
|
T91 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4445809 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T15 |
4 |
| auto[1] |
auto[1] |
auto[1] |
657805 |
1 |
|
|
T75 |
1 |
|
T88 |
2 |
|
T92 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12552450 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
7 |
| auto[1] |
10249617 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21474075 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1327992 |
1 |
|
|
T2 |
1 |
|
T90 |
2 |
|
T91 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12517505 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10284562 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T14 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4478077 |
1 |
|
|
T11 |
3 |
|
T14 |
1 |
|
T15 |
6 |
| auto[1] |
auto[0] |
auto[1] |
663745 |
1 |
|
|
T90 |
2 |
|
T95 |
1 |
|
T47 |
2749 |
| auto[1] |
auto[1] |
auto[0] |
4478493 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T15 |
4 |
| auto[1] |
auto[1] |
auto[1] |
664247 |
1 |
|
|
T2 |
1 |
|
T91 |
2 |
|
T95 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12541741 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
20 |
| auto[1] |
10260326 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21473037 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1329030 |
1 |
|
|
T74 |
5 |
|
T8 |
2 |
|
T90 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12507605 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10294462 |
1 |
|
|
T11 |
3 |
|
T14 |
2 |
|
T15 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4482142 |
1 |
|
|
T11 |
2 |
|
T14 |
1 |
|
T15 |
5 |
| auto[1] |
auto[0] |
auto[1] |
664253 |
1 |
|
|
T47 |
2818 |
|
T98 |
3 |
|
T66 |
5376 |
| auto[1] |
auto[1] |
auto[0] |
4483290 |
1 |
|
|
T11 |
1 |
|
T14 |
1 |
|
T15 |
5 |
| auto[1] |
auto[1] |
auto[1] |
664777 |
1 |
|
|
T74 |
5 |
|
T8 |
2 |
|
T90 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12554403 |
1 |
|
|
T23 |
7 |
|
T20 |
2 |
|
T21 |
23 |
| auto[1] |
10247664 |
1 |
|
|
T23 |
5 |
|
T21 |
7 |
|
T22 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21471453 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1330614 |
1 |
|
|
T88 |
2 |
|
T8 |
2 |
|
T89 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12495416 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10306651 |
1 |
|
|
T1 |
1 |
|
T11 |
6 |
|
T14 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4499536 |
1 |
|
|
T1 |
1 |
|
T11 |
6 |
|
T14 |
1 |
| auto[1] |
auto[0] |
auto[1] |
666342 |
1 |
|
|
T8 |
2 |
|
T91 |
2 |
|
T92 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4476501 |
1 |
|
|
T15 |
3 |
|
T2 |
1 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[1] |
664272 |
1 |
|
|
T88 |
2 |
|
T89 |
2 |
|
T47 |
2836 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12541361 |
1 |
|
|
T23 |
7 |
|
T20 |
2 |
|
T21 |
22 |
| auto[1] |
10260706 |
1 |
|
|
T23 |
5 |
|
T21 |
8 |
|
T22 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21481557 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1320510 |
1 |
|
|
T2 |
1 |
|
T74 |
2 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12579352 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10222715 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4464233 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
7 |
| auto[1] |
auto[0] |
auto[1] |
661956 |
1 |
|
|
T2 |
1 |
|
T74 |
2 |
|
T90 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4437972 |
1 |
|
|
T15 |
4 |
|
T16 |
1 |
|
T36 |
2 |
| auto[1] |
auto[1] |
auto[1] |
658554 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T89 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12582332 |
1 |
|
|
T23 |
4 |
|
T20 |
1 |
|
T21 |
15 |
| auto[1] |
10219735 |
1 |
|
|
T23 |
8 |
|
T20 |
1 |
|
T21 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21475264 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1326803 |
1 |
|
|
T5 |
1 |
|
T90 |
1 |
|
T91 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12527424 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10274643 |
1 |
|
|
T1 |
1 |
|
T11 |
8 |
|
T14 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4491429 |
1 |
|
|
T11 |
4 |
|
T14 |
3 |
|
T15 |
6 |
| auto[1] |
auto[0] |
auto[1] |
666586 |
1 |
|
|
T5 |
1 |
|
T91 |
1 |
|
T92 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4456411 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T15 |
4 |
| auto[1] |
auto[1] |
auto[1] |
660217 |
1 |
|
|
T90 |
1 |
|
T95 |
1 |
|
T47 |
2986 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12534959 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
17 |
| auto[1] |
10267108 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21476869 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1325198 |
1 |
|
|
T2 |
1 |
|
T75 |
2 |
|
T8 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12520683 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10281384 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4495197 |
1 |
|
|
T11 |
8 |
|
T14 |
2 |
|
T15 |
9 |
| auto[1] |
auto[0] |
auto[1] |
665828 |
1 |
|
|
T90 |
2 |
|
T77 |
1 |
|
T95 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4460989 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T14 |
1 |
| auto[1] |
auto[1] |
auto[1] |
659370 |
1 |
|
|
T2 |
1 |
|
T75 |
2 |
|
T8 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12606435 |
1 |
|
|
T23 |
7 |
|
T20 |
2 |
|
T21 |
20 |
| auto[1] |
10195632 |
1 |
|
|
T23 |
5 |
|
T21 |
10 |
|
T22 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21479124 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1322943 |
1 |
|
|
T75 |
2 |
|
T91 |
1 |
|
T92 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12545152 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10256915 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4500372 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
667458 |
1 |
|
|
T47 |
2879 |
|
T98 |
3 |
|
T66 |
5501 |
| auto[1] |
auto[1] |
auto[0] |
4433600 |
1 |
|
|
T11 |
1 |
|
T14 |
2 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[1] |
655485 |
1 |
|
|
T75 |
2 |
|
T91 |
1 |
|
T92 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12521516 |
1 |
|
|
T23 |
5 |
|
T20 |
1 |
|
T21 |
20 |
| auto[1] |
10280551 |
1 |
|
|
T23 |
7 |
|
T20 |
1 |
|
T21 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21483174 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1318893 |
1 |
|
|
T5 |
1 |
|
T90 |
3 |
|
T91 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12573643 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10228424 |
1 |
|
|
T1 |
2 |
|
T11 |
6 |
|
T15 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4447618 |
1 |
|
|
T1 |
1 |
|
T11 |
5 |
|
T15 |
5 |
| auto[1] |
auto[0] |
auto[1] |
658524 |
1 |
|
|
T5 |
1 |
|
T90 |
3 |
|
T91 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4461913 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T15 |
4 |
| auto[1] |
auto[1] |
auto[1] |
660369 |
1 |
|
|
T92 |
1 |
|
T47 |
2886 |
|
T98 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12528730 |
1 |
|
|
T23 |
7 |
|
T20 |
2 |
|
T21 |
15 |
| auto[1] |
10273337 |
1 |
|
|
T23 |
5 |
|
T21 |
15 |
|
T22 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21480385 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1321682 |
1 |
|
|
T74 |
1 |
|
T88 |
2 |
|
T90 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12549589 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10252478 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4459143 |
1 |
|
|
T20 |
1 |
|
T14 |
2 |
|
T15 |
9 |
| auto[1] |
auto[0] |
auto[1] |
660473 |
1 |
|
|
T74 |
1 |
|
T90 |
2 |
|
T77 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4471653 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T14 |
1 |
| auto[1] |
auto[1] |
auto[1] |
661209 |
1 |
|
|
T88 |
2 |
|
T90 |
1 |
|
T91 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12540668 |
1 |
|
|
T23 |
7 |
|
T20 |
2 |
|
T21 |
23 |
| auto[1] |
10261399 |
1 |
|
|
T23 |
5 |
|
T21 |
7 |
|
T22 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21476001 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1326066 |
1 |
|
|
T75 |
3 |
|
T88 |
4 |
|
T90 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12521173 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10280894 |
1 |
|
|
T11 |
7 |
|
T14 |
3 |
|
T15 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4495989 |
1 |
|
|
T11 |
5 |
|
T14 |
1 |
|
T15 |
7 |
| auto[1] |
auto[0] |
auto[1] |
667598 |
1 |
|
|
T90 |
1 |
|
T91 |
1 |
|
T92 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4458839 |
1 |
|
|
T11 |
2 |
|
T14 |
2 |
|
T15 |
6 |
| auto[1] |
auto[1] |
auto[1] |
658468 |
1 |
|
|
T75 |
3 |
|
T88 |
4 |
|
T95 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12526252 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
16 |
| auto[1] |
10275815 |
1 |
|
|
T21 |
14 |
|
T22 |
9 |
|
T1 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21477941 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1324126 |
1 |
|
|
T75 |
2 |
|
T10 |
1 |
|
T91 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12536383 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10265684 |
1 |
|
|
T20 |
1 |
|
T1 |
2 |
|
T11 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4466390 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
660663 |
1 |
|
|
T10 |
1 |
|
T47 |
2772 |
|
T42 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4475168 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T14 |
2 |
| auto[1] |
auto[1] |
auto[1] |
663463 |
1 |
|
|
T75 |
2 |
|
T91 |
3 |
|
T95 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12569779 |
1 |
|
|
T23 |
2 |
|
T20 |
2 |
|
T21 |
14 |
| auto[1] |
10232288 |
1 |
|
|
T23 |
10 |
|
T21 |
16 |
|
T22 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21483045 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1319022 |
1 |
|
|
T2 |
1 |
|
T74 |
2 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12568549 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10233518 |
1 |
|
|
T20 |
1 |
|
T1 |
2 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4472886 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
663442 |
1 |
|
|
T75 |
1 |
|
T88 |
3 |
|
T8 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4441610 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[1] |
655580 |
1 |
|
|
T2 |
1 |
|
T74 |
2 |
|
T89 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12534840 |
1 |
|
|
T23 |
9 |
|
T20 |
1 |
|
T21 |
13 |
| auto[1] |
10267227 |
1 |
|
|
T23 |
3 |
|
T20 |
1 |
|
T21 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21477623 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1324444 |
1 |
|
|
T75 |
3 |
|
T5 |
1 |
|
T88 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12531044 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10271023 |
1 |
|
|
T20 |
1 |
|
T1 |
1 |
|
T11 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4478996 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T14 |
1 |
| auto[1] |
auto[0] |
auto[1] |
663471 |
1 |
|
|
T88 |
3 |
|
T90 |
1 |
|
T91 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4467583 |
1 |
|
|
T20 |
1 |
|
T11 |
1 |
|
T14 |
2 |
| auto[1] |
auto[1] |
auto[1] |
660973 |
1 |
|
|
T75 |
3 |
|
T5 |
1 |
|
T95 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12516003 |
1 |
|
|
T23 |
2 |
|
T20 |
1 |
|
T21 |
11 |
| auto[1] |
10286064 |
1 |
|
|
T23 |
10 |
|
T20 |
1 |
|
T21 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21476087 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1325980 |
1 |
|
|
T74 |
1 |
|
T75 |
1 |
|
T88 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12522461 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
10279606 |
1 |
|
|
T11 |
3 |
|
T14 |
3 |
|
T15 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4469563 |
1 |
|
|
T11 |
3 |
|
T14 |
3 |
|
T15 |
6 |
| auto[1] |
auto[0] |
auto[1] |
662339 |
1 |
|
|
T74 |
1 |
|
T75 |
1 |
|
T88 |
6 |
| auto[1] |
auto[1] |
auto[0] |
4484063 |
1 |
|
|
T15 |
5 |
|
T2 |
2 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[1] |
663641 |
1 |
|
|
T8 |
2 |
|
T76 |
1 |
|
T93 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12519956 |
1 |
|
|
T23 |
9 |
|
T20 |
1 |
|
T21 |
12 |
| auto[1] |
10282111 |
1 |
|
|
T23 |
3 |
|
T20 |
1 |
|
T21 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21469243 |
1 |
|
|
T23 |
12 |
|
T20 |
2 |
|
T21 |
30 |
| auto[1] |
1332824 |
1 |
|
|
T74 |
2 |
|
T88 |
7 |
|
T89 |
3 |