Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12497375 |
1 |
|
|
T23 |
12 |
|
T20 |
1 |
|
T21 |
30 |
| auto[1] |
10304692 |
1 |
|
|
T20 |
1 |
|
T1 |
2 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4472860 |
1 |
|
|
T11 |
5 |
|
T15 |
8 |
|
T16 |
1 |
| auto[1] |
auto[0] |
auto[1] |
664514 |
1 |
|
|
T88 |
7 |
|
T91 |
3 |
|
T76 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4499008 |
1 |
|
|
T20 |
1 |
|
T1 |
2 |
|
T14 |
4 |
| auto[1] |
auto[1] |
auto[1] |
668310 |
1 |
|
|
T74 |
2 |
|
T89 |
3 |
|
T47 |
2697 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |