Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 970
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T760 /workspace/coverage/default/25.gpio_stress_all.1456583166 Jan 17 03:41:17 PM PST 24 Jan 17 03:43:02 PM PST 24 27411781849 ps
T761 /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3989125062 Jan 17 03:40:15 PM PST 24 Jan 17 03:40:20 PM PST 24 99650287 ps
T762 /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2271692290 Jan 17 03:39:43 PM PST 24 Jan 17 03:39:47 PM PST 24 51026550 ps
T763 /workspace/coverage/default/14.gpio_smoke.1834980164 Jan 17 03:40:21 PM PST 24 Jan 17 03:40:24 PM PST 24 80144288 ps
T764 /workspace/coverage/default/6.gpio_rand_intr_trigger.599132345 Jan 17 03:40:01 PM PST 24 Jan 17 03:40:04 PM PST 24 108505017 ps
T765 /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.218532047 Jan 17 03:41:01 PM PST 24 Jan 17 03:41:04 PM PST 24 53689124 ps
T766 /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.152477990 Jan 17 03:39:51 PM PST 24 Jan 17 03:39:53 PM PST 24 218147915 ps
T767 /workspace/coverage/default/29.gpio_random_dout_din.398432254 Jan 17 03:41:26 PM PST 24 Jan 17 03:41:29 PM PST 24 119906299 ps
T768 /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1928666102 Jan 17 03:39:57 PM PST 24 Jan 17 03:40:01 PM PST 24 88932885 ps
T769 /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3215694263 Jan 17 03:40:06 PM PST 24 Jan 17 03:40:15 PM PST 24 302444184 ps
T770 /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2023003746 Jan 17 03:40:05 PM PST 24 Jan 17 03:59:17 PM PST 24 379125850835 ps
T771 /workspace/coverage/default/7.gpio_filter_stress.227706728 Jan 17 03:40:00 PM PST 24 Jan 17 03:40:22 PM PST 24 6667970088 ps
T772 /workspace/coverage/default/46.gpio_rand_intr_trigger.810661017 Jan 17 03:42:13 PM PST 24 Jan 17 03:42:18 PM PST 24 384935730 ps
T773 /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.956687695 Jan 17 03:41:23 PM PST 24 Jan 17 03:41:25 PM PST 24 79597163 ps
T774 /workspace/coverage/default/44.gpio_rand_intr_trigger.109993170 Jan 17 03:42:08 PM PST 24 Jan 17 03:42:15 PM PST 24 246636191 ps
T775 /workspace/coverage/default/49.gpio_intr_rand_pgm.2763870240 Jan 17 03:42:35 PM PST 24 Jan 17 03:42:43 PM PST 24 51785249 ps
T776 /workspace/coverage/default/42.gpio_rand_intr_trigger.2894193830 Jan 17 03:42:11 PM PST 24 Jan 17 03:42:16 PM PST 24 401384932 ps
T777 /workspace/coverage/default/37.gpio_full_random.2725406897 Jan 17 03:41:44 PM PST 24 Jan 17 03:41:53 PM PST 24 231058664 ps
T778 /workspace/coverage/default/5.gpio_full_random.2168489110 Jan 17 03:39:59 PM PST 24 Jan 17 03:40:00 PM PST 24 74905569 ps
T779 /workspace/coverage/default/15.gpio_filter_stress.904087809 Jan 17 03:40:36 PM PST 24 Jan 17 03:40:52 PM PST 24 463479463 ps
T780 /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2569568117 Jan 17 03:41:34 PM PST 24 Jan 17 03:41:36 PM PST 24 46467599 ps
T781 /workspace/coverage/default/6.gpio_filter_stress.3991437419 Jan 17 03:39:57 PM PST 24 Jan 17 03:40:16 PM PST 24 1280042691 ps
T782 /workspace/coverage/default/46.gpio_random_dout_din.442018635 Jan 17 03:42:16 PM PST 24 Jan 17 03:42:18 PM PST 24 43515790 ps
T783 /workspace/coverage/default/11.gpio_alert_test.1805679198 Jan 17 03:40:17 PM PST 24 Jan 17 03:40:20 PM PST 24 26307682 ps
T784 /workspace/coverage/default/26.gpio_random_dout_din.1092848980 Jan 17 03:41:14 PM PST 24 Jan 17 03:41:17 PM PST 24 72787193 ps
T785 /workspace/coverage/default/20.gpio_random_dout_din.696603666 Jan 17 03:40:45 PM PST 24 Jan 17 03:40:50 PM PST 24 44509100 ps
T786 /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1713837183 Jan 17 03:39:55 PM PST 24 Jan 17 03:39:57 PM PST 24 191094295 ps
T787 /workspace/coverage/default/42.gpio_stress_all.3927880526 Jan 17 03:42:05 PM PST 24 Jan 17 03:42:28 PM PST 24 5698794241 ps
T788 /workspace/coverage/default/46.gpio_full_random.3740389201 Jan 17 03:42:13 PM PST 24 Jan 17 03:42:15 PM PST 24 32685965 ps
T789 /workspace/coverage/default/13.gpio_stress_all.3019460778 Jan 17 03:40:19 PM PST 24 Jan 17 03:41:32 PM PST 24 17992610589 ps
T790 /workspace/coverage/default/36.gpio_random_dout_din.3386396702 Jan 17 03:41:40 PM PST 24 Jan 17 03:41:51 PM PST 24 32600615 ps
T82 /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2114391590 Jan 17 03:42:05 PM PST 24 Jan 17 03:54:16 PM PST 24 25806911671 ps
T791 /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.611110072 Jan 17 03:41:11 PM PST 24 Jan 17 03:46:24 PM PST 24 34040956925 ps
T792 /workspace/coverage/default/37.gpio_filter_stress.1971215473 Jan 17 03:41:48 PM PST 24 Jan 17 03:42:19 PM PST 24 2287441283 ps
T793 /workspace/coverage/default/22.gpio_stress_all.3800604502 Jan 17 03:40:53 PM PST 24 Jan 17 03:42:28 PM PST 24 31176590356 ps
T794 /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.547107727 Jan 17 03:40:14 PM PST 24 Jan 17 03:54:00 PM PST 24 154931278811 ps
T795 /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2127825587 Jan 17 03:42:01 PM PST 24 Jan 17 03:42:05 PM PST 24 146616707 ps
T796 /workspace/coverage/default/46.gpio_alert_test.2925243598 Jan 17 03:42:26 PM PST 24 Jan 17 03:42:27 PM PST 24 29260664 ps
T797 /workspace/coverage/default/32.gpio_stress_all.1498541030 Jan 17 03:41:43 PM PST 24 Jan 17 03:42:48 PM PST 24 4515132627 ps
T798 /workspace/coverage/default/38.gpio_smoke.1228987418 Jan 17 03:41:45 PM PST 24 Jan 17 03:41:53 PM PST 24 84391354 ps
T799 /workspace/coverage/default/36.gpio_smoke.2184026979 Jan 17 03:41:46 PM PST 24 Jan 17 03:41:53 PM PST 24 61768349 ps
T800 /workspace/coverage/default/28.gpio_alert_test.539844599 Jan 17 03:41:20 PM PST 24 Jan 17 03:41:22 PM PST 24 30321551 ps
T801 /workspace/coverage/default/44.gpio_random_dout_din.3786898304 Jan 17 03:42:07 PM PST 24 Jan 17 03:42:13 PM PST 24 71313808 ps
T802 /workspace/coverage/default/40.gpio_stress_all.3111318582 Jan 17 03:41:58 PM PST 24 Jan 17 03:45:08 PM PST 24 26464388443 ps
T803 /workspace/coverage/default/8.gpio_intr_rand_pgm.240535800 Jan 17 03:40:06 PM PST 24 Jan 17 03:40:07 PM PST 24 25956893 ps
T804 /workspace/coverage/default/18.gpio_full_random.645834561 Jan 17 03:40:45 PM PST 24 Jan 17 03:40:50 PM PST 24 174810867 ps
T805 /workspace/coverage/default/22.gpio_alert_test.1344707069 Jan 17 03:41:01 PM PST 24 Jan 17 03:41:02 PM PST 24 13492933 ps
T806 /workspace/coverage/default/14.gpio_alert_test.3911510791 Jan 17 03:40:24 PM PST 24 Jan 17 03:40:26 PM PST 24 44650832 ps
T807 /workspace/coverage/default/38.gpio_intr_rand_pgm.2997713049 Jan 17 03:41:48 PM PST 24 Jan 17 03:41:53 PM PST 24 27431761 ps
T808 /workspace/coverage/default/14.gpio_intr_rand_pgm.2485724072 Jan 17 03:40:15 PM PST 24 Jan 17 03:40:21 PM PST 24 721938167 ps
T809 /workspace/coverage/default/27.gpio_random_dout_din.3394989422 Jan 17 03:41:16 PM PST 24 Jan 17 03:41:19 PM PST 24 418345003 ps
T810 /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2670778013 Jan 17 03:41:51 PM PST 24 Jan 17 04:10:11 PM PST 24 65824316268 ps
T811 /workspace/coverage/default/32.gpio_smoke.2148894901 Jan 17 03:41:26 PM PST 24 Jan 17 03:41:28 PM PST 24 40413548 ps
T812 /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1068777620 Jan 17 03:40:06 PM PST 24 Jan 17 03:48:05 PM PST 24 107187529541 ps
T813 /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.89680928 Jan 17 03:40:35 PM PST 24 Jan 17 03:40:39 PM PST 24 98781924 ps
T814 /workspace/coverage/default/37.gpio_alert_test.1167266670 Jan 17 03:41:41 PM PST 24 Jan 17 03:41:51 PM PST 24 27873301 ps
T815 /workspace/coverage/default/42.gpio_random_dout_din.1826428055 Jan 17 03:42:05 PM PST 24 Jan 17 03:42:09 PM PST 24 59915153 ps
T816 /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.279486221 Jan 17 03:39:31 PM PST 24 Jan 17 03:39:33 PM PST 24 36775020 ps
T817 /workspace/coverage/default/10.gpio_intr_rand_pgm.3273698219 Jan 17 03:40:05 PM PST 24 Jan 17 03:40:07 PM PST 24 301548926 ps
T818 /workspace/coverage/default/33.gpio_stress_all.1847017259 Jan 17 03:41:37 PM PST 24 Jan 17 03:43:02 PM PST 24 40793878212 ps
T819 /workspace/coverage/default/12.gpio_full_random.2312837020 Jan 17 03:40:18 PM PST 24 Jan 17 03:40:21 PM PST 24 263912947 ps
T820 /workspace/coverage/default/8.gpio_alert_test.1307768990 Jan 17 03:40:06 PM PST 24 Jan 17 03:40:10 PM PST 24 21373046 ps
T821 /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1228235950 Jan 17 03:42:16 PM PST 24 Jan 17 03:42:18 PM PST 24 39677375 ps
T822 /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1865897405 Jan 17 03:40:06 PM PST 24 Jan 17 03:45:10 PM PST 24 43396466169 ps
T823 /workspace/coverage/default/35.gpio_alert_test.2348085604 Jan 17 03:41:37 PM PST 24 Jan 17 03:41:42 PM PST 24 12132941 ps
T824 /workspace/coverage/default/1.gpio_full_random.2460613848 Jan 17 03:39:49 PM PST 24 Jan 17 03:39:53 PM PST 24 350954474 ps
T825 /workspace/coverage/default/15.gpio_rand_intr_trigger.4027220105 Jan 17 03:40:35 PM PST 24 Jan 17 03:40:39 PM PST 24 80268233 ps
T826 /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1085943859 Jan 17 03:40:21 PM PST 24 Jan 17 03:40:23 PM PST 24 92275386 ps
T827 /workspace/coverage/default/20.gpio_full_random.2193386726 Jan 17 03:40:53 PM PST 24 Jan 17 03:40:55 PM PST 24 150372011 ps
T828 /workspace/coverage/default/3.gpio_random_dout_din.2513498358 Jan 17 03:39:55 PM PST 24 Jan 17 03:39:56 PM PST 24 37580561 ps
T829 /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1360252871 Jan 17 03:39:53 PM PST 24 Jan 17 03:39:54 PM PST 24 33592205 ps
T830 /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1397756707 Jan 17 03:40:41 PM PST 24 Jan 17 03:48:24 PM PST 24 32231032995 ps
T831 /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.812226053 Jan 17 03:39:46 PM PST 24 Jan 17 03:39:51 PM PST 24 33055913 ps
T832 /workspace/coverage/default/10.gpio_alert_test.395844096 Jan 17 03:40:15 PM PST 24 Jan 17 03:40:20 PM PST 24 22546402 ps
T833 /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1507243369 Jan 17 03:41:16 PM PST 24 Jan 17 03:41:23 PM PST 24 101405021 ps
T834 /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4056775947 Jan 17 03:41:18 PM PST 24 Jan 17 04:20:15 PM PST 24 654300244733 ps
T835 /workspace/coverage/default/18.gpio_stress_all.92144999 Jan 17 03:40:49 PM PST 24 Jan 17 03:43:22 PM PST 24 20676667667 ps
T836 /workspace/coverage/default/1.gpio_stress_all.510514345 Jan 17 03:39:40 PM PST 24 Jan 17 03:40:22 PM PST 24 14366686604 ps
T837 /workspace/coverage/default/9.gpio_rand_intr_trigger.1213399324 Jan 17 03:40:06 PM PST 24 Jan 17 03:40:11 PM PST 24 134330313 ps
T838 /workspace/coverage/default/33.gpio_filter_stress.1980015824 Jan 17 03:41:39 PM PST 24 Jan 17 03:42:00 PM PST 24 922693358 ps
T839 /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3562568998 Jan 17 03:40:01 PM PST 24 Jan 17 03:40:03 PM PST 24 46534571 ps
T840 /workspace/coverage/default/39.gpio_filter_stress.1230028740 Jan 17 03:41:55 PM PST 24 Jan 17 03:42:06 PM PST 24 200944911 ps
T841 /workspace/coverage/default/45.gpio_intr_rand_pgm.2800375111 Jan 17 03:42:09 PM PST 24 Jan 17 03:42:13 PM PST 24 35148901 ps
T842 /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3229898663 Jan 17 03:42:05 PM PST 24 Jan 17 03:42:10 PM PST 24 70174633 ps
T843 /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3715034855 Jan 17 03:41:32 PM PST 24 Jan 17 03:41:33 PM PST 24 46325919 ps
T844 /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1240025461 Jan 17 03:40:14 PM PST 24 Jan 17 03:40:22 PM PST 24 62797965 ps
T845 /workspace/coverage/default/9.gpio_intr_rand_pgm.176937800 Jan 17 03:40:03 PM PST 24 Jan 17 03:40:05 PM PST 24 45637975 ps
T846 /workspace/coverage/default/38.gpio_alert_test.153692833 Jan 17 03:41:49 PM PST 24 Jan 17 03:41:53 PM PST 24 23522909 ps
T847 /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1694324475 Jan 17 03:41:20 PM PST 24 Jan 17 03:41:22 PM PST 24 69853057 ps
T848 /workspace/coverage/default/24.gpio_stress_all.2289059410 Jan 17 03:41:04 PM PST 24 Jan 17 03:43:57 PM PST 24 24328487497 ps
T849 /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1262455797 Jan 17 03:40:42 PM PST 24 Jan 17 03:40:50 PM PST 24 111248149 ps
T850 /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3627427604 Jan 17 03:39:47 PM PST 24 Jan 17 03:39:53 PM PST 24 101853334 ps
T851 /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4194324282 Jan 17 03:40:13 PM PST 24 Jan 17 03:40:20 PM PST 24 82866968 ps
T852 /workspace/coverage/default/24.gpio_rand_intr_trigger.2135406031 Jan 17 03:41:05 PM PST 24 Jan 17 03:41:10 PM PST 24 199380504 ps
T853 /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1225984395 Jan 17 03:39:40 PM PST 24 Jan 17 03:39:47 PM PST 24 42999677 ps
T854 /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.917122574 Jan 17 03:41:29 PM PST 24 Jan 17 03:41:30 PM PST 24 28834402 ps
T855 /workspace/coverage/default/27.gpio_smoke.2806924874 Jan 17 03:41:09 PM PST 24 Jan 17 03:41:17 PM PST 24 73260769 ps
T856 /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.218156695 Jan 17 03:42:08 PM PST 24 Jan 17 03:42:15 PM PST 24 277075718 ps
T857 /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3686897723 Jan 17 03:41:10 PM PST 24 Jan 17 03:41:18 PM PST 24 243734274 ps
T858 /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4056521695 Jan 17 03:42:29 PM PST 24 Jan 17 03:42:32 PM PST 24 107675565 ps
T859 /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.542844035 Jan 17 03:40:13 PM PST 24 Jan 17 03:40:20 PM PST 24 247673727 ps
T860 /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3551595419 Jan 17 03:41:24 PM PST 24 Jan 17 03:41:25 PM PST 24 23586263 ps
T861 /workspace/coverage/default/13.gpio_filter_stress.3364519197 Jan 17 03:40:22 PM PST 24 Jan 17 03:40:30 PM PST 24 236656953 ps
T862 /workspace/coverage/default/24.gpio_random_dout_din.3217922633 Jan 17 03:40:58 PM PST 24 Jan 17 03:40:59 PM PST 24 47789042 ps
T863 /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.326514796 Jan 17 03:39:47 PM PST 24 Jan 17 04:14:40 PM PST 24 163944479467 ps
T864 /workspace/coverage/default/4.gpio_smoke.4051904065 Jan 17 03:39:57 PM PST 24 Jan 17 03:39:59 PM PST 24 116790311 ps
T865 /workspace/coverage/default/25.gpio_alert_test.1435327766 Jan 17 03:41:13 PM PST 24 Jan 17 03:41:16 PM PST 24 31133006 ps
T866 /workspace/coverage/default/31.gpio_random_dout_din.3174810369 Jan 17 03:41:29 PM PST 24 Jan 17 03:41:31 PM PST 24 187310948 ps
T867 /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2235164248 Jan 17 03:42:08 PM PST 24 Jan 17 03:42:13 PM PST 24 84221873 ps
T868 /workspace/coverage/default/19.gpio_stress_all.4269619962 Jan 17 03:40:53 PM PST 24 Jan 17 03:43:25 PM PST 24 23817801757 ps
T869 /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1055114916 Jan 17 03:41:23 PM PST 24 Jan 17 03:41:24 PM PST 24 64620784 ps
T870 /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2336695185 Jan 17 03:42:09 PM PST 24 Jan 17 03:42:13 PM PST 24 25100775 ps
T871 /workspace/coverage/default/25.gpio_random_dout_din.3537626874 Jan 17 03:41:09 PM PST 24 Jan 17 03:41:16 PM PST 24 145498055 ps
T872 /workspace/coverage/default/29.gpio_stress_all.1537981250 Jan 17 03:41:13 PM PST 24 Jan 17 03:45:05 PM PST 24 15003531734 ps
T873 /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1449318394 Jan 17 03:40:06 PM PST 24 Jan 17 04:02:22 PM PST 24 118706123776 ps
T874 /workspace/coverage/default/28.gpio_intr_rand_pgm.2551213269 Jan 17 03:41:14 PM PST 24 Jan 17 03:41:17 PM PST 24 105573072 ps
T875 /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.174089310 Jan 17 03:41:34 PM PST 24 Jan 17 03:58:06 PM PST 24 54824665202 ps
T876 /workspace/coverage/default/13.gpio_random_dout_din.4220810782 Jan 17 03:40:16 PM PST 24 Jan 17 03:40:20 PM PST 24 87247119 ps
T877 /workspace/coverage/default/24.gpio_full_random.2748805934 Jan 17 03:41:04 PM PST 24 Jan 17 03:41:08 PM PST 24 65145714 ps
T878 /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.900867705 Jan 17 03:40:54 PM PST 24 Jan 17 04:10:55 PM PST 24 636870946856 ps
T879 /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1563397046 Jan 17 03:41:26 PM PST 24 Jan 17 04:15:23 PM PST 24 191722088789 ps
T880 /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2595187027 Jan 17 03:40:00 PM PST 24 Jan 17 03:40:02 PM PST 24 43445793 ps
T881 /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3577518593 Jan 17 03:41:38 PM PST 24 Jan 17 03:41:44 PM PST 24 33502046 ps
T882 /workspace/coverage/default/30.gpio_stress_all.3105243530 Jan 17 03:41:25 PM PST 24 Jan 17 03:42:48 PM PST 24 31151179294 ps
T883 /workspace/coverage/default/25.gpio_filter_stress.1721687307 Jan 17 03:41:15 PM PST 24 Jan 17 03:41:38 PM PST 24 2449238615 ps
T884 /workspace/coverage/cover_reg_top/24.gpio_intr_test.767167886 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:16 PM PST 24 17633744 ps
T885 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1470835393 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 37507629 ps
T886 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1256996180 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 195640098 ps
T887 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3118468891 Jan 17 12:33:53 PM PST 24 Jan 17 12:33:56 PM PST 24 59420890 ps
T888 /workspace/coverage/cover_reg_top/9.gpio_intr_test.960794068 Jan 17 12:34:03 PM PST 24 Jan 17 12:34:06 PM PST 24 35032203 ps
T889 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1356906938 Jan 17 12:34:21 PM PST 24 Jan 17 12:34:22 PM PST 24 31096614 ps
T890 /workspace/coverage/cover_reg_top/7.gpio_intr_test.673810444 Jan 17 12:33:53 PM PST 24 Jan 17 12:33:55 PM PST 24 24706032 ps
T891 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.586710276 Jan 17 12:34:12 PM PST 24 Jan 17 12:34:17 PM PST 24 132861646 ps
T892 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.494228054 Jan 17 12:34:11 PM PST 24 Jan 17 12:34:16 PM PST 24 12618344 ps
T893 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.267435003 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 17431563 ps
T894 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3170676027 Jan 17 12:34:09 PM PST 24 Jan 17 12:34:16 PM PST 24 15309191 ps
T895 /workspace/coverage/cover_reg_top/34.gpio_intr_test.4180256024 Jan 17 12:34:14 PM PST 24 Jan 17 12:34:17 PM PST 24 43333262 ps
T896 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3911080033 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 52793458 ps
T897 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3447764765 Jan 17 12:34:11 PM PST 24 Jan 17 12:34:16 PM PST 24 14306647 ps
T898 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3437170642 Jan 17 12:33:46 PM PST 24 Jan 17 12:33:47 PM PST 24 28547150 ps
T899 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2562823164 Jan 17 12:34:19 PM PST 24 Jan 17 12:34:21 PM PST 24 82505796 ps
T900 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1923957548 Jan 17 12:33:57 PM PST 24 Jan 17 12:33:58 PM PST 24 14237819 ps
T901 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1066057500 Jan 17 12:33:51 PM PST 24 Jan 17 12:33:54 PM PST 24 564370282 ps
T902 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.943946277 Jan 17 12:33:55 PM PST 24 Jan 17 12:33:58 PM PST 24 215758870 ps
T903 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3532737713 Jan 17 12:33:49 PM PST 24 Jan 17 12:33:54 PM PST 24 100409078 ps
T904 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2128159895 Jan 17 12:33:59 PM PST 24 Jan 17 12:34:01 PM PST 24 15102611 ps
T34 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1535325695 Jan 17 12:33:57 PM PST 24 Jan 17 12:33:59 PM PST 24 385478710 ps
T905 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1239100522 Jan 17 12:33:54 PM PST 24 Jan 17 12:33:56 PM PST 24 37413362 ps
T906 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.412406312 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:16 PM PST 24 47580955 ps
T907 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1030615413 Jan 17 12:34:06 PM PST 24 Jan 17 12:34:15 PM PST 24 95691399 ps
T908 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3927524427 Jan 17 12:33:45 PM PST 24 Jan 17 12:33:47 PM PST 24 138473572 ps
T909 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3719197141 Jan 17 12:33:55 PM PST 24 Jan 17 12:33:59 PM PST 24 323402167 ps
T96 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3290991529 Jan 17 12:34:05 PM PST 24 Jan 17 12:34:07 PM PST 24 50211383 ps
T910 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2734101414 Jan 17 12:34:06 PM PST 24 Jan 17 12:34:15 PM PST 24 495136595 ps
T911 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.830928779 Jan 17 12:33:55 PM PST 24 Jan 17 12:33:57 PM PST 24 21744797 ps
T912 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2675163551 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 40407949 ps
T83 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2794474147 Jan 17 12:33:48 PM PST 24 Jan 17 12:33:52 PM PST 24 33848163 ps
T913 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4064660564 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 160531594 ps
T914 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.409636673 Jan 17 12:33:46 PM PST 24 Jan 17 12:33:49 PM PST 24 13200425 ps
T915 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1616921344 Jan 17 12:34:07 PM PST 24 Jan 17 12:34:16 PM PST 24 14452889 ps
T916 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2602304487 Jan 17 12:34:02 PM PST 24 Jan 17 12:34:07 PM PST 24 144712459 ps
T917 /workspace/coverage/cover_reg_top/17.gpio_intr_test.731626577 Jan 17 12:34:03 PM PST 24 Jan 17 12:34:06 PM PST 24 11866445 ps
T84 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2765381907 Jan 17 12:33:55 PM PST 24 Jan 17 12:33:57 PM PST 24 42271638 ps
T918 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2971982702 Jan 17 12:34:19 PM PST 24 Jan 17 12:34:21 PM PST 24 27638520 ps
T919 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1664742697 Jan 17 12:33:56 PM PST 24 Jan 17 12:33:58 PM PST 24 97950927 ps
T920 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3909570316 Jan 17 12:33:53 PM PST 24 Jan 17 12:33:55 PM PST 24 110293852 ps
T921 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.719320569 Jan 17 12:33:37 PM PST 24 Jan 17 12:33:39 PM PST 24 20059800 ps
T922 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3709778143 Jan 17 12:34:06 PM PST 24 Jan 17 12:34:15 PM PST 24 23605254 ps
T923 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1899330787 Jan 17 12:34:18 PM PST 24 Jan 17 12:34:20 PM PST 24 55857148 ps
T924 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.830327619 Jan 17 12:33:50 PM PST 24 Jan 17 12:33:55 PM PST 24 258969477 ps
T925 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.401325326 Jan 17 12:33:45 PM PST 24 Jan 17 12:33:46 PM PST 24 54321367 ps
T926 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4017081082 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:17 PM PST 24 159875925 ps
T927 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3218270344 Jan 17 12:33:58 PM PST 24 Jan 17 12:33:59 PM PST 24 59083735 ps
T928 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1288229958 Jan 17 12:33:52 PM PST 24 Jan 17 12:33:54 PM PST 24 33166326 ps
T929 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3884438646 Jan 17 12:33:39 PM PST 24 Jan 17 12:33:41 PM PST 24 16042040 ps
T930 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1342044819 Jan 17 12:34:14 PM PST 24 Jan 17 12:34:19 PM PST 24 144304468 ps
T931 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2944532527 Jan 17 12:34:02 PM PST 24 Jan 17 12:34:06 PM PST 24 44490576 ps
T932 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2142735319 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:04 PM PST 24 18797600 ps
T933 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3226618041 Jan 17 12:34:04 PM PST 24 Jan 17 12:34:07 PM PST 24 13055439 ps
T934 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3856024265 Jan 17 12:33:46 PM PST 24 Jan 17 12:33:48 PM PST 24 63909644 ps
T935 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3977078447 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 29102409 ps
T936 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2860039701 Jan 17 12:34:05 PM PST 24 Jan 17 12:34:07 PM PST 24 15735186 ps
T937 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.792995767 Jan 17 12:33:47 PM PST 24 Jan 17 12:33:51 PM PST 24 25148470 ps
T938 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3061819948 Jan 17 12:34:02 PM PST 24 Jan 17 12:34:06 PM PST 24 47971377 ps
T939 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1529155973 Jan 17 12:33:57 PM PST 24 Jan 17 12:33:59 PM PST 24 217089649 ps
T85 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2626189209 Jan 17 12:34:06 PM PST 24 Jan 17 12:34:14 PM PST 24 54777780 ps
T940 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.392858930 Jan 17 12:33:56 PM PST 24 Jan 17 12:33:59 PM PST 24 96884536 ps
T941 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.118969371 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:17 PM PST 24 197040656 ps
T942 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.652476109 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 55905309 ps
T943 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3926885575 Jan 17 12:34:08 PM PST 24 Jan 17 12:34:16 PM PST 24 29679724 ps
T944 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.135293123 Jan 17 12:34:04 PM PST 24 Jan 17 12:34:07 PM PST 24 51036192 ps
T945 /workspace/coverage/cover_reg_top/44.gpio_intr_test.151850412 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:16 PM PST 24 13109558 ps
T946 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2026876910 Jan 17 12:34:05 PM PST 24 Jan 17 12:34:07 PM PST 24 56624293 ps
T35 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1213480291 Jan 17 12:34:02 PM PST 24 Jan 17 12:34:06 PM PST 24 375947931 ps
T947 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2285414217 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:16 PM PST 24 27412058 ps
T948 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3508070052 Jan 17 12:34:09 PM PST 24 Jan 17 12:34:16 PM PST 24 17460669 ps
T949 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1933346794 Jan 17 12:33:51 PM PST 24 Jan 17 12:33:54 PM PST 24 34905085 ps
T950 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1937149085 Jan 17 12:33:59 PM PST 24 Jan 17 12:34:03 PM PST 24 19415322 ps
T951 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2713665476 Jan 17 12:34:04 PM PST 24 Jan 17 12:34:07 PM PST 24 31002827 ps
T952 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3695626509 Jan 17 12:34:06 PM PST 24 Jan 17 12:34:15 PM PST 24 18471649 ps
T87 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3511108655 Jan 17 12:33:49 PM PST 24 Jan 17 12:33:53 PM PST 24 17560414 ps
T953 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.85808855 Jan 17 12:33:57 PM PST 24 Jan 17 12:33:58 PM PST 24 37595123 ps
T954 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2575750875 Jan 17 12:33:51 PM PST 24 Jan 17 12:33:53 PM PST 24 22660451 ps
T955 /workspace/coverage/cover_reg_top/0.gpio_intr_test.4157157012 Jan 17 12:33:38 PM PST 24 Jan 17 12:33:40 PM PST 24 36431986 ps
T956 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3428072410 Jan 17 12:34:00 PM PST 24 Jan 17 12:34:03 PM PST 24 36692129 ps
T957 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2586409649 Jan 17 12:33:53 PM PST 24 Jan 17 12:33:56 PM PST 24 684807850 ps
T958 /workspace/coverage/cover_reg_top/16.gpio_intr_test.492148928 Jan 17 12:34:02 PM PST 24 Jan 17 12:34:06 PM PST 24 11729932 ps
T959 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2094024673 Jan 17 12:34:00 PM PST 24 Jan 17 12:34:04 PM PST 24 44871795 ps
T960 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1590786209 Jan 17 12:33:54 PM PST 24 Jan 17 12:33:56 PM PST 24 23877832 ps
T961 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1331703406 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:06 PM PST 24 117277022 ps
T962 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4054076211 Jan 17 12:33:54 PM PST 24 Jan 17 12:33:56 PM PST 24 102695497 ps
T963 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2007375375 Jan 17 12:34:04 PM PST 24 Jan 17 12:34:07 PM PST 24 25404865 ps
T964 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3469657166 Jan 17 12:33:51 PM PST 24 Jan 17 12:33:56 PM PST 24 690733016 ps
T86 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1652614342 Jan 17 12:34:07 PM PST 24 Jan 17 12:34:18 PM PST 24 258408843 ps
T965 /workspace/coverage/cover_reg_top/49.gpio_intr_test.840606903 Jan 17 12:34:10 PM PST 24 Jan 17 12:34:16 PM PST 24 12074892 ps
T966 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1975578126 Jan 17 12:34:01 PM PST 24 Jan 17 12:34:05 PM PST 24 26671673 ps
T967 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4188540419 Jan 17 12:34:08 PM PST 24 Jan 17 12:34:16 PM PST 24 17025947 ps
T968 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.859316250 Jan 17 12:33:54 PM PST 24 Jan 17 12:33:57 PM PST 24 312696957 ps
T969 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1631432606 Jan 17 12:33:50 PM PST 24 Jan 17 12:33:53 PM PST 24 165759941 ps
T970 /workspace/coverage/cover_reg_top/47.gpio_intr_test.835899660 Jan 17 12:34:04 PM PST 24 Jan 17 12:34:06 PM PST 24 38761586 ps

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3430411278
Short name T15
Test name
Test status
Simulation time 782071323 ps
CPU time 1.38 seconds
Started Jan 17 12:33:56 PM PST 24
Finished Jan 17 12:33:58 PM PST 24
Peak memory 198228 kb
Host smart-6d7c8d32-1fde-4f57-b24b-710cfa907f76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430411278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3430411278
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3333292673
Short name T38
Test name
Test status
Simulation time 30183141 ps
CPU time 1.12 seconds
Started Jan 17 01:01:26 PM PST 24
Finished Jan 17 01:01:28 PM PST 24
Peak memory 197728 kb
Host smart-079f3bc2-c0d4-4454-8e46-fe3887c4574c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3333292673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3333292673
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2722023784
Short name T43
Test name
Test status
Simulation time 265435664 ps
CPU time 2.86 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:41 PM PST 24
Peak memory 196452 kb
Host smart-8cadb3e8-3d64-436d-a611-f6b0dd69d462
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722023784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2722023784
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1259249406
Short name T66
Test name
Test status
Simulation time 79217497709 ps
CPU time 439.24 seconds
Started Jan 17 03:41:21 PM PST 24
Finished Jan 17 03:48:41 PM PST 24
Peak memory 198384 kb
Host smart-1500a2c0-4ca1-4c68-9f1c-553e6248ae77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1259249406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1259249406
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1104400216
Short name T19
Test name
Test status
Simulation time 194545811 ps
CPU time 1.31 seconds
Started Jan 17 12:33:51 PM PST 24
Finished Jan 17 12:33:54 PM PST 24
Peak memory 198240 kb
Host smart-ceb57ca5-b4f4-45a3-8efb-4c1f431d59d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104400216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1104400216
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3333947723
Short name T2
Test name
Test status
Simulation time 553319228 ps
CPU time 0.86 seconds
Started Jan 17 12:33:53 PM PST 24
Finished Jan 17 12:33:55 PM PST 24
Peak memory 196408 kb
Host smart-033e316a-08c7-4b63-a3f8-61dd2cb8fb7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333947723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3333947723
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3877547003
Short name T97
Test name
Test status
Simulation time 11820042 ps
CPU time 0.61 seconds
Started Jan 17 12:34:09 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194020 kb
Host smart-176358d1-6a7d-46d2-9d4a-ff45b5e226bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877547003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3877547003
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2144658719
Short name T101
Test name
Test status
Simulation time 33058758 ps
CPU time 0.95 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 198156 kb
Host smart-66898b09-e782-4395-92ea-48f9b7dd4f98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144658719 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2144658719
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3082803861
Short name T55
Test name
Test status
Simulation time 384899297 ps
CPU time 0.94 seconds
Started Jan 17 03:39:41 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 214688 kb
Host smart-abd17b8d-c213-4b5a-bced-4160c33db59b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082803861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3082803861
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3303262657
Short name T28
Test name
Test status
Simulation time 1453210311 ps
CPU time 2.01 seconds
Started Jan 17 12:34:00 PM PST 24
Finished Jan 17 12:34:04 PM PST 24
Peak memory 198312 kb
Host smart-54ab6b63-28f3-419e-a65e-1940716bf199
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303262657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3303262657
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2061069374
Short name T133
Test name
Test status
Simulation time 91425152 ps
CPU time 1.35 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196688 kb
Host smart-103a1569-c793-4d9d-8385-9c40800de9cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2061069374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2061069374
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/12.gpio_alert_test.953270604
Short name T353
Test name
Test status
Simulation time 11577012 ps
CPU time 0.56 seconds
Started Jan 17 03:40:16 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 194068 kb
Host smart-abe820d3-6c0d-4499-a9dd-3101dfe3a94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953270604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.953270604
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2618663943
Short name T91
Test name
Test status
Simulation time 90683970 ps
CPU time 0.84 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 197216 kb
Host smart-9ceec695-237d-4f05-afeb-f5a53de6b6bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618663943 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2618663943
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1611453704
Short name T33
Test name
Test status
Simulation time 401317325 ps
CPU time 1.47 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 198536 kb
Host smart-237c56d2-ef00-4b09-a03e-3828595f9748
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611453704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1611453704
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.359543064
Short name T17
Test name
Test status
Simulation time 38465822 ps
CPU time 1.81 seconds
Started Jan 17 12:33:43 PM PST 24
Finished Jan 17 12:33:45 PM PST 24
Peak memory 198300 kb
Host smart-591ff1ce-b43c-4d20-ae21-765f296e90b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359543064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.359543064
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2751019866
Short name T21
Test name
Test status
Simulation time 12943901 ps
CPU time 0.63 seconds
Started Jan 17 12:34:00 PM PST 24
Finished Jan 17 12:34:03 PM PST 24
Peak memory 194508 kb
Host smart-ee35b426-c919-4b73-aba2-ebdd8923ff79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751019866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2751019866
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4169061483
Short name T93
Test name
Test status
Simulation time 79697875 ps
CPU time 0.73 seconds
Started Jan 17 12:33:52 PM PST 24
Finished Jan 17 12:33:54 PM PST 24
Peak memory 195224 kb
Host smart-f4ff129c-3fca-4fa9-852b-e401696dc3cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169061483 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4169061483
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.980096121
Short name T1
Test name
Test status
Simulation time 96129547 ps
CPU time 0.86 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 198104 kb
Host smart-31174353-534b-433b-bc26-24874ca09ba9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980096121 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.980096121
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.195867818
Short name T79
Test name
Test status
Simulation time 13178922 ps
CPU time 0.64 seconds
Started Jan 17 12:33:45 PM PST 24
Finished Jan 17 12:33:46 PM PST 24
Peak memory 194984 kb
Host smart-440a523a-7e07-4c51-a511-f792c2bd9ad2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195867818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.195867818
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3469657166
Short name T964
Test name
Test status
Simulation time 690733016 ps
CPU time 2.91 seconds
Started Jan 17 12:33:51 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 197296 kb
Host smart-f41049d3-10a1-41f8-bada-43ae921fed76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469657166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3469657166
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.621133946
Short name T30
Test name
Test status
Simulation time 47460882 ps
CPU time 0.65 seconds
Started Jan 17 12:33:41 PM PST 24
Finished Jan 17 12:33:42 PM PST 24
Peak memory 194852 kb
Host smart-21c8701d-d0d2-461c-8448-2699abcca0ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621133946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.621133946
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.792995767
Short name T937
Test name
Test status
Simulation time 25148470 ps
CPU time 0.85 seconds
Started Jan 17 12:33:47 PM PST 24
Finished Jan 17 12:33:51 PM PST 24
Peak memory 198124 kb
Host smart-f7a57c7a-bb74-452b-92c9-a4851931872b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792995767 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.792995767
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.696615076
Short name T18
Test name
Test status
Simulation time 34379902 ps
CPU time 0.57 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 193548 kb
Host smart-eb0b26d6-40fd-4121-aefb-7c83f679afec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696615076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.696615076
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.4157157012
Short name T955
Test name
Test status
Simulation time 36431986 ps
CPU time 0.57 seconds
Started Jan 17 12:33:38 PM PST 24
Finished Jan 17 12:33:40 PM PST 24
Peak memory 194516 kb
Host smart-22fb25cb-41ce-4dcf-b786-374822312f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157157012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.4157157012
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.719320569
Short name T921
Test name
Test status
Simulation time 20059800 ps
CPU time 0.79 seconds
Started Jan 17 12:33:37 PM PST 24
Finished Jan 17 12:33:39 PM PST 24
Peak memory 197124 kb
Host smart-52ce5aee-1db3-463e-bc1c-c085f9cfbf2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719320569 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.719320569
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.830327619
Short name T924
Test name
Test status
Simulation time 258969477 ps
CPU time 2.59 seconds
Started Jan 17 12:33:50 PM PST 24
Finished Jan 17 12:33:55 PM PST 24
Peak memory 198344 kb
Host smart-d6af9e42-be1b-4198-b8f2-e31c577e979b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830327619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.830327619
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.480805904
Short name T7
Test name
Test status
Simulation time 443189051 ps
CPU time 0.88 seconds
Started Jan 17 12:33:39 PM PST 24
Finished Jan 17 12:33:41 PM PST 24
Peak memory 197344 kb
Host smart-ec221a8a-07a6-4551-9572-dc37795d11eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480805904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.480805904
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1933346794
Short name T949
Test name
Test status
Simulation time 34905085 ps
CPU time 0.65 seconds
Started Jan 17 12:33:51 PM PST 24
Finished Jan 17 12:33:54 PM PST 24
Peak memory 194516 kb
Host smart-aae26efe-5d87-4caa-9602-36d1df4981e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933346794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1933346794
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.563165007
Short name T121
Test name
Test status
Simulation time 103171995 ps
CPU time 2.11 seconds
Started Jan 17 12:33:43 PM PST 24
Finished Jan 17 12:33:46 PM PST 24
Peak memory 196604 kb
Host smart-95fc5d35-6bc2-4a4d-b46f-00bd64d2587d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563165007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.563165007
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.67018719
Short name T31
Test name
Test status
Simulation time 79085338 ps
CPU time 0.64 seconds
Started Jan 17 12:33:50 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 194812 kb
Host smart-ed730e4a-28a3-4c74-9784-12baf20b2bc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67018719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.67018719
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3927524427
Short name T908
Test name
Test status
Simulation time 138473572 ps
CPU time 0.95 seconds
Started Jan 17 12:33:45 PM PST 24
Finished Jan 17 12:33:47 PM PST 24
Peak memory 198088 kb
Host smart-b12074b3-6f0b-472a-8bd3-9db96300ba94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927524427 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3927524427
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.546022143
Short name T114
Test name
Test status
Simulation time 34760892 ps
CPU time 0.6 seconds
Started Jan 17 12:33:47 PM PST 24
Finished Jan 17 12:33:51 PM PST 24
Peak memory 195296 kb
Host smart-da1ace0c-a39d-4517-b5f7-fc846b392e0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546022143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.546022143
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.80925664
Short name T23
Test name
Test status
Simulation time 23165999 ps
CPU time 0.58 seconds
Started Jan 17 12:33:45 PM PST 24
Finished Jan 17 12:33:47 PM PST 24
Peak memory 193844 kb
Host smart-0e795158-4e90-449e-8623-f9fb5594794a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80925664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.80925664
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.401325326
Short name T925
Test name
Test status
Simulation time 54321367 ps
CPU time 0.76 seconds
Started Jan 17 12:33:45 PM PST 24
Finished Jan 17 12:33:46 PM PST 24
Peak memory 195648 kb
Host smart-99e87343-1907-43d6-96de-0153ea07c4ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401325326 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.401325326
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2886218988
Short name T36
Test name
Test status
Simulation time 141626528 ps
CPU time 1.15 seconds
Started Jan 17 12:33:47 PM PST 24
Finished Jan 17 12:33:51 PM PST 24
Peak memory 198248 kb
Host smart-d3f952ca-d5f5-49a3-ba20-b16ee7bfba60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886218988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2886218988
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4188540419
Short name T967
Test name
Test status
Simulation time 17025947 ps
CPU time 0.92 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 197956 kb
Host smart-9e70b0e3-bd23-4171-b644-04595b4b5149
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188540419 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4188540419
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1937149085
Short name T950
Test name
Test status
Simulation time 19415322 ps
CPU time 0.67 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:03 PM PST 24
Peak memory 194812 kb
Host smart-00e50a7e-f4fd-4b58-a4bf-5d3728a99379
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937149085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1937149085
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3532737713
Short name T903
Test name
Test status
Simulation time 100409078 ps
CPU time 2.3 seconds
Started Jan 17 12:33:49 PM PST 24
Finished Jan 17 12:33:54 PM PST 24
Peak memory 198296 kb
Host smart-d97da23b-d237-4eee-abdb-58faa7128802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532737713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3532737713
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2714835272
Short name T119
Test name
Test status
Simulation time 54879713 ps
CPU time 0.9 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:03 PM PST 24
Peak memory 197136 kb
Host smart-433b6bc1-6da2-4fd0-a678-a001689709be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714835272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2714835272
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.494228054
Short name T892
Test name
Test status
Simulation time 12618344 ps
CPU time 0.61 seconds
Started Jan 17 12:34:11 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194792 kb
Host smart-1b9ce0a8-2d19-45e6-a9b4-84701aba4161
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494228054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.494228054
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2708327249
Short name T120
Test name
Test status
Simulation time 17162127 ps
CPU time 0.6 seconds
Started Jan 17 12:33:58 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 193928 kb
Host smart-5e64e103-33ca-4d6e-8cca-5f12eb9140ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708327249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2708327249
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2529159138
Short name T75
Test name
Test status
Simulation time 29487225 ps
CPU time 0.77 seconds
Started Jan 17 12:33:58 PM PST 24
Finished Jan 17 12:34:00 PM PST 24
Peak memory 196896 kb
Host smart-c5fd7446-ecc5-45aa-bf6d-d821f69826af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529159138 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2529159138
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1331703406
Short name T961
Test name
Test status
Simulation time 117277022 ps
CPU time 2.24 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 198300 kb
Host smart-3f427f70-a3e5-45b1-9323-5678414304c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331703406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1331703406
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3962621121
Short name T99
Test name
Test status
Simulation time 117191165 ps
CPU time 1.07 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 197968 kb
Host smart-f635915d-5dd0-44b1-b685-66b7645101fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962621121 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3962621121
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.503110166
Short name T20
Test name
Test status
Simulation time 12956258 ps
CPU time 0.6 seconds
Started Jan 17 12:34:09 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 195344 kb
Host smart-670e00ae-7faf-411f-b5d5-943e7ea4d468
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503110166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.503110166
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1923957548
Short name T900
Test name
Test status
Simulation time 14237819 ps
CPU time 0.58 seconds
Started Jan 17 12:33:57 PM PST 24
Finished Jan 17 12:33:58 PM PST 24
Peak memory 193892 kb
Host smart-de8c1024-44bd-47b7-9c6b-a43e308a938c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923957548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1923957548
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.392858930
Short name T940
Test name
Test status
Simulation time 96884536 ps
CPU time 1.16 seconds
Started Jan 17 12:33:56 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 198348 kb
Host smart-6071d85c-5ef6-4b3f-b2ce-25862f9efc4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392858930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.392858930
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1535325695
Short name T34
Test name
Test status
Simulation time 385478710 ps
CPU time 1.43 seconds
Started Jan 17 12:33:57 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 198244 kb
Host smart-11b74dfb-e2c9-4069-9aaf-c2f6c02c1c1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535325695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1535325695
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2713665476
Short name T951
Test name
Test status
Simulation time 31002827 ps
CPU time 0.67 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 197020 kb
Host smart-ac8f21a5-2aa1-4030-b292-af776de6fc91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713665476 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2713665476
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2731614099
Short name T77
Test name
Test status
Simulation time 37547786 ps
CPU time 0.63 seconds
Started Jan 17 12:33:53 PM PST 24
Finished Jan 17 12:33:55 PM PST 24
Peak memory 194772 kb
Host smart-ca6c00f0-d526-47b8-93d0-992c46f815f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731614099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2731614099
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2549652006
Short name T109
Test name
Test status
Simulation time 57424493 ps
CPU time 0.57 seconds
Started Jan 17 12:33:50 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 193920 kb
Host smart-d909cc13-7812-4dcf-8e1b-b0cd1779c2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549652006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2549652006
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2166605539
Short name T90
Test name
Test status
Simulation time 17111808 ps
CPU time 0.78 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:03 PM PST 24
Peak memory 197160 kb
Host smart-97606b28-1399-4cd4-96dc-5d942e521aed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166605539 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2166605539
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3529177326
Short name T117
Test name
Test status
Simulation time 366248622 ps
CPU time 2.02 seconds
Started Jan 17 12:34:06 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 198244 kb
Host smart-a9304811-4475-453d-affb-7f2edd9ecc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529177326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3529177326
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3290991529
Short name T96
Test name
Test status
Simulation time 50211383 ps
CPU time 0.88 seconds
Started Jan 17 12:34:05 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 197352 kb
Host smart-ef6098ff-82b0-4cb9-80e4-eba6a9de9360
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290991529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3290991529
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1897395722
Short name T16
Test name
Test status
Simulation time 19155226 ps
CPU time 0.69 seconds
Started Jan 17 12:34:15 PM PST 24
Finished Jan 17 12:34:20 PM PST 24
Peak memory 198052 kb
Host smart-366b47fe-b68f-4c4b-becb-5e6ef19446b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897395722 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1897395722
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2626189209
Short name T85
Test name
Test status
Simulation time 54777780 ps
CPU time 0.6 seconds
Started Jan 17 12:34:06 PM PST 24
Finished Jan 17 12:34:14 PM PST 24
Peak memory 195288 kb
Host smart-d9eb4b41-84d4-452a-9ef8-3f063ffcd49f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626189209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2626189209
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1975578126
Short name T966
Test name
Test status
Simulation time 26671673 ps
CPU time 0.67 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 194540 kb
Host smart-b6b47613-8ce9-45cb-b19d-beb10dce2462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975578126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1975578126
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4054076211
Short name T962
Test name
Test status
Simulation time 102695497 ps
CPU time 0.65 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 195040 kb
Host smart-b4f3e99a-6f40-4578-b603-71f48b829e5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054076211 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4054076211
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1365144569
Short name T118
Test name
Test status
Simulation time 44520499 ps
CPU time 2.24 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 198220 kb
Host smart-9361e14b-d49f-4dcc-a0aa-bd6f568f8682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365144569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1365144569
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1342044819
Short name T930
Test name
Test status
Simulation time 144304468 ps
CPU time 0.84 seconds
Started Jan 17 12:34:14 PM PST 24
Finished Jan 17 12:34:19 PM PST 24
Peak memory 197896 kb
Host smart-15448016-d0fc-4952-adb3-f6fd36443315
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342044819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1342044819
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2094024673
Short name T959
Test name
Test status
Simulation time 44871795 ps
CPU time 0.74 seconds
Started Jan 17 12:34:00 PM PST 24
Finished Jan 17 12:34:04 PM PST 24
Peak memory 198068 kb
Host smart-71ee6d58-849a-4441-9ab0-941f27cfdafb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094024673 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2094024673
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2971982702
Short name T918
Test name
Test status
Simulation time 27638520 ps
CPU time 0.61 seconds
Started Jan 17 12:34:19 PM PST 24
Finished Jan 17 12:34:21 PM PST 24
Peak memory 194964 kb
Host smart-1bcb6c48-84e6-4376-a809-2f0dba3b6800
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971982702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2971982702
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.565999357
Short name T80
Test name
Test status
Simulation time 29423874 ps
CPU time 0.56 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 193956 kb
Host smart-63932296-6cc2-4b4e-9278-f7b083645428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565999357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.565999357
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2562823164
Short name T899
Test name
Test status
Simulation time 82505796 ps
CPU time 0.71 seconds
Started Jan 17 12:34:19 PM PST 24
Finished Jan 17 12:34:21 PM PST 24
Peak memory 196348 kb
Host smart-b2c95c0b-2ea9-450c-a388-ce23a9bd643d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562823164 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2562823164
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1780993907
Short name T29
Test name
Test status
Simulation time 56227258 ps
CPU time 2.71 seconds
Started Jan 17 12:34:00 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 198352 kb
Host smart-bd6ff238-9b49-49c4-bd0f-fb839edcb39d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780993907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1780993907
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4064660564
Short name T913
Test name
Test status
Simulation time 160531594 ps
CPU time 0.89 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 197408 kb
Host smart-2e8d2c71-3d55-4f31-aaf9-0775b78a78a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064660564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.4064660564
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2734101414
Short name T910
Test name
Test status
Simulation time 495136595 ps
CPU time 1.01 seconds
Started Jan 17 12:34:06 PM PST 24
Finished Jan 17 12:34:15 PM PST 24
Peak memory 198144 kb
Host smart-5f1735c3-1e66-4061-a982-06b3fee39e9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734101414 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2734101414
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.85808855
Short name T953
Test name
Test status
Simulation time 37595123 ps
CPU time 0.59 seconds
Started Jan 17 12:33:57 PM PST 24
Finished Jan 17 12:33:58 PM PST 24
Peak memory 194896 kb
Host smart-540eded4-14b5-4264-8522-3ffe419d21f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85808855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_
csr_rw.85808855
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.492148928
Short name T958
Test name
Test status
Simulation time 11729932 ps
CPU time 0.56 seconds
Started Jan 17 12:34:02 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 194552 kb
Host smart-9b13c01f-ecf1-4450-8465-cca073d6fcac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492148928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.492148928
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4003347692
Short name T89
Test name
Test status
Simulation time 72262638 ps
CPU time 0.87 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:01 PM PST 24
Peak memory 197256 kb
Host smart-80e7aac4-2a49-44d5-98f4-cc3e0866a4d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003347692 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4003347692
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3215454894
Short name T100
Test name
Test status
Simulation time 263006248 ps
CPU time 0.85 seconds
Started Jan 17 12:34:18 PM PST 24
Finished Jan 17 12:34:20 PM PST 24
Peak memory 198004 kb
Host smart-304ef324-2d78-4e0a-b728-cfa856c0b14f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215454894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3215454894
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.769298851
Short name T71
Test name
Test status
Simulation time 19742375 ps
CPU time 0.7 seconds
Started Jan 17 12:34:14 PM PST 24
Finished Jan 17 12:34:18 PM PST 24
Peak memory 197872 kb
Host smart-1e83161e-768e-438b-a170-ffe72e0eaac5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769298851 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.769298851
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3975040992
Short name T78
Test name
Test status
Simulation time 27633899 ps
CPU time 0.57 seconds
Started Jan 17 12:34:22 PM PST 24
Finished Jan 17 12:34:23 PM PST 24
Peak memory 194748 kb
Host smart-4b8b67b9-4e5b-4e04-a578-b6de6b7b4104
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975040992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3975040992
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.731626577
Short name T917
Test name
Test status
Simulation time 11866445 ps
CPU time 0.65 seconds
Started Jan 17 12:34:03 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 194628 kb
Host smart-7ac96a2a-1ae2-4f56-ba26-1bea2c46fba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731626577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.731626577
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3911080033
Short name T896
Test name
Test status
Simulation time 52793458 ps
CPU time 0.74 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 195244 kb
Host smart-3a785e3e-189a-4d59-939f-107bfe752fd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911080033 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3911080033
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1115591762
Short name T6
Test name
Test status
Simulation time 111379736 ps
CPU time 1.32 seconds
Started Jan 17 12:34:02 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 198300 kb
Host smart-988ca153-fb3d-4de0-b2ef-b221d7c15fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115591762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1115591762
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1213480291
Short name T35
Test name
Test status
Simulation time 375947931 ps
CPU time 1.33 seconds
Started Jan 17 12:34:02 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 198188 kb
Host smart-5d90c052-d323-489f-be6d-e958d87c24b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213480291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1213480291
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2675163551
Short name T912
Test name
Test status
Simulation time 40407949 ps
CPU time 1.08 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 198128 kb
Host smart-b50b62a7-ce9a-44ce-b955-211f03e722b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675163551 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2675163551
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1256996180
Short name T886
Test name
Test status
Simulation time 195640098 ps
CPU time 0.66 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 194936 kb
Host smart-b9138200-3989-426a-9fde-c90c14bab8ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256996180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1256996180
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2285414217
Short name T947
Test name
Test status
Simulation time 27412058 ps
CPU time 0.6 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193992 kb
Host smart-137ee9ed-366d-44cf-ac69-12cd42170b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285414217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2285414217
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.135293123
Short name T944
Test name
Test status
Simulation time 51036192 ps
CPU time 0.59 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 194544 kb
Host smart-13877e94-b3a2-45fe-859c-464861bc1a26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135293123 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.135293123
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.118969371
Short name T941
Test name
Test status
Simulation time 197040656 ps
CPU time 1.55 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:17 PM PST 24
Peak memory 198304 kb
Host smart-59f1a94a-c170-4b44-b6d8-c94726f62c11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118969371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.118969371
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4017081082
Short name T926
Test name
Test status
Simulation time 159875925 ps
CPU time 1.44 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:17 PM PST 24
Peak memory 198264 kb
Host smart-c91943d5-6777-402e-82aa-9d3cf396de8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017081082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.4017081082
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3977078447
Short name T935
Test name
Test status
Simulation time 29102409 ps
CPU time 0.92 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 198128 kb
Host smart-8f8dfcf5-b3cb-4fee-a78b-bd000630324f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977078447 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3977078447
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.412406312
Short name T906
Test name
Test status
Simulation time 47580955 ps
CPU time 0.64 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 195140 kb
Host smart-51b9c4a6-9014-4ed9-9693-12dc693f7cf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412406312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.412406312
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3926885575
Short name T943
Test name
Test status
Simulation time 29679724 ps
CPU time 0.6 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194484 kb
Host smart-f500b6de-b0e8-421e-8336-b361d3f4ff34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926885575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3926885575
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.267435003
Short name T893
Test name
Test status
Simulation time 17431563 ps
CPU time 0.65 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 194960 kb
Host smart-54deab82-da72-4859-a4e2-5b29974e98d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267435003 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.267435003
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.603007966
Short name T73
Test name
Test status
Simulation time 309364222 ps
CPU time 1.9 seconds
Started Jan 17 12:34:19 PM PST 24
Finished Jan 17 12:34:22 PM PST 24
Peak memory 198428 kb
Host smart-a943cc2a-af43-4804-9c54-a0c40d4838ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603007966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.603007966
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3630923040
Short name T14
Test name
Test status
Simulation time 260984298 ps
CPU time 0.88 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:01 PM PST 24
Peak memory 198000 kb
Host smart-93a9843e-5a5e-4607-83a9-4bba71272c8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630923040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3630923040
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3385851555
Short name T3
Test name
Test status
Simulation time 527622507 ps
CPU time 2.52 seconds
Started Jan 17 12:33:46 PM PST 24
Finished Jan 17 12:33:52 PM PST 24
Peak memory 197204 kb
Host smart-3e349894-6f62-42f8-b66f-204f46595237
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385851555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3385851555
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1239100522
Short name T905
Test name
Test status
Simulation time 37413362 ps
CPU time 0.59 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 195440 kb
Host smart-cf2769cb-6b56-4a22-920f-b7f8964b5af9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239100522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1239100522
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3685792630
Short name T9
Test name
Test status
Simulation time 61220329 ps
CPU time 0.74 seconds
Started Jan 17 12:33:49 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 198060 kb
Host smart-cb7d0f82-d85c-4f50-a971-723642870ccd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685792630 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3685792630
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.830928779
Short name T911
Test name
Test status
Simulation time 21744797 ps
CPU time 0.59 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 194900 kb
Host smart-1c52e894-15dd-4a1a-ad75-aaa033526d84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830928779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.830928779
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.288069188
Short name T106
Test name
Test status
Simulation time 45415737 ps
CPU time 0.64 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 194212 kb
Host smart-2e079e15-7f35-425d-9e94-2d1736c846c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288069188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.288069188
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1631432606
Short name T969
Test name
Test status
Simulation time 165759941 ps
CPU time 0.85 seconds
Started Jan 17 12:33:50 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 197036 kb
Host smart-295be955-d27e-4ae1-bf97-5ffaa654d565
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631432606 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1631432606
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1558045745
Short name T110
Test name
Test status
Simulation time 245887139 ps
CPU time 1.25 seconds
Started Jan 17 12:33:42 PM PST 24
Finished Jan 17 12:33:44 PM PST 24
Peak memory 198368 kb
Host smart-116f067e-9ab9-473b-bf1f-76217eec3254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558045745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1558045745
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1991181311
Short name T4
Test name
Test status
Simulation time 89341441 ps
CPU time 1.18 seconds
Started Jan 17 12:33:36 PM PST 24
Finished Jan 17 12:33:39 PM PST 24
Peak memory 198260 kb
Host smart-9158a7a5-42ce-4784-ba9d-4eef612983a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991181311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1991181311
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.864743093
Short name T108
Test name
Test status
Simulation time 55707345 ps
CPU time 0.6 seconds
Started Jan 17 12:34:09 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193912 kb
Host smart-e978209c-0534-4f30-b8e0-8f4c10fe055f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864743093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.864743093
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1356906938
Short name T889
Test name
Test status
Simulation time 31096614 ps
CPU time 0.57 seconds
Started Jan 17 12:34:21 PM PST 24
Finished Jan 17 12:34:22 PM PST 24
Peak memory 193808 kb
Host smart-83b8f549-ef51-4236-97aa-3accfa34ac78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356906938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1356906938
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3061819948
Short name T938
Test name
Test status
Simulation time 47971377 ps
CPU time 0.59 seconds
Started Jan 17 12:34:02 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 194588 kb
Host smart-d3ab32cd-268d-4c09-b777-48bc742f427f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061819948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3061819948
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3709778143
Short name T922
Test name
Test status
Simulation time 23605254 ps
CPU time 0.62 seconds
Started Jan 17 12:34:06 PM PST 24
Finished Jan 17 12:34:15 PM PST 24
Peak memory 193972 kb
Host smart-54883465-e7e3-48df-b356-d328f9c49ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709778143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3709778143
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.767167886
Short name T884
Test name
Test status
Simulation time 17633744 ps
CPU time 0.62 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194716 kb
Host smart-d1480e20-b19d-460a-978d-928cc3a07a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767167886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.767167886
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3447764765
Short name T897
Test name
Test status
Simulation time 14306647 ps
CPU time 0.6 seconds
Started Jan 17 12:34:11 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194620 kb
Host smart-6df443b8-7528-4161-9ed6-c0915f98d072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447764765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3447764765
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1078093899
Short name T105
Test name
Test status
Simulation time 33801673 ps
CPU time 0.6 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 193896 kb
Host smart-0582f2ec-2b94-4fe5-8ee0-49a268f82fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078093899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1078093899
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1470835393
Short name T885
Test name
Test status
Simulation time 37507629 ps
CPU time 0.65 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 194068 kb
Host smart-e21b4488-8a1e-418c-b24e-7b3b3393e072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470835393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1470835393
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1899330787
Short name T923
Test name
Test status
Simulation time 55857148 ps
CPU time 0.56 seconds
Started Jan 17 12:34:18 PM PST 24
Finished Jan 17 12:34:20 PM PST 24
Peak memory 193840 kb
Host smart-b7c64619-e183-44a9-8edf-8176ecce9622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899330787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1899330787
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3437170642
Short name T898
Test name
Test status
Simulation time 28547150 ps
CPU time 0.65 seconds
Started Jan 17 12:33:46 PM PST 24
Finished Jan 17 12:33:47 PM PST 24
Peak memory 194788 kb
Host smart-aa547e7b-cbae-4efd-89b2-b73aba979175
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437170642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3437170642
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3118468891
Short name T887
Test name
Test status
Simulation time 59420890 ps
CPU time 2.15 seconds
Started Jan 17 12:33:53 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 197180 kb
Host smart-8100824f-12d0-4670-b491-d404e8b4583f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118468891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3118468891
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3884438646
Short name T929
Test name
Test status
Simulation time 16042040 ps
CPU time 0.63 seconds
Started Jan 17 12:33:39 PM PST 24
Finished Jan 17 12:33:41 PM PST 24
Peak memory 194764 kb
Host smart-94ba6aec-e613-4633-8503-b9299a705d19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884438646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3884438646
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.558256974
Short name T27
Test name
Test status
Simulation time 22734319 ps
CPU time 0.75 seconds
Started Jan 17 12:33:42 PM PST 24
Finished Jan 17 12:33:44 PM PST 24
Peak memory 198160 kb
Host smart-63b70571-98d3-4035-be3d-ffcd6157c951
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558256974 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.558256974
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3990491589
Short name T76
Test name
Test status
Simulation time 27781612 ps
CPU time 0.61 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 195780 kb
Host smart-95d098c8-7fef-4b3c-bf85-490aec818494
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990491589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3990491589
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1288229958
Short name T928
Test name
Test status
Simulation time 33166326 ps
CPU time 0.61 seconds
Started Jan 17 12:33:52 PM PST 24
Finished Jan 17 12:33:54 PM PST 24
Peak memory 193936 kb
Host smart-3af3d44b-f47b-483b-ba1b-d2395cc10b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288229958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1288229958
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2972960806
Short name T92
Test name
Test status
Simulation time 31565647 ps
CPU time 0.75 seconds
Started Jan 17 12:33:40 PM PST 24
Finished Jan 17 12:33:41 PM PST 24
Peak memory 196620 kb
Host smart-186a8028-88d0-4f39-8f98-939abf88e4a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972960806 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2972960806
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2586409649
Short name T957
Test name
Test status
Simulation time 684807850 ps
CPU time 1.61 seconds
Started Jan 17 12:33:53 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 198384 kb
Host smart-45f9b04f-e15c-4e6c-8c7d-d1fdddccf7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586409649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2586409649
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.859316250
Short name T968
Test name
Test status
Simulation time 312696957 ps
CPU time 1.41 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 198236 kb
Host smart-6cbdb6f6-e23e-410c-98b6-e025b2075cc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859316250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.859316250
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.108058399
Short name T81
Test name
Test status
Simulation time 42642451 ps
CPU time 0.55 seconds
Started Jan 17 12:34:20 PM PST 24
Finished Jan 17 12:34:22 PM PST 24
Peak memory 194544 kb
Host smart-304e5d50-a9d3-4367-99ba-c5be088e41ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108058399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.108058399
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2860039701
Short name T936
Test name
Test status
Simulation time 15735186 ps
CPU time 0.62 seconds
Started Jan 17 12:34:05 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 194640 kb
Host smart-ecdbba1f-4d55-4a94-9c8f-f1ec5662a441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860039701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2860039701
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2128159895
Short name T904
Test name
Test status
Simulation time 15102611 ps
CPU time 0.62 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:01 PM PST 24
Peak memory 194020 kb
Host smart-5399b24b-0ce5-4ba4-9160-2ab599fd0432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128159895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2128159895
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1616921344
Short name T915
Test name
Test status
Simulation time 14452889 ps
CPU time 0.57 seconds
Started Jan 17 12:34:07 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193880 kb
Host smart-d972e64a-d21e-4a10-b499-91e76eb82667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616921344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1616921344
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4180256024
Short name T895
Test name
Test status
Simulation time 43333262 ps
CPU time 0.6 seconds
Started Jan 17 12:34:14 PM PST 24
Finished Jan 17 12:34:17 PM PST 24
Peak memory 194616 kb
Host smart-1c721aa9-7d9f-43a2-aa88-f8d3b9abad5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180256024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4180256024
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2184041337
Short name T112
Test name
Test status
Simulation time 13979978 ps
CPU time 0.62 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194688 kb
Host smart-89564892-e82a-4cc1-8a4b-2316af05faf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184041337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2184041337
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1030615413
Short name T907
Test name
Test status
Simulation time 95691399 ps
CPU time 0.61 seconds
Started Jan 17 12:34:06 PM PST 24
Finished Jan 17 12:34:15 PM PST 24
Peak memory 194576 kb
Host smart-ab2ea60a-c857-4294-a99e-9651e611c590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030615413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1030615413
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3695626509
Short name T952
Test name
Test status
Simulation time 18471649 ps
CPU time 0.63 seconds
Started Jan 17 12:34:06 PM PST 24
Finished Jan 17 12:34:15 PM PST 24
Peak memory 194016 kb
Host smart-49547215-fd6c-4cf2-ae40-c12632df72b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695626509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3695626509
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2867217116
Short name T13
Test name
Test status
Simulation time 16157806 ps
CPU time 0.59 seconds
Started Jan 17 12:34:09 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193820 kb
Host smart-8e1b91fa-74c7-4389-8dd2-b104c9bdbc2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867217116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2867217116
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1967940092
Short name T113
Test name
Test status
Simulation time 24208402 ps
CPU time 0.6 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194004 kb
Host smart-4167351d-776b-492a-84d7-68e15a93d4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967940092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1967940092
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2026876910
Short name T946
Test name
Test status
Simulation time 56624293 ps
CPU time 0.65 seconds
Started Jan 17 12:34:05 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 195252 kb
Host smart-3d2de167-4965-4d0e-87bb-9c8b3aa60a10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026876910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2026876910
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1652614342
Short name T86
Test name
Test status
Simulation time 258408843 ps
CPU time 2.52 seconds
Started Jan 17 12:34:07 PM PST 24
Finished Jan 17 12:34:18 PM PST 24
Peak memory 197112 kb
Host smart-67887b11-bc3d-4063-bc47-5288b3f0ee0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652614342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1652614342
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.409636673
Short name T914
Test name
Test status
Simulation time 13200425 ps
CPU time 0.6 seconds
Started Jan 17 12:33:46 PM PST 24
Finished Jan 17 12:33:49 PM PST 24
Peak memory 195288 kb
Host smart-2df8d936-4194-46a7-b0de-8963c32b62bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409636673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.409636673
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2765381907
Short name T84
Test name
Test status
Simulation time 42271638 ps
CPU time 0.64 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 195080 kb
Host smart-464173fb-fbdb-4b6d-8187-a7b55bb7a396
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765381907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2765381907
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4035487942
Short name T116
Test name
Test status
Simulation time 29700091 ps
CPU time 0.6 seconds
Started Jan 17 12:33:59 PM PST 24
Finished Jan 17 12:34:01 PM PST 24
Peak memory 194592 kb
Host smart-c4a24fd0-ee20-4aa0-a9f0-b1bb8d510f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035487942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4035487942
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1999777150
Short name T88
Test name
Test status
Simulation time 36379159 ps
CPU time 0.88 seconds
Started Jan 17 12:33:49 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 196544 kb
Host smart-6e74a39b-6b82-43f4-8011-6ab7e81d2879
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999777150 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1999777150
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.802739702
Short name T37
Test name
Test status
Simulation time 219482542 ps
CPU time 2.87 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 198312 kb
Host smart-5f9f62b3-d8c5-4e4f-80b0-e7fc675e6b97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802739702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.802739702
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2737234439
Short name T11
Test name
Test status
Simulation time 117265494 ps
CPU time 1.12 seconds
Started Jan 17 12:33:48 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 198184 kb
Host smart-934dfd50-7f01-4bc4-94f0-fdbbb06299c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737234439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2737234439
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2755279792
Short name T115
Test name
Test status
Simulation time 28914045 ps
CPU time 0.56 seconds
Started Jan 17 12:34:07 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193956 kb
Host smart-b6a9b08c-acdd-4ab8-b389-7c1daaa01de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755279792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2755279792
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3508070052
Short name T948
Test name
Test status
Simulation time 17460669 ps
CPU time 0.62 seconds
Started Jan 17 12:34:09 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193952 kb
Host smart-df84ed23-1bd2-43c2-bef2-a3914c5c8cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508070052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3508070052
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2944532527
Short name T931
Test name
Test status
Simulation time 44490576 ps
CPU time 0.6 seconds
Started Jan 17 12:34:02 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 193952 kb
Host smart-9b377105-a5cc-46b9-9bc5-deb941f2550f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944532527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2944532527
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3226618041
Short name T933
Test name
Test status
Simulation time 13055439 ps
CPU time 0.63 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 194628 kb
Host smart-5262b387-352d-40b2-b06c-bc68082c3ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226618041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3226618041
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.151850412
Short name T945
Test name
Test status
Simulation time 13109558 ps
CPU time 0.61 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193948 kb
Host smart-687d38ee-7605-4feb-8b8a-1fc10b8bf41a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151850412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.151850412
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3243902439
Short name T22
Test name
Test status
Simulation time 32985847 ps
CPU time 0.6 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 193824 kb
Host smart-16b7d131-a249-452a-9aa3-c081d9b4c42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243902439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3243902439
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3170676027
Short name T894
Test name
Test status
Simulation time 15309191 ps
CPU time 0.67 seconds
Started Jan 17 12:34:09 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194576 kb
Host smart-9351f049-2c02-4f62-8e14-543c374b3aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170676027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3170676027
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.835899660
Short name T970
Test name
Test status
Simulation time 38761586 ps
CPU time 0.63 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 193896 kb
Host smart-9b66f380-dc9e-4c16-b8b7-f2a65e5b0595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835899660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.835899660
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2602152664
Short name T107
Test name
Test status
Simulation time 52236105 ps
CPU time 0.56 seconds
Started Jan 17 12:34:08 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194004 kb
Host smart-6cb9cbe2-ce05-4222-a24d-479790799eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602152664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2602152664
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.840606903
Short name T965
Test name
Test status
Simulation time 12074892 ps
CPU time 0.58 seconds
Started Jan 17 12:34:10 PM PST 24
Finished Jan 17 12:34:16 PM PST 24
Peak memory 194612 kb
Host smart-caf8d316-1baf-4cfc-a08a-9a2db5aba0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840606903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.840606903
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1590786209
Short name T960
Test name
Test status
Simulation time 23877832 ps
CPU time 0.73 seconds
Started Jan 17 12:33:54 PM PST 24
Finished Jan 17 12:33:56 PM PST 24
Peak memory 198076 kb
Host smart-dbbb9363-eefb-46e9-860e-23033805904a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590786209 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1590786209
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1245539432
Short name T10
Test name
Test status
Simulation time 14712710 ps
CPU time 0.6 seconds
Started Jan 17 12:33:56 PM PST 24
Finished Jan 17 12:33:57 PM PST 24
Peak memory 194640 kb
Host smart-446ebce4-6ffb-423f-a2b5-94f591d8b3e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245539432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1245539432
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3909570316
Short name T920
Test name
Test status
Simulation time 110293852 ps
CPU time 0.63 seconds
Started Jan 17 12:33:53 PM PST 24
Finished Jan 17 12:33:55 PM PST 24
Peak memory 193920 kb
Host smart-18a15de3-10ea-4e20-a413-66241fe687c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909570316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3909570316
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2986616413
Short name T74
Test name
Test status
Simulation time 156085197 ps
CPU time 0.71 seconds
Started Jan 17 12:33:48 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 196992 kb
Host smart-a5b72dfd-45b3-4f92-8a36-289235a414d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986616413 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2986616413
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3719197141
Short name T909
Test name
Test status
Simulation time 323402167 ps
CPU time 2.75 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 198412 kb
Host smart-12315104-30ac-4461-a3af-7762140f3ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719197141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3719197141
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3218270344
Short name T927
Test name
Test status
Simulation time 59083735 ps
CPU time 0.92 seconds
Started Jan 17 12:33:58 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 198128 kb
Host smart-fc483dd7-6314-4e98-8b4f-17052adf413c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218270344 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3218270344
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3511108655
Short name T87
Test name
Test status
Simulation time 17560414 ps
CPU time 0.61 seconds
Started Jan 17 12:33:49 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 195752 kb
Host smart-8a86796b-3b7d-4909-891e-b8f30cd08ebd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511108655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3511108655
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2142735319
Short name T932
Test name
Test status
Simulation time 18797600 ps
CPU time 0.55 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:04 PM PST 24
Peak memory 194516 kb
Host smart-990f04c9-4589-4b16-8913-e84d1d4f0f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142735319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2142735319
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3898421453
Short name T8
Test name
Test status
Simulation time 110509878 ps
CPU time 0.76 seconds
Started Jan 17 12:33:50 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 196620 kb
Host smart-ef5544d5-cfa5-43b4-8a98-7b94bace25e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898421453 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3898421453
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1070251089
Short name T12
Test name
Test status
Simulation time 88014215 ps
CPU time 1.26 seconds
Started Jan 17 12:34:00 PM PST 24
Finished Jan 17 12:34:04 PM PST 24
Peak memory 198252 kb
Host smart-b9e99974-c7cd-4a95-8e4a-52955db85603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070251089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1070251089
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2602304487
Short name T916
Test name
Test status
Simulation time 144712459 ps
CPU time 1.44 seconds
Started Jan 17 12:34:02 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 198124 kb
Host smart-6fe7e3f9-b70f-4902-baa6-71c5a964429d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602304487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2602304487
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1070176939
Short name T111
Test name
Test status
Simulation time 41395469 ps
CPU time 0.98 seconds
Started Jan 17 12:33:56 PM PST 24
Finished Jan 17 12:33:58 PM PST 24
Peak memory 198056 kb
Host smart-03bf76b4-aebb-45ea-a0ba-0dd583fe29fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070176939 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1070176939
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2794474147
Short name T83
Test name
Test status
Simulation time 33848163 ps
CPU time 0.57 seconds
Started Jan 17 12:33:48 PM PST 24
Finished Jan 17 12:33:52 PM PST 24
Peak memory 193460 kb
Host smart-2b349477-af1a-435a-afa5-7068fbb2742e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794474147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2794474147
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.673810444
Short name T890
Test name
Test status
Simulation time 24706032 ps
CPU time 0.6 seconds
Started Jan 17 12:33:53 PM PST 24
Finished Jan 17 12:33:55 PM PST 24
Peak memory 194656 kb
Host smart-a6f468bd-f59f-4c86-b8ce-0aa60a80b08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673810444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.673810444
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3856024265
Short name T934
Test name
Test status
Simulation time 63909644 ps
CPU time 0.81 seconds
Started Jan 17 12:33:46 PM PST 24
Finished Jan 17 12:33:48 PM PST 24
Peak memory 196708 kb
Host smart-37e80ca0-c1f1-48f3-8421-3f2b9862f138
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856024265 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3856024265
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1664742697
Short name T919
Test name
Test status
Simulation time 97950927 ps
CPU time 1.4 seconds
Started Jan 17 12:33:56 PM PST 24
Finished Jan 17 12:33:58 PM PST 24
Peak memory 198352 kb
Host smart-6cba6951-9e1c-4c6a-af97-9e0d6b58ab59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664742697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1664742697
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1066057500
Short name T901
Test name
Test status
Simulation time 564370282 ps
CPU time 1.39 seconds
Started Jan 17 12:33:51 PM PST 24
Finished Jan 17 12:33:54 PM PST 24
Peak memory 198232 kb
Host smart-4c4e0a5b-0e33-47e9-99a5-c7c9a7316dff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066057500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1066057500
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3428072410
Short name T956
Test name
Test status
Simulation time 36692129 ps
CPU time 0.67 seconds
Started Jan 17 12:34:00 PM PST 24
Finished Jan 17 12:34:03 PM PST 24
Peak memory 196596 kb
Host smart-c7997994-8532-4502-a36e-7bc3bf18e353
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428072410 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3428072410
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2575750875
Short name T954
Test name
Test status
Simulation time 22660451 ps
CPU time 0.6 seconds
Started Jan 17 12:33:51 PM PST 24
Finished Jan 17 12:33:53 PM PST 24
Peak memory 194840 kb
Host smart-136a37a3-582f-4f16-87eb-bfd415d38257
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575750875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2575750875
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2374436331
Short name T72
Test name
Test status
Simulation time 30927463 ps
CPU time 0.62 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 194596 kb
Host smart-f2cf207d-dd96-4473-b0d5-e0446389264d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374436331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2374436331
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.652476109
Short name T942
Test name
Test status
Simulation time 55905309 ps
CPU time 0.81 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 197152 kb
Host smart-bc47b81f-84c8-43b5-9b62-a048f1e7bcf2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652476109 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.652476109
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.943946277
Short name T902
Test name
Test status
Simulation time 215758870 ps
CPU time 2.51 seconds
Started Jan 17 12:33:55 PM PST 24
Finished Jan 17 12:33:58 PM PST 24
Peak memory 198608 kb
Host smart-1cc90552-78e9-43fe-8b71-1eb162ff385f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943946277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.943946277
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1529155973
Short name T939
Test name
Test status
Simulation time 217089649 ps
CPU time 1.39 seconds
Started Jan 17 12:33:57 PM PST 24
Finished Jan 17 12:33:59 PM PST 24
Peak memory 198276 kb
Host smart-c0931d6f-279d-4e19-a64b-060df90e5c64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529155973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1529155973
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2007375375
Short name T963
Test name
Test status
Simulation time 25404865 ps
CPU time 0.77 seconds
Started Jan 17 12:34:04 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 198188 kb
Host smart-7aa28054-9eeb-4892-8630-10aea570964b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007375375 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2007375375
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3124642178
Short name T94
Test name
Test status
Simulation time 58291608 ps
CPU time 0.6 seconds
Started Jan 17 12:34:01 PM PST 24
Finished Jan 17 12:34:05 PM PST 24
Peak memory 194792 kb
Host smart-6b1a5a38-cb1b-4feb-b7c6-18a2087c1ca1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124642178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3124642178
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.960794068
Short name T888
Test name
Test status
Simulation time 35032203 ps
CPU time 0.58 seconds
Started Jan 17 12:34:03 PM PST 24
Finished Jan 17 12:34:06 PM PST 24
Peak memory 193924 kb
Host smart-294b698c-4327-44cf-9bac-0c856a51e668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960794068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.960794068
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3120537542
Short name T5
Test name
Test status
Simulation time 39807100 ps
CPU time 0.69 seconds
Started Jan 17 12:34:05 PM PST 24
Finished Jan 17 12:34:07 PM PST 24
Peak memory 194924 kb
Host smart-a01a02f5-b709-420f-bb72-f6a033ce51bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120537542 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3120537542
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.586710276
Short name T891
Test name
Test status
Simulation time 132861646 ps
CPU time 1.76 seconds
Started Jan 17 12:34:12 PM PST 24
Finished Jan 17 12:34:17 PM PST 24
Peak memory 198332 kb
Host smart-9206176d-1604-4dd9-a3b1-0646bfa58933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586710276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.586710276
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.122279470
Short name T60
Test name
Test status
Simulation time 12392630 ps
CPU time 0.63 seconds
Started Jan 17 03:39:43 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 195068 kb
Host smart-d137a871-abcf-48c4-a187-bf6333c58607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122279470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.122279470
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1218647060
Short name T300
Test name
Test status
Simulation time 171792126 ps
CPU time 0.73 seconds
Started Jan 17 03:39:31 PM PST 24
Finished Jan 17 03:39:33 PM PST 24
Peak memory 195384 kb
Host smart-0619fd84-cb44-4043-a550-fdcc95ada951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218647060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1218647060
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1547096322
Short name T270
Test name
Test status
Simulation time 172317045 ps
CPU time 5.78 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 197052 kb
Host smart-119245a8-2457-4769-92c4-8761f44c21b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547096322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1547096322
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1998425283
Short name T702
Test name
Test status
Simulation time 122109816 ps
CPU time 0.67 seconds
Started Jan 17 03:39:46 PM PST 24
Finished Jan 17 03:39:51 PM PST 24
Peak memory 194452 kb
Host smart-a7bf63e6-7181-4732-a452-366ac6e49eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998425283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1998425283
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.819346775
Short name T429
Test name
Test status
Simulation time 118047617 ps
CPU time 0.79 seconds
Started Jan 17 03:39:35 PM PST 24
Finished Jan 17 03:39:37 PM PST 24
Peak memory 196084 kb
Host smart-418287bc-34fa-4e33-bdbb-928e9cffe250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819346775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.819346775
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1435328450
Short name T559
Test name
Test status
Simulation time 95561331 ps
CPU time 3.76 seconds
Started Jan 17 03:39:34 PM PST 24
Finished Jan 17 03:39:40 PM PST 24
Peak memory 197396 kb
Host smart-b4886e1e-d434-4eac-ab63-3b2a21dac044
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435328450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1435328450
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4199818280
Short name T398
Test name
Test status
Simulation time 526025742 ps
CPU time 2.67 seconds
Started Jan 17 03:39:34 PM PST 24
Finished Jan 17 03:39:39 PM PST 24
Peak memory 197268 kb
Host smart-6f80e126-14e4-4ba2-88f8-1d4a9cd5d36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199818280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4199818280
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3926330417
Short name T437
Test name
Test status
Simulation time 43236248 ps
CPU time 1.02 seconds
Started Jan 17 03:39:35 PM PST 24
Finished Jan 17 03:39:37 PM PST 24
Peak memory 196048 kb
Host smart-82967320-2baf-49bf-9e71-a1d77e6568a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926330417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3926330417
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.279486221
Short name T816
Test name
Test status
Simulation time 36775020 ps
CPU time 1.25 seconds
Started Jan 17 03:39:31 PM PST 24
Finished Jan 17 03:39:33 PM PST 24
Peak memory 198188 kb
Host smart-d9ea39eb-1349-4108-86f4-99877af659f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279486221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.279486221
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3194693408
Short name T644
Test name
Test status
Simulation time 185213231 ps
CPU time 3.16 seconds
Started Jan 17 03:39:42 PM PST 24
Finished Jan 17 03:39:49 PM PST 24
Peak memory 197948 kb
Host smart-5f657774-6f13-47c2-b87a-a0e4119c835e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194693408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3194693408
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3511213004
Short name T342
Test name
Test status
Simulation time 63916297 ps
CPU time 0.92 seconds
Started Jan 17 03:39:30 PM PST 24
Finished Jan 17 03:39:32 PM PST 24
Peak memory 197208 kb
Host smart-1d0a4fb3-b6aa-41cd-b8f1-94ef4bb8e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511213004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3511213004
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3869693010
Short name T681
Test name
Test status
Simulation time 433211803 ps
CPU time 1.61 seconds
Started Jan 17 03:39:31 PM PST 24
Finished Jan 17 03:39:34 PM PST 24
Peak memory 196840 kb
Host smart-9fff328d-3060-4545-bf94-1b6546d970b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869693010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3869693010
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.4065358169
Short name T735
Test name
Test status
Simulation time 8631606385 ps
CPU time 48.62 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 03:40:40 PM PST 24
Peak memory 198204 kb
Host smart-45af8ee9-e6ac-46dc-91bf-c716289e5283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065358169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.4065358169
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1119988814
Short name T495
Test name
Test status
Simulation time 32165506953 ps
CPU time 960.92 seconds
Started Jan 17 03:39:42 PM PST 24
Finished Jan 17 03:55:47 PM PST 24
Peak memory 198336 kb
Host smart-89732dca-8966-4ee1-bcdb-298d2597e466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1119988814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1119988814
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.732892962
Short name T482
Test name
Test status
Simulation time 10491278 ps
CPU time 0.61 seconds
Started Jan 17 03:39:43 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 194348 kb
Host smart-d236c1d6-3266-4674-945b-712ff1fd6c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732892962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.732892962
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1831854279
Short name T664
Test name
Test status
Simulation time 54152164 ps
CPU time 0.61 seconds
Started Jan 17 03:39:46 PM PST 24
Finished Jan 17 03:39:50 PM PST 24
Peak memory 193772 kb
Host smart-9cecb528-f8b0-434e-b9a8-6ae32553f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831854279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1831854279
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1811997571
Short name T516
Test name
Test status
Simulation time 493401848 ps
CPU time 12.74 seconds
Started Jan 17 03:39:41 PM PST 24
Finished Jan 17 03:39:59 PM PST 24
Peak memory 198148 kb
Host smart-e23f763b-abac-452b-834e-ffdef1fb8755
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811997571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1811997571
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2460613848
Short name T824
Test name
Test status
Simulation time 350954474 ps
CPU time 1.07 seconds
Started Jan 17 03:39:49 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 197584 kb
Host smart-500f2aa5-38da-4449-a7e9-9ac064ed8671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460613848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2460613848
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3005175439
Short name T257
Test name
Test status
Simulation time 44509492 ps
CPU time 1.28 seconds
Started Jan 17 03:39:39 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 197128 kb
Host smart-682d4858-9253-4b97-b938-c2d7562fe468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005175439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3005175439
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1225984395
Short name T853
Test name
Test status
Simulation time 42999677 ps
CPU time 1.24 seconds
Started Jan 17 03:39:40 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 196396 kb
Host smart-ef3052c8-0896-493c-9ba0-0ab6c1f73232
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225984395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1225984395
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2999537535
Short name T318
Test name
Test status
Simulation time 186826248 ps
CPU time 2.29 seconds
Started Jan 17 03:39:40 PM PST 24
Finished Jan 17 03:39:48 PM PST 24
Peak memory 195844 kb
Host smart-052ad4e0-8687-4210-95ef-7ce9119f76b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999537535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2999537535
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4253007055
Short name T577
Test name
Test status
Simulation time 17166606 ps
CPU time 0.75 seconds
Started Jan 17 03:39:49 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 195472 kb
Host smart-0c70e150-24c0-47c4-bba9-b5ca69962ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253007055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4253007055
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3409250488
Short name T562
Test name
Test status
Simulation time 36904381 ps
CPU time 0.89 seconds
Started Jan 17 03:39:44 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 196680 kb
Host smart-4881abcc-cdd8-4f10-b991-b272c43ea780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409250488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3409250488
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2570454357
Short name T260
Test name
Test status
Simulation time 1735169963 ps
CPU time 5.07 seconds
Started Jan 17 03:39:41 PM PST 24
Finished Jan 17 03:39:51 PM PST 24
Peak memory 198092 kb
Host smart-4fc9c899-6912-42fd-91a4-3e34ac3af8dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570454357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2570454357
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2687023446
Short name T26
Test name
Test status
Simulation time 497568751 ps
CPU time 0.85 seconds
Started Jan 17 03:39:42 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 213456 kb
Host smart-e26f6b65-a8b0-42a3-90eb-2432ccd793ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687023446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2687023446
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2148890581
Short name T294
Test name
Test status
Simulation time 50442625 ps
CPU time 0.96 seconds
Started Jan 17 03:39:40 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 195644 kb
Host smart-27dadd96-1c33-4541-aaca-9273797df30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148890581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2148890581
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4013169237
Short name T245
Test name
Test status
Simulation time 365564771 ps
CPU time 1.27 seconds
Started Jan 17 03:39:46 PM PST 24
Finished Jan 17 03:39:51 PM PST 24
Peak memory 198048 kb
Host smart-b1af5977-ca8a-4b00-b4f8-26131f55b5e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013169237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4013169237
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.510514345
Short name T836
Test name
Test status
Simulation time 14366686604 ps
CPU time 35.91 seconds
Started Jan 17 03:39:40 PM PST 24
Finished Jan 17 03:40:22 PM PST 24
Peak memory 198188 kb
Host smart-076a39fc-1f16-4e26-a5fa-a474e41539f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510514345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.510514345
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1518386935
Short name T494
Test name
Test status
Simulation time 93135087092 ps
CPU time 715.23 seconds
Started Jan 17 03:39:40 PM PST 24
Finished Jan 17 03:51:42 PM PST 24
Peak memory 198392 kb
Host smart-c13d6fca-2cbb-48fa-92e7-cd30304a9049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1518386935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1518386935
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.395844096
Short name T832
Test name
Test status
Simulation time 22546402 ps
CPU time 0.61 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 194072 kb
Host smart-4ec2fcc7-1bff-4cd9-b178-7dee092ad90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395844096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.395844096
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1154413737
Short name T284
Test name
Test status
Simulation time 19033195 ps
CPU time 0.64 seconds
Started Jan 17 03:40:07 PM PST 24
Finished Jan 17 03:40:11 PM PST 24
Peak memory 193988 kb
Host smart-ca3a8215-061f-4674-b9b3-a779a17fc4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154413737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1154413737
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2658544890
Short name T272
Test name
Test status
Simulation time 1853470073 ps
CPU time 21.3 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:41 PM PST 24
Peak memory 198320 kb
Host smart-a1a63276-26c6-45c0-ba92-4b6b8706066e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658544890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2658544890
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.685200035
Short name T694
Test name
Test status
Simulation time 62606837 ps
CPU time 1.05 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196656 kb
Host smart-02674bba-cac9-434c-8ae1-dffbfb9ccf62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685200035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.685200035
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3273698219
Short name T817
Test name
Test status
Simulation time 301548926 ps
CPU time 0.95 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 196892 kb
Host smart-915d8d66-63b1-4776-b61b-ffe6b53ada96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273698219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3273698219
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.542844035
Short name T859
Test name
Test status
Simulation time 247673727 ps
CPU time 1.33 seconds
Started Jan 17 03:40:13 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196852 kb
Host smart-10b67da9-5ebc-4c0c-9134-97decc8419ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542844035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.542844035
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.4010295775
Short name T255
Test name
Test status
Simulation time 63817004 ps
CPU time 1.63 seconds
Started Jan 17 03:40:12 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196912 kb
Host smart-5cf7c8c0-f67a-4cd2-abdf-9d7151398424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010295775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.4010295775
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3002220512
Short name T747
Test name
Test status
Simulation time 46977541 ps
CPU time 0.94 seconds
Started Jan 17 03:40:09 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 195880 kb
Host smart-1a21f13b-1b68-447b-a56a-65ef7cb275a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002220512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3002220512
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1012213586
Short name T374
Test name
Test status
Simulation time 23215896 ps
CPU time 0.68 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:08 PM PST 24
Peak memory 194480 kb
Host smart-b97222cf-6ff1-4838-897f-3b942fb523c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012213586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1012213586
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3431787379
Short name T507
Test name
Test status
Simulation time 648926876 ps
CPU time 4.44 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 198096 kb
Host smart-3b804db6-e2bc-40a2-819d-f197af5a0190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431787379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3431787379
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.690709454
Short name T302
Test name
Test status
Simulation time 39834342 ps
CPU time 0.94 seconds
Started Jan 17 03:40:10 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 195504 kb
Host smart-48bdd391-a141-4a27-84ec-951a31f3394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690709454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.690709454
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.392575711
Short name T279
Test name
Test status
Simulation time 86861879 ps
CPU time 0.98 seconds
Started Jan 17 03:40:07 PM PST 24
Finished Jan 17 03:40:11 PM PST 24
Peak memory 195536 kb
Host smart-fd4f0b37-d1c2-4ac0-a225-54f7f8e111d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392575711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.392575711
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3507123576
Short name T470
Test name
Test status
Simulation time 11639969774 ps
CPU time 158.49 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:42:58 PM PST 24
Peak memory 198160 kb
Host smart-373bb407-d0a3-491c-b4c2-1199f8724483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507123576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3507123576
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1645354548
Short name T321
Test name
Test status
Simulation time 83262263381 ps
CPU time 1461.22 seconds
Started Jan 17 03:40:16 PM PST 24
Finished Jan 17 04:04:41 PM PST 24
Peak memory 198444 kb
Host smart-31596843-aaff-4004-9351-cde8669b4203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1645354548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1645354548
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1805679198
Short name T783
Test name
Test status
Simulation time 26307682 ps
CPU time 0.59 seconds
Started Jan 17 03:40:17 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 194080 kb
Host smart-1340525d-3a5f-4761-b1e7-2e5870552c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805679198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1805679198
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4194324282
Short name T851
Test name
Test status
Simulation time 82866968 ps
CPU time 0.69 seconds
Started Jan 17 03:40:13 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 194124 kb
Host smart-aee39d74-d815-498a-b157-ab8d502c6913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194324282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4194324282
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1052007108
Short name T235
Test name
Test status
Simulation time 995802279 ps
CPU time 16.84 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:36 PM PST 24
Peak memory 197168 kb
Host smart-862b1e5d-d6cb-4618-88c8-901d45b252ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052007108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1052007108
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1346747731
Short name T355
Test name
Test status
Simulation time 748461441 ps
CPU time 0.84 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196588 kb
Host smart-235f6b0b-9ce4-4dab-9e58-a7a2e876a184
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346747731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1346747731
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1740347857
Short name T588
Test name
Test status
Simulation time 52818340 ps
CPU time 1.08 seconds
Started Jan 17 03:40:17 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 197020 kb
Host smart-d24a30e7-a1ee-4586-96ba-620974e2a05e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740347857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1740347857
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2731045301
Short name T564
Test name
Test status
Simulation time 88995239 ps
CPU time 3.73 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 198192 kb
Host smart-671d2279-c034-4590-a4e9-df8e2b40eaaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731045301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2731045301
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2525222430
Short name T266
Test name
Test status
Simulation time 102284922 ps
CPU time 1.71 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 196608 kb
Host smart-08feec62-e97b-4548-9e6e-6d05849f065b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525222430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2525222430
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2182468487
Short name T281
Test name
Test status
Simulation time 24208662 ps
CPU time 0.93 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196732 kb
Host smart-1e7cdfef-5202-4cae-8382-2a44e5447624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182468487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2182468487
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2968599676
Short name T336
Test name
Test status
Simulation time 143941935 ps
CPU time 1.36 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 195960 kb
Host smart-250d6271-0c70-44da-b2fa-b2968eac4a0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968599676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2968599676
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2056517873
Short name T553
Test name
Test status
Simulation time 3500823575 ps
CPU time 6.6 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:26 PM PST 24
Peak memory 198124 kb
Host smart-806b64c2-986a-4de6-a80d-42155ffdcd19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056517873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2056517873
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2215587002
Short name T61
Test name
Test status
Simulation time 51431623 ps
CPU time 0.95 seconds
Started Jan 17 03:40:11 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 196352 kb
Host smart-24e32fbe-6470-492c-8d89-fcdc57aa984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215587002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2215587002
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3989125062
Short name T761
Test name
Test status
Simulation time 99650287 ps
CPU time 1.05 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 195620 kb
Host smart-39944e5f-a4d9-4955-94e9-367c8cba8920
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989125062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3989125062
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.213038672
Short name T226
Test name
Test status
Simulation time 9198432579 ps
CPU time 71.76 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:41:31 PM PST 24
Peak memory 198284 kb
Host smart-f033d7b7-e5c1-46b4-ba00-40b293104630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213038672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.213038672
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.547107727
Short name T794
Test name
Test status
Simulation time 154931278811 ps
CPU time 820.71 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:54:00 PM PST 24
Peak memory 198372 kb
Host smart-199cdd4b-9da4-4935-8d44-327472bad194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=547107727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.547107727
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2609017681
Short name T714
Test name
Test status
Simulation time 86934026 ps
CPU time 0.92 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 196048 kb
Host smart-6f813050-dd4d-44dd-9f32-c2e2ddde00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609017681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2609017681
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2092606062
Short name T476
Test name
Test status
Simulation time 715770963 ps
CPU time 19.12 seconds
Started Jan 17 03:40:20 PM PST 24
Finished Jan 17 03:40:41 PM PST 24
Peak memory 195692 kb
Host smart-124e5ee4-2368-426f-8a70-eaab881abedd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092606062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2092606062
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2312837020
Short name T819
Test name
Test status
Simulation time 263912947 ps
CPU time 1.05 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 198136 kb
Host smart-58a014aa-41d7-4853-b5f7-72f1fa118a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312837020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2312837020
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2867568616
Short name T707
Test name
Test status
Simulation time 155111177 ps
CPU time 1.43 seconds
Started Jan 17 03:40:19 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 198160 kb
Host smart-3be1c09b-3971-498c-b606-5efe5cc0e202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867568616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2867568616
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1240025461
Short name T844
Test name
Test status
Simulation time 62797965 ps
CPU time 2.29 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:22 PM PST 24
Peak memory 198280 kb
Host smart-6ef79238-e9a6-41f8-a1e6-e67d873d93e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240025461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1240025461
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1626288270
Short name T732
Test name
Test status
Simulation time 142884894 ps
CPU time 3.61 seconds
Started Jan 17 03:40:19 PM PST 24
Finished Jan 17 03:40:25 PM PST 24
Peak memory 197264 kb
Host smart-b6150179-e7d5-4ea6-9604-a52923962b1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626288270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1626288270
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1227470112
Short name T456
Test name
Test status
Simulation time 122403395 ps
CPU time 0.74 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 195412 kb
Host smart-15e25201-555c-4a35-87cc-4a77aa0dd391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227470112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1227470112
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3159576956
Short name T599
Test name
Test status
Simulation time 26184501 ps
CPU time 0.95 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 195848 kb
Host smart-0569087f-c9d6-43d4-99a3-0b1836370c5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159576956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3159576956
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.371583077
Short name T556
Test name
Test status
Simulation time 316889952 ps
CPU time 3.88 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:26 PM PST 24
Peak memory 198088 kb
Host smart-674c3a88-c865-4292-b40a-e4f543dc4bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371583077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.371583077
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3306422589
Short name T447
Test name
Test status
Simulation time 39696373 ps
CPU time 1.22 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 195784 kb
Host smart-2ef3a6e0-b189-4863-bda5-ceaaf43d1d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306422589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3306422589
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3712855207
Short name T545
Test name
Test status
Simulation time 168550505 ps
CPU time 1.09 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 195632 kb
Host smart-f40be496-e5ed-43ab-b025-08ec203e1f1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712855207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3712855207
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.45215537
Short name T739
Test name
Test status
Simulation time 60559742892 ps
CPU time 180.42 seconds
Started Jan 17 03:40:17 PM PST 24
Finished Jan 17 03:43:20 PM PST 24
Peak memory 198240 kb
Host smart-9ed27f15-1ca0-47dd-bbc7-5d24147d0e3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45215537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gp
io_stress_all.45215537
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3773971550
Short name T565
Test name
Test status
Simulation time 233341525368 ps
CPU time 1312.44 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 04:02:12 PM PST 24
Peak memory 198376 kb
Host smart-e215d1bb-6000-4896-9dbd-89eece19eaf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3773971550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3773971550
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1736413836
Short name T483
Test name
Test status
Simulation time 12307484 ps
CPU time 0.57 seconds
Started Jan 17 03:40:16 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 194744 kb
Host smart-0b8a0b62-cce5-4283-90de-f8c7e71213c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736413836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1736413836
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.197755440
Short name T292
Test name
Test status
Simulation time 22275268 ps
CPU time 0.83 seconds
Started Jan 17 03:40:17 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 195252 kb
Host smart-09dc4e84-474a-4ee9-ad92-387a5ecd44ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197755440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.197755440
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3364519197
Short name T861
Test name
Test status
Simulation time 236656953 ps
CPU time 7.44 seconds
Started Jan 17 03:40:22 PM PST 24
Finished Jan 17 03:40:30 PM PST 24
Peak memory 197036 kb
Host smart-a3ff3e07-3f87-483e-aee9-bda7280d1889
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364519197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3364519197
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3564671310
Short name T379
Test name
Test status
Simulation time 43104898 ps
CPU time 0.71 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 195376 kb
Host smart-ca27c827-ca79-4c01-9c94-42127f660d17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564671310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3564671310
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1584099582
Short name T666
Test name
Test status
Simulation time 33434816 ps
CPU time 0.75 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 195364 kb
Host smart-ae91cdea-48c6-4167-8bed-8dbaee0d3b2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584099582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1584099582
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2527881318
Short name T351
Test name
Test status
Simulation time 44802797 ps
CPU time 1.97 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 198208 kb
Host smart-2a5f288c-25e3-4bf0-a342-f652d8b873f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527881318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2527881318
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2867509429
Short name T706
Test name
Test status
Simulation time 85003663 ps
CPU time 1.58 seconds
Started Jan 17 03:40:18 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 196232 kb
Host smart-8b62d2cf-ce57-49a9-807f-57faf8cc00bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867509429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2867509429
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.4220810782
Short name T876
Test name
Test status
Simulation time 87247119 ps
CPU time 1.15 seconds
Started Jan 17 03:40:16 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196244 kb
Host smart-f11fd200-4869-4d74-920b-00119921fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220810782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.4220810782
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3501685556
Short name T721
Test name
Test status
Simulation time 24547360 ps
CPU time 0.99 seconds
Started Jan 17 03:40:19 PM PST 24
Finished Jan 17 03:40:22 PM PST 24
Peak memory 196132 kb
Host smart-8f45e2ae-4d43-4a78-8e5b-46966886f116
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501685556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3501685556
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1687000075
Short name T622
Test name
Test status
Simulation time 450044183 ps
CPU time 2.48 seconds
Started Jan 17 03:40:17 PM PST 24
Finished Jan 17 03:40:22 PM PST 24
Peak memory 198060 kb
Host smart-e46c2c7f-9f11-4893-93f0-28798f3d16ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687000075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1687000075
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2606999076
Short name T521
Test name
Test status
Simulation time 62708806 ps
CPU time 1.2 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 195952 kb
Host smart-bf94ce50-f0ad-4a64-8679-207394f0c676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606999076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2606999076
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1085943859
Short name T826
Test name
Test status
Simulation time 92275386 ps
CPU time 1.29 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 196928 kb
Host smart-80d5408e-e734-4bac-b933-7322a56ee878
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085943859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1085943859
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3019460778
Short name T789
Test name
Test status
Simulation time 17992610589 ps
CPU time 71.14 seconds
Started Jan 17 03:40:19 PM PST 24
Finished Jan 17 03:41:32 PM PST 24
Peak memory 198284 kb
Host smart-27096901-e42e-472a-ad4e-5a0dbde99633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019460778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3019460778
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3557003640
Short name T693
Test name
Test status
Simulation time 214660107400 ps
CPU time 913.66 seconds
Started Jan 17 03:40:19 PM PST 24
Finished Jan 17 03:55:35 PM PST 24
Peak memory 198400 kb
Host smart-1dec40da-a5ab-4465-8ed8-20fba2dd20c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3557003640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3557003640
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3911510791
Short name T806
Test name
Test status
Simulation time 44650832 ps
CPU time 0.57 seconds
Started Jan 17 03:40:24 PM PST 24
Finished Jan 17 03:40:26 PM PST 24
Peak memory 194264 kb
Host smart-1482ad4d-5898-4d2c-8902-2a3ebf65bad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911510791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3911510791
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3355276801
Short name T756
Test name
Test status
Simulation time 103572727 ps
CPU time 0.85 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 197332 kb
Host smart-230c76b2-1e58-44c0-b3e7-550a39e24d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355276801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3355276801
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3256535343
Short name T661
Test name
Test status
Simulation time 2705021583 ps
CPU time 19.93 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:42 PM PST 24
Peak memory 198276 kb
Host smart-62d3e493-934f-4cd6-8c4f-deedd9106124
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256535343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3256535343
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1525998501
Short name T658
Test name
Test status
Simulation time 307249879 ps
CPU time 1.01 seconds
Started Jan 17 03:40:28 PM PST 24
Finished Jan 17 03:40:30 PM PST 24
Peak memory 196372 kb
Host smart-b91aaf23-f034-4377-98b2-1a728cc3e19d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525998501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1525998501
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2485724072
Short name T808
Test name
Test status
Simulation time 721938167 ps
CPU time 1.2 seconds
Started Jan 17 03:40:15 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 196792 kb
Host smart-f0757261-a060-461c-8fda-9fc6d47961d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485724072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2485724072
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2676470731
Short name T372
Test name
Test status
Simulation time 47191640 ps
CPU time 1.96 seconds
Started Jan 17 03:40:20 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 198196 kb
Host smart-b5813609-89e7-46ac-8484-28269972173d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676470731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2676470731
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3169500968
Short name T591
Test name
Test status
Simulation time 116625946 ps
CPU time 1.07 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 195860 kb
Host smart-ac8d84cc-2196-4057-8c4c-88bad706a3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169500968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3169500968
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2729334780
Short name T419
Test name
Test status
Simulation time 29553977 ps
CPU time 1.1 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 195892 kb
Host smart-3ff67a2f-1c6a-4af2-b890-a5d8d2bbadfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729334780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2729334780
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2673449552
Short name T360
Test name
Test status
Simulation time 59283756 ps
CPU time 1.24 seconds
Started Jan 17 03:40:22 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 196904 kb
Host smart-a7a20e56-1516-4c8a-973a-28498f8c49d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673449552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2673449552
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3901547092
Short name T217
Test name
Test status
Simulation time 425026175 ps
CPU time 2.13 seconds
Started Jan 17 03:40:20 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 198124 kb
Host smart-93f42ef6-22dd-439c-843e-6b78617820f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901547092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3901547092
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1834980164
Short name T763
Test name
Test status
Simulation time 80144288 ps
CPU time 1.26 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:24 PM PST 24
Peak memory 196876 kb
Host smart-efad2dbb-d5bb-47ae-9e17-eb589674c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834980164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1834980164
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3046449232
Short name T736
Test name
Test status
Simulation time 127871878 ps
CPU time 1.06 seconds
Started Jan 17 03:40:21 PM PST 24
Finished Jan 17 03:40:23 PM PST 24
Peak memory 195776 kb
Host smart-a0a31220-db5d-4208-8138-d655555113f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046449232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3046449232
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2846438004
Short name T584
Test name
Test status
Simulation time 127715464248 ps
CPU time 146.08 seconds
Started Jan 17 03:40:27 PM PST 24
Finished Jan 17 03:42:54 PM PST 24
Peak memory 198228 kb
Host smart-e922b127-6ead-4d61-b4e0-a22a56151e4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846438004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2846438004
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.752498978
Short name T338
Test name
Test status
Simulation time 74188965510 ps
CPU time 717.1 seconds
Started Jan 17 03:40:26 PM PST 24
Finished Jan 17 03:52:24 PM PST 24
Peak memory 198424 kb
Host smart-cbf7b233-34fa-437b-a903-071933fb9c24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=752498978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.752498978
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2480989958
Short name T481
Test name
Test status
Simulation time 15329770 ps
CPU time 0.59 seconds
Started Jan 17 03:40:34 PM PST 24
Finished Jan 17 03:40:37 PM PST 24
Peak memory 194252 kb
Host smart-ba8268cc-ddd4-472a-a434-a35e0e063789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480989958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2480989958
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.89680928
Short name T813
Test name
Test status
Simulation time 98781924 ps
CPU time 0.76 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 195272 kb
Host smart-503354d9-17cb-480b-a8a7-47bc39c2383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89680928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.89680928
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.904087809
Short name T779
Test name
Test status
Simulation time 463479463 ps
CPU time 13.52 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 196868 kb
Host smart-56032243-e390-4f7e-9730-844da98ffcab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904087809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.904087809
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1468047259
Short name T384
Test name
Test status
Simulation time 17210145 ps
CPU time 0.63 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 194632 kb
Host smart-54e95f11-3cac-4d26-a873-296724390b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468047259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1468047259
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.107244073
Short name T254
Test name
Test status
Simulation time 211661250 ps
CPU time 1.12 seconds
Started Jan 17 03:40:28 PM PST 24
Finished Jan 17 03:40:30 PM PST 24
Peak memory 196108 kb
Host smart-fc7e9ffb-8922-47e8-8866-62cd332a628c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107244073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.107244073
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4027220105
Short name T825
Test name
Test status
Simulation time 80268233 ps
CPU time 1.1 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 195724 kb
Host smart-dca04e98-8de1-42a3-b83f-7585fac016f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027220105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4027220105
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.834057663
Short name T65
Test name
Test status
Simulation time 92620260 ps
CPU time 1.14 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 195972 kb
Host smart-ab43beea-6f2a-4ebd-b4e2-3a4c8dc8ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834057663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.834057663
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1018453981
Short name T546
Test name
Test status
Simulation time 104421159 ps
CPU time 1.02 seconds
Started Jan 17 03:40:28 PM PST 24
Finished Jan 17 03:40:29 PM PST 24
Peak memory 196080 kb
Host smart-5d2be0c4-b4c6-4ac0-8003-2352f3eb8591
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018453981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1018453981
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.79007056
Short name T656
Test name
Test status
Simulation time 606542844 ps
CPU time 2.74 seconds
Started Jan 17 03:40:34 PM PST 24
Finished Jan 17 03:40:40 PM PST 24
Peak memory 197952 kb
Host smart-7d9bebc1-5f97-421f-b6b9-6d76ef53cd6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79007056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand
om_long_reg_writes_reg_reads.79007056
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1977015792
Short name T480
Test name
Test status
Simulation time 58397664 ps
CPU time 1.15 seconds
Started Jan 17 03:40:22 PM PST 24
Finished Jan 17 03:40:25 PM PST 24
Peak memory 195648 kb
Host smart-a951248e-1d86-4614-a4c4-a7c9090bb1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977015792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1977015792
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3303424966
Short name T274
Test name
Test status
Simulation time 173946825 ps
CPU time 1.05 seconds
Started Jan 17 03:40:27 PM PST 24
Finished Jan 17 03:40:29 PM PST 24
Peak memory 196520 kb
Host smart-3c3d3d32-bea7-442b-825f-49b65f151462
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303424966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3303424966
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3160304931
Short name T690
Test name
Test status
Simulation time 10316573002 ps
CPU time 131.74 seconds
Started Jan 17 03:40:39 PM PST 24
Finished Jan 17 03:42:53 PM PST 24
Peak memory 198180 kb
Host smart-780db0f6-76f8-487a-bca4-98406bf3c303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160304931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3160304931
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3663388417
Short name T612
Test name
Test status
Simulation time 219405880388 ps
CPU time 1658.45 seconds
Started Jan 17 03:40:39 PM PST 24
Finished Jan 17 04:08:20 PM PST 24
Peak memory 198324 kb
Host smart-2e72e597-0eb1-4594-9b06-fe526d7514d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3663388417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3663388417
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2969965693
Short name T306
Test name
Test status
Simulation time 156063831 ps
CPU time 0.57 seconds
Started Jan 17 03:40:33 PM PST 24
Finished Jan 17 03:40:36 PM PST 24
Peak memory 194252 kb
Host smart-eaf593ae-bfdb-4cbc-98da-7e0df2eacb8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969965693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2969965693
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.721981644
Short name T261
Test name
Test status
Simulation time 14579097 ps
CPU time 0.62 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 194076 kb
Host smart-c826d2cd-6f8f-444a-a908-bf8d1bd56253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721981644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.721981644
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3502630977
Short name T511
Test name
Test status
Simulation time 211387145 ps
CPU time 12.15 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 196320 kb
Host smart-f822cbaa-5571-4516-b57a-c5c8316e4d3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502630977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3502630977
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3512011385
Short name T667
Test name
Test status
Simulation time 266166941 ps
CPU time 0.99 seconds
Started Jan 17 03:40:34 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 197240 kb
Host smart-30c98cd5-5adc-47b8-a78e-5456b62f4a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512011385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3512011385
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3783886146
Short name T356
Test name
Test status
Simulation time 42179826 ps
CPU time 1.2 seconds
Started Jan 17 03:40:34 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 196276 kb
Host smart-2b9e2022-febe-458a-beba-c9a2b15d8e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783886146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3783886146
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2685503557
Short name T682
Test name
Test status
Simulation time 615471046 ps
CPU time 2.56 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:40:41 PM PST 24
Peak memory 198168 kb
Host smart-2f80d436-72ab-40d9-96f5-d5d495dd978b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685503557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2685503557
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3294937031
Short name T335
Test name
Test status
Simulation time 209870881 ps
CPU time 2.11 seconds
Started Jan 17 03:40:37 PM PST 24
Finished Jan 17 03:40:42 PM PST 24
Peak memory 196304 kb
Host smart-dce88da8-622d-4f8c-80ee-9bc52d1755e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294937031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3294937031
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2253433663
Short name T734
Test name
Test status
Simulation time 21895925 ps
CPU time 0.68 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 194476 kb
Host smart-43c297d3-2100-4bfe-a892-1db58327032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253433663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2253433663
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2362681131
Short name T307
Test name
Test status
Simulation time 126169604 ps
CPU time 1.29 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 198192 kb
Host smart-4cc28013-8b41-43f5-ad18-ed872c6a7ad0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362681131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2362681131
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3231879851
Short name T520
Test name
Test status
Simulation time 397957697 ps
CPU time 3.31 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:42 PM PST 24
Peak memory 198120 kb
Host smart-438fce65-a113-49c5-99b0-3a280115020b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231879851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3231879851
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.811724614
Short name T583
Test name
Test status
Simulation time 47118849 ps
CPU time 1.07 seconds
Started Jan 17 03:40:33 PM PST 24
Finished Jan 17 03:40:35 PM PST 24
Peak memory 195864 kb
Host smart-59c91f42-2211-41ee-aa86-a9cbe46f39cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811724614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.811724614
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2337252002
Short name T301
Test name
Test status
Simulation time 182423805 ps
CPU time 1.47 seconds
Started Jan 17 03:40:37 PM PST 24
Finished Jan 17 03:40:41 PM PST 24
Peak memory 196820 kb
Host smart-3961b319-d9db-488b-b9fa-8c7ec960ea26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337252002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2337252002
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3811832417
Short name T533
Test name
Test status
Simulation time 24449933827 ps
CPU time 170.86 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:43:29 PM PST 24
Peak memory 198224 kb
Host smart-7a9bbd99-1f67-48d5-b0a2-30b4c54aab4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811832417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3811832417
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3806948700
Short name T541
Test name
Test status
Simulation time 65417047425 ps
CPU time 1752.43 seconds
Started Jan 17 03:40:34 PM PST 24
Finished Jan 17 04:09:49 PM PST 24
Peak memory 198408 kb
Host smart-b51ff199-a2c0-44b7-9849-72d9e7d1bf7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3806948700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3806948700
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3749258654
Short name T731
Test name
Test status
Simulation time 32253218 ps
CPU time 0.56 seconds
Started Jan 17 03:40:41 PM PST 24
Finished Jan 17 03:40:49 PM PST 24
Peak memory 193996 kb
Host smart-3b548653-8243-4d85-bb71-0c4200aa874c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749258654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3749258654
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3463110056
Short name T299
Test name
Test status
Simulation time 132665695 ps
CPU time 0.96 seconds
Started Jan 17 03:40:39 PM PST 24
Finished Jan 17 03:40:42 PM PST 24
Peak memory 196064 kb
Host smart-f4932e27-d06a-4a05-aa50-5968354a0f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463110056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3463110056
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2284636691
Short name T628
Test name
Test status
Simulation time 2022553378 ps
CPU time 8.36 seconds
Started Jan 17 03:40:40 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 197144 kb
Host smart-b15bd542-7048-43f8-ad47-58c4db93944f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284636691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2284636691
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3394640761
Short name T224
Test name
Test status
Simulation time 91752696 ps
CPU time 0.85 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:40:40 PM PST 24
Peak memory 196080 kb
Host smart-68930ca4-e80c-4b25-8c54-12cf1a08fc3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394640761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3394640761
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1110534056
Short name T259
Test name
Test status
Simulation time 37719393 ps
CPU time 0.85 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:40 PM PST 24
Peak memory 196296 kb
Host smart-ca712b6c-f635-4e82-8661-fe80d423418a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110534056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1110534056
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2262402421
Short name T463
Test name
Test status
Simulation time 202053513 ps
CPU time 2.12 seconds
Started Jan 17 03:40:41 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 196564 kb
Host smart-16e7a391-4323-47c8-99cc-1b281ee0fd1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262402421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2262402421
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.907787786
Short name T728
Test name
Test status
Simulation time 501946550 ps
CPU time 2.89 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:40:42 PM PST 24
Peak memory 197112 kb
Host smart-3e48cd95-5ede-4502-bed9-b5b007b64704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907787786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
907787786
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3890577578
Short name T759
Test name
Test status
Simulation time 21572948 ps
CPU time 0.66 seconds
Started Jan 17 03:40:40 PM PST 24
Finished Jan 17 03:40:49 PM PST 24
Peak memory 194360 kb
Host smart-075117de-1914-4291-aa53-f1a5b45f41a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890577578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3890577578
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1505960073
Short name T290
Test name
Test status
Simulation time 55506225 ps
CPU time 0.68 seconds
Started Jan 17 03:40:43 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 195384 kb
Host smart-ce468daf-e343-40dc-b3d7-e0c71f1e1e9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505960073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1505960073
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3657463190
Short name T462
Test name
Test status
Simulation time 220293231 ps
CPU time 2.88 seconds
Started Jan 17 03:40:40 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 198096 kb
Host smart-b3041d96-4c01-48cf-a73e-4e2fc0e576c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657463190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3657463190
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.808491247
Short name T699
Test name
Test status
Simulation time 196231331 ps
CPU time 1.38 seconds
Started Jan 17 03:40:42 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 195684 kb
Host smart-d6948b93-ec04-4f5e-be63-048bae6c16df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808491247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.808491247
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1170896639
Short name T262
Test name
Test status
Simulation time 214659422 ps
CPU time 1.11 seconds
Started Jan 17 03:40:35 PM PST 24
Finished Jan 17 03:40:39 PM PST 24
Peak memory 195844 kb
Host smart-4d203277-87f4-4b89-a72f-8543e7781d10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170896639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1170896639
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3508030038
Short name T633
Test name
Test status
Simulation time 5535483331 ps
CPU time 155.77 seconds
Started Jan 17 03:40:36 PM PST 24
Finished Jan 17 03:43:15 PM PST 24
Peak memory 198272 kb
Host smart-ba0647cf-7ce9-4f84-8e4f-2244be5c85f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508030038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3508030038
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1397756707
Short name T830
Test name
Test status
Simulation time 32231032995 ps
CPU time 454.91 seconds
Started Jan 17 03:40:41 PM PST 24
Finished Jan 17 03:48:24 PM PST 24
Peak memory 198448 kb
Host smart-8cdd3996-5d95-4d33-804f-f4c194efcfff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1397756707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1397756707
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.749995867
Short name T45
Test name
Test status
Simulation time 12860477 ps
CPU time 0.58 seconds
Started Jan 17 03:40:49 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 194304 kb
Host smart-214ddeb5-bd8b-4924-9f58-ac5420f89933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749995867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.749995867
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3126976651
Short name T450
Test name
Test status
Simulation time 176342309 ps
CPU time 0.96 seconds
Started Jan 17 03:40:44 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 196592 kb
Host smart-d74aabde-88f4-48e9-87b9-ec391b5c2062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126976651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3126976651
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.379723504
Short name T688
Test name
Test status
Simulation time 1258870070 ps
CPU time 11.06 seconds
Started Jan 17 03:40:47 PM PST 24
Finished Jan 17 03:41:00 PM PST 24
Peak memory 195460 kb
Host smart-c4ae20fc-be3e-4b42-ae87-cece4c080fba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379723504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.379723504
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.645834561
Short name T804
Test name
Test status
Simulation time 174810867 ps
CPU time 1.06 seconds
Started Jan 17 03:40:45 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 196648 kb
Host smart-06041f37-af78-4044-bf67-8523aad780a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645834561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.645834561
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1336553783
Short name T409
Test name
Test status
Simulation time 58663475 ps
CPU time 0.81 seconds
Started Jan 17 03:40:40 PM PST 24
Finished Jan 17 03:40:49 PM PST 24
Peak memory 195660 kb
Host smart-bb416e63-8be7-472a-938c-16d0c8fbe738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336553783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1336553783
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4178191842
Short name T415
Test name
Test status
Simulation time 88598691 ps
CPU time 2.89 seconds
Started Jan 17 03:40:48 PM PST 24
Finished Jan 17 03:40:53 PM PST 24
Peak memory 198224 kb
Host smart-bd61b70f-d955-42c5-8a16-9d2ac0bffd0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178191842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4178191842
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2163979706
Short name T451
Test name
Test status
Simulation time 211806014 ps
CPU time 1.3 seconds
Started Jan 17 03:40:42 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 196756 kb
Host smart-4e616ab8-f4db-4be6-b3e9-905c5267dce0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163979706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2163979706
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2379202015
Short name T642
Test name
Test status
Simulation time 19105147 ps
CPU time 0.81 seconds
Started Jan 17 03:40:41 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 196088 kb
Host smart-95c9a15c-842c-4160-8725-4dd2a441ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379202015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2379202015
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3399714362
Short name T423
Test name
Test status
Simulation time 107174980 ps
CPU time 0.66 seconds
Started Jan 17 03:40:43 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 194284 kb
Host smart-cc15cc33-2b95-4775-92ac-6dfb2c9e66e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399714362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3399714362
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2306749758
Short name T460
Test name
Test status
Simulation time 165991976 ps
CPU time 2.2 seconds
Started Jan 17 03:40:46 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 197772 kb
Host smart-133ccd59-8116-4ceb-9517-626a3d3558ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306749758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2306749758
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3458949289
Short name T674
Test name
Test status
Simulation time 222554508 ps
CPU time 1 seconds
Started Jan 17 03:40:41 PM PST 24
Finished Jan 17 03:40:49 PM PST 24
Peak memory 195724 kb
Host smart-94a52806-3322-4fb0-b33b-58da86169a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458949289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3458949289
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1262455797
Short name T849
Test name
Test status
Simulation time 111248149 ps
CPU time 1.02 seconds
Started Jan 17 03:40:42 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 195820 kb
Host smart-04599633-25b2-4e80-b1a6-b699312ecb0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262455797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1262455797
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.92144999
Short name T835
Test name
Test status
Simulation time 20676667667 ps
CPU time 151.24 seconds
Started Jan 17 03:40:49 PM PST 24
Finished Jan 17 03:43:22 PM PST 24
Peak memory 198256 kb
Host smart-aede3c57-408a-40d8-af30-9307d07f1434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92144999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gp
io_stress_all.92144999
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.900867705
Short name T878
Test name
Test status
Simulation time 636870946856 ps
CPU time 1800.29 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 04:10:55 PM PST 24
Peak memory 198428 kb
Host smart-e6b5d7d6-e218-4382-a0cb-7f9be11ccb30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=900867705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.900867705
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1614065582
Short name T639
Test name
Test status
Simulation time 55138207 ps
CPU time 0.56 seconds
Started Jan 17 03:40:47 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 194036 kb
Host smart-ecec7ee4-a103-47b8-8bb9-b979b8cdc5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614065582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1614065582
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4174085937
Short name T422
Test name
Test status
Simulation time 172932907 ps
CPU time 0.94 seconds
Started Jan 17 03:40:51 PM PST 24
Finished Jan 17 03:40:53 PM PST 24
Peak memory 197316 kb
Host smart-9ab0f01d-76af-45ad-976f-8fb45425cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174085937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4174085937
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3284002261
Short name T619
Test name
Test status
Simulation time 159078609 ps
CPU time 8.21 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:41:03 PM PST 24
Peak memory 198148 kb
Host smart-2735914b-c609-42af-96d7-2ad921b0e0b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284002261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3284002261
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4016866112
Short name T684
Test name
Test status
Simulation time 154330026 ps
CPU time 0.94 seconds
Started Jan 17 03:40:46 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 197304 kb
Host smart-825e54eb-b5a9-42c6-a1c1-a03ba2854f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016866112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4016866112
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3903495548
Short name T531
Test name
Test status
Simulation time 296808072 ps
CPU time 1.27 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 196088 kb
Host smart-c5fd3e29-caa3-412a-aa6e-91c9e749d7ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903495548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3903495548
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.584874440
Short name T641
Test name
Test status
Simulation time 1253588004 ps
CPU time 3.16 seconds
Started Jan 17 03:40:47 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 196456 kb
Host smart-98606c85-6d58-412d-a70d-55d621918103
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584874440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.584874440
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3680838837
Short name T493
Test name
Test status
Simulation time 327837970 ps
CPU time 2.65 seconds
Started Jan 17 03:40:50 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 197016 kb
Host smart-6d5366cf-9608-43be-8d7f-5c1d9a78e412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680838837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3680838837
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4014758985
Short name T635
Test name
Test status
Simulation time 195472967 ps
CPU time 0.97 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 196096 kb
Host smart-62da74e0-646c-4980-ac65-7941111c8b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014758985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4014758985
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.709994142
Short name T253
Test name
Test status
Simulation time 14925856 ps
CPU time 0.7 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 196220 kb
Host smart-5a0722dc-3a84-480d-8343-c0838043a995
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709994142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.709994142
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.520030801
Short name T352
Test name
Test status
Simulation time 1865165706 ps
CPU time 3.36 seconds
Started Jan 17 03:40:50 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 198056 kb
Host smart-e96c2feb-97fd-4bf2-ac73-c778627f7bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520030801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.520030801
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3332880505
Short name T417
Test name
Test status
Simulation time 119334943 ps
CPU time 0.99 seconds
Started Jan 17 03:40:51 PM PST 24
Finished Jan 17 03:40:53 PM PST 24
Peak memory 195848 kb
Host smart-dd72073d-3228-45a4-ba3a-92fbfb6b05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332880505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3332880505
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3809938594
Short name T663
Test name
Test status
Simulation time 59755372 ps
CPU time 1.13 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 195876 kb
Host smart-13d5fae9-80dc-4185-9bc8-0f84078991f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809938594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3809938594
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4269619962
Short name T868
Test name
Test status
Simulation time 23817801757 ps
CPU time 150.79 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:43:25 PM PST 24
Peak memory 198244 kb
Host smart-175e35c0-342e-4713-938b-61ff269cc57c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269619962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4269619962
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3883313265
Short name T343
Test name
Test status
Simulation time 81252847993 ps
CPU time 1210.74 seconds
Started Jan 17 03:40:42 PM PST 24
Finished Jan 17 04:01:00 PM PST 24
Peak memory 198444 kb
Host smart-331e8d72-f4f5-414c-91d5-a5623b53d130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3883313265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3883313265
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1431247819
Short name T488
Test name
Test status
Simulation time 82937102 ps
CPU time 0.59 seconds
Started Jan 17 03:39:48 PM PST 24
Finished Jan 17 03:39:52 PM PST 24
Peak memory 194996 kb
Host smart-e3e7771d-5932-49ef-8c1e-164e7805d711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431247819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1431247819
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3571660597
Short name T278
Test name
Test status
Simulation time 32098441 ps
CPU time 0.71 seconds
Started Jan 17 03:39:49 PM PST 24
Finished Jan 17 03:39:52 PM PST 24
Peak memory 193852 kb
Host smart-27623745-b5b9-4fc9-9870-eb0e381e6ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571660597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3571660597
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3221127589
Short name T718
Test name
Test status
Simulation time 809239695 ps
CPU time 23.42 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:40:19 PM PST 24
Peak memory 197352 kb
Host smart-d8c63935-69f6-42b1-b22d-0df63fd87092
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221127589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3221127589
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2921271010
Short name T524
Test name
Test status
Simulation time 279974217 ps
CPU time 1.07 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 196712 kb
Host smart-6e45e388-dd49-4b65-a08e-ca6afbbf9705
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921271010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2921271010
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1315687259
Short name T430
Test name
Test status
Simulation time 1421772967 ps
CPU time 1.44 seconds
Started Jan 17 03:39:44 PM PST 24
Finished Jan 17 03:39:48 PM PST 24
Peak memory 198104 kb
Host smart-572d285d-3bc0-4a21-8d91-6c5dad1cbd10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315687259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1315687259
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.818143189
Short name T727
Test name
Test status
Simulation time 150033094 ps
CPU time 1.76 seconds
Started Jan 17 03:39:48 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 198284 kb
Host smart-51fddcf4-8ba0-4ec4-8fd9-c69b4b0825f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818143189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.818143189
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1992240217
Short name T645
Test name
Test status
Simulation time 90892685 ps
CPU time 1.36 seconds
Started Jan 17 03:39:43 PM PST 24
Finished Jan 17 03:39:48 PM PST 24
Peak memory 196608 kb
Host smart-b1c8782f-caee-4097-851a-788e6e3bbbbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992240217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1992240217
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3960662368
Short name T295
Test name
Test status
Simulation time 28681598 ps
CPU time 1.05 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 196108 kb
Host smart-3a35a6e3-e8fc-4f4e-aad5-b6c6a4656a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960662368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3960662368
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.812226053
Short name T831
Test name
Test status
Simulation time 33055913 ps
CPU time 1.27 seconds
Started Jan 17 03:39:46 PM PST 24
Finished Jan 17 03:39:51 PM PST 24
Peak memory 195932 kb
Host smart-842f4dd3-497b-48aa-b297-6593784e99cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812226053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.812226053
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1560876495
Short name T729
Test name
Test status
Simulation time 235223748 ps
CPU time 5.4 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 198164 kb
Host smart-68638194-fcaf-4a17-af57-de14f1569237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560876495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1560876495
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4113301748
Short name T56
Test name
Test status
Simulation time 36331124 ps
CPU time 0.78 seconds
Started Jan 17 03:39:49 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 213520 kb
Host smart-13a2c0a5-125b-41a6-856b-2b6746c71e64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113301748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4113301748
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2840940894
Short name T349
Test name
Test status
Simulation time 183449973 ps
CPU time 1.53 seconds
Started Jan 17 03:39:41 PM PST 24
Finished Jan 17 03:39:48 PM PST 24
Peak memory 196956 kb
Host smart-b88f322e-786e-4a6b-b7c4-2f128fbafe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840940894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2840940894
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.360614449
Short name T742
Test name
Test status
Simulation time 188187718 ps
CPU time 1.16 seconds
Started Jan 17 03:39:42 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 196332 kb
Host smart-629a7f2e-2951-445e-801b-2e5896a79a74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360614449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.360614449
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2009229452
Short name T264
Test name
Test status
Simulation time 24882968663 ps
CPU time 183 seconds
Started Jan 17 03:39:44 PM PST 24
Finished Jan 17 03:42:49 PM PST 24
Peak memory 198240 kb
Host smart-e49559cd-830d-4cd5-b6ad-ca24a52bb753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009229452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2009229452
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.326514796
Short name T863
Test name
Test status
Simulation time 163944479467 ps
CPU time 2088.56 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 04:14:40 PM PST 24
Peak memory 198412 kb
Host smart-3bb6f8f4-dbe1-489f-a041-a09f50ecd5ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=326514796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.326514796
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1361761126
Short name T44
Test name
Test status
Simulation time 39579960 ps
CPU time 0.57 seconds
Started Jan 17 03:40:45 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 194028 kb
Host smart-702c34b0-4b57-45ef-b22c-a0015d755d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361761126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1361761126
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.8962818
Short name T543
Test name
Test status
Simulation time 470637029 ps
CPU time 0.92 seconds
Started Jan 17 03:40:50 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 197112 kb
Host smart-75f31a19-7ab1-4da8-b1c9-298c949902d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8962818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.8962818
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3375094297
Short name T327
Test name
Test status
Simulation time 1833762970 ps
CPU time 23.67 seconds
Started Jan 17 03:40:49 PM PST 24
Finished Jan 17 03:41:15 PM PST 24
Peak memory 196916 kb
Host smart-9e4d591e-1ce6-45c5-b9e0-70eeab61c2f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375094297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3375094297
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2193386726
Short name T827
Test name
Test status
Simulation time 150372011 ps
CPU time 0.97 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 197248 kb
Host smart-74a38bf9-743d-420c-bac7-200f222e2291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193386726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2193386726
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2524081366
Short name T229
Test name
Test status
Simulation time 76023858 ps
CPU time 1.38 seconds
Started Jan 17 03:40:49 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 197136 kb
Host smart-363acd0f-992a-4f84-8c1c-babfffe2aca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524081366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2524081366
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.712281529
Short name T428
Test name
Test status
Simulation time 28168321 ps
CPU time 1.23 seconds
Started Jan 17 03:40:49 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 198212 kb
Host smart-9c06fd20-227a-43fd-868c-9957713e21b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712281529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.712281529
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1647315902
Short name T508
Test name
Test status
Simulation time 244134073 ps
CPU time 2.04 seconds
Started Jan 17 03:40:50 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 196952 kb
Host smart-07094199-378c-4ba4-9177-4ae8f9977a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647315902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1647315902
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.696603666
Short name T785
Test name
Test status
Simulation time 44509100 ps
CPU time 0.69 seconds
Started Jan 17 03:40:45 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 194452 kb
Host smart-b63ad882-ba94-4486-8f4d-30adac4055d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696603666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.696603666
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1668689721
Short name T296
Test name
Test status
Simulation time 27231906 ps
CPU time 0.83 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 03:40:53 PM PST 24
Peak memory 195556 kb
Host smart-e8e4df3e-eed6-490c-ad18-ab9279413205
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668689721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1668689721
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2833338684
Short name T407
Test name
Test status
Simulation time 38255957 ps
CPU time 1.85 seconds
Started Jan 17 03:40:45 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 197984 kb
Host smart-6ea0093d-e151-4dd2-8e11-5f7d0971b1d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833338684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2833338684
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1159512742
Short name T665
Test name
Test status
Simulation time 419805500 ps
CPU time 1.46 seconds
Started Jan 17 03:40:47 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 196908 kb
Host smart-d10fda13-7ca6-4bbf-8f86-d5d1de0bcc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159512742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1159512742
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2374313327
Short name T251
Test name
Test status
Simulation time 84031645 ps
CPU time 1.46 seconds
Started Jan 17 03:40:47 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 196812 kb
Host smart-84ee46ff-abc0-48f5-a85c-7e7f639fbff2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374313327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2374313327
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2580291749
Short name T567
Test name
Test status
Simulation time 9445329271 ps
CPU time 69.28 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 198256 kb
Host smart-ccf05020-387e-4699-a46d-95be9829774c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580291749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2580291749
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.815469081
Short name T627
Test name
Test status
Simulation time 257062758461 ps
CPU time 1448.69 seconds
Started Jan 17 03:40:51 PM PST 24
Finished Jan 17 04:05:01 PM PST 24
Peak memory 198564 kb
Host smart-dc77e0ba-d541-4f32-9a9c-e449605a4b9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=815469081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.815469081
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2897164123
Short name T539
Test name
Test status
Simulation time 46526507 ps
CPU time 0.59 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:02 PM PST 24
Peak memory 194248 kb
Host smart-c00443f4-02a9-4815-8aa0-044ec40adfa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897164123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2897164123
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.165116053
Short name T348
Test name
Test status
Simulation time 98912439 ps
CPU time 0.66 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:40:56 PM PST 24
Peak memory 194100 kb
Host smart-2d678da6-d020-4093-9790-dcf8cacbf72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165116053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.165116053
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1313240608
Short name T621
Test name
Test status
Simulation time 675988662 ps
CPU time 25.23 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 195620 kb
Host smart-f2d7259c-d6f7-4b23-9a48-39a01dab699d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313240608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1313240608
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3534189002
Short name T218
Test name
Test status
Simulation time 338530737 ps
CPU time 0.94 seconds
Started Jan 17 03:40:56 PM PST 24
Finished Jan 17 03:40:57 PM PST 24
Peak memory 196084 kb
Host smart-ecb391c9-d282-438d-9d45-83bbf17c9e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534189002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3534189002
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3926161649
Short name T98
Test name
Test status
Simulation time 44476230 ps
CPU time 1.16 seconds
Started Jan 17 03:40:50 PM PST 24
Finished Jan 17 03:40:53 PM PST 24
Peak memory 196316 kb
Host smart-bbc14aa5-6c8f-4fe0-8be0-7bd767014a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926161649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3926161649
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4124878750
Short name T571
Test name
Test status
Simulation time 44424101 ps
CPU time 1.49 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 196624 kb
Host smart-74e93798-acf0-4256-ac62-6a02d73f55bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124878750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4124878750
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3732126399
Short name T432
Test name
Test status
Simulation time 162943372 ps
CPU time 2.71 seconds
Started Jan 17 03:40:50 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 197332 kb
Host smart-5f7f52d3-3592-4687-b248-9e9499ec5212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732126399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3732126399
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1139178573
Short name T669
Test name
Test status
Simulation time 238568494 ps
CPU time 1.19 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:55 PM PST 24
Peak memory 196128 kb
Host smart-70ee820b-9f20-4a4c-9ce2-ac531630171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139178573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1139178573
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1301291221
Short name T573
Test name
Test status
Simulation time 74154583 ps
CPU time 0.93 seconds
Started Jan 17 03:40:55 PM PST 24
Finished Jan 17 03:40:57 PM PST 24
Peak memory 196820 kb
Host smart-60612460-8030-4ef8-b438-5fea4726fc0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301291221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1301291221
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2995826235
Short name T287
Test name
Test status
Simulation time 50300212 ps
CPU time 2.3 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:40:57 PM PST 24
Peak memory 198092 kb
Host smart-7edbec0e-bd9a-4243-8691-56d4cfbee300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995826235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2995826235
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2363320545
Short name T685
Test name
Test status
Simulation time 159810189 ps
CPU time 1.32 seconds
Started Jan 17 03:40:46 PM PST 24
Finished Jan 17 03:40:51 PM PST 24
Peak memory 197868 kb
Host smart-3449350f-9cae-4bad-ab2c-18d9846f6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363320545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2363320545
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3609774188
Short name T210
Test name
Test status
Simulation time 59920080 ps
CPU time 0.99 seconds
Started Jan 17 03:40:46 PM PST 24
Finished Jan 17 03:40:50 PM PST 24
Peak memory 195632 kb
Host smart-463a5b0a-c6ad-4d4a-a11b-2bf7a4452c28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609774188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3609774188
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3312423570
Short name T459
Test name
Test status
Simulation time 2304802460 ps
CPU time 36.16 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:41:30 PM PST 24
Peak memory 198008 kb
Host smart-44864a56-06d0-47d6-9ea9-448f7ecd87be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312423570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3312423570
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3003094548
Short name T452
Test name
Test status
Simulation time 151002673600 ps
CPU time 1849.68 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 04:11:43 PM PST 24
Peak memory 198408 kb
Host smart-6ea9e2ff-db20-49dc-8316-8e8787b8ca97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3003094548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3003094548
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1344707069
Short name T805
Test name
Test status
Simulation time 13492933 ps
CPU time 0.62 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:02 PM PST 24
Peak memory 194020 kb
Host smart-46de84cf-fd5a-4bbd-85c0-c081e292de1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344707069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1344707069
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3317136809
Short name T477
Test name
Test status
Simulation time 17305177 ps
CPU time 0.65 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 194172 kb
Host smart-a3018402-f95d-49cf-b7fe-950b49988f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317136809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3317136809
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1568416897
Short name T225
Test name
Test status
Simulation time 3944793195 ps
CPU time 28.1 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:41:22 PM PST 24
Peak memory 196688 kb
Host smart-0b4dcbd8-5a85-4063-83c6-c81e712f1145
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568416897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1568416897
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3738617394
Short name T457
Test name
Test status
Simulation time 301295090 ps
CPU time 1.15 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:03 PM PST 24
Peak memory 196788 kb
Host smart-f95b4451-9be9-476e-b3e0-91f59d096294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738617394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3738617394
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1932110267
Short name T334
Test name
Test status
Simulation time 300862080 ps
CPU time 0.99 seconds
Started Jan 17 03:40:52 PM PST 24
Finished Jan 17 03:40:54 PM PST 24
Peak memory 196064 kb
Host smart-5254da6d-084e-451c-839e-5bd22488a21a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932110267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1932110267
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3358424264
Short name T102
Test name
Test status
Simulation time 39824499 ps
CPU time 1.68 seconds
Started Jan 17 03:40:56 PM PST 24
Finished Jan 17 03:40:59 PM PST 24
Peak memory 196552 kb
Host smart-945bcd36-7f10-47a5-931a-bbbb0606d49e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358424264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3358424264
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.604505220
Short name T386
Test name
Test status
Simulation time 918010492 ps
CPU time 3.3 seconds
Started Jan 17 03:40:56 PM PST 24
Finished Jan 17 03:41:00 PM PST 24
Peak memory 195980 kb
Host smart-8b5779b2-41e5-4355-9204-83677811c3a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604505220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
604505220
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4182297973
Short name T413
Test name
Test status
Simulation time 15668456 ps
CPU time 0.69 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:40:56 PM PST 24
Peak memory 194428 kb
Host smart-43bfcfa2-6c39-4293-9b81-1ffd9d88248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182297973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4182297973
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1076386852
Short name T550
Test name
Test status
Simulation time 35702098 ps
CPU time 0.93 seconds
Started Jan 17 03:40:56 PM PST 24
Finished Jan 17 03:40:57 PM PST 24
Peak memory 196852 kb
Host smart-ab2c154e-b9d6-44dc-97ba-95fb6f7d1b06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076386852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1076386852
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2939530463
Short name T613
Test name
Test status
Simulation time 116170889 ps
CPU time 3.02 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:05 PM PST 24
Peak memory 198100 kb
Host smart-edb0fce6-b1e3-41f5-bac6-7b3708331c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939530463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2939530463
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2836694955
Short name T540
Test name
Test status
Simulation time 83291538 ps
CPU time 1.44 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:40:56 PM PST 24
Peak memory 196820 kb
Host smart-6f7a385e-4e92-4366-aef8-93b8798732d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836694955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2836694955
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3791387034
Short name T62
Test name
Test status
Simulation time 89248788 ps
CPU time 1.28 seconds
Started Jan 17 03:40:49 PM PST 24
Finished Jan 17 03:40:52 PM PST 24
Peak memory 196348 kb
Host smart-29be887c-1284-4efb-ba52-fc432e97ba3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791387034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3791387034
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3800604502
Short name T793
Test name
Test status
Simulation time 31176590356 ps
CPU time 94.61 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:42:28 PM PST 24
Peak memory 198268 kb
Host smart-d675b524-00c2-4c0c-9326-580d0b1b5a85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800604502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3800604502
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2937949777
Short name T420
Test name
Test status
Simulation time 442890488131 ps
CPU time 865.89 seconds
Started Jan 17 03:40:53 PM PST 24
Finished Jan 17 03:55:19 PM PST 24
Peak memory 198420 kb
Host smart-94a621c1-214e-4277-8311-2c62960dc29c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2937949777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2937949777
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2614089361
Short name T46
Test name
Test status
Simulation time 39826098 ps
CPU time 0.6 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:03 PM PST 24
Peak memory 194776 kb
Host smart-42e6b9a9-ccf3-4c63-8db7-e3cdb910fa12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614089361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2614089361
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1526999066
Short name T527
Test name
Test status
Simulation time 39891877 ps
CPU time 0.9 seconds
Started Jan 17 03:41:02 PM PST 24
Finished Jan 17 03:41:03 PM PST 24
Peak memory 196256 kb
Host smart-c1f2a2b4-ec0e-4642-8c22-0a2b5ee31b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526999066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1526999066
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4168996984
Short name T214
Test name
Test status
Simulation time 86622481 ps
CPU time 4.15 seconds
Started Jan 17 03:41:03 PM PST 24
Finished Jan 17 03:41:08 PM PST 24
Peak memory 195964 kb
Host smart-3107f491-b141-4843-b64d-7cee8bf30420
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168996984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4168996984
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.166714143
Short name T414
Test name
Test status
Simulation time 79244560 ps
CPU time 1.02 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:40:56 PM PST 24
Peak memory 198000 kb
Host smart-158a51b1-dbaf-4b7c-829b-8529cdcb7f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166714143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.166714143
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2507751493
Short name T436
Test name
Test status
Simulation time 74391885 ps
CPU time 1.44 seconds
Started Jan 17 03:41:02 PM PST 24
Finished Jan 17 03:41:04 PM PST 24
Peak memory 198160 kb
Host smart-40c67225-8e79-4e90-9319-2b13bc6e627f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507751493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2507751493
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.218532047
Short name T765
Test name
Test status
Simulation time 53689124 ps
CPU time 1.37 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:04 PM PST 24
Peak memory 196660 kb
Host smart-4dc5a45b-c2eb-4abe-9914-cff3909a566d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218532047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.218532047
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2627126260
Short name T605
Test name
Test status
Simulation time 363993623 ps
CPU time 2.62 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:05 PM PST 24
Peak memory 197336 kb
Host smart-fd8ae83d-a56c-4cf9-be71-bb512faeee39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627126260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2627126260
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.4119332045
Short name T392
Test name
Test status
Simulation time 59282351 ps
CPU time 0.8 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:02 PM PST 24
Peak memory 196248 kb
Host smart-80fc4278-8ec9-4604-97fb-d64af7d5ce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119332045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.4119332045
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1031029691
Short name T648
Test name
Test status
Simulation time 95899174 ps
CPU time 1.12 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:40:56 PM PST 24
Peak memory 196084 kb
Host smart-5d0a5739-b6b6-4acc-9d1b-88637cdd9ec3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031029691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1031029691
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.434821605
Short name T596
Test name
Test status
Simulation time 805728117 ps
CPU time 3.92 seconds
Started Jan 17 03:40:54 PM PST 24
Finished Jan 17 03:40:59 PM PST 24
Peak memory 197988 kb
Host smart-f586b69d-8088-4709-85e4-1f42a9ebbc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434821605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.434821605
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2726494676
Short name T395
Test name
Test status
Simulation time 470087683 ps
CPU time 1.06 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:03 PM PST 24
Peak memory 196612 kb
Host smart-7bf41617-f750-4624-965c-35158c31e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726494676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2726494676
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3475581169
Short name T730
Test name
Test status
Simulation time 75277878 ps
CPU time 1.37 seconds
Started Jan 17 03:40:55 PM PST 24
Finished Jan 17 03:40:57 PM PST 24
Peak memory 196904 kb
Host smart-b86d0f31-0b35-4375-95ef-3ff347d4c0f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475581169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3475581169
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3781936035
Short name T236
Test name
Test status
Simulation time 8427744815 ps
CPU time 198.59 seconds
Started Jan 17 03:40:57 PM PST 24
Finished Jan 17 03:44:16 PM PST 24
Peak memory 198224 kb
Host smart-564d71ef-d865-4ebc-8b11-fe4259949ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781936035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3781936035
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3817606093
Short name T474
Test name
Test status
Simulation time 173554360384 ps
CPU time 648.9 seconds
Started Jan 17 03:40:59 PM PST 24
Finished Jan 17 03:51:48 PM PST 24
Peak memory 198356 kb
Host smart-ab365ddd-6b81-42a0-a38b-6cf66e2517f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3817606093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3817606093
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1318355686
Short name T283
Test name
Test status
Simulation time 34552223 ps
CPU time 0.6 seconds
Started Jan 17 03:41:06 PM PST 24
Finished Jan 17 03:41:08 PM PST 24
Peak memory 193992 kb
Host smart-5f23c7f1-c354-4655-8cfe-15959c68d770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318355686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1318355686
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2436800610
Short name T733
Test name
Test status
Simulation time 42006418 ps
CPU time 0.88 seconds
Started Jan 17 03:40:56 PM PST 24
Finished Jan 17 03:40:57 PM PST 24
Peak memory 196664 kb
Host smart-88b936f1-609d-4131-9a47-29156252a803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436800610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2436800610
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2929003715
Short name T668
Test name
Test status
Simulation time 4811951548 ps
CPU time 20.16 seconds
Started Jan 17 03:41:02 PM PST 24
Finished Jan 17 03:41:23 PM PST 24
Peak memory 197128 kb
Host smart-853ad38a-85fc-406e-89cf-c78cb45cc763
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929003715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2929003715
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2748805934
Short name T877
Test name
Test status
Simulation time 65145714 ps
CPU time 0.96 seconds
Started Jan 17 03:41:04 PM PST 24
Finished Jan 17 03:41:08 PM PST 24
Peak memory 197076 kb
Host smart-0b5bdc74-4bcd-4d28-a98a-75d26e054b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748805934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2748805934
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.966052439
Short name T95
Test name
Test status
Simulation time 25291661 ps
CPU time 0.7 seconds
Started Jan 17 03:41:03 PM PST 24
Finished Jan 17 03:41:05 PM PST 24
Peak memory 195092 kb
Host smart-03f8935d-5653-47e0-b165-425afd5270d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966052439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.966052439
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2837043710
Short name T370
Test name
Test status
Simulation time 84806811 ps
CPU time 3.37 seconds
Started Jan 17 03:41:04 PM PST 24
Finished Jan 17 03:41:11 PM PST 24
Peak memory 198228 kb
Host smart-824f37b5-a029-40c3-9677-44b37bef94b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837043710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2837043710
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2135406031
Short name T852
Test name
Test status
Simulation time 199380504 ps
CPU time 3.01 seconds
Started Jan 17 03:41:05 PM PST 24
Finished Jan 17 03:41:10 PM PST 24
Peak memory 198176 kb
Host smart-ed142b72-863c-4760-8c6f-e81ede47e6d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135406031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2135406031
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3217922633
Short name T862
Test name
Test status
Simulation time 47789042 ps
CPU time 0.8 seconds
Started Jan 17 03:40:58 PM PST 24
Finished Jan 17 03:40:59 PM PST 24
Peak memory 196248 kb
Host smart-9596ad20-289a-42e9-b382-d20d98927c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217922633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3217922633
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.98655674
Short name T585
Test name
Test status
Simulation time 675374441 ps
CPU time 0.96 seconds
Started Jan 17 03:40:59 PM PST 24
Finished Jan 17 03:41:01 PM PST 24
Peak memory 195944 kb
Host smart-45241121-a7ed-4750-9cae-4f475088d03c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98655674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup_
pulldown.98655674
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2597703250
Short name T617
Test name
Test status
Simulation time 622119391 ps
CPU time 5.09 seconds
Started Jan 17 03:41:05 PM PST 24
Finished Jan 17 03:41:13 PM PST 24
Peak memory 198140 kb
Host smart-0e4dab30-16da-4f4b-99e1-0f835d5d23f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597703250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2597703250
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3875344021
Short name T491
Test name
Test status
Simulation time 159905488 ps
CPU time 1.08 seconds
Started Jan 17 03:41:01 PM PST 24
Finished Jan 17 03:41:02 PM PST 24
Peak memory 195648 kb
Host smart-ad3e5b98-8092-4e95-a352-d0429f0f3a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875344021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3875344021
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2383079674
Short name T716
Test name
Test status
Simulation time 86295314 ps
CPU time 1.26 seconds
Started Jan 17 03:41:05 PM PST 24
Finished Jan 17 03:41:09 PM PST 24
Peak memory 196340 kb
Host smart-58eaa771-3c4d-457c-b351-c48e748fe9cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383079674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2383079674
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2289059410
Short name T848
Test name
Test status
Simulation time 24328487497 ps
CPU time 169.75 seconds
Started Jan 17 03:41:04 PM PST 24
Finished Jan 17 03:43:57 PM PST 24
Peak memory 198240 kb
Host smart-cf1f8975-3908-4d8c-9527-6f130b99ccc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289059410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2289059410
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.611110072
Short name T791
Test name
Test status
Simulation time 34040956925 ps
CPU time 307.86 seconds
Started Jan 17 03:41:11 PM PST 24
Finished Jan 17 03:46:24 PM PST 24
Peak memory 198416 kb
Host smart-d2c1581e-2153-419f-b9ec-b363222f4374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=611110072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.611110072
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1435327766
Short name T865
Test name
Test status
Simulation time 31133006 ps
CPU time 0.55 seconds
Started Jan 17 03:41:13 PM PST 24
Finished Jan 17 03:41:16 PM PST 24
Peak memory 192740 kb
Host smart-7972f6a2-f7d7-492b-9260-ec418e7c5aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435327766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1435327766
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2246622564
Short name T692
Test name
Test status
Simulation time 16363210 ps
CPU time 0.7 seconds
Started Jan 17 03:41:06 PM PST 24
Finished Jan 17 03:41:09 PM PST 24
Peak memory 194052 kb
Host smart-f2de905b-a4e7-4349-a32a-d9fb6fefbaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246622564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2246622564
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1721687307
Short name T883
Test name
Test status
Simulation time 2449238615 ps
CPU time 21.88 seconds
Started Jan 17 03:41:15 PM PST 24
Finished Jan 17 03:41:38 PM PST 24
Peak memory 198280 kb
Host smart-5694a34b-6b57-41df-bbfe-20ef1400c2c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721687307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1721687307
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.934755310
Short name T438
Test name
Test status
Simulation time 98208241 ps
CPU time 0.76 seconds
Started Jan 17 03:41:12 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 196716 kb
Host smart-f46ebea6-43e7-44c6-affb-63b8761eb8af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934755310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.934755310
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2546098967
Short name T484
Test name
Test status
Simulation time 70565402 ps
CPU time 1.05 seconds
Started Jan 17 03:41:03 PM PST 24
Finished Jan 17 03:41:07 PM PST 24
Peak memory 195920 kb
Host smart-364ff6cf-db3a-463a-a72e-73400a8fb75c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546098967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2546098967
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3686897723
Short name T857
Test name
Test status
Simulation time 243734274 ps
CPU time 2.5 seconds
Started Jan 17 03:41:10 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 197424 kb
Host smart-d7bbac08-cf1e-4528-9215-9a445d166b14
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686897723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3686897723
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2937746405
Short name T587
Test name
Test status
Simulation time 158491888 ps
CPU time 3.52 seconds
Started Jan 17 03:41:06 PM PST 24
Finished Jan 17 03:41:11 PM PST 24
Peak memory 197044 kb
Host smart-689885f0-a6a6-41dc-90fe-026475a02368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937746405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2937746405
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3537626874
Short name T871
Test name
Test status
Simulation time 145498055 ps
CPU time 1.15 seconds
Started Jan 17 03:41:09 PM PST 24
Finished Jan 17 03:41:16 PM PST 24
Peak memory 196232 kb
Host smart-16cf0d0b-c2e7-493d-9de7-66981195d6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537626874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3537626874
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2459528097
Short name T289
Test name
Test status
Simulation time 107944166 ps
CPU time 1.14 seconds
Started Jan 17 03:41:07 PM PST 24
Finished Jan 17 03:41:10 PM PST 24
Peak memory 196960 kb
Host smart-b19a9476-1df3-42f1-b830-5ac04990211d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459528097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2459528097
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.826298956
Short name T750
Test name
Test status
Simulation time 363107129 ps
CPU time 5.96 seconds
Started Jan 17 03:41:10 PM PST 24
Finished Jan 17 03:41:22 PM PST 24
Peak memory 198100 kb
Host smart-67f4b084-ae0f-4402-96bd-5d7a2a4c277a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826298956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.826298956
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.572509662
Short name T244
Test name
Test status
Simulation time 230523402 ps
CPU time 1.16 seconds
Started Jan 17 03:41:03 PM PST 24
Finished Jan 17 03:41:05 PM PST 24
Peak memory 195884 kb
Host smart-18de34de-cce3-403e-9ee2-58d16cceea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572509662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.572509662
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3122892539
Short name T242
Test name
Test status
Simulation time 110137945 ps
CPU time 0.99 seconds
Started Jan 17 03:41:07 PM PST 24
Finished Jan 17 03:41:09 PM PST 24
Peak memory 195616 kb
Host smart-04029d54-6231-4e1c-8773-39e9cdd3ed22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122892539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3122892539
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1456583166
Short name T760
Test name
Test status
Simulation time 27411781849 ps
CPU time 103.06 seconds
Started Jan 17 03:41:17 PM PST 24
Finished Jan 17 03:43:02 PM PST 24
Peak memory 198256 kb
Host smart-fc94ef3c-ae9f-4175-9d69-a650111fcdf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456583166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1456583166
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3376960494
Short name T368
Test name
Test status
Simulation time 50319941 ps
CPU time 0.56 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 194776 kb
Host smart-db725c26-08bb-401e-861c-93c80a64c763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376960494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3376960494
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2172568032
Short name T273
Test name
Test status
Simulation time 18973960 ps
CPU time 0.63 seconds
Started Jan 17 03:41:17 PM PST 24
Finished Jan 17 03:41:19 PM PST 24
Peak memory 194044 kb
Host smart-b4ae9a9b-8356-4a80-8f06-29cb88b6a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172568032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2172568032
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2902287913
Short name T234
Test name
Test status
Simulation time 665463883 ps
CPU time 21.09 seconds
Started Jan 17 03:41:12 PM PST 24
Finished Jan 17 03:41:37 PM PST 24
Peak memory 198140 kb
Host smart-e7fba030-a344-4333-be9e-9662930c4662
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902287913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2902287913
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3610226301
Short name T365
Test name
Test status
Simulation time 35782651 ps
CPU time 0.78 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 196016 kb
Host smart-7045c783-626e-490e-8681-5a4faea87bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610226301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3610226301
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1392941925
Short name T458
Test name
Test status
Simulation time 336403269 ps
CPU time 1.27 seconds
Started Jan 17 03:41:11 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 196952 kb
Host smart-e5d490d5-5cf5-47cb-8278-2521dd5ba596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392941925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1392941925
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4038142106
Short name T517
Test name
Test status
Simulation time 338469376 ps
CPU time 3.37 seconds
Started Jan 17 03:41:09 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 198316 kb
Host smart-02f86275-04e2-4a71-b417-54c6898e471d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038142106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4038142106
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2862987757
Short name T653
Test name
Test status
Simulation time 143915646 ps
CPU time 2.31 seconds
Started Jan 17 03:41:11 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 196644 kb
Host smart-d3351e17-9684-49ca-8075-3b1d3038d4b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862987757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2862987757
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1092848980
Short name T784
Test name
Test status
Simulation time 72787193 ps
CPU time 0.86 seconds
Started Jan 17 03:41:14 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 196700 kb
Host smart-15a79dcd-3cee-438b-899f-19cc17b5423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092848980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1092848980
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4151966661
Short name T256
Test name
Test status
Simulation time 161628474 ps
CPU time 1.13 seconds
Started Jan 17 03:41:20 PM PST 24
Finished Jan 17 03:41:23 PM PST 24
Peak memory 196796 kb
Host smart-9d70a79b-f952-4b2f-a244-ffb9b4873d7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151966661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4151966661
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.626151347
Short name T293
Test name
Test status
Simulation time 367261424 ps
CPU time 1.66 seconds
Started Jan 17 03:41:12 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 197976 kb
Host smart-dc613436-dc15-4e90-a492-928a59a14a23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626151347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.626151347
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.249555914
Short name T212
Test name
Test status
Simulation time 73225944 ps
CPU time 1.38 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 03:41:21 PM PST 24
Peak memory 196624 kb
Host smart-2e9eb035-c7b3-468e-842f-d9225ebe2842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249555914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.249555914
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3176276459
Short name T514
Test name
Test status
Simulation time 85209747 ps
CPU time 1.47 seconds
Started Jan 17 03:41:09 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 198088 kb
Host smart-5a892b67-308f-4b7b-bd8c-e9e1a9ee833a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176276459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3176276459
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2205830996
Short name T320
Test name
Test status
Simulation time 7198812503 ps
CPU time 23.18 seconds
Started Jan 17 03:41:17 PM PST 24
Finished Jan 17 03:41:41 PM PST 24
Peak memory 198216 kb
Host smart-3c08a46d-f428-4a61-9db3-cffb484039ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205830996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2205830996
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.983507084
Short name T322
Test name
Test status
Simulation time 15794356348 ps
CPU time 335.87 seconds
Started Jan 17 03:41:13 PM PST 24
Finished Jan 17 03:46:52 PM PST 24
Peak memory 198408 kb
Host smart-16f1307a-568d-49a5-a011-fba80c631bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=983507084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.983507084
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3911675697
Short name T649
Test name
Test status
Simulation time 11562307 ps
CPU time 0.58 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:18 PM PST 24
Peak memory 194776 kb
Host smart-494b1c7e-6993-4279-a029-f40b383ec644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911675697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3911675697
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1230281225
Short name T745
Test name
Test status
Simulation time 41092636 ps
CPU time 0.75 seconds
Started Jan 17 03:41:14 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 195308 kb
Host smart-cc0857b4-b5bf-4487-bd12-ed3dc8b88015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230281225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1230281225
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.619639756
Short name T473
Test name
Test status
Simulation time 934645369 ps
CPU time 6.7 seconds
Started Jan 17 03:41:20 PM PST 24
Finished Jan 17 03:41:28 PM PST 24
Peak memory 197052 kb
Host smart-fc9f4030-022a-45d7-b36a-354d00834b19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619639756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.619639756
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3409827206
Short name T346
Test name
Test status
Simulation time 142561831 ps
CPU time 1.07 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:19 PM PST 24
Peak memory 196692 kb
Host smart-9a1aec40-77d5-4416-8984-71c6edf746a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409827206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3409827206
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1785135922
Short name T378
Test name
Test status
Simulation time 965660317 ps
CPU time 1.11 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 03:41:21 PM PST 24
Peak memory 196012 kb
Host smart-8831c27b-c3fb-4554-b57f-c8194b27bb31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785135922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1785135922
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3548081287
Short name T568
Test name
Test status
Simulation time 1026115076 ps
CPU time 2.69 seconds
Started Jan 17 03:41:17 PM PST 24
Finished Jan 17 03:41:21 PM PST 24
Peak memory 198140 kb
Host smart-c95a81bd-9e6a-42b7-bb74-a68a2639f00e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548081287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3548081287
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1390477750
Short name T602
Test name
Test status
Simulation time 108756621 ps
CPU time 1.85 seconds
Started Jan 17 03:41:19 PM PST 24
Finished Jan 17 03:41:22 PM PST 24
Peak memory 196612 kb
Host smart-3e8b895b-4339-4399-ad4c-63dd315e783c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390477750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1390477750
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3394989422
Short name T809
Test name
Test status
Simulation time 418345003 ps
CPU time 1.3 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:19 PM PST 24
Peak memory 197264 kb
Host smart-29c8ec89-faa0-4e31-969b-e407773f5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394989422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3394989422
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.155533995
Short name T391
Test name
Test status
Simulation time 16910033 ps
CPU time 0.8 seconds
Started Jan 17 03:41:21 PM PST 24
Finished Jan 17 03:41:22 PM PST 24
Peak memory 196248 kb
Host smart-e27c20f6-ccbd-445a-9ab9-ff2894fa9ee4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155533995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.155533995
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.800984090
Short name T746
Test name
Test status
Simulation time 190990117 ps
CPU time 2.99 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:21 PM PST 24
Peak memory 198188 kb
Host smart-7b0f0ed2-6555-4027-aa80-ee9f301f9e51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800984090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.800984090
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2806924874
Short name T855
Test name
Test status
Simulation time 73260769 ps
CPU time 1.25 seconds
Started Jan 17 03:41:09 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 195836 kb
Host smart-080cfb3a-32ea-43b0-a9ae-4c585ef104f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806924874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2806924874
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4017746564
Short name T228
Test name
Test status
Simulation time 88781328 ps
CPU time 1.27 seconds
Started Jan 17 03:41:14 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 197280 kb
Host smart-317e9f4d-4a7e-489d-8c8f-0ca28df26312
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017746564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4017746564
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.299855943
Short name T303
Test name
Test status
Simulation time 5907382845 ps
CPU time 68.75 seconds
Started Jan 17 03:41:15 PM PST 24
Finished Jan 17 03:42:25 PM PST 24
Peak memory 198252 kb
Host smart-1feb8d6f-ffc7-4de3-8031-eaba449d7635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299855943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.299855943
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3362168530
Short name T723
Test name
Test status
Simulation time 319042443315 ps
CPU time 2565.71 seconds
Started Jan 17 03:41:13 PM PST 24
Finished Jan 17 04:24:02 PM PST 24
Peak memory 198416 kb
Host smart-87235d46-1df3-46e1-adb3-ffe31963ce64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3362168530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3362168530
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.539844599
Short name T800
Test name
Test status
Simulation time 30321551 ps
CPU time 0.55 seconds
Started Jan 17 03:41:20 PM PST 24
Finished Jan 17 03:41:22 PM PST 24
Peak memory 194000 kb
Host smart-4f7a23ba-42c5-4d4d-96dd-c30c6204e023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539844599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.539844599
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1694324475
Short name T847
Test name
Test status
Simulation time 69853057 ps
CPU time 0.8 seconds
Started Jan 17 03:41:20 PM PST 24
Finished Jan 17 03:41:22 PM PST 24
Peak memory 196112 kb
Host smart-601d60f2-ef59-4dc5-bb95-de60fc801b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694324475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1694324475
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.171244247
Short name T544
Test name
Test status
Simulation time 1772194609 ps
CPU time 15.98 seconds
Started Jan 17 03:41:19 PM PST 24
Finished Jan 17 03:41:36 PM PST 24
Peak memory 195692 kb
Host smart-1f3617d1-84a9-4b5e-b73b-077ddba17013
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171244247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.171244247
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2562447508
Short name T268
Test name
Test status
Simulation time 45038282 ps
CPU time 0.82 seconds
Started Jan 17 03:41:21 PM PST 24
Finished Jan 17 03:41:23 PM PST 24
Peak memory 195920 kb
Host smart-ad69fd0e-3d49-44ea-83d3-e2633b7188c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562447508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2562447508
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2551213269
Short name T874
Test name
Test status
Simulation time 105573072 ps
CPU time 0.96 seconds
Started Jan 17 03:41:14 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 196708 kb
Host smart-4fab3f7d-7a06-4b81-84f3-ce4744ab2287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551213269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2551213269
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2697959349
Short name T461
Test name
Test status
Simulation time 261580445 ps
CPU time 1.08 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:28 PM PST 24
Peak memory 196140 kb
Host smart-2120372d-5e6e-4a10-adb8-20d730030d15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697959349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2697959349
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4127002345
Short name T380
Test name
Test status
Simulation time 67308179 ps
CPU time 1.02 seconds
Started Jan 17 03:41:12 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 195500 kb
Host smart-93e47891-2d9a-4441-a785-f9e9e3dc58e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127002345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4127002345
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4155504798
Short name T503
Test name
Test status
Simulation time 346433208 ps
CPU time 1.26 seconds
Started Jan 17 03:41:17 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 198252 kb
Host smart-a501057e-5af8-435b-a474-34d421d29776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155504798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4155504798
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3551595419
Short name T860
Test name
Test status
Simulation time 23586263 ps
CPU time 0.89 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:25 PM PST 24
Peak memory 196028 kb
Host smart-16fd9a45-76e3-4145-81d6-e18999dfd8db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551595419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3551595419
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1507243369
Short name T833
Test name
Test status
Simulation time 101405021 ps
CPU time 4.91 seconds
Started Jan 17 03:41:16 PM PST 24
Finished Jan 17 03:41:23 PM PST 24
Peak memory 198184 kb
Host smart-a8aefee5-a5b6-42db-9f21-ff581cc23a87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507243369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1507243369
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4146650632
Short name T211
Test name
Test status
Simulation time 41932098 ps
CPU time 1.2 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 03:41:21 PM PST 24
Peak memory 196680 kb
Host smart-a211ecbd-05eb-42ad-84f1-cd4257171a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146650632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4146650632
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.956687695
Short name T773
Test name
Test status
Simulation time 79597163 ps
CPU time 1.19 seconds
Started Jan 17 03:41:23 PM PST 24
Finished Jan 17 03:41:25 PM PST 24
Peak memory 195636 kb
Host smart-92f769c6-c33c-4903-aa1d-4c81545d7d7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956687695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.956687695
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3598939105
Short name T679
Test name
Test status
Simulation time 10281238254 ps
CPU time 142.78 seconds
Started Jan 17 03:41:22 PM PST 24
Finished Jan 17 03:43:46 PM PST 24
Peak memory 197756 kb
Host smart-4eff6a2d-c619-4953-8f23-f991d98c7d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598939105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3598939105
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.4072935797
Short name T705
Test name
Test status
Simulation time 77135663310 ps
CPU time 927.47 seconds
Started Jan 17 03:41:21 PM PST 24
Finished Jan 17 03:56:50 PM PST 24
Peak memory 198304 kb
Host smart-346255a7-14c3-4d71-9dbd-f28f0977154d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4072935797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.4072935797
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3722404317
Short name T63
Test name
Test status
Simulation time 19305054 ps
CPU time 0.57 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 194760 kb
Host smart-6eb2339a-b171-4f4d-882c-a92240d1c387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722404317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3722404317
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1055114916
Short name T869
Test name
Test status
Simulation time 64620784 ps
CPU time 0.8 seconds
Started Jan 17 03:41:23 PM PST 24
Finished Jan 17 03:41:24 PM PST 24
Peak memory 195344 kb
Host smart-bbc07052-43f0-46ae-a4ec-38099d18d5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055114916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1055114916
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2455208712
Short name T740
Test name
Test status
Simulation time 309693617 ps
CPU time 9.93 seconds
Started Jan 17 03:41:22 PM PST 24
Finished Jan 17 03:41:33 PM PST 24
Peak memory 197768 kb
Host smart-182ea5c1-b67e-48f7-9c6e-226541580de9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455208712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2455208712
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2326060380
Short name T57
Test name
Test status
Simulation time 33677938 ps
CPU time 0.73 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 195472 kb
Host smart-2b96349b-8843-4cbb-9bac-2d9fb928003f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326060380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2326060380
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1145546065
Short name T247
Test name
Test status
Simulation time 175509390 ps
CPU time 1.41 seconds
Started Jan 17 03:41:23 PM PST 24
Finished Jan 17 03:41:25 PM PST 24
Peak memory 195964 kb
Host smart-302b2bc5-9b7d-4eb9-b2a6-10a1802d4dd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145546065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1145546065
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4210320816
Short name T537
Test name
Test status
Simulation time 398043513 ps
CPU time 2.22 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:27 PM PST 24
Peak memory 198264 kb
Host smart-9b31e7f7-7b78-4c55-a26b-5a1412e246d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210320816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4210320816
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1468783689
Short name T575
Test name
Test status
Simulation time 106680772 ps
CPU time 3 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:28 PM PST 24
Peak memory 195960 kb
Host smart-1c4a9ea5-dbaa-4889-8ccb-d4df53ea1af2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468783689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1468783689
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.398432254
Short name T767
Test name
Test status
Simulation time 119906299 ps
CPU time 1.26 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:29 PM PST 24
Peak memory 196812 kb
Host smart-45e1d0a7-0ff7-4da7-8f0c-ca1e08ec845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398432254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.398432254
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.520946837
Short name T326
Test name
Test status
Simulation time 180926618 ps
CPU time 1.01 seconds
Started Jan 17 03:41:23 PM PST 24
Finished Jan 17 03:41:24 PM PST 24
Peak memory 196064 kb
Host smart-274369fd-04fd-4f4c-9e91-7e7f16e420e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520946837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.520946837
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1522086878
Short name T655
Test name
Test status
Simulation time 163324716 ps
CPU time 3.26 seconds
Started Jan 17 03:41:20 PM PST 24
Finished Jan 17 03:41:24 PM PST 24
Peak memory 198092 kb
Host smart-aad9a70b-6d1a-489c-91b9-f8b6c96139e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522086878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1522086878
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2601820084
Short name T631
Test name
Test status
Simulation time 97029378 ps
CPU time 1.13 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:26 PM PST 24
Peak memory 195908 kb
Host smart-f78a7364-12d7-4a4f-b277-2cace4c75942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601820084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2601820084
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.556556011
Short name T697
Test name
Test status
Simulation time 340339576 ps
CPU time 1.17 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:26 PM PST 24
Peak memory 195980 kb
Host smart-98006afb-42af-4c22-96c2-d5602959620d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556556011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.556556011
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1537981250
Short name T872
Test name
Test status
Simulation time 15003531734 ps
CPU time 229.47 seconds
Started Jan 17 03:41:13 PM PST 24
Finished Jan 17 03:45:05 PM PST 24
Peak memory 198160 kb
Host smart-2b2f1653-29a6-49c5-8087-f25c2c077884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537981250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1537981250
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4056775947
Short name T834
Test name
Test status
Simulation time 654300244733 ps
CPU time 2336.02 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 04:20:15 PM PST 24
Peak memory 198348 kb
Host smart-b355850b-3135-462f-9fb0-b055eaab1724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4056775947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4056775947
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.311014015
Short name T471
Test name
Test status
Simulation time 12517685 ps
CPU time 0.59 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 194144 kb
Host smart-977ad453-7b61-42d6-b14c-941a7b1873ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311014015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.311014015
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.544744776
Short name T433
Test name
Test status
Simulation time 116229578 ps
CPU time 0.81 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 195460 kb
Host smart-ff7def32-0289-4876-9a9b-bef4d09b136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544744776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.544744776
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3905251659
Short name T623
Test name
Test status
Simulation time 3948445148 ps
CPU time 24.3 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 196752 kb
Host smart-fe120f40-c187-447e-bb2e-405783d1e0ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905251659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3905251659
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1140867856
Short name T643
Test name
Test status
Simulation time 273413387 ps
CPU time 0.83 seconds
Started Jan 17 03:39:48 PM PST 24
Finished Jan 17 03:39:52 PM PST 24
Peak memory 196000 kb
Host smart-2c738950-62aa-428c-a653-f3764f318ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140867856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1140867856
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1578055888
Short name T475
Test name
Test status
Simulation time 141772060 ps
CPU time 1.03 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 195908 kb
Host smart-b4cd8482-86d8-4f94-bd86-ec0303665f64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578055888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1578055888
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4170728313
Short name T486
Test name
Test status
Simulation time 167147189 ps
CPU time 3.78 seconds
Started Jan 17 03:39:46 PM PST 24
Finished Jan 17 03:39:54 PM PST 24
Peak memory 198320 kb
Host smart-122a7874-294e-4b33-a393-68612a741b37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170728313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4170728313
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2144675425
Short name T291
Test name
Test status
Simulation time 52266638 ps
CPU time 1.24 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 195748 kb
Host smart-b5f8b3ea-5f4c-4ce4-9133-1d04178bbd38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144675425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2144675425
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2513498358
Short name T828
Test name
Test status
Simulation time 37580561 ps
CPU time 0.98 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 196860 kb
Host smart-6d20b221-6061-4560-aa6e-89bf65f3eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513498358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2513498358
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3627427604
Short name T850
Test name
Test status
Simulation time 101853334 ps
CPU time 1.08 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 196776 kb
Host smart-c1f69330-901d-4760-89e0-49e47ea844bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627427604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3627427604
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.23115981
Short name T651
Test name
Test status
Simulation time 389945972 ps
CPU time 4.78 seconds
Started Jan 17 03:39:47 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 198128 kb
Host smart-ba9a0ad8-fcb2-47fd-b089-c2eaf105aa62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23115981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rando
m_long_reg_writes_reg_reads.23115981
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3616370898
Short name T24
Test name
Test status
Simulation time 309278794 ps
CPU time 0.99 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 213780 kb
Host smart-b1eea092-f16d-4cb9-b178-83e9054f1f07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616370898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3616370898
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1132546558
Short name T312
Test name
Test status
Simulation time 347779049 ps
CPU time 1.31 seconds
Started Jan 17 03:39:49 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 197244 kb
Host smart-5ef19b3f-7217-4883-a96b-a82eca21077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132546558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1132546558
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2271692290
Short name T762
Test name
Test status
Simulation time 51026550 ps
CPU time 1.05 seconds
Started Jan 17 03:39:43 PM PST 24
Finished Jan 17 03:39:47 PM PST 24
Peak memory 195636 kb
Host smart-d8e99563-ddda-4e4d-a53c-33d7688165b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271692290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2271692290
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4253540297
Short name T383
Test name
Test status
Simulation time 63587283830 ps
CPU time 178.47 seconds
Started Jan 17 03:39:45 PM PST 24
Finished Jan 17 03:42:48 PM PST 24
Peak memory 198276 kb
Host smart-6db029d7-9e5a-472d-a7fe-51c8278e6d7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253540297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4253540297
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3756736275
Short name T529
Test name
Test status
Simulation time 79946015733 ps
CPU time 1350.5 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 04:02:27 PM PST 24
Peak memory 198416 kb
Host smart-e7965aea-4f65-48af-a536-46e62fffefc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3756736275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3756736275
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3287291810
Short name T448
Test name
Test status
Simulation time 36125634 ps
CPU time 0.55 seconds
Started Jan 17 03:41:27 PM PST 24
Finished Jan 17 03:41:29 PM PST 24
Peak memory 194292 kb
Host smart-179201cf-1281-46ce-b839-98da50a8f8ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287291810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3287291810
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4293138954
Short name T601
Test name
Test status
Simulation time 144488602 ps
CPU time 0.92 seconds
Started Jan 17 03:41:18 PM PST 24
Finished Jan 17 03:41:20 PM PST 24
Peak memory 196376 kb
Host smart-c919aa33-1232-46bd-acd7-e91cb138b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293138954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4293138954
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2335015144
Short name T441
Test name
Test status
Simulation time 3884174520 ps
CPU time 27.96 seconds
Started Jan 17 03:41:25 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 197008 kb
Host smart-7412d9bf-0618-45f1-87f5-d93a9ef8c9c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335015144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2335015144
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3690785000
Short name T344
Test name
Test status
Simulation time 71570723 ps
CPU time 1 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:31 PM PST 24
Peak memory 196492 kb
Host smart-40ceddfb-946b-4293-b026-b1972a83ff9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690785000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3690785000
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.373756583
Short name T548
Test name
Test status
Simulation time 136790404 ps
CPU time 0.77 seconds
Started Jan 17 03:41:25 PM PST 24
Finished Jan 17 03:41:27 PM PST 24
Peak memory 195580 kb
Host smart-6d1709ed-59c4-4df7-bb47-cb171ba97e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373756583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.373756583
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3381105098
Short name T41
Test name
Test status
Simulation time 32414087 ps
CPU time 0.94 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:31 PM PST 24
Peak memory 196880 kb
Host smart-36d07bbc-d313-4c6c-bb5d-7e0f974e979b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381105098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3381105098
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1813405673
Short name T277
Test name
Test status
Simulation time 159964877 ps
CPU time 2.44 seconds
Started Jan 17 03:41:20 PM PST 24
Finished Jan 17 03:41:23 PM PST 24
Peak memory 197284 kb
Host smart-8e709503-5d8f-4a2b-ac95-3cae70e167e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813405673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1813405673
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1529778219
Short name T589
Test name
Test status
Simulation time 105160326 ps
CPU time 1.51 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:29 PM PST 24
Peak memory 196156 kb
Host smart-11a04be2-3443-4679-8907-cecd7882840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529778219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1529778219
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1157776350
Short name T325
Test name
Test status
Simulation time 294756827 ps
CPU time 0.87 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:28 PM PST 24
Peak memory 195352 kb
Host smart-09f50ba8-478c-4ed6-961b-f6166d7fde8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157776350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1157776350
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2931017799
Short name T479
Test name
Test status
Simulation time 539452476 ps
CPU time 3.68 seconds
Started Jan 17 03:41:25 PM PST 24
Finished Jan 17 03:41:29 PM PST 24
Peak memory 198100 kb
Host smart-46ddd4e1-f2af-40cb-a97e-c17a0da5065c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931017799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2931017799
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1574367437
Short name T738
Test name
Test status
Simulation time 165138059 ps
CPU time 1.26 seconds
Started Jan 17 03:41:14 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 196748 kb
Host smart-08f71a39-7298-428f-b9e3-5f9ea2b24fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574367437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1574367437
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.310635056
Short name T258
Test name
Test status
Simulation time 291879570 ps
CPU time 1.4 seconds
Started Jan 17 03:41:19 PM PST 24
Finished Jan 17 03:41:21 PM PST 24
Peak memory 195664 kb
Host smart-f45a8121-9bbd-4c0b-8857-15250c524fcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310635056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.310635056
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3105243530
Short name T882
Test name
Test status
Simulation time 31151179294 ps
CPU time 82.1 seconds
Started Jan 17 03:41:25 PM PST 24
Finished Jan 17 03:42:48 PM PST 24
Peak memory 198276 kb
Host smart-429e5f82-c26b-43c8-ad16-9c733d1224a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105243530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3105243530
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1133782141
Short name T310
Test name
Test status
Simulation time 91079946521 ps
CPU time 1805.5 seconds
Started Jan 17 03:41:28 PM PST 24
Finished Jan 17 04:11:35 PM PST 24
Peak memory 198352 kb
Host smart-e76d563f-bb23-4341-b72d-87397e4aafd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1133782141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1133782141
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3855804489
Short name T510
Test name
Test status
Simulation time 50333028 ps
CPU time 0.58 seconds
Started Jan 17 03:41:25 PM PST 24
Finished Jan 17 03:41:26 PM PST 24
Peak memory 195028 kb
Host smart-c81eb63d-6b2b-4eab-acfd-2124310fc738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855804489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3855804489
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2595414489
Short name T752
Test name
Test status
Simulation time 30026184 ps
CPU time 0.76 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:25 PM PST 24
Peak memory 195296 kb
Host smart-732e8ab3-124b-4967-ba31-53b8331f8ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595414489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2595414489
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1937549530
Short name T499
Test name
Test status
Simulation time 78867742 ps
CPU time 4.21 seconds
Started Jan 17 03:41:25 PM PST 24
Finished Jan 17 03:41:30 PM PST 24
Peak memory 196076 kb
Host smart-ee402365-f7ff-46e7-9db7-2f977b5a31a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937549530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1937549530
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3595821701
Short name T358
Test name
Test status
Simulation time 24243307 ps
CPU time 0.74 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:27 PM PST 24
Peak memory 195544 kb
Host smart-959875c3-2505-4185-bd15-64ffad75dbb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595821701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3595821701
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4190539152
Short name T347
Test name
Test status
Simulation time 47696830 ps
CPU time 1 seconds
Started Jan 17 03:41:28 PM PST 24
Finished Jan 17 03:41:29 PM PST 24
Peak memory 195908 kb
Host smart-805e50ec-48e1-4ab7-92f2-3791e8690b1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190539152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4190539152
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3918664892
Short name T650
Test name
Test status
Simulation time 55484608 ps
CPU time 2.16 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:27 PM PST 24
Peak memory 196492 kb
Host smart-5cc481b6-712b-4df0-bbd4-388a59ad1ebd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918664892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3918664892
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.4210787229
Short name T671
Test name
Test status
Simulation time 455745842 ps
CPU time 3.36 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:33 PM PST 24
Peak memory 198132 kb
Host smart-c7f8a154-ec02-4fd5-9fd8-955852d2bea9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210787229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.4210787229
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3174810369
Short name T866
Test name
Test status
Simulation time 187310948 ps
CPU time 0.99 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:31 PM PST 24
Peak memory 196120 kb
Host smart-f15998c9-e5b9-4448-a1b4-cf04f5107610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174810369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3174810369
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4171003709
Short name T724
Test name
Test status
Simulation time 56855206 ps
CPU time 1.16 seconds
Started Jan 17 03:41:28 PM PST 24
Finished Jan 17 03:41:30 PM PST 24
Peak memory 196252 kb
Host smart-e1ec9bd6-96fa-493b-8407-d4c35905c844
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171003709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4171003709
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1000237767
Short name T426
Test name
Test status
Simulation time 195760913 ps
CPU time 3.37 seconds
Started Jan 17 03:41:24 PM PST 24
Finished Jan 17 03:41:29 PM PST 24
Peak memory 198080 kb
Host smart-0481c2d4-64f8-4fd8-acf8-7a664161db3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000237767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1000237767
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2184090549
Short name T434
Test name
Test status
Simulation time 45983936 ps
CPU time 1.12 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:31 PM PST 24
Peak memory 195684 kb
Host smart-34478f8b-d8f9-4665-805e-3c95ba9e3121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184090549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2184090549
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.917122574
Short name T854
Test name
Test status
Simulation time 28834402 ps
CPU time 0.67 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:30 PM PST 24
Peak memory 194276 kb
Host smart-b9d9feed-bac6-4370-bd40-dec2da638d67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917122574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.917122574
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3918446238
Short name T364
Test name
Test status
Simulation time 78816355778 ps
CPU time 139.91 seconds
Started Jan 17 03:41:28 PM PST 24
Finished Jan 17 03:43:49 PM PST 24
Peak memory 198260 kb
Host smart-dc247eeb-cbef-4a53-a225-7b0952e194e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918446238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3918446238
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1563397046
Short name T879
Test name
Test status
Simulation time 191722088789 ps
CPU time 2036.53 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 04:15:23 PM PST 24
Peak memory 198388 kb
Host smart-48de8c44-6edb-44d4-b743-14b47e6a9da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1563397046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1563397046
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.534459464
Short name T341
Test name
Test status
Simulation time 119507507 ps
CPU time 0.63 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 194296 kb
Host smart-97ca3df5-1ee4-465e-b682-ffa355b276f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534459464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.534459464
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3715034855
Short name T843
Test name
Test status
Simulation time 46325919 ps
CPU time 0.87 seconds
Started Jan 17 03:41:32 PM PST 24
Finished Jan 17 03:41:33 PM PST 24
Peak memory 196484 kb
Host smart-996f48eb-2689-416a-954f-7e7631f9e58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715034855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3715034855
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.323176935
Short name T542
Test name
Test status
Simulation time 1825994542 ps
CPU time 24.44 seconds
Started Jan 17 03:41:29 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 196964 kb
Host smart-f13bacc2-e3a2-4d09-a811-3fce431fb696
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323176935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.323176935
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1274043852
Short name T222
Test name
Test status
Simulation time 52803095 ps
CPU time 0.84 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 196804 kb
Host smart-98eacb81-b721-435f-9fa3-e5f52ce79789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274043852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1274043852
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2032041095
Short name T246
Test name
Test status
Simulation time 43955362 ps
CPU time 0.97 seconds
Started Jan 17 03:41:35 PM PST 24
Finished Jan 17 03:41:39 PM PST 24
Peak memory 196144 kb
Host smart-717dd599-f1fb-47e3-911e-25b3ac699ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032041095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2032041095
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1971816697
Short name T581
Test name
Test status
Simulation time 79841227 ps
CPU time 3.17 seconds
Started Jan 17 03:41:28 PM PST 24
Finished Jan 17 03:41:32 PM PST 24
Peak memory 198332 kb
Host smart-02f155e5-7f7d-4574-8a37-d5c555d6be1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971816697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1971816697
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1643242367
Short name T704
Test name
Test status
Simulation time 58590696 ps
CPU time 1.45 seconds
Started Jan 17 03:41:31 PM PST 24
Finished Jan 17 03:41:33 PM PST 24
Peak memory 196260 kb
Host smart-02773cc0-4a96-4510-96b9-8ee4901b2910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643242367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1643242367
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2787450472
Short name T518
Test name
Test status
Simulation time 58077913 ps
CPU time 0.86 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:27 PM PST 24
Peak memory 197340 kb
Host smart-4d9d6b9e-a1b0-4475-9f1b-d0b8c0eb1fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787450472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2787450472
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3924662612
Short name T563
Test name
Test status
Simulation time 15842639 ps
CPU time 0.71 seconds
Started Jan 17 03:41:30 PM PST 24
Finished Jan 17 03:41:32 PM PST 24
Peak memory 194396 kb
Host smart-11a15bfa-d47c-4fc6-8d9f-c178f0124479
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924662612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3924662612
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2550765202
Short name T387
Test name
Test status
Simulation time 25853304 ps
CPU time 1.34 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:41:45 PM PST 24
Peak memory 198152 kb
Host smart-0c8a2430-30d7-487b-8433-6e28c4fb9782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550765202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2550765202
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2148894901
Short name T811
Test name
Test status
Simulation time 40413548 ps
CPU time 0.96 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:28 PM PST 24
Peak memory 196108 kb
Host smart-df29834d-3aea-440b-bf1b-425183da365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148894901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2148894901
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3712591474
Short name T400
Test name
Test status
Simulation time 177617822 ps
CPU time 1.02 seconds
Started Jan 17 03:41:26 PM PST 24
Finished Jan 17 03:41:28 PM PST 24
Peak memory 197500 kb
Host smart-5748945a-1765-4cea-9070-9eebf6aa6774
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712591474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3712591474
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1498541030
Short name T797
Test name
Test status
Simulation time 4515132627 ps
CPU time 57.51 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:42:48 PM PST 24
Peak memory 198284 kb
Host smart-f546cdd6-f8d6-4cd1-8ac4-83d3b60f4c5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498541030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1498541030
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.174089310
Short name T875
Test name
Test status
Simulation time 54824665202 ps
CPU time 990.07 seconds
Started Jan 17 03:41:34 PM PST 24
Finished Jan 17 03:58:06 PM PST 24
Peak memory 198676 kb
Host smart-d4503fe8-bc2f-4a28-807e-4ee408c68324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=174089310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.174089310
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3610370095
Short name T478
Test name
Test status
Simulation time 35318081 ps
CPU time 0.57 seconds
Started Jan 17 03:41:42 PM PST 24
Finished Jan 17 03:41:51 PM PST 24
Peak memory 194096 kb
Host smart-3130caa8-9a89-4fbd-a082-d59bdc509749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610370095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3610370095
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2053203641
Short name T221
Test name
Test status
Simulation time 12177733 ps
CPU time 0.6 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 194792 kb
Host smart-63a4aaa9-0314-446f-9f18-dcaf94292f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053203641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2053203641
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1980015824
Short name T838
Test name
Test status
Simulation time 922693358 ps
CPU time 16.47 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:42:00 PM PST 24
Peak memory 198164 kb
Host smart-075f53f2-7c6c-4abb-b701-a43ed8b92143
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980015824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1980015824
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2247963401
Short name T354
Test name
Test status
Simulation time 302119665 ps
CPU time 1.02 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 196608 kb
Host smart-525945d4-8340-4c69-aeac-d31f8b48481a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247963401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2247963401
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.434425252
Short name T492
Test name
Test status
Simulation time 34781730 ps
CPU time 1.11 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 196908 kb
Host smart-bd1592d4-11bf-425a-b7cb-47f8968e8cb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434425252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.434425252
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3126928329
Short name T509
Test name
Test status
Simulation time 26439440 ps
CPU time 1.24 seconds
Started Jan 17 03:41:35 PM PST 24
Finished Jan 17 03:41:40 PM PST 24
Peak memory 197444 kb
Host smart-af151cbb-7219-4477-afff-ad0a03dab4e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126928329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3126928329
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.189957467
Short name T519
Test name
Test status
Simulation time 319393383 ps
CPU time 2.76 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 197104 kb
Host smart-56259620-b040-4098-8aae-33cd96c99610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189957467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
189957467
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1678039455
Short name T445
Test name
Test status
Simulation time 51647477 ps
CPU time 1.06 seconds
Started Jan 17 03:41:31 PM PST 24
Finished Jan 17 03:41:33 PM PST 24
Peak memory 196060 kb
Host smart-3956012c-d511-4057-8a48-0252466135fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678039455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1678039455
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2569568117
Short name T780
Test name
Test status
Simulation time 46467599 ps
CPU time 0.95 seconds
Started Jan 17 03:41:34 PM PST 24
Finished Jan 17 03:41:36 PM PST 24
Peak memory 197092 kb
Host smart-dcff04fe-e6cd-4d38-a0f8-0bac562ae8d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569568117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2569568117
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.582381238
Short name T637
Test name
Test status
Simulation time 107649793 ps
CPU time 1.32 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 198008 kb
Host smart-258ebcdf-95bb-43f6-8f1b-2e7c498845ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582381238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.582381238
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4028752394
Short name T331
Test name
Test status
Simulation time 290974227 ps
CPU time 1.22 seconds
Started Jan 17 03:41:28 PM PST 24
Finished Jan 17 03:41:30 PM PST 24
Peak memory 196552 kb
Host smart-60eea46c-9654-4cdc-b26d-0164f0afd3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028752394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4028752394
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1118979659
Short name T319
Test name
Test status
Simulation time 399522048 ps
CPU time 1.37 seconds
Started Jan 17 03:41:41 PM PST 24
Finished Jan 17 03:41:52 PM PST 24
Peak memory 198120 kb
Host smart-b0d81d03-d662-462a-8196-e9956290db12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118979659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1118979659
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1847017259
Short name T818
Test name
Test status
Simulation time 40793878212 ps
CPU time 80.1 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:43:02 PM PST 24
Peak memory 198284 kb
Host smart-9481d39a-c806-49cb-8273-9d88e1c37473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847017259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1847017259
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2397341756
Short name T497
Test name
Test status
Simulation time 72153651451 ps
CPU time 295.71 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:46:39 PM PST 24
Peak memory 198412 kb
Host smart-d7462059-fb01-4fb1-8c5c-3b40c270f6a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2397341756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2397341756
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1014294179
Short name T59
Test name
Test status
Simulation time 14590735 ps
CPU time 0.57 seconds
Started Jan 17 03:41:35 PM PST 24
Finished Jan 17 03:41:39 PM PST 24
Peak memory 194064 kb
Host smart-32779dc4-522d-4dfd-8128-88f1ee10ca86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014294179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1014294179
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.641983867
Short name T560
Test name
Test status
Simulation time 62042702 ps
CPU time 0.83 seconds
Started Jan 17 03:41:35 PM PST 24
Finished Jan 17 03:41:41 PM PST 24
Peak memory 196212 kb
Host smart-23807135-819b-4b36-962c-aff3f28212f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641983867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.641983867
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3154112068
Short name T753
Test name
Test status
Simulation time 1552962595 ps
CPU time 25.72 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:42:09 PM PST 24
Peak memory 197032 kb
Host smart-f44c187a-e53b-4591-bff4-2780a4b4d94e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154112068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3154112068
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3879744817
Short name T213
Test name
Test status
Simulation time 173891543 ps
CPU time 1.09 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 196584 kb
Host smart-0b8c0ba6-7e03-4fbc-82e2-cc5667ea9067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879744817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3879744817
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1101261852
Short name T315
Test name
Test status
Simulation time 54851153 ps
CPU time 1.41 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 196960 kb
Host smart-e11d28fa-84ab-4493-9d54-bc4f474e825d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101261852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1101261852
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.747804645
Short name T402
Test name
Test status
Simulation time 126132621 ps
CPU time 2.73 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 198260 kb
Host smart-58532ff3-b7b4-4ef7-a6b9-4ee40b18dbda
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747804645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.747804645
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3266145363
Short name T249
Test name
Test status
Simulation time 558032721 ps
CPU time 2.58 seconds
Started Jan 17 03:41:41 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195960 kb
Host smart-0d9cbbf7-3b0b-4730-b3a0-6673fde3cb03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266145363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3266145363
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3881189490
Short name T366
Test name
Test status
Simulation time 37760526 ps
CPU time 0.84 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 196600 kb
Host smart-47484d45-1ffb-4782-ab48-05d7fc979fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881189490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3881189490
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4105160708
Short name T620
Test name
Test status
Simulation time 53554936 ps
CPU time 1.09 seconds
Started Jan 17 03:41:42 PM PST 24
Finished Jan 17 03:41:52 PM PST 24
Peak memory 195912 kb
Host smart-82c01007-5d31-4113-a78a-aac3274fb570
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105160708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4105160708
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1847604563
Short name T243
Test name
Test status
Simulation time 122255600 ps
CPU time 5.28 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:48 PM PST 24
Peak memory 198116 kb
Host smart-deb4b445-c5f3-4169-a626-66385cb76cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847604563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1847604563
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1451238039
Short name T695
Test name
Test status
Simulation time 244509603 ps
CPU time 1.19 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 195932 kb
Host smart-00b17097-49fb-4916-b726-22579f7394cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451238039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1451238039
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2253968662
Short name T237
Test name
Test status
Simulation time 133341492 ps
CPU time 1.46 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 196876 kb
Host smart-34b53525-5a24-4a0a-9270-e6603dbf0a5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253968662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2253968662
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4092037574
Short name T230
Test name
Test status
Simulation time 14777530757 ps
CPU time 188.8 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:44:52 PM PST 24
Peak memory 198312 kb
Host smart-c56418ac-1237-4223-b83b-c67267830c13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092037574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4092037574
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3401410823
Short name T67
Test name
Test status
Simulation time 104786216036 ps
CPU time 1786.61 seconds
Started Jan 17 03:41:41 PM PST 24
Finished Jan 17 04:11:37 PM PST 24
Peak memory 198372 kb
Host smart-04226ab0-227a-4bcb-9eaa-e92bdfc4c5f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3401410823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3401410823
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2348085604
Short name T823
Test name
Test status
Simulation time 12132941 ps
CPU time 0.61 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:42 PM PST 24
Peak memory 194020 kb
Host smart-782ed977-cd3d-454a-b3bd-cdfe88b5c88a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348085604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2348085604
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4225720375
Short name T634
Test name
Test status
Simulation time 117487860 ps
CPU time 0.84 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 196044 kb
Host smart-f431db2a-1bef-4d8b-8d94-401e9d8c88b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225720375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4225720375
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.54143855
Short name T389
Test name
Test status
Simulation time 1698138273 ps
CPU time 23.15 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:42:05 PM PST 24
Peak memory 197032 kb
Host smart-7bfb7c3b-41e3-4160-a4e8-109573c3a103
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54143855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress
.54143855
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2712647119
Short name T680
Test name
Test status
Simulation time 335340037 ps
CPU time 0.76 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 194792 kb
Host smart-80cfc5af-00d3-48f7-8da8-91d7c70218a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712647119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2712647119
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.940303709
Short name T345
Test name
Test status
Simulation time 182367598 ps
CPU time 1.29 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 197292 kb
Host smart-e872c05b-568d-4def-9074-b4e6cc8d7b3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940303709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.940303709
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.556917148
Short name T579
Test name
Test status
Simulation time 51466393 ps
CPU time 2.19 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:45 PM PST 24
Peak memory 198252 kb
Host smart-791d8272-510d-4881-9283-6d28058dad47
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556917148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.556917148
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1563432636
Short name T421
Test name
Test status
Simulation time 435186173 ps
CPU time 3.87 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:46 PM PST 24
Peak memory 198168 kb
Host smart-e14ed993-92e1-4f86-8f5b-bc165a6dd979
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563432636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1563432636
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1851221824
Short name T304
Test name
Test status
Simulation time 566921213 ps
CPU time 1.29 seconds
Started Jan 17 03:41:40 PM PST 24
Finished Jan 17 03:41:51 PM PST 24
Peak memory 196904 kb
Host smart-00a74a4a-2424-446f-adc0-99a4dcd9cebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851221824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1851221824
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.995892218
Short name T719
Test name
Test status
Simulation time 383543549 ps
CPU time 1.39 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 198164 kb
Host smart-d213ef2f-536e-4623-8e8b-f74bffbed923
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995892218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.995892218
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.222169534
Short name T609
Test name
Test status
Simulation time 120513208 ps
CPU time 5.57 seconds
Started Jan 17 03:41:37 PM PST 24
Finished Jan 17 03:41:47 PM PST 24
Peak memory 198052 kb
Host smart-a536d75e-a928-4c29-923c-2eae5b4f1826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222169534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.222169534
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2886298895
Short name T465
Test name
Test status
Simulation time 33897692 ps
CPU time 0.85 seconds
Started Jan 17 03:41:42 PM PST 24
Finished Jan 17 03:41:52 PM PST 24
Peak memory 195960 kb
Host smart-37a4db80-402c-4564-a538-4e1e3374762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886298895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2886298895
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2847668228
Short name T252
Test name
Test status
Simulation time 85751126 ps
CPU time 0.85 seconds
Started Jan 17 03:41:36 PM PST 24
Finished Jan 17 03:41:41 PM PST 24
Peak memory 196484 kb
Host smart-0d76176d-488e-4826-a026-84724d085d5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847668228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2847668228
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2473327340
Short name T757
Test name
Test status
Simulation time 53092597190 ps
CPU time 166.52 seconds
Started Jan 17 03:41:39 PM PST 24
Finished Jan 17 03:44:30 PM PST 24
Peak memory 198316 kb
Host smart-a1048e9e-7aaa-4b7a-b6ac-bd261f93dba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473327340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2473327340
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1789728005
Short name T442
Test name
Test status
Simulation time 106396566011 ps
CPU time 719.46 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:53:42 PM PST 24
Peak memory 198372 kb
Host smart-a2e07220-148b-4ca7-b064-aee62be8c87a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1789728005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1789728005
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2738509615
Short name T552
Test name
Test status
Simulation time 13132603 ps
CPU time 0.59 seconds
Started Jan 17 03:41:44 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 194284 kb
Host smart-eaf74d8d-57ce-4a82-9a3b-14890ca4df23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738509615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2738509615
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3577518593
Short name T881
Test name
Test status
Simulation time 33502046 ps
CPU time 0.83 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:44 PM PST 24
Peak memory 195608 kb
Host smart-767a3baf-655b-4bf9-8e6f-b79ca5a8c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577518593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3577518593
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3283125350
Short name T647
Test name
Test status
Simulation time 746494175 ps
CPU time 13.5 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:42:05 PM PST 24
Peak memory 196892 kb
Host smart-7a28a587-a739-4bfe-9ddd-acde306e25eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283125350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3283125350
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1639164798
Short name T267
Test name
Test status
Simulation time 99980194 ps
CPU time 0.83 seconds
Started Jan 17 03:41:44 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 196048 kb
Host smart-688d89ab-f5bd-475c-b851-1283c52f65a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639164798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1639164798
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3156529513
Short name T332
Test name
Test status
Simulation time 32633276 ps
CPU time 0.99 seconds
Started Jan 17 03:41:41 PM PST 24
Finished Jan 17 03:41:51 PM PST 24
Peak memory 196216 kb
Host smart-5741249d-adc3-4933-9f34-1a9a571f5cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156529513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3156529513
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.267436826
Short name T597
Test name
Test status
Simulation time 179830587 ps
CPU time 3.65 seconds
Started Jan 17 03:41:36 PM PST 24
Finished Jan 17 03:41:45 PM PST 24
Peak memory 198128 kb
Host smart-89e4f783-5c4d-4383-8d8a-9fc41eb45e9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267436826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.267436826
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2995040016
Short name T528
Test name
Test status
Simulation time 33427048 ps
CPU time 1.09 seconds
Started Jan 17 03:41:38 PM PST 24
Finished Jan 17 03:41:43 PM PST 24
Peak memory 196364 kb
Host smart-76f43784-df44-4ad8-9b0d-6261639cad8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995040016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2995040016
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3386396702
Short name T790
Test name
Test status
Simulation time 32600615 ps
CPU time 1.29 seconds
Started Jan 17 03:41:40 PM PST 24
Finished Jan 17 03:41:51 PM PST 24
Peak memory 195952 kb
Host smart-57259df4-1290-4980-a2ef-ce3a190aaa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386396702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3386396702
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.244259200
Short name T726
Test name
Test status
Simulation time 222823309 ps
CPU time 1.48 seconds
Started Jan 17 03:41:40 PM PST 24
Finished Jan 17 03:41:45 PM PST 24
Peak memory 197040 kb
Host smart-d3b63fca-8346-4a43-b044-5cd47cbc9032
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244259200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.244259200
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4225604397
Short name T615
Test name
Test status
Simulation time 999196242 ps
CPU time 3.25 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 198104 kb
Host smart-47266912-dc99-4bf4-938a-49db658e0d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225604397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4225604397
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2184026979
Short name T799
Test name
Test status
Simulation time 61768349 ps
CPU time 1.16 seconds
Started Jan 17 03:41:46 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 196588 kb
Host smart-422f4eb9-bdaa-4d07-bd51-11e5cd8668f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184026979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2184026979
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1656176354
Short name T401
Test name
Test status
Simulation time 524684501 ps
CPU time 1.27 seconds
Started Jan 17 03:41:36 PM PST 24
Finished Jan 17 03:41:42 PM PST 24
Peak memory 196024 kb
Host smart-5681450a-1271-4b56-9d77-49c3c4cdbe51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656176354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1656176354
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1629099134
Short name T691
Test name
Test status
Simulation time 32972427803 ps
CPU time 225.09 seconds
Started Jan 17 03:41:42 PM PST 24
Finished Jan 17 03:45:36 PM PST 24
Peak memory 198184 kb
Host smart-8809fab4-19d5-402f-82e6-a66802a751b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629099134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1629099134
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1967330067
Short name T373
Test name
Test status
Simulation time 56612672169 ps
CPU time 773.45 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:54:45 PM PST 24
Peak memory 198388 kb
Host smart-f8a06b4d-dda1-4ff8-9ad9-0b34c0245470
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1967330067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1967330067
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1167266670
Short name T814
Test name
Test status
Simulation time 27873301 ps
CPU time 0.56 seconds
Started Jan 17 03:41:41 PM PST 24
Finished Jan 17 03:41:51 PM PST 24
Peak memory 194124 kb
Host smart-6b801b60-99ca-4eea-8220-94cffc6678b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167266670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1167266670
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3787660724
Short name T741
Test name
Test status
Simulation time 23190411 ps
CPU time 0.73 seconds
Started Jan 17 03:41:45 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195364 kb
Host smart-cb90c6b9-f831-470f-b74d-5525f70ade40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787660724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3787660724
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1971215473
Short name T792
Test name
Test status
Simulation time 2287441283 ps
CPU time 27.16 seconds
Started Jan 17 03:41:48 PM PST 24
Finished Jan 17 03:42:19 PM PST 24
Peak memory 196828 kb
Host smart-41e26cc7-f2f7-446b-9587-8615b87368f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971215473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1971215473
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2725406897
Short name T777
Test name
Test status
Simulation time 231058664 ps
CPU time 0.97 seconds
Started Jan 17 03:41:44 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 198128 kb
Host smart-49ae9cdf-9f64-4f12-996c-64a1db8ec59b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725406897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2725406897
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2121910209
Short name T636
Test name
Test status
Simulation time 181497161 ps
CPU time 1.34 seconds
Started Jan 17 03:41:44 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 198184 kb
Host smart-2ba112b8-bfed-4e9d-9c31-c45f44d9b69e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121910209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2121910209
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2921136789
Short name T720
Test name
Test status
Simulation time 39635379 ps
CPU time 1.67 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 198100 kb
Host smart-67c165bd-6138-46d4-ba1f-02de75b07add
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921136789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2921136789
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4037463848
Short name T616
Test name
Test status
Simulation time 256516592 ps
CPU time 1.62 seconds
Started Jan 17 03:41:46 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 196292 kb
Host smart-f130136f-0e9a-4a26-900e-b7b1a5761dff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037463848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4037463848
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.652792021
Short name T328
Test name
Test status
Simulation time 38980703 ps
CPU time 1.01 seconds
Started Jan 17 03:41:44 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195952 kb
Host smart-39f522c6-9ccc-4790-969b-f1d7d711499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652792021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.652792021
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3858463338
Short name T215
Test name
Test status
Simulation time 168514783 ps
CPU time 1.11 seconds
Started Jan 17 03:41:47 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195992 kb
Host smart-6f73c407-7ec4-4159-b44b-68093e4e9539
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858463338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3858463338
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3938131433
Short name T754
Test name
Test status
Simulation time 108525301 ps
CPU time 5.13 seconds
Started Jan 17 03:41:48 PM PST 24
Finished Jan 17 03:41:57 PM PST 24
Peak memory 198052 kb
Host smart-1db1bca2-acd4-46b1-b580-650a2c9f7020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938131433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3938131433
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1694963024
Short name T708
Test name
Test status
Simulation time 528122384 ps
CPU time 1.49 seconds
Started Jan 17 03:41:43 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 196956 kb
Host smart-c7e0f8ed-08aa-45f3-9c5f-2f74ff130069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694963024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1694963024
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.458686881
Short name T717
Test name
Test status
Simulation time 77113450 ps
CPU time 1.01 seconds
Started Jan 17 03:41:48 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 197072 kb
Host smart-efe65271-ce72-4d2f-92b0-b5419d9a4abd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458686881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.458686881
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1337420471
Short name T712
Test name
Test status
Simulation time 69489661026 ps
CPU time 146.9 seconds
Started Jan 17 03:41:44 PM PST 24
Finished Jan 17 03:44:19 PM PST 24
Peak memory 198264 kb
Host smart-496a747b-d7a5-4517-a2b8-58da3d384472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337420471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1337420471
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.157266304
Short name T748
Test name
Test status
Simulation time 96738267501 ps
CPU time 1557.27 seconds
Started Jan 17 03:41:47 PM PST 24
Finished Jan 17 04:07:50 PM PST 24
Peak memory 198420 kb
Host smart-c462e8db-531e-4e1e-8582-768b67019435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=157266304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.157266304
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.153692833
Short name T846
Test name
Test status
Simulation time 23522909 ps
CPU time 0.59 seconds
Started Jan 17 03:41:49 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 194916 kb
Host smart-fe90ca2a-1eab-40bf-88a9-e84d55a2f5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153692833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.153692833
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1197830631
Short name T220
Test name
Test status
Simulation time 37963541 ps
CPU time 0.65 seconds
Started Jan 17 03:41:50 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 193912 kb
Host smart-8a9c2afb-a9b2-46b0-ab10-224f11416083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197830631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1197830631
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2072452987
Short name T530
Test name
Test status
Simulation time 1351903451 ps
CPU time 5.96 seconds
Started Jan 17 03:42:04 PM PST 24
Finished Jan 17 03:42:11 PM PST 24
Peak memory 197040 kb
Host smart-5c21c514-c6b6-4ce2-93d2-589dff0d48dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072452987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2072452987
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4235576022
Short name T652
Test name
Test status
Simulation time 79802212 ps
CPU time 0.85 seconds
Started Jan 17 03:41:50 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 196796 kb
Host smart-545ee252-5104-48b2-b32e-b312679ec379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235576022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4235576022
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2997713049
Short name T807
Test name
Test status
Simulation time 27431761 ps
CPU time 0.65 seconds
Started Jan 17 03:41:48 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195120 kb
Host smart-1c8b6cb9-0ea6-45fb-a1d8-2d33af002c95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997713049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2997713049
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2477956380
Short name T404
Test name
Test status
Simulation time 76684524 ps
CPU time 2.97 seconds
Started Jan 17 03:41:52 PM PST 24
Finished Jan 17 03:41:58 PM PST 24
Peak memory 198084 kb
Host smart-300b9851-b73e-4f67-9946-47c94344dc73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477956380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2477956380
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3725951297
Short name T755
Test name
Test status
Simulation time 159838412 ps
CPU time 1.84 seconds
Started Jan 17 03:41:51 PM PST 24
Finished Jan 17 03:41:56 PM PST 24
Peak memory 196868 kb
Host smart-6ec63c95-736b-47c9-b975-f72f523de6db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725951297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3725951297
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.215391551
Short name T490
Test name
Test status
Simulation time 60365305 ps
CPU time 1.16 seconds
Started Jan 17 03:41:51 PM PST 24
Finished Jan 17 03:41:55 PM PST 24
Peak memory 197480 kb
Host smart-f06ecb72-bce7-4514-a5a8-693d0699b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215391551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.215391551
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4117564690
Short name T390
Test name
Test status
Simulation time 55512199 ps
CPU time 1.06 seconds
Started Jan 17 03:41:47 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 196640 kb
Host smart-6ed1a187-6533-41c3-93b5-064dc0879a37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117564690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4117564690
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1103692658
Short name T408
Test name
Test status
Simulation time 278563412 ps
CPU time 4.49 seconds
Started Jan 17 03:41:52 PM PST 24
Finished Jan 17 03:41:59 PM PST 24
Peak memory 198148 kb
Host smart-ebb7d7d8-23eb-496a-8a5f-d0be4470a692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103692658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1103692658
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1228987418
Short name T798
Test name
Test status
Simulation time 84391354 ps
CPU time 1.32 seconds
Started Jan 17 03:41:45 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195612 kb
Host smart-647c4a46-4719-4119-bc51-7fe154300c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228987418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1228987418
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.997234116
Short name T388
Test name
Test status
Simulation time 361663642 ps
CPU time 1.29 seconds
Started Jan 17 03:41:50 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 195908 kb
Host smart-6e2a6d24-92d3-43a5-949a-8c3f3b803a77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997234116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.997234116
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2896705320
Short name T578
Test name
Test status
Simulation time 10965350856 ps
CPU time 83.49 seconds
Started Jan 17 03:41:48 PM PST 24
Finished Jan 17 03:43:16 PM PST 24
Peak memory 198112 kb
Host smart-ec1a50bd-27f0-4542-82b0-1cf692a3ea92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896705320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2896705320
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2670778013
Short name T810
Test name
Test status
Simulation time 65824316268 ps
CPU time 1696.21 seconds
Started Jan 17 03:41:51 PM PST 24
Finished Jan 17 04:10:11 PM PST 24
Peak memory 198332 kb
Host smart-0d5d5dac-e66d-4959-b910-3ef0f390d389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2670778013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2670778013
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2220359925
Short name T297
Test name
Test status
Simulation time 19850048 ps
CPU time 0.57 seconds
Started Jan 17 03:41:54 PM PST 24
Finished Jan 17 03:41:56 PM PST 24
Peak memory 194720 kb
Host smart-66b54c58-13cd-421a-b07c-031003277ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220359925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2220359925
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1325677804
Short name T58
Test name
Test status
Simulation time 28207906 ps
CPU time 0.83 seconds
Started Jan 17 03:41:54 PM PST 24
Finished Jan 17 03:41:56 PM PST 24
Peak memory 195452 kb
Host smart-24bb63d4-faf0-440f-812f-3e141ec4b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325677804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1325677804
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1230028740
Short name T840
Test name
Test status
Simulation time 200944911 ps
CPU time 10.74 seconds
Started Jan 17 03:41:55 PM PST 24
Finished Jan 17 03:42:06 PM PST 24
Peak memory 197316 kb
Host smart-e17711be-9c02-45c6-8aa1-9b8df9d83ebf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230028740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1230028740
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2505694473
Short name T316
Test name
Test status
Simulation time 106772941 ps
CPU time 0.73 seconds
Started Jan 17 03:41:53 PM PST 24
Finished Jan 17 03:41:56 PM PST 24
Peak memory 195484 kb
Host smart-209ffe4f-5c14-466b-8b86-b7f7ee0b7d7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505694473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2505694473
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3542995148
Short name T640
Test name
Test status
Simulation time 40963241 ps
CPU time 0.84 seconds
Started Jan 17 03:41:49 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 196740 kb
Host smart-fb0bfa76-c04d-4179-994a-2cedce6dc5db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542995148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3542995148
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.190964319
Short name T485
Test name
Test status
Simulation time 47362378 ps
CPU time 1.85 seconds
Started Jan 17 03:41:50 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 198168 kb
Host smart-d198bda6-8209-4880-9eee-c63d00ca8532
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190964319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.190964319
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2171172092
Short name T700
Test name
Test status
Simulation time 437560276 ps
CPU time 2.75 seconds
Started Jan 17 03:41:51 PM PST 24
Finished Jan 17 03:41:57 PM PST 24
Peak memory 197332 kb
Host smart-c6e86837-3435-4997-952c-190c5df0776b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171172092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2171172092
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3690585176
Short name T416
Test name
Test status
Simulation time 72878786 ps
CPU time 0.85 seconds
Started Jan 17 03:41:49 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 197240 kb
Host smart-345ebcdf-fc7a-4caf-9ea8-3132d27fe3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690585176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3690585176
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3317372005
Short name T536
Test name
Test status
Simulation time 17528876 ps
CPU time 0.72 seconds
Started Jan 17 03:41:49 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195400 kb
Host smart-c839f0bd-e42e-4fba-b442-f01560624984
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317372005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3317372005
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3658309311
Short name T375
Test name
Test status
Simulation time 1042578830 ps
CPU time 6.39 seconds
Started Jan 17 03:41:53 PM PST 24
Finished Jan 17 03:42:01 PM PST 24
Peak memory 198060 kb
Host smart-ae2feea1-0206-4214-a52a-80fb741187fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658309311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3658309311
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2743351050
Short name T535
Test name
Test status
Simulation time 102576340 ps
CPU time 0.77 seconds
Started Jan 17 03:41:49 PM PST 24
Finished Jan 17 03:41:53 PM PST 24
Peak memory 195264 kb
Host smart-4af3e67e-d856-498e-99fe-fb1adf33876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743351050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2743351050
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2158798904
Short name T513
Test name
Test status
Simulation time 348070943 ps
CPU time 1.38 seconds
Started Jan 17 03:41:49 PM PST 24
Finished Jan 17 03:41:54 PM PST 24
Peak memory 196836 kb
Host smart-92f97d70-b73c-48c1-8ddf-775d2c3354c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158798904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2158798904
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2409665952
Short name T317
Test name
Test status
Simulation time 12458560459 ps
CPU time 140.03 seconds
Started Jan 17 03:41:55 PM PST 24
Finished Jan 17 03:44:16 PM PST 24
Peak memory 198312 kb
Host smart-388780c4-af3c-4d4d-8385-defb7434cb98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409665952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2409665952
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3358994394
Short name T743
Test name
Test status
Simulation time 10259533057 ps
CPU time 356.71 seconds
Started Jan 17 03:41:54 PM PST 24
Finished Jan 17 03:47:52 PM PST 24
Peak memory 198384 kb
Host smart-8299fc26-b49f-486a-97b8-dda780ce507a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3358994394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3358994394
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.539577577
Short name T397
Test name
Test status
Simulation time 35649233 ps
CPU time 0.55 seconds
Started Jan 17 03:39:54 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 194088 kb
Host smart-73956362-fee8-43ff-9da1-90a3a5d0e08d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539577577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.539577577
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1360252871
Short name T829
Test name
Test status
Simulation time 33592205 ps
CPU time 0.85 seconds
Started Jan 17 03:39:53 PM PST 24
Finished Jan 17 03:39:54 PM PST 24
Peak memory 196020 kb
Host smart-09675efe-fedb-41f2-a0aa-df6fa1a0d91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360252871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1360252871
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4027453724
Short name T630
Test name
Test status
Simulation time 831682179 ps
CPU time 5.1 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:40:02 PM PST 24
Peak memory 195760 kb
Host smart-8a2db7ea-7371-4a4c-a28b-4fbe636103a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027453724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4027453724
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.851342861
Short name T455
Test name
Test status
Simulation time 46560970 ps
CPU time 0.74 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 195492 kb
Host smart-ece1826a-770a-4dbb-a6ed-dd87f634e3d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851342861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.851342861
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.61173822
Short name T359
Test name
Test status
Simulation time 183926522 ps
CPU time 1.3 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 197264 kb
Host smart-d1db3498-b7d2-4170-971b-09e5e4e7befb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61173822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.61173822
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1151449634
Short name T446
Test name
Test status
Simulation time 387734215 ps
CPU time 3.24 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:59 PM PST 24
Peak memory 196584 kb
Host smart-153b443a-b28a-4eaf-9162-204928845f22
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151449634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1151449634
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3407357708
Short name T675
Test name
Test status
Simulation time 54768883 ps
CPU time 1.31 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 196816 kb
Host smart-be9e060c-813b-4507-b87a-eec373d4a903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407357708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3407357708
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3290271142
Short name T496
Test name
Test status
Simulation time 53808641 ps
CPU time 1.13 seconds
Started Jan 17 03:39:58 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 196232 kb
Host smart-6038d7cb-e02d-4795-a294-7dfe0e551fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290271142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3290271142
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1713837183
Short name T786
Test name
Test status
Simulation time 191094295 ps
CPU time 1.31 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 197064 kb
Host smart-7ae7e88f-ea46-43aa-9ad2-c397a34f9e94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713837183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1713837183
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3138204319
Short name T104
Test name
Test status
Simulation time 40217251 ps
CPU time 2 seconds
Started Jan 17 03:39:57 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 198140 kb
Host smart-625a46cd-7b4f-44f2-b265-3b5dedffdfd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138204319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3138204319
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1429188305
Short name T25
Test name
Test status
Simulation time 319239080 ps
CPU time 0.97 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 214796 kb
Host smart-04d63464-ac22-42c0-8c81-aa609b06ec72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429188305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1429188305
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4051904065
Short name T864
Test name
Test status
Simulation time 116790311 ps
CPU time 1.06 seconds
Started Jan 17 03:39:57 PM PST 24
Finished Jan 17 03:39:59 PM PST 24
Peak memory 195824 kb
Host smart-16a87a6f-74a3-4fca-b01c-b5467a6620b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051904065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4051904065
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.322576058
Short name T629
Test name
Test status
Simulation time 83620668 ps
CPU time 0.91 seconds
Started Jan 17 03:39:54 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 196484 kb
Host smart-42830770-e355-4165-b11f-8315e3869830
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322576058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.322576058
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2037882618
Short name T611
Test name
Test status
Simulation time 38295913581 ps
CPU time 179.03 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:42:55 PM PST 24
Peak memory 198284 kb
Host smart-442f3f99-4f13-41be-a3d3-6206dd8c7047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037882618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2037882618
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.824677190
Short name T382
Test name
Test status
Simulation time 151026412567 ps
CPU time 1036.59 seconds
Started Jan 17 03:39:54 PM PST 24
Finished Jan 17 03:57:11 PM PST 24
Peak memory 198376 kb
Host smart-f33b43c7-dbca-4b28-9334-346c4fb5de89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=824677190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.824677190
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1149946359
Short name T677
Test name
Test status
Simulation time 11743362 ps
CPU time 0.62 seconds
Started Jan 17 03:42:04 PM PST 24
Finished Jan 17 03:42:06 PM PST 24
Peak memory 194760 kb
Host smart-d5f3534d-69d5-44ac-9c57-010ad86ecd1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149946359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1149946359
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1563639031
Short name T32
Test name
Test status
Simulation time 25744959 ps
CPU time 0.8 seconds
Started Jan 17 03:41:59 PM PST 24
Finished Jan 17 03:42:01 PM PST 24
Peak memory 196076 kb
Host smart-6a975991-0cf4-4082-b843-efa0a4a2e241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563639031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1563639031
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2902378266
Short name T657
Test name
Test status
Simulation time 196954806 ps
CPU time 10.24 seconds
Started Jan 17 03:42:04 PM PST 24
Finished Jan 17 03:42:15 PM PST 24
Peak memory 197216 kb
Host smart-c88360e0-10c3-4a29-99fc-472175d63491
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902378266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2902378266
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3602877738
Short name T232
Test name
Test status
Simulation time 65923418 ps
CPU time 0.91 seconds
Started Jan 17 03:42:00 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 196684 kb
Host smart-356ec0c6-0999-429f-8f6a-324c27991fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602877738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3602877738
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3078109033
Short name T659
Test name
Test status
Simulation time 79213917 ps
CPU time 0.92 seconds
Started Jan 17 03:42:00 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 195732 kb
Host smart-4802c53d-615d-4c6d-a350-600f2233a379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078109033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3078109033
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3158728
Short name T638
Test name
Test status
Simulation time 514188441 ps
CPU time 2.53 seconds
Started Jan 17 03:42:04 PM PST 24
Finished Jan 17 03:42:08 PM PST 24
Peak memory 198228 kb
Host smart-0f234442-9471-40a2-8cdf-2d144311b009
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.gpio_intr_with_filter_rand_intr_event.3158728
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.955080782
Short name T504
Test name
Test status
Simulation time 385784650 ps
CPU time 2.06 seconds
Started Jan 17 03:42:00 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 196640 kb
Host smart-033ba0f9-ca6d-4cac-af0c-9bef7e370ff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955080782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
955080782
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1736947515
Short name T551
Test name
Test status
Simulation time 58462818 ps
CPU time 0.88 seconds
Started Jan 17 03:41:56 PM PST 24
Finished Jan 17 03:41:58 PM PST 24
Peak memory 196716 kb
Host smart-b33ffa10-47a0-4be0-b277-ac7ca41545cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736947515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1736947515
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3229898663
Short name T842
Test name
Test status
Simulation time 70174633 ps
CPU time 1.3 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:42:10 PM PST 24
Peak memory 198228 kb
Host smart-b0b772c5-c7d7-4e51-bfcb-55dad61d5f0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229898663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3229898663
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1219817340
Short name T411
Test name
Test status
Simulation time 134213396 ps
CPU time 3.31 seconds
Started Jan 17 03:42:00 PM PST 24
Finished Jan 17 03:42:04 PM PST 24
Peak memory 198112 kb
Host smart-b2bafcbf-e666-443d-b4a4-8f7f49c53ce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219817340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1219817340
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.175301563
Short name T367
Test name
Test status
Simulation time 125908805 ps
CPU time 1.25 seconds
Started Jan 17 03:41:54 PM PST 24
Finished Jan 17 03:41:56 PM PST 24
Peak memory 196672 kb
Host smart-2ebed7c5-4ef8-43bd-b32a-b6f83be76f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175301563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.175301563
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3629268756
Short name T686
Test name
Test status
Simulation time 995868075 ps
CPU time 1.32 seconds
Started Jan 17 03:41:56 PM PST 24
Finished Jan 17 03:41:58 PM PST 24
Peak memory 198112 kb
Host smart-f6f26f7e-7a19-49a6-9330-38b05f075182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629268756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3629268756
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3111318582
Short name T802
Test name
Test status
Simulation time 26464388443 ps
CPU time 188.67 seconds
Started Jan 17 03:41:58 PM PST 24
Finished Jan 17 03:45:08 PM PST 24
Peak memory 198256 kb
Host smart-77a1c5a4-0e0f-44bc-b359-3167095f99c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111318582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3111318582
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2114391590
Short name T82
Test name
Test status
Simulation time 25806911671 ps
CPU time 727.37 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:54:16 PM PST 24
Peak memory 198372 kb
Host smart-a9772adb-7cce-4cf6-b5e1-af02ddcaea4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2114391590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2114391590
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3223922922
Short name T453
Test name
Test status
Simulation time 12773394 ps
CPU time 0.57 seconds
Started Jan 17 03:42:01 PM PST 24
Finished Jan 17 03:42:03 PM PST 24
Peak memory 194116 kb
Host smart-3ffb0e59-5312-48f1-a1f0-7ce458c9fd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223922922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3223922922
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1755634642
Short name T654
Test name
Test status
Simulation time 90803615 ps
CPU time 0.98 seconds
Started Jan 17 03:42:04 PM PST 24
Finished Jan 17 03:42:06 PM PST 24
Peak memory 196096 kb
Host smart-b4e20203-5d54-404b-8a6c-d91ab7f1ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755634642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1755634642
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.4142585811
Short name T405
Test name
Test status
Simulation time 953942664 ps
CPU time 12.73 seconds
Started Jan 17 03:41:57 PM PST 24
Finished Jan 17 03:42:11 PM PST 24
Peak memory 196932 kb
Host smart-4cbf8eef-8b6a-4fbc-b343-15cac250f499
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142585811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.4142585811
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3244778762
Short name T593
Test name
Test status
Simulation time 149046561 ps
CPU time 0.88 seconds
Started Jan 17 03:42:01 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 196064 kb
Host smart-6992f288-152f-4f3c-882f-301949bd3f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244778762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3244778762
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.486252511
Short name T555
Test name
Test status
Simulation time 182165161 ps
CPU time 1.23 seconds
Started Jan 17 03:42:00 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 196204 kb
Host smart-e9cf14b6-b8e0-4975-a584-e88164b6cfeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486252511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.486252511
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2127825587
Short name T795
Test name
Test status
Simulation time 146616707 ps
CPU time 3.37 seconds
Started Jan 17 03:42:01 PM PST 24
Finished Jan 17 03:42:05 PM PST 24
Peak memory 198192 kb
Host smart-52c03165-60da-444c-873e-2e747ba9d14e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127825587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2127825587
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1082447737
Short name T357
Test name
Test status
Simulation time 155889940 ps
CPU time 3.43 seconds
Started Jan 17 03:41:59 PM PST 24
Finished Jan 17 03:42:03 PM PST 24
Peak memory 195968 kb
Host smart-118d5aea-777d-4ba2-903d-e097d3a38abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082447737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1082447737
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3164774764
Short name T515
Test name
Test status
Simulation time 37843759 ps
CPU time 0.76 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:42:09 PM PST 24
Peak memory 196284 kb
Host smart-2a08c8fa-0c58-4402-8b46-f14a8a69f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164774764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3164774764
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3695933317
Short name T443
Test name
Test status
Simulation time 229074889 ps
CPU time 1.36 seconds
Started Jan 17 03:41:59 PM PST 24
Finished Jan 17 03:42:01 PM PST 24
Peak memory 195956 kb
Host smart-79d7e1ff-4a31-4cff-a22d-0991c998b4b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695933317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3695933317
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2099965379
Short name T505
Test name
Test status
Simulation time 167047521 ps
CPU time 3.95 seconds
Started Jan 17 03:42:01 PM PST 24
Finished Jan 17 03:42:06 PM PST 24
Peak memory 198108 kb
Host smart-9e251505-7a08-4405-b898-1a59b8cdb218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099965379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2099965379
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.103898835
Short name T231
Test name
Test status
Simulation time 89046382 ps
CPU time 1.38 seconds
Started Jan 17 03:41:58 PM PST 24
Finished Jan 17 03:42:00 PM PST 24
Peak memory 195696 kb
Host smart-58b3cf98-7851-4379-acf9-3a57db78a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103898835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.103898835
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2186314792
Short name T618
Test name
Test status
Simulation time 264858601 ps
CPU time 1.36 seconds
Started Jan 17 03:42:00 PM PST 24
Finished Jan 17 03:42:02 PM PST 24
Peak memory 196460 kb
Host smart-313d29aa-0a99-4b5b-8bd9-6166f4e65296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186314792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2186314792
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.448275733
Short name T240
Test name
Test status
Simulation time 30960739145 ps
CPU time 95.05 seconds
Started Jan 17 03:41:57 PM PST 24
Finished Jan 17 03:43:33 PM PST 24
Peak memory 198240 kb
Host smart-87e489bc-d3d2-4fea-836a-b838f5104263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448275733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.448275733
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4075701940
Short name T561
Test name
Test status
Simulation time 1091799289132 ps
CPU time 1513.27 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 04:07:25 PM PST 24
Peak memory 198508 kb
Host smart-0234f6c6-e892-4988-a0c3-65dea53b9c62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4075701940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4075701940
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2950639516
Short name T286
Test name
Test status
Simulation time 35322438 ps
CPU time 0.58 seconds
Started Jan 17 03:42:11 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 194812 kb
Host smart-9d6d1a12-1b9c-4072-aef1-a77783a4a96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950639516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2950639516
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1231793804
Short name T64
Test name
Test status
Simulation time 128442940 ps
CPU time 0.84 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 03:42:09 PM PST 24
Peak memory 195212 kb
Host smart-22421271-e226-4d04-9d3c-303cce2759e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231793804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1231793804
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.753504422
Short name T323
Test name
Test status
Simulation time 168109940 ps
CPU time 8.62 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 196344 kb
Host smart-2647b94d-7ba4-4321-8a2e-964a4264a97d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753504422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.753504422
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.194981401
Short name T683
Test name
Test status
Simulation time 639657586 ps
CPU time 0.96 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:12 PM PST 24
Peak memory 197284 kb
Host smart-6db9e860-0cda-4344-830e-02a1aa297706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194981401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.194981401
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1303327197
Short name T288
Test name
Test status
Simulation time 100032824 ps
CPU time 0.87 seconds
Started Jan 17 03:42:10 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196612 kb
Host smart-93f7a53d-7d89-486a-bfa6-5ee8973e8687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303327197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1303327197
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.218156695
Short name T856
Test name
Test status
Simulation time 277075718 ps
CPU time 2.89 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:15 PM PST 24
Peak memory 198184 kb
Host smart-5750e7e2-bfb7-4c79-863c-9fb5f4f74fd8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218156695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.218156695
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2894193830
Short name T776
Test name
Test status
Simulation time 401384932 ps
CPU time 3.47 seconds
Started Jan 17 03:42:11 PM PST 24
Finished Jan 17 03:42:16 PM PST 24
Peak memory 196652 kb
Host smart-57f17cbf-1942-4aaf-9708-c8293364bd57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894193830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2894193830
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1826428055
Short name T815
Test name
Test status
Simulation time 59915153 ps
CPU time 1.34 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:42:09 PM PST 24
Peak memory 198200 kb
Host smart-8f1b0e04-058d-40b8-b488-8ca315274605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826428055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1826428055
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.182049497
Short name T522
Test name
Test status
Simulation time 52289196 ps
CPU time 1.15 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196844 kb
Host smart-216c7ed0-2b14-40b3-b465-871d6a01c630
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182049497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.182049497
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1597740629
Short name T282
Test name
Test status
Simulation time 22619146 ps
CPU time 1.07 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 197992 kb
Host smart-86043c38-c718-4143-bd37-ab771e9e7c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597740629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1597740629
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.722799064
Short name T324
Test name
Test status
Simulation time 75669106 ps
CPU time 1.42 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 03:42:10 PM PST 24
Peak memory 196088 kb
Host smart-70907660-03ba-4cd4-b5bc-066e553a770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722799064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.722799064
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3160058683
Short name T549
Test name
Test status
Simulation time 146077824 ps
CPU time 1.02 seconds
Started Jan 17 03:42:03 PM PST 24
Finished Jan 17 03:42:05 PM PST 24
Peak memory 197316 kb
Host smart-727e6ee2-394a-437c-a7eb-124db493b2aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160058683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3160058683
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3927880526
Short name T787
Test name
Test status
Simulation time 5698794241 ps
CPU time 19.89 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:42:28 PM PST 24
Peak memory 198296 kb
Host smart-d9fd1d23-db52-4a9c-9694-e735d3772b2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927880526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3927880526
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2188344806
Short name T68
Test name
Test status
Simulation time 82114613499 ps
CPU time 1402.35 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 04:05:34 PM PST 24
Peak memory 198412 kb
Host smart-56f62280-b57d-49a2-84f2-3cf186500a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2188344806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2188344806
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1556992850
Short name T744
Test name
Test status
Simulation time 43222645 ps
CPU time 0.58 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 194044 kb
Host smart-158b2c41-9d72-4566-a6c6-94a5a27329ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556992850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1556992850
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2336695185
Short name T870
Test name
Test status
Simulation time 25100775 ps
CPU time 0.76 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 195212 kb
Host smart-7a84fb7b-0477-4956-9fc3-ae9316a10298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336695185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2336695185
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2329874028
Short name T469
Test name
Test status
Simulation time 803347122 ps
CPU time 10.6 seconds
Started Jan 17 03:42:04 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 196388 kb
Host smart-1f6897ec-1089-428f-8f61-8097bb3758b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329874028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2329874028
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2233302928
Short name T280
Test name
Test status
Simulation time 28118299 ps
CPU time 0.65 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 194368 kb
Host smart-1752392f-522c-43d0-8b43-8d15c88915cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233302928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2233302928
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3278184908
Short name T525
Test name
Test status
Simulation time 174338953 ps
CPU time 1.42 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 197572 kb
Host smart-eccf9033-4033-4b9e-909b-1f2f79577a01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278184908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3278184908
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1919691751
Short name T610
Test name
Test status
Simulation time 243455398 ps
CPU time 2.65 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 198044 kb
Host smart-9727aeb8-d606-4ecb-af25-3d4913139685
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919691751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1919691751
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4246765699
Short name T305
Test name
Test status
Simulation time 159554744 ps
CPU time 2.9 seconds
Started Jan 17 03:42:12 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 197408 kb
Host smart-2b8dde42-757c-49f8-a19d-b49a5afa7fc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246765699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4246765699
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1442265199
Short name T672
Test name
Test status
Simulation time 186516966 ps
CPU time 1.23 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:42:09 PM PST 24
Peak memory 198204 kb
Host smart-ca29933f-8efa-44e8-81ae-dc7b772c4f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442265199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1442265199
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1128358009
Short name T396
Test name
Test status
Simulation time 54851059 ps
CPU time 0.78 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 03:42:12 PM PST 24
Peak memory 196128 kb
Host smart-07cfe0f2-1b08-47ff-a968-9ebcdc014be9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128358009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1128358009
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2397498979
Short name T660
Test name
Test status
Simulation time 379415515 ps
CPU time 5.06 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:16 PM PST 24
Peak memory 198108 kb
Host smart-4cc14cdf-5c88-4c70-9901-980060c23b02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397498979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2397498979
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2730582992
Short name T467
Test name
Test status
Simulation time 250900361 ps
CPU time 0.86 seconds
Started Jan 17 03:42:05 PM PST 24
Finished Jan 17 03:42:08 PM PST 24
Peak memory 195344 kb
Host smart-e8f25ae7-27f6-4c45-b67c-7d5adf684ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730582992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2730582992
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.525857882
Short name T576
Test name
Test status
Simulation time 221397804 ps
CPU time 1.06 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196640 kb
Host smart-8f5dbf0f-c0d3-4fa8-b105-b7eefb8fddff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525857882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.525857882
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3763018105
Short name T47
Test name
Test status
Simulation time 45000834877 ps
CPU time 176.22 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:45:08 PM PST 24
Peak memory 198248 kb
Host smart-96f134c5-e65f-421c-b738-0e3c00bf8a76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763018105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3763018105
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3264628334
Short name T399
Test name
Test status
Simulation time 3893613777 ps
CPU time 139.37 seconds
Started Jan 17 03:42:06 PM PST 24
Finished Jan 17 03:44:30 PM PST 24
Peak memory 198328 kb
Host smart-0242e57b-ea13-4007-ad1d-dff9e6a4be29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3264628334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3264628334
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3899703903
Short name T487
Test name
Test status
Simulation time 32400416 ps
CPU time 0.56 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 03:42:15 PM PST 24
Peak memory 193976 kb
Host smart-9cfbd694-9f05-42c4-bb4e-043eaf0bdcc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899703903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3899703903
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2235164248
Short name T867
Test name
Test status
Simulation time 84221873 ps
CPU time 0.88 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 197128 kb
Host smart-98a29670-9708-4161-812e-960be2cc60d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235164248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2235164248
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2738286165
Short name T569
Test name
Test status
Simulation time 310044900 ps
CPU time 16.67 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:29 PM PST 24
Peak memory 198144 kb
Host smart-5e3b2033-11e1-4aca-8361-c017c6aa5ee3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738286165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2738286165
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1390492637
Short name T381
Test name
Test status
Simulation time 116983685 ps
CPU time 0.96 seconds
Started Jan 17 03:42:11 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 198004 kb
Host smart-f029ef2e-cb11-4b32-b692-89859bd88284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390492637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1390492637
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1699398232
Short name T523
Test name
Test status
Simulation time 51585233 ps
CPU time 1.35 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 198124 kb
Host smart-4f412dba-7a7e-43ef-80c1-ed1bbc6423a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699398232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1699398232
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3808574684
Short name T435
Test name
Test status
Simulation time 135336914 ps
CPU time 1.6 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 03:42:16 PM PST 24
Peak memory 197000 kb
Host smart-13fbd3f0-e9b6-46cf-b810-c91b94e03e49
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808574684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3808574684
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.109993170
Short name T774
Test name
Test status
Simulation time 246636191 ps
CPU time 2.53 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:15 PM PST 24
Peak memory 195940 kb
Host smart-727e5223-fe4a-455e-baee-49b66dc8e0b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109993170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
109993170
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3786898304
Short name T801
Test name
Test status
Simulation time 71313808 ps
CPU time 1.4 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196652 kb
Host smart-88378cfe-d0cb-4dcd-8292-0faff927322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786898304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3786898304
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1028764865
Short name T594
Test name
Test status
Simulation time 158255349 ps
CPU time 0.92 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 196152 kb
Host smart-3983bd7c-aa62-4b2d-84ce-43b4f38dd1f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028764865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1028764865
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3112344463
Short name T722
Test name
Test status
Simulation time 102833121 ps
CPU time 4.75 seconds
Started Jan 17 03:42:17 PM PST 24
Finished Jan 17 03:42:23 PM PST 24
Peak memory 198144 kb
Host smart-60c91fe5-dee1-4c28-97e7-110bfb4c07e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112344463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3112344463
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.4076706152
Short name T711
Test name
Test status
Simulation time 42247443 ps
CPU time 1.21 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196544 kb
Host smart-b19c7a67-2d68-4187-82d1-ea303c709994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076706152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.4076706152
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.538573727
Short name T574
Test name
Test status
Simulation time 482822902 ps
CPU time 0.95 seconds
Started Jan 17 03:42:07 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196260 kb
Host smart-730efe48-21ba-46f3-aba4-24451f116469
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538573727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.538573727
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2760806475
Short name T275
Test name
Test status
Simulation time 860491112 ps
CPU time 25.75 seconds
Started Jan 17 03:42:12 PM PST 24
Finished Jan 17 03:42:39 PM PST 24
Peak memory 198164 kb
Host smart-5ac53db2-c053-4def-a9c0-20b9728df9da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760806475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2760806475
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.385362859
Short name T412
Test name
Test status
Simulation time 101863982758 ps
CPU time 357.86 seconds
Started Jan 17 03:42:12 PM PST 24
Finished Jan 17 03:48:11 PM PST 24
Peak memory 198544 kb
Host smart-b97afea6-d7ca-41e0-8a4d-80989bd54637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=385362859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.385362859
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1354928202
Short name T424
Test name
Test status
Simulation time 60950457 ps
CPU time 0.57 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 194756 kb
Host smart-2a0f9c1b-dc6c-45ab-aec9-cf94fca53d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354928202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1354928202
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3578574692
Short name T233
Test name
Test status
Simulation time 29964076 ps
CPU time 0.75 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 195276 kb
Host smart-959b8bb0-1e61-4e00-83b1-c4c4f7c2146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578574692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3578574692
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3271096257
Short name T239
Test name
Test status
Simulation time 1449891604 ps
CPU time 20.15 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:37 PM PST 24
Peak memory 196492 kb
Host smart-e762f6fe-58fc-474c-866f-cc4fa706ecca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271096257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3271096257
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2888932879
Short name T600
Test name
Test status
Simulation time 49569765 ps
CPU time 0.79 seconds
Started Jan 17 03:43:22 PM PST 24
Finished Jan 17 03:43:24 PM PST 24
Peak memory 196740 kb
Host smart-e7b40371-26df-4f4b-9be2-6527d0db92be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888932879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2888932879
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2800375111
Short name T841
Test name
Test status
Simulation time 35148901 ps
CPU time 0.74 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 195484 kb
Host smart-2ad12b6b-4ee0-4ffa-9512-e453d2658409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800375111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2800375111
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.446389852
Short name T554
Test name
Test status
Simulation time 450859467 ps
CPU time 1.69 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 196588 kb
Host smart-2c470c17-f195-4a47-9ca5-c76bc7f11070
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446389852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.446389852
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4287931762
Short name T425
Test name
Test status
Simulation time 95128547 ps
CPU time 1.96 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 196204 kb
Host smart-a447a75b-aec5-4b08-b4fb-84a5ef31c757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287931762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4287931762
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4032119509
Short name T758
Test name
Test status
Simulation time 32539980 ps
CPU time 0.96 seconds
Started Jan 17 03:42:11 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 197348 kb
Host smart-d9b348d7-5fb1-4b41-a319-6f9a94eecb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032119509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4032119509
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2165774026
Short name T454
Test name
Test status
Simulation time 619079357 ps
CPU time 1.39 seconds
Started Jan 17 03:42:12 PM PST 24
Finished Jan 17 03:42:15 PM PST 24
Peak memory 196648 kb
Host smart-a5d2680a-531a-458d-ad17-332a79a780a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165774026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2165774026
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.191789626
Short name T512
Test name
Test status
Simulation time 401303415 ps
CPU time 4.65 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:21 PM PST 24
Peak memory 198108 kb
Host smart-dd7490a4-8bc2-4b03-b773-10704d765d15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191789626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.191789626
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2492865260
Short name T248
Test name
Test status
Simulation time 174656548 ps
CPU time 1.26 seconds
Started Jan 17 03:42:11 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 197272 kb
Host smart-595c2a3f-b31f-43c0-b083-95a5da355807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492865260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2492865260
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1051141251
Short name T427
Test name
Test status
Simulation time 69472459 ps
CPU time 1 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 195368 kb
Host smart-aa5897be-e4c3-49a7-b7b6-8caacf5745ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051141251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1051141251
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2180489678
Short name T603
Test name
Test status
Simulation time 42690738293 ps
CPU time 242.73 seconds
Started Jan 17 03:42:14 PM PST 24
Finished Jan 17 03:46:18 PM PST 24
Peak memory 198284 kb
Host smart-8e65e619-d7b7-4acc-ac8c-d5208925d8e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180489678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2180489678
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2732144009
Short name T376
Test name
Test status
Simulation time 212879034505 ps
CPU time 2271.16 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 04:20:06 PM PST 24
Peak memory 198412 kb
Host smart-37a5c3be-b755-42e3-825a-4e734150ffdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2732144009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2732144009
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2925243598
Short name T796
Test name
Test status
Simulation time 29260664 ps
CPU time 0.57 seconds
Started Jan 17 03:42:26 PM PST 24
Finished Jan 17 03:42:27 PM PST 24
Peak memory 194252 kb
Host smart-f5eb29d6-3540-44cf-976d-d315ce5e450f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925243598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2925243598
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3866491900
Short name T662
Test name
Test status
Simulation time 15613491 ps
CPU time 0.63 seconds
Started Jan 17 03:42:17 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 194056 kb
Host smart-d477ac64-f7d2-43ec-b6ce-6dac66055ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866491900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3866491900
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.138282120
Short name T532
Test name
Test status
Simulation time 236663296 ps
CPU time 3.45 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:19 PM PST 24
Peak memory 195924 kb
Host smart-3454c8e2-f854-4103-9e57-af194f5dedac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138282120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.138282120
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3740389201
Short name T788
Test name
Test status
Simulation time 32685965 ps
CPU time 0.7 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 03:42:15 PM PST 24
Peak memory 194684 kb
Host smart-1669bbb6-f4d9-43dd-8a68-0dff3a1b5af4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740389201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3740389201
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.80696390
Short name T751
Test name
Test status
Simulation time 77411139 ps
CPU time 0.84 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 196536 kb
Host smart-db9083d2-e9e3-4e0d-9684-e77e4b564c4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80696390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.80696390
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.4053079408
Short name T489
Test name
Test status
Simulation time 39838579 ps
CPU time 1.06 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196232 kb
Host smart-b2a24aa0-3860-4670-aa77-c04632b2b5af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053079408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.4053079408
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.810661017
Short name T772
Test name
Test status
Simulation time 384935730 ps
CPU time 3.19 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 195872 kb
Host smart-80cf0653-2bad-4fae-ae65-0bb564f46bc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810661017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
810661017
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.442018635
Short name T782
Test name
Test status
Simulation time 43515790 ps
CPU time 1.03 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 196916 kb
Host smart-540dcd5d-9164-4edc-a4b3-be6da933d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442018635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.442018635
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2003913032
Short name T330
Test name
Test status
Simulation time 14632704 ps
CPU time 0.69 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 196076 kb
Host smart-d1e65c5a-435f-4373-876d-7e64489e0243
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003913032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2003913032
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2646327153
Short name T276
Test name
Test status
Simulation time 259193170 ps
CPU time 3.2 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 198096 kb
Host smart-e12846d0-3b2f-4e4d-ad99-c67d365537c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646327153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2646327153
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.600759226
Short name T410
Test name
Test status
Simulation time 94044862 ps
CPU time 1.5 seconds
Started Jan 17 03:42:09 PM PST 24
Finished Jan 17 03:42:14 PM PST 24
Peak memory 197008 kb
Host smart-f48242b3-8d27-4bc6-a073-e5f49f9d25b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600759226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.600759226
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.188429675
Short name T439
Test name
Test status
Simulation time 76995411 ps
CPU time 1.13 seconds
Started Jan 17 03:42:08 PM PST 24
Finished Jan 17 03:42:13 PM PST 24
Peak memory 196400 kb
Host smart-d33aa6ba-e7e4-4515-b394-8e3c030c0472
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188429675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.188429675
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2482704408
Short name T607
Test name
Test status
Simulation time 6946468329 ps
CPU time 104.9 seconds
Started Jan 17 03:42:18 PM PST 24
Finished Jan 17 03:44:03 PM PST 24
Peak memory 198284 kb
Host smart-68df1853-3d61-401c-a00e-b4d2edaa7963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482704408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2482704408
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.685490420
Short name T614
Test name
Test status
Simulation time 196339908347 ps
CPU time 804.69 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:55:41 PM PST 24
Peak memory 198420 kb
Host smart-50fd0385-045a-4a16-9db4-a97f4699f914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=685490420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.685490420
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3756367237
Short name T626
Test name
Test status
Simulation time 86620111 ps
CPU time 0.56 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 194112 kb
Host smart-b4eff89f-8c81-487c-99a7-393d8b9b8328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756367237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3756367237
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3797921791
Short name T502
Test name
Test status
Simulation time 375559698 ps
CPU time 0.76 seconds
Started Jan 17 03:42:17 PM PST 24
Finished Jan 17 03:42:19 PM PST 24
Peak memory 195324 kb
Host smart-2a001893-f3b7-43e2-aed7-7d9064d9b855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797921791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3797921791
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.4257338882
Short name T418
Test name
Test status
Simulation time 3053172810 ps
CPU time 26.08 seconds
Started Jan 17 03:42:26 PM PST 24
Finished Jan 17 03:42:53 PM PST 24
Peak memory 196868 kb
Host smart-c6c27170-f70e-43ea-b541-47a05265985e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257338882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.4257338882
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.27228046
Short name T250
Test name
Test status
Simulation time 86286835 ps
CPU time 1.08 seconds
Started Jan 17 03:42:17 PM PST 24
Finished Jan 17 03:42:19 PM PST 24
Peak memory 196744 kb
Host smart-3cc26b59-6919-4989-a0ec-3f2f7042b9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27228046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.27228046
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.4054234321
Short name T393
Test name
Test status
Simulation time 701449587 ps
CPU time 0.9 seconds
Started Jan 17 03:42:19 PM PST 24
Finished Jan 17 03:42:21 PM PST 24
Peak memory 196636 kb
Host smart-a8efb23a-97eb-4ab3-a8ff-bd92622df3cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054234321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.4054234321
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4086644500
Short name T580
Test name
Test status
Simulation time 37741349 ps
CPU time 1.27 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:19 PM PST 24
Peak memory 196640 kb
Host smart-70b515f3-6a7b-4030-ad0d-680a227e0065
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086644500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4086644500
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1302873844
Short name T687
Test name
Test status
Simulation time 47649690 ps
CPU time 1.04 seconds
Started Jan 17 03:42:26 PM PST 24
Finished Jan 17 03:42:27 PM PST 24
Peak memory 195692 kb
Host smart-f4478c2e-99d4-4564-8862-257f7ad089bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302873844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1302873844
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2189341335
Short name T369
Test name
Test status
Simulation time 49995074 ps
CPU time 0.77 seconds
Started Jan 17 03:42:15 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 195392 kb
Host smart-b32dc1c6-87b1-4267-966c-264b56f17fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189341335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2189341335
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2123078578
Short name T464
Test name
Test status
Simulation time 21421162 ps
CPU time 0.79 seconds
Started Jan 17 03:42:26 PM PST 24
Finished Jan 17 03:42:27 PM PST 24
Peak memory 196124 kb
Host smart-80814bbf-c316-461b-b7ba-3fc7c75b66d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123078578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2123078578
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3585910333
Short name T572
Test name
Test status
Simulation time 261811713 ps
CPU time 5.14 seconds
Started Jan 17 03:42:17 PM PST 24
Finished Jan 17 03:42:23 PM PST 24
Peak memory 198044 kb
Host smart-1fb0054c-8a60-4ed2-bf71-6bf34265d99e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585910333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3585910333
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.507001497
Short name T339
Test name
Test status
Simulation time 55599319 ps
CPU time 0.9 seconds
Started Jan 17 03:42:13 PM PST 24
Finished Jan 17 03:42:16 PM PST 24
Peak memory 196120 kb
Host smart-4385d69d-96eb-4e4b-a880-4b76b4bb2f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507001497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.507001497
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2864336943
Short name T646
Test name
Test status
Simulation time 62465750 ps
CPU time 1.04 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 195596 kb
Host smart-eb82e550-ecc6-49cd-a2ff-796d6d2ffab0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864336943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2864336943
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3556117908
Short name T227
Test name
Test status
Simulation time 27459570790 ps
CPU time 169.32 seconds
Started Jan 17 03:42:17 PM PST 24
Finished Jan 17 03:45:07 PM PST 24
Peak memory 198276 kb
Host smart-9643408a-df15-422f-9f28-5cdee20977de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556117908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3556117908
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2594215577
Short name T271
Test name
Test status
Simulation time 363218769674 ps
CPU time 683.97 seconds
Started Jan 17 03:42:18 PM PST 24
Finished Jan 17 03:53:43 PM PST 24
Peak memory 198384 kb
Host smart-483e71a3-eb4a-4589-ace2-9714ec0c69c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2594215577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2594215577
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2113732170
Short name T582
Test name
Test status
Simulation time 13079724 ps
CPU time 0.59 seconds
Started Jan 17 03:42:32 PM PST 24
Finished Jan 17 03:42:34 PM PST 24
Peak memory 194352 kb
Host smart-82e0b7c8-90aa-4354-a1e3-8cf78138b5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113732170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2113732170
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1751866179
Short name T377
Test name
Test status
Simulation time 17690111 ps
CPU time 0.69 seconds
Started Jan 17 03:42:22 PM PST 24
Finished Jan 17 03:42:24 PM PST 24
Peak memory 194156 kb
Host smart-ab4d3155-a987-4e37-a110-5a2e762c9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751866179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1751866179
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3735426001
Short name T703
Test name
Test status
Simulation time 2484576490 ps
CPU time 21.46 seconds
Started Jan 17 03:42:27 PM PST 24
Finished Jan 17 03:42:49 PM PST 24
Peak memory 197184 kb
Host smart-5e4eab1e-1da2-4d54-bc13-caea358d226f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735426001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3735426001
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3310472515
Short name T709
Test name
Test status
Simulation time 137227369 ps
CPU time 0.97 seconds
Started Jan 17 03:42:30 PM PST 24
Finished Jan 17 03:42:32 PM PST 24
Peak memory 196744 kb
Host smart-8f15e291-72ab-4552-b24f-0f839cc2d451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310472515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3310472515
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3016077411
Short name T689
Test name
Test status
Simulation time 163772276 ps
CPU time 1.22 seconds
Started Jan 17 03:42:26 PM PST 24
Finished Jan 17 03:42:28 PM PST 24
Peak memory 195868 kb
Host smart-eac8b9d6-2dcc-4c63-9bc6-2fa3d11115ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016077411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3016077411
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3246762324
Short name T371
Test name
Test status
Simulation time 133933293 ps
CPU time 1.56 seconds
Started Jan 17 03:42:21 PM PST 24
Finished Jan 17 03:42:23 PM PST 24
Peak memory 198288 kb
Host smart-0d3733cf-1939-4cc7-b7ad-37295ffac46b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246762324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3246762324
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2556407080
Short name T285
Test name
Test status
Simulation time 437748722 ps
CPU time 2.64 seconds
Started Jan 17 03:42:23 PM PST 24
Finished Jan 17 03:42:26 PM PST 24
Peak memory 198176 kb
Host smart-8cce48bf-9375-4de1-bc8a-12e37f64ab21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556407080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2556407080
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1822469792
Short name T713
Test name
Test status
Simulation time 31622896 ps
CPU time 1.05 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:17 PM PST 24
Peak memory 196204 kb
Host smart-48103c0c-bda6-4e7a-a239-b5ff574e960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822469792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1822469792
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1012155150
Short name T223
Test name
Test status
Simulation time 38439809 ps
CPU time 0.95 seconds
Started Jan 17 03:42:19 PM PST 24
Finished Jan 17 03:42:21 PM PST 24
Peak memory 196392 kb
Host smart-af59040a-f7c3-406a-8a51-565867593cf6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012155150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1012155150
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2387979212
Short name T498
Test name
Test status
Simulation time 632046314 ps
CPU time 5.29 seconds
Started Jan 17 03:42:29 PM PST 24
Finished Jan 17 03:42:36 PM PST 24
Peak memory 198124 kb
Host smart-066a8246-4061-43da-ad9f-be4400424e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387979212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2387979212
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.7487453
Short name T506
Test name
Test status
Simulation time 41400844 ps
CPU time 0.82 seconds
Started Jan 17 03:42:19 PM PST 24
Finished Jan 17 03:42:20 PM PST 24
Peak memory 195304 kb
Host smart-a7add99b-ff9b-4e07-b319-2f2c55269dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7487453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.7487453
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1228235950
Short name T821
Test name
Test status
Simulation time 39677375 ps
CPU time 0.88 seconds
Started Jan 17 03:42:16 PM PST 24
Finished Jan 17 03:42:18 PM PST 24
Peak memory 197264 kb
Host smart-1e8e54c1-1aba-4472-89ca-f55781430a82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228235950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1228235950
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2148183445
Short name T678
Test name
Test status
Simulation time 4375308485 ps
CPU time 110.18 seconds
Started Jan 17 03:42:28 PM PST 24
Finished Jan 17 03:44:20 PM PST 24
Peak memory 198260 kb
Host smart-fb27f0a3-50da-4a58-9201-3c50059014e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148183445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2148183445
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1442595578
Short name T592
Test name
Test status
Simulation time 311418983860 ps
CPU time 2113.04 seconds
Started Jan 17 03:42:28 PM PST 24
Finished Jan 17 04:17:42 PM PST 24
Peak memory 198348 kb
Host smart-31cae46b-c50e-490c-aaa3-efdd868134a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1442595578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1442595578
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1219308937
Short name T466
Test name
Test status
Simulation time 19514724 ps
CPU time 0.58 seconds
Started Jan 17 03:42:30 PM PST 24
Finished Jan 17 03:42:32 PM PST 24
Peak memory 194036 kb
Host smart-3e8282a3-9a78-490b-982d-ff30ad6f15eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219308937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1219308937
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.535186337
Short name T570
Test name
Test status
Simulation time 56977675 ps
CPU time 0.7 seconds
Started Jan 17 03:42:32 PM PST 24
Finished Jan 17 03:42:34 PM PST 24
Peak memory 194144 kb
Host smart-e815a340-b37e-4e76-b086-44b1bb505d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535186337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.535186337
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2763090506
Short name T337
Test name
Test status
Simulation time 1579370205 ps
CPU time 26.97 seconds
Started Jan 17 03:42:31 PM PST 24
Finished Jan 17 03:43:00 PM PST 24
Peak memory 197092 kb
Host smart-8d63c5e2-f31a-4f77-ae3b-95c6340c83e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763090506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2763090506
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2359489252
Short name T676
Test name
Test status
Simulation time 129909722 ps
CPU time 0.78 seconds
Started Jan 17 03:42:28 PM PST 24
Finished Jan 17 03:42:30 PM PST 24
Peak memory 196472 kb
Host smart-35ed7fd2-a5ae-42ac-a463-10f6c8be5631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359489252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2359489252
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2763870240
Short name T775
Test name
Test status
Simulation time 51785249 ps
CPU time 0.98 seconds
Started Jan 17 03:42:35 PM PST 24
Finished Jan 17 03:42:43 PM PST 24
Peak memory 195808 kb
Host smart-4e5ea31a-3351-4cd7-a274-91fb9bdcc4ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763870240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2763870240
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2320341842
Short name T363
Test name
Test status
Simulation time 60746439 ps
CPU time 2.53 seconds
Started Jan 17 03:42:30 PM PST 24
Finished Jan 17 03:42:34 PM PST 24
Peak memory 198212 kb
Host smart-c845bc4a-8506-4d95-a4db-a9fc5ff71055
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320341842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2320341842
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.724709060
Short name T350
Test name
Test status
Simulation time 146296114 ps
CPU time 1.05 seconds
Started Jan 17 03:42:31 PM PST 24
Finished Jan 17 03:42:33 PM PST 24
Peak memory 195564 kb
Host smart-e176c47d-e180-4785-851b-092a7f7c7e5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724709060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
724709060
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3713205769
Short name T624
Test name
Test status
Simulation time 38728534 ps
CPU time 0.63 seconds
Started Jan 17 03:42:27 PM PST 24
Finished Jan 17 03:42:28 PM PST 24
Peak memory 195112 kb
Host smart-8c761971-e4b4-4194-a447-b047e2bbc83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713205769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3713205769
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4056521695
Short name T858
Test name
Test status
Simulation time 107675565 ps
CPU time 1.22 seconds
Started Jan 17 03:42:29 PM PST 24
Finished Jan 17 03:42:32 PM PST 24
Peak memory 197060 kb
Host smart-2b98841b-0721-4f9d-b524-15a0709604c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056521695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.4056521695
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2107235121
Short name T468
Test name
Test status
Simulation time 380064407 ps
CPU time 2 seconds
Started Jan 17 03:42:32 PM PST 24
Finished Jan 17 03:42:35 PM PST 24
Peak memory 198164 kb
Host smart-70fab9ea-cc4f-4efd-83bb-fa7cc994ee98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107235121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2107235121
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2150120463
Short name T394
Test name
Test status
Simulation time 59686572 ps
CPU time 1.17 seconds
Started Jan 17 03:42:28 PM PST 24
Finished Jan 17 03:42:29 PM PST 24
Peak memory 195728 kb
Host smart-725f88d1-0c70-48e3-b945-f5b69548cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150120463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2150120463
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2271990705
Short name T308
Test name
Test status
Simulation time 240004113 ps
CPU time 1.2 seconds
Started Jan 17 03:42:31 PM PST 24
Finished Jan 17 03:42:35 PM PST 24
Peak memory 195700 kb
Host smart-24cd7293-1f92-454b-a638-de2b9aef4bde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271990705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2271990705
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1600221958
Short name T403
Test name
Test status
Simulation time 4052321632 ps
CPU time 58.95 seconds
Started Jan 17 03:42:34 PM PST 24
Finished Jan 17 03:43:41 PM PST 24
Peak memory 198248 kb
Host smart-e13ce3db-1712-4eb3-bbab-fb6775c776bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600221958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1600221958
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3867689638
Short name T313
Test name
Test status
Simulation time 11258194290 ps
CPU time 54.43 seconds
Started Jan 17 03:42:30 PM PST 24
Finished Jan 17 03:43:27 PM PST 24
Peak memory 198412 kb
Host smart-a539a7e2-d141-40b7-b5df-26ef4a2e1884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3867689638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3867689638
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.572891789
Short name T595
Test name
Test status
Simulation time 41561132 ps
CPU time 0.57 seconds
Started Jan 17 03:39:59 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 193992 kb
Host smart-bcfa0a09-3f67-4e83-9e5c-406cf4643ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572891789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.572891789
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1346346098
Short name T715
Test name
Test status
Simulation time 47611036 ps
CPU time 0.84 seconds
Started Jan 17 03:39:58 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 196368 kb
Host smart-d96216cb-d3a4-47f9-b0d5-b1f3a5788678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346346098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1346346098
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2980936963
Short name T590
Test name
Test status
Simulation time 2771172962 ps
CPU time 20.28 seconds
Started Jan 17 03:39:57 PM PST 24
Finished Jan 17 03:40:18 PM PST 24
Peak memory 196784 kb
Host smart-8cc6cbda-ba78-4769-a74c-ad405e8a82d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980936963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2980936963
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2168489110
Short name T778
Test name
Test status
Simulation time 74905569 ps
CPU time 0.76 seconds
Started Jan 17 03:39:59 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 195840 kb
Host smart-81aaa345-0994-441d-bef3-b82a8c1a189d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168489110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2168489110
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3615353940
Short name T586
Test name
Test status
Simulation time 19652991 ps
CPU time 0.73 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 195392 kb
Host smart-392fcde2-df36-4d48-aa87-00c8e914835f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615353940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3615353940
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1426567303
Short name T698
Test name
Test status
Simulation time 37758844 ps
CPU time 0.97 seconds
Started Jan 17 03:39:57 PM PST 24
Finished Jan 17 03:39:59 PM PST 24
Peak memory 196372 kb
Host smart-06ab9fd2-59e4-4591-b53a-cb675c20efda
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426567303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1426567303
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2224590272
Short name T449
Test name
Test status
Simulation time 156468654 ps
CPU time 3.2 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 197084 kb
Host smart-78e6f913-d0cb-4430-af4a-30e9056efba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224590272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2224590272
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1057081128
Short name T501
Test name
Test status
Simulation time 71939135 ps
CPU time 1.24 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 197008 kb
Host smart-98c2dc96-c0aa-416c-b1dd-bacf298081ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057081128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1057081128
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1005496141
Short name T670
Test name
Test status
Simulation time 25637294 ps
CPU time 0.97 seconds
Started Jan 17 03:39:54 PM PST 24
Finished Jan 17 03:39:56 PM PST 24
Peak memory 196756 kb
Host smart-c107c2e1-4eea-424c-a407-cb1c4f4fd635
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005496141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1005496141
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3215694263
Short name T769
Test name
Test status
Simulation time 302444184 ps
CPU time 5.06 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:15 PM PST 24
Peak memory 197900 kb
Host smart-6bdd6bbc-e7bd-4f11-844c-35ee610de922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215694263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3215694263
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3921433537
Short name T219
Test name
Test status
Simulation time 82571679 ps
CPU time 1.42 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 197000 kb
Host smart-c3ea0259-b8d8-4c31-86c8-3409c706fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921433537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3921433537
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.152477990
Short name T766
Test name
Test status
Simulation time 218147915 ps
CPU time 1.16 seconds
Started Jan 17 03:39:51 PM PST 24
Finished Jan 17 03:39:53 PM PST 24
Peak memory 196596 kb
Host smart-4dc8520f-8d00-428e-90a3-1a54e5d228d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152477990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.152477990
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2895676332
Short name T558
Test name
Test status
Simulation time 11817855655 ps
CPU time 32.43 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:40:28 PM PST 24
Peak memory 198288 kb
Host smart-bdf80aec-15a0-4565-9d2b-ac343528f344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895676332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2895676332
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1865897405
Short name T822
Test name
Test status
Simulation time 43396466169 ps
CPU time 299.86 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:45:10 PM PST 24
Peak memory 198060 kb
Host smart-de43be43-6f04-412e-894b-f152ee25b394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1865897405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1865897405
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.515045959
Short name T385
Test name
Test status
Simulation time 20409466 ps
CPU time 0.55 seconds
Started Jan 17 03:40:01 PM PST 24
Finished Jan 17 03:40:02 PM PST 24
Peak memory 194052 kb
Host smart-f8533d9f-ecb5-44c6-adf6-6e2bed37d9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515045959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.515045959
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.765756511
Short name T265
Test name
Test status
Simulation time 35089983 ps
CPU time 0.67 seconds
Started Jan 17 03:39:58 PM PST 24
Finished Jan 17 03:39:59 PM PST 24
Peak memory 193988 kb
Host smart-ca072499-891c-48d9-94cd-15decb4447c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765756511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.765756511
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3991437419
Short name T781
Test name
Test status
Simulation time 1280042691 ps
CPU time 17.71 seconds
Started Jan 17 03:39:57 PM PST 24
Finished Jan 17 03:40:16 PM PST 24
Peak memory 195692 kb
Host smart-9426b8c3-dc82-4384-a1ed-0f9498f77023
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991437419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3991437419
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2549426020
Short name T625
Test name
Test status
Simulation time 67113857 ps
CPU time 0.95 seconds
Started Jan 17 03:39:58 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 197756 kb
Host smart-73c07322-d74d-4b7a-a5b4-6bdee18e3608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549426020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2549426020
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3021889485
Short name T238
Test name
Test status
Simulation time 420840106 ps
CPU time 1.51 seconds
Started Jan 17 03:40:01 PM PST 24
Finished Jan 17 03:40:03 PM PST 24
Peak memory 197288 kb
Host smart-2735d736-bcb1-48f7-bb6b-09f1d9f9ab1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021889485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3021889485
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.739474675
Short name T329
Test name
Test status
Simulation time 47306318 ps
CPU time 1.85 seconds
Started Jan 17 03:39:58 PM PST 24
Finished Jan 17 03:40:01 PM PST 24
Peak memory 198420 kb
Host smart-de252300-e14e-438b-a51a-37a7161d26cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739474675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.739474675
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.599132345
Short name T764
Test name
Test status
Simulation time 108505017 ps
CPU time 1.82 seconds
Started Jan 17 03:40:01 PM PST 24
Finished Jan 17 03:40:04 PM PST 24
Peak memory 196864 kb
Host smart-25594cf5-0b40-4838-b696-7b9b068cbd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599132345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.599132345
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1078281827
Short name T241
Test name
Test status
Simulation time 166418900 ps
CPU time 1.03 seconds
Started Jan 17 03:39:55 PM PST 24
Finished Jan 17 03:39:57 PM PST 24
Peak memory 196100 kb
Host smart-a9305e74-8a56-4d70-bb42-29c58939e807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078281827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1078281827
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.333375442
Short name T444
Test name
Test status
Simulation time 52814317 ps
CPU time 0.7 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:10 PM PST 24
Peak memory 194024 kb
Host smart-3103aed3-1ade-48d7-b6ee-3d33171d1803
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333375442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.333375442
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1928666102
Short name T768
Test name
Test status
Simulation time 88932885 ps
CPU time 2.21 seconds
Started Jan 17 03:39:57 PM PST 24
Finished Jan 17 03:40:01 PM PST 24
Peak memory 198072 kb
Host smart-39f7af5d-a0e0-4c0e-8c00-26cbeef8135a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928666102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1928666102
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3006010553
Short name T406
Test name
Test status
Simulation time 34409054 ps
CPU time 1.06 seconds
Started Jan 17 03:39:56 PM PST 24
Finished Jan 17 03:39:58 PM PST 24
Peak memory 195612 kb
Host smart-43bd52bf-0605-420d-866f-dbb4664dfa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006010553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3006010553
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2811836887
Short name T534
Test name
Test status
Simulation time 29665208 ps
CPU time 0.88 seconds
Started Jan 17 03:39:59 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 195928 kb
Host smart-2de93b6f-5506-47e9-9d04-5cfac32d5093
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811836887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2811836887
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1020515519
Short name T216
Test name
Test status
Simulation time 10835750585 ps
CPU time 130.29 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:42:20 PM PST 24
Peak memory 197908 kb
Host smart-ad6890f6-7826-428d-a2ef-581865e403bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020515519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1020515519
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1068777620
Short name T812
Test name
Test status
Simulation time 107187529541 ps
CPU time 475.48 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:48:05 PM PST 24
Peak memory 206148 kb
Host smart-acf94f9b-b676-4a71-964a-b826865dd442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1068777620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1068777620
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.540623071
Short name T749
Test name
Test status
Simulation time 11952827 ps
CPU time 0.58 seconds
Started Jan 17 03:40:00 PM PST 24
Finished Jan 17 03:40:01 PM PST 24
Peak memory 194096 kb
Host smart-2e31cfc4-7fb8-43ea-aa77-77cc5d8ac24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540623071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.540623071
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3562568998
Short name T839
Test name
Test status
Simulation time 46534571 ps
CPU time 1 seconds
Started Jan 17 03:40:01 PM PST 24
Finished Jan 17 03:40:03 PM PST 24
Peak memory 197304 kb
Host smart-5a775b8a-7332-4988-ae50-1a1ec2541cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562568998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3562568998
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.227706728
Short name T771
Test name
Test status
Simulation time 6667970088 ps
CPU time 20.82 seconds
Started Jan 17 03:40:00 PM PST 24
Finished Jan 17 03:40:22 PM PST 24
Peak memory 196804 kb
Host smart-a32bd140-1915-4be2-bc0f-b8ca37b48e34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227706728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.227706728
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.198542983
Short name T737
Test name
Test status
Simulation time 109943355 ps
CPU time 0.95 seconds
Started Jan 17 03:40:13 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 198144 kb
Host smart-f0002ae7-f675-48c9-9a7c-2b7f93c4f76f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198542983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.198542983
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3516861052
Short name T526
Test name
Test status
Simulation time 91686689 ps
CPU time 1.13 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196276 kb
Host smart-38ee2856-7f3d-44e8-b2a7-4a11ef66d5ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516861052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3516861052
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.236624377
Short name T598
Test name
Test status
Simulation time 83206280 ps
CPU time 0.93 seconds
Started Jan 17 03:39:59 PM PST 24
Finished Jan 17 03:40:00 PM PST 24
Peak memory 196888 kb
Host smart-a45df651-c519-4946-a840-c081b139ac7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236624377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.236624377
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3480987902
Short name T333
Test name
Test status
Simulation time 514585358 ps
CPU time 3.08 seconds
Started Jan 17 03:40:01 PM PST 24
Finished Jan 17 03:40:05 PM PST 24
Peak memory 197548 kb
Host smart-6c8dbdb0-2d5c-457e-afc9-5328ef416836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480987902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3480987902
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1912694608
Short name T431
Test name
Test status
Simulation time 94286739 ps
CPU time 1.22 seconds
Started Jan 17 03:39:59 PM PST 24
Finished Jan 17 03:40:01 PM PST 24
Peak memory 195968 kb
Host smart-b4317003-0267-46d7-997a-751504f44685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912694608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1912694608
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3049135778
Short name T440
Test name
Test status
Simulation time 51582175 ps
CPU time 1.18 seconds
Started Jan 17 03:39:59 PM PST 24
Finished Jan 17 03:40:01 PM PST 24
Peak memory 196880 kb
Host smart-6b9acedf-af5e-4b12-8de5-2df050f9e354
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049135778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3049135778
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1943408116
Short name T632
Test name
Test status
Simulation time 119534264 ps
CPU time 5.3 seconds
Started Jan 17 03:40:02 PM PST 24
Finished Jan 17 03:40:08 PM PST 24
Peak memory 198076 kb
Host smart-16dac4d3-36b4-41fb-9939-a2f00e5689bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943408116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1943408116
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1546900034
Short name T263
Test name
Test status
Simulation time 37581842 ps
CPU time 0.99 seconds
Started Jan 17 03:40:13 PM PST 24
Finished Jan 17 03:40:20 PM PST 24
Peak memory 196392 kb
Host smart-e4d502a5-5335-4e39-8008-2b14f7d520d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546900034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1546900034
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2595187027
Short name T880
Test name
Test status
Simulation time 43445793 ps
CPU time 1.12 seconds
Started Jan 17 03:40:00 PM PST 24
Finished Jan 17 03:40:02 PM PST 24
Peak memory 195668 kb
Host smart-b5c054e9-e90a-4622-837b-8083febf4f6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595187027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2595187027
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2829135912
Short name T606
Test name
Test status
Simulation time 34381624263 ps
CPU time 86.99 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:41:46 PM PST 24
Peak memory 198284 kb
Host smart-26afecc0-de77-437b-8b3d-c5268629f9c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829135912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2829135912
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1449318394
Short name T873
Test name
Test status
Simulation time 118706123776 ps
CPU time 1332.11 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 04:02:22 PM PST 24
Peak memory 198408 kb
Host smart-87b77ffd-6357-49cc-bd37-a8b1ed48eec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1449318394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1449318394
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1307768990
Short name T820
Test name
Test status
Simulation time 21373046 ps
CPU time 0.61 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:10 PM PST 24
Peak memory 194792 kb
Host smart-8ddb9b35-3312-4948-89f2-d6cbac7afdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307768990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1307768990
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1207754287
Short name T725
Test name
Test status
Simulation time 38050092 ps
CPU time 0.75 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 196056 kb
Host smart-948cca4a-d984-4d2b-8143-dd7d52bc83d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207754287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1207754287
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2917772910
Short name T500
Test name
Test status
Simulation time 694914527 ps
CPU time 24.66 seconds
Started Jan 17 03:40:17 PM PST 24
Finished Jan 17 03:40:44 PM PST 24
Peak memory 196980 kb
Host smart-090b4ac1-5f7e-4543-9238-7c0217ad22f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917772910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2917772910
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.496052641
Short name T309
Test name
Test status
Simulation time 1030931735 ps
CPU time 0.92 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:11 PM PST 24
Peak memory 196088 kb
Host smart-484c1dbb-f5f5-418a-bcf8-f5f3cd7ca118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496052641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.496052641
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.240535800
Short name T803
Test name
Test status
Simulation time 25956893 ps
CPU time 0.72 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 195064 kb
Host smart-c0bde922-1f6e-4609-a658-cea25a546c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240535800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.240535800
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2556728070
Short name T298
Test name
Test status
Simulation time 320225216 ps
CPU time 3.33 seconds
Started Jan 17 03:40:07 PM PST 24
Finished Jan 17 03:40:14 PM PST 24
Peak memory 198180 kb
Host smart-a552d3dd-b22b-44cb-841a-c81d08044e7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556728070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2556728070
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1016215795
Short name T701
Test name
Test status
Simulation time 291613515 ps
CPU time 3.54 seconds
Started Jan 17 03:40:07 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 196644 kb
Host smart-a20b28e3-6691-4aaa-b5ac-49d6dcc2735d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016215795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1016215795
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.114088132
Short name T269
Test name
Test status
Simulation time 101520276 ps
CPU time 0.65 seconds
Started Jan 17 03:40:04 PM PST 24
Finished Jan 17 03:40:06 PM PST 24
Peak memory 195036 kb
Host smart-05cf3720-dd8c-4a74-8c94-0ce296566a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114088132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.114088132
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3776057676
Short name T472
Test name
Test status
Simulation time 27528113 ps
CPU time 0.72 seconds
Started Jan 17 03:40:12 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 194232 kb
Host smart-2c19271f-afaf-4cec-9106-4ebd1b922e5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776057676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3776057676
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3054050208
Short name T314
Test name
Test status
Simulation time 653810592 ps
CPU time 1.36 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 198132 kb
Host smart-3e8a46d5-1d1e-48d2-8d46-e532bc60557c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054050208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3054050208
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2580264948
Short name T608
Test name
Test status
Simulation time 698508787 ps
CPU time 1.41 seconds
Started Jan 17 03:40:14 PM PST 24
Finished Jan 17 03:40:21 PM PST 24
Peak memory 196844 kb
Host smart-9d0df598-11e4-4bee-baa6-a435f781eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580264948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2580264948
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2334498282
Short name T311
Test name
Test status
Simulation time 152753691 ps
CPU time 1.42 seconds
Started Jan 17 03:40:07 PM PST 24
Finished Jan 17 03:40:11 PM PST 24
Peak memory 196944 kb
Host smart-d371d2ad-4e57-43c9-8743-0d0de293aa3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334498282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2334498282
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1410956561
Short name T557
Test name
Test status
Simulation time 62642983174 ps
CPU time 243.1 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:44:09 PM PST 24
Peak memory 198192 kb
Host smart-c5a94c99-e54c-49c0-a26d-8f60f65650d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410956561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1410956561
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2364521368
Short name T710
Test name
Test status
Simulation time 221834301291 ps
CPU time 1308.01 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 04:01:57 PM PST 24
Peak memory 198392 kb
Host smart-ecf8ccd5-d24c-43c7-a9df-6df5bffe3f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2364521368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2364521368
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4000325232
Short name T566
Test name
Test status
Simulation time 41823113 ps
CPU time 0.56 seconds
Started Jan 17 03:40:08 PM PST 24
Finished Jan 17 03:40:12 PM PST 24
Peak memory 194072 kb
Host smart-f99566d0-d855-4d60-8439-d8cc094b1256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000325232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4000325232
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2957527323
Short name T604
Test name
Test status
Simulation time 52305865 ps
CPU time 0.98 seconds
Started Jan 17 03:40:10 PM PST 24
Finished Jan 17 03:40:13 PM PST 24
Peak memory 196068 kb
Host smart-c1dcf7b4-2575-44b0-b2ce-a1f2bfb368ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957527323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2957527323
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1738276491
Short name T361
Test name
Test status
Simulation time 963118473 ps
CPU time 21.59 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:28 PM PST 24
Peak memory 198128 kb
Host smart-8b591d7a-df14-459f-8de7-35887ee1c92f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738276491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1738276491
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3885936868
Short name T42
Test name
Test status
Simulation time 322946632 ps
CPU time 1.19 seconds
Started Jan 17 03:40:08 PM PST 24
Finished Jan 17 03:40:12 PM PST 24
Peak memory 197972 kb
Host smart-4f230073-1d9c-4893-9268-9ca08572433c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885936868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3885936868
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.176937800
Short name T845
Test name
Test status
Simulation time 45637975 ps
CPU time 1.13 seconds
Started Jan 17 03:40:03 PM PST 24
Finished Jan 17 03:40:05 PM PST 24
Peak memory 195916 kb
Host smart-0606772f-ba64-48f0-aeab-0405aef49cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176937800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.176937800
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1720358779
Short name T103
Test name
Test status
Simulation time 59416563 ps
CPU time 2.33 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:40:08 PM PST 24
Peak memory 198212 kb
Host smart-d0cc3321-d7ab-4eb9-bc52-bbb0a7024f04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720358779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1720358779
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1213399324
Short name T837
Test name
Test status
Simulation time 134330313 ps
CPU time 1.62 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:11 PM PST 24
Peak memory 196832 kb
Host smart-677c0121-3c45-45c3-bf84-576fc657540b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213399324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1213399324
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3968666309
Short name T362
Test name
Test status
Simulation time 61184106 ps
CPU time 1.43 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:09 PM PST 24
Peak memory 197296 kb
Host smart-57f69071-5709-4bc6-8f71-b4a321915dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968666309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3968666309
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.861208734
Short name T673
Test name
Test status
Simulation time 38544278 ps
CPU time 0.97 seconds
Started Jan 17 03:40:07 PM PST 24
Finished Jan 17 03:40:11 PM PST 24
Peak memory 196900 kb
Host smart-385ccac4-8dc7-456b-8d4c-356d984a974b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861208734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.861208734
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3932024748
Short name T547
Test name
Test status
Simulation time 132112905 ps
CPU time 2.41 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:40:08 PM PST 24
Peak memory 198064 kb
Host smart-ef53bc1e-4098-4b78-9cca-9cc76384019e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932024748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3932024748
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2126549067
Short name T538
Test name
Test status
Simulation time 64279084 ps
CPU time 1.28 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:40:07 PM PST 24
Peak memory 196004 kb
Host smart-16a83b7c-648d-48dd-b251-8a53b7068be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126549067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2126549067
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.478801441
Short name T696
Test name
Test status
Simulation time 42267001 ps
CPU time 0.77 seconds
Started Jan 17 03:40:06 PM PST 24
Finished Jan 17 03:40:08 PM PST 24
Peak memory 196012 kb
Host smart-61836913-0f7a-415f-8cd9-a4733f366fc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478801441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.478801441
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.426990741
Short name T340
Test name
Test status
Simulation time 78726287209 ps
CPU time 249.21 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:44:15 PM PST 24
Peak memory 198232 kb
Host smart-10e4c111-0505-4e18-9379-3ed72836c223
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426990741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.426990741
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2023003746
Short name T770
Test name
Test status
Simulation time 379125850835 ps
CPU time 1150.47 seconds
Started Jan 17 03:40:05 PM PST 24
Finished Jan 17 03:59:17 PM PST 24
Peak memory 206644 kb
Host smart-66e2df02-8137-4e76-ba0b-5ab81ab79bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2023003746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2023003746
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1804770964
Short name T199
Test name
Test status
Simulation time 50585730 ps
CPU time 1.1 seconds
Started Jan 17 01:01:14 PM PST 24
Finished Jan 17 01:01:18 PM PST 24
Peak memory 195368 kb
Host smart-720f9f50-1225-460e-a25b-cd43b9b0f251
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1804770964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1804770964
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4149383176
Short name T197
Test name
Test status
Simulation time 98744211 ps
CPU time 1.41 seconds
Started Jan 17 01:01:16 PM PST 24
Finished Jan 17 01:01:20 PM PST 24
Peak memory 196420 kb
Host smart-d256e13f-4fe6-43d6-b538-577dfcdcfc3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149383176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4149383176
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3378112775
Short name T145
Test name
Test status
Simulation time 75551687 ps
CPU time 0.96 seconds
Started Jan 17 01:01:21 PM PST 24
Finished Jan 17 01:01:23 PM PST 24
Peak memory 196396 kb
Host smart-a7fcafe7-b62f-41f0-931d-1d205e4896ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3378112775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3378112775
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.990985570
Short name T177
Test name
Test status
Simulation time 33596977 ps
CPU time 0.84 seconds
Started Jan 17 01:01:22 PM PST 24
Finished Jan 17 01:01:23 PM PST 24
Peak memory 195240 kb
Host smart-a2e4036c-661e-47ac-9b7c-b44eb185097c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990985570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.990985570
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.200222793
Short name T155
Test name
Test status
Simulation time 65380848 ps
CPU time 1.35 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196632 kb
Host smart-15166a74-aa62-4024-8f7a-0ac3d244089d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=200222793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.200222793
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2763720144
Short name T54
Test name
Test status
Simulation time 160782044 ps
CPU time 1.04 seconds
Started Jan 17 01:01:20 PM PST 24
Finished Jan 17 01:01:22 PM PST 24
Peak memory 195596 kb
Host smart-3c83c040-2cb7-47f4-935c-0b32a82d531a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763720144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2763720144
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1773765373
Short name T139
Test name
Test status
Simulation time 33906223 ps
CPU time 1.06 seconds
Started Jan 17 01:01:23 PM PST 24
Finished Jan 17 01:01:24 PM PST 24
Peak memory 196092 kb
Host smart-33eb51e5-8a49-442f-a974-539960ff1d33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1773765373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1773765373
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.406531030
Short name T190
Test name
Test status
Simulation time 123611345 ps
CPU time 0.82 seconds
Started Jan 17 01:01:27 PM PST 24
Finished Jan 17 01:01:28 PM PST 24
Peak memory 195204 kb
Host smart-352c9032-4949-4a77-8125-ee82ae85777d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406531030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.406531030
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.985856152
Short name T142
Test name
Test status
Simulation time 61024856 ps
CPU time 1.01 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196244 kb
Host smart-f8ed9d68-3726-405f-bc33-26d288e117ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=985856152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.985856152
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.328192028
Short name T179
Test name
Test status
Simulation time 266216125 ps
CPU time 1.07 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 195344 kb
Host smart-a6a4b14b-cc8e-4334-9bc1-1c079dca5843
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328192028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.328192028
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4160537757
Short name T123
Test name
Test status
Simulation time 67563202 ps
CPU time 1.27 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196712 kb
Host smart-63c19e31-4cd7-4c7e-b8b0-2ad686d02410
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4160537757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.4160537757
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2770866389
Short name T180
Test name
Test status
Simulation time 79516093 ps
CPU time 0.91 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:26 PM PST 24
Peak memory 196000 kb
Host smart-882d3715-7e95-4791-9708-b322b5854ffa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770866389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2770866389
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4238347673
Short name T150
Test name
Test status
Simulation time 73256267 ps
CPU time 1.42 seconds
Started Jan 17 01:01:23 PM PST 24
Finished Jan 17 01:01:25 PM PST 24
Peak memory 196584 kb
Host smart-ff27e0b7-04d1-4205-b990-5e2e78bad469
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4238347673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4238347673
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.143651568
Short name T53
Test name
Test status
Simulation time 192108525 ps
CPU time 1.23 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196228 kb
Host smart-4e4c8881-5020-4479-a4ce-eb040b20c774
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143651568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.143651568
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.890907857
Short name T184
Test name
Test status
Simulation time 156783571 ps
CPU time 0.99 seconds
Started Jan 17 01:01:20 PM PST 24
Finished Jan 17 01:01:22 PM PST 24
Peak memory 195412 kb
Host smart-b9ff5fab-af5d-4b76-a3f2-3dd4b3713308
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=890907857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.890907857
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1541053207
Short name T175
Test name
Test status
Simulation time 46010872 ps
CPU time 1.14 seconds
Started Jan 17 01:01:24 PM PST 24
Finished Jan 17 01:01:25 PM PST 24
Peak memory 195492 kb
Host smart-17b03ecb-a4cf-4204-8903-6a6d1a6408ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541053207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1541053207
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688740649
Short name T146
Test name
Test status
Simulation time 225698048 ps
CPU time 1.17 seconds
Started Jan 17 01:01:23 PM PST 24
Finished Jan 17 01:01:25 PM PST 24
Peak memory 195680 kb
Host smart-99f926cd-0b7e-4582-add4-00129ab888dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688740649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2688740649
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1637900790
Short name T51
Test name
Test status
Simulation time 69220331 ps
CPU time 1.15 seconds
Started Jan 17 01:01:26 PM PST 24
Finished Jan 17 01:01:28 PM PST 24
Peak memory 196300 kb
Host smart-711412af-3a48-41c4-83c5-34d735ff00af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1637900790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1637900790
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2176817710
Short name T135
Test name
Test status
Simulation time 59221672 ps
CPU time 1.41 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196300 kb
Host smart-6455d701-e46d-47d6-8533-bad0899b9793
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176817710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2176817710
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2364383114
Short name T208
Test name
Test status
Simulation time 55033218 ps
CPU time 1.07 seconds
Started Jan 17 01:01:34 PM PST 24
Finished Jan 17 01:01:37 PM PST 24
Peak memory 195640 kb
Host smart-69c6b382-5f7d-4277-92d6-16c6c1c975e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2364383114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2364383114
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.905095233
Short name T170
Test name
Test status
Simulation time 159422231 ps
CPU time 1.05 seconds
Started Jan 17 01:01:35 PM PST 24
Finished Jan 17 01:01:38 PM PST 24
Peak memory 196408 kb
Host smart-14582ddc-5d48-4076-accb-882848ff1ace
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905095233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.905095233
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3629932052
Short name T48
Test name
Test status
Simulation time 89810626 ps
CPU time 0.74 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:45 PM PST 24
Peak memory 195180 kb
Host smart-b1e8c456-28cc-4375-9b4f-09556c575d99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3629932052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3629932052
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1709417095
Short name T191
Test name
Test status
Simulation time 105992196 ps
CPU time 1.15 seconds
Started Jan 17 01:01:34 PM PST 24
Finished Jan 17 01:01:37 PM PST 24
Peak memory 197676 kb
Host smart-6f614767-f5b2-44bd-9720-4ae3115fbf63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709417095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1709417095
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.589887660
Short name T178
Test name
Test status
Simulation time 113351324 ps
CPU time 1.09 seconds
Started Jan 17 01:01:26 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196388 kb
Host smart-a71446ad-1d15-4d79-af6d-58368f20c9fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=589887660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.589887660
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.745098524
Short name T160
Test name
Test status
Simulation time 147643166 ps
CPU time 1.07 seconds
Started Jan 17 01:01:26 PM PST 24
Finished Jan 17 01:01:28 PM PST 24
Peak memory 197696 kb
Host smart-31a2c1e8-9ffe-4555-94a5-21839c4e3eb8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745098524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.745098524
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3439261055
Short name T128
Test name
Test status
Simulation time 90682189 ps
CPU time 1.38 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197720 kb
Host smart-4ada37d7-d404-41ea-9eee-c7c4d6efc89e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3439261055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3439261055
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778566351
Short name T168
Test name
Test status
Simulation time 44089138 ps
CPU time 0.89 seconds
Started Jan 17 01:01:34 PM PST 24
Finished Jan 17 01:01:37 PM PST 24
Peak memory 195004 kb
Host smart-7030f3ea-6860-4888-9d0f-2d62bc8a7ada
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778566351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.778566351
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3304967494
Short name T172
Test name
Test status
Simulation time 144846985 ps
CPU time 1.13 seconds
Started Jan 17 01:01:33 PM PST 24
Finished Jan 17 01:01:36 PM PST 24
Peak memory 195364 kb
Host smart-257dda06-7ee9-429a-b931-136a62f55e2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3304967494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3304967494
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.366230421
Short name T185
Test name
Test status
Simulation time 168537105 ps
CPU time 1.38 seconds
Started Jan 17 01:01:42 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196756 kb
Host smart-b14e119d-cc2c-4b53-924b-ae5f13e7bf14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366230421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.366230421
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3307667228
Short name T151
Test name
Test status
Simulation time 39213606 ps
CPU time 1 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196472 kb
Host smart-912f093c-f982-43c2-87d2-967842509ab4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3307667228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3307667228
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.145141585
Short name T134
Test name
Test status
Simulation time 42218587 ps
CPU time 1.11 seconds
Started Jan 17 01:01:34 PM PST 24
Finished Jan 17 01:01:37 PM PST 24
Peak memory 195592 kb
Host smart-96288396-7e6b-4959-a2a8-8fa043b1c8c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145141585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.145141585
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2924079448
Short name T174
Test name
Test status
Simulation time 120104023 ps
CPU time 1.28 seconds
Started Jan 17 01:01:31 PM PST 24
Finished Jan 17 01:01:34 PM PST 24
Peak memory 197732 kb
Host smart-57109295-0ca2-4c2e-9ba3-5bf4fac7d8d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2924079448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2924079448
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.699760551
Short name T148
Test name
Test status
Simulation time 88468094 ps
CPU time 1.41 seconds
Started Jan 17 01:01:45 PM PST 24
Finished Jan 17 01:01:48 PM PST 24
Peak memory 195396 kb
Host smart-9496cc22-f214-4e46-a58d-c8b053a5c9e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699760551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.699760551
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3037306496
Short name T125
Test name
Test status
Simulation time 309914698 ps
CPU time 1.04 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197696 kb
Host smart-ad26475b-f884-4a13-9838-32f235a6edfd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3037306496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3037306496
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3161926247
Short name T70
Test name
Test status
Simulation time 1013935965 ps
CPU time 1.63 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195000 kb
Host smart-f10dd59d-9dc7-4bae-a216-0cef2dbaaf35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161926247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3161926247
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3687375087
Short name T49
Test name
Test status
Simulation time 37231519 ps
CPU time 1.18 seconds
Started Jan 17 01:01:35 PM PST 24
Finished Jan 17 01:01:37 PM PST 24
Peak memory 196664 kb
Host smart-95a65717-9f82-4cc6-9f5f-bbf733f45fbe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3687375087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3687375087
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.583539361
Short name T141
Test name
Test status
Simulation time 94492216 ps
CPU time 1.56 seconds
Started Jan 17 01:01:34 PM PST 24
Finished Jan 17 01:01:38 PM PST 24
Peak memory 197660 kb
Host smart-b821cda9-19c5-4c7c-9204-587b72003c31
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583539361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.583539361
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4287729389
Short name T39
Test name
Test status
Simulation time 92392462 ps
CPU time 1.45 seconds
Started Jan 17 01:01:40 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197768 kb
Host smart-4d154608-222b-4c87-8c6c-10988742fd9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4287729389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4287729389
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.789253186
Short name T130
Test name
Test status
Simulation time 51249113 ps
CPU time 1.09 seconds
Started Jan 17 01:01:35 PM PST 24
Finished Jan 17 01:01:38 PM PST 24
Peak memory 197908 kb
Host smart-502885ba-397c-4d02-96a2-a9ed6a144f6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789253186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.789253186
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1625879157
Short name T202
Test name
Test status
Simulation time 113016651 ps
CPU time 0.91 seconds
Started Jan 17 01:01:33 PM PST 24
Finished Jan 17 01:01:36 PM PST 24
Peak memory 195276 kb
Host smart-7f108fa1-8edc-4a06-ac67-6a74afd9651e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1625879157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1625879157
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2163753203
Short name T144
Test name
Test status
Simulation time 148881924 ps
CPU time 1.21 seconds
Started Jan 17 01:01:33 PM PST 24
Finished Jan 17 01:01:36 PM PST 24
Peak memory 195380 kb
Host smart-b8fb4d83-9a83-4982-b495-b20437d87538
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163753203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2163753203
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2116815617
Short name T129
Test name
Test status
Simulation time 53381094 ps
CPU time 0.9 seconds
Started Jan 17 01:01:32 PM PST 24
Finished Jan 17 01:01:36 PM PST 24
Peak memory 196188 kb
Host smart-d3b22502-ae25-4c88-8fc2-f7e961fdf025
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2116815617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2116815617
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2642992702
Short name T183
Test name
Test status
Simulation time 148240112 ps
CPU time 1.37 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195740 kb
Host smart-39107040-270b-4302-8c54-1cfb05bbb332
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642992702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2642992702
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1249777899
Short name T162
Test name
Test status
Simulation time 134350877 ps
CPU time 1.02 seconds
Started Jan 17 01:01:36 PM PST 24
Finished Jan 17 01:01:45 PM PST 24
Peak memory 195596 kb
Host smart-0c8bbdcf-8469-4774-9b0e-e66877d9abcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1249777899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1249777899
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3760267557
Short name T40
Test name
Test status
Simulation time 555458609 ps
CPU time 1 seconds
Started Jan 17 01:01:45 PM PST 24
Finished Jan 17 01:01:48 PM PST 24
Peak memory 196368 kb
Host smart-7d3dfe7f-9a32-4ca0-9d8d-479d9a038f7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760267557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3760267557
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1244395051
Short name T195
Test name
Test status
Simulation time 164424075 ps
CPU time 1.25 seconds
Started Jan 17 01:01:23 PM PST 24
Finished Jan 17 01:01:25 PM PST 24
Peak memory 196392 kb
Host smart-2af5c402-abdc-4b1b-89e5-6137d345eab9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1244395051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1244395051
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2899179362
Short name T189
Test name
Test status
Simulation time 46586250 ps
CPU time 1.35 seconds
Started Jan 17 01:01:21 PM PST 24
Finished Jan 17 01:01:23 PM PST 24
Peak memory 196112 kb
Host smart-a232220b-9c73-4d2d-956f-6a155a85a779
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899179362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2899179362
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2192564736
Short name T161
Test name
Test status
Simulation time 173120098 ps
CPU time 1.46 seconds
Started Jan 17 01:01:34 PM PST 24
Finished Jan 17 01:01:38 PM PST 24
Peak memory 196628 kb
Host smart-961eb914-fe52-4167-afc5-0aadfa98ff75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2192564736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2192564736
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1083817079
Short name T143
Test name
Test status
Simulation time 46500688 ps
CPU time 0.93 seconds
Started Jan 17 01:01:32 PM PST 24
Finished Jan 17 01:01:36 PM PST 24
Peak memory 196248 kb
Host smart-e3170c51-d2f6-4b51-8a12-f772cb7a13a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083817079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1083817079
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2742454142
Short name T158
Test name
Test status
Simulation time 418897007 ps
CPU time 1.24 seconds
Started Jan 17 01:01:42 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197708 kb
Host smart-95d9870d-27c8-460a-9d9d-34351de911f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2742454142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2742454142
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.407698977
Short name T69
Test name
Test status
Simulation time 209338759 ps
CPU time 1.05 seconds
Started Jan 17 01:01:41 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197728 kb
Host smart-7695905d-7a5b-4183-885f-95b2645fd222
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407698977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.407698977
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4048153184
Short name T188
Test name
Test status
Simulation time 681834568 ps
CPU time 0.98 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195328 kb
Host smart-a3325844-36e9-4ab1-a259-e46da6c03443
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4048153184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4048153184
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1035524452
Short name T127
Test name
Test status
Simulation time 73520212 ps
CPU time 1.27 seconds
Started Jan 17 01:01:42 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196288 kb
Host smart-0aefdf4f-e93f-4d55-a4dc-891a0e87f1ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035524452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1035524452
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1607585123
Short name T203
Test name
Test status
Simulation time 70042241 ps
CPU time 1.21 seconds
Started Jan 17 01:01:41 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195596 kb
Host smart-53a204b7-23a0-4a7b-8401-34470a1519d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1607585123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1607585123
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114170545
Short name T200
Test name
Test status
Simulation time 164068726 ps
CPU time 0.84 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195104 kb
Host smart-71c74f50-9695-4b89-95d4-64221298eccc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114170545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3114170545
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.32404020
Short name T176
Test name
Test status
Simulation time 74944532 ps
CPU time 1.2 seconds
Started Jan 17 01:01:41 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195320 kb
Host smart-64d80a33-d807-4911-ac3e-34dda02bfa05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=32404020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.32404020
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.892513720
Short name T173
Test name
Test status
Simulation time 108612461 ps
CPU time 0.96 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195352 kb
Host smart-e798a16f-0ac6-4304-a29b-2a27b7628ad6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892513720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.892513720
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.177073321
Short name T204
Test name
Test status
Simulation time 139378756 ps
CPU time 1.07 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197600 kb
Host smart-1c3bd1a0-c474-4177-a3a9-ce63c30b6d22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=177073321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.177073321
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4222485983
Short name T206
Test name
Test status
Simulation time 100103394 ps
CPU time 1.18 seconds
Started Jan 17 01:01:40 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195408 kb
Host smart-e0db2697-f150-4604-89ea-39683e8baf3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222485983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4222485983
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3684199623
Short name T192
Test name
Test status
Simulation time 306222262 ps
CPU time 1.11 seconds
Started Jan 17 01:01:42 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197720 kb
Host smart-04a944d7-02cb-4be0-aaa9-467695cb45c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3684199623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3684199623
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3082873718
Short name T126
Test name
Test status
Simulation time 294199231 ps
CPU time 1.38 seconds
Started Jan 17 01:01:46 PM PST 24
Finished Jan 17 01:01:48 PM PST 24
Peak memory 195916 kb
Host smart-9aa08011-469a-4aec-a3e7-da3387cc95f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082873718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3082873718
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1257255100
Short name T157
Test name
Test status
Simulation time 76481424 ps
CPU time 1.4 seconds
Started Jan 17 01:01:45 PM PST 24
Finished Jan 17 01:01:48 PM PST 24
Peak memory 197696 kb
Host smart-7aec8834-f5ae-4d6d-a990-687893324865
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1257255100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1257255100
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1777482023
Short name T122
Test name
Test status
Simulation time 56091779 ps
CPU time 0.98 seconds
Started Jan 17 01:01:40 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197680 kb
Host smart-33f13cbb-f7d5-491f-a374-f15238af7060
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777482023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1777482023
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2371705871
Short name T124
Test name
Test status
Simulation time 93293339 ps
CPU time 0.8 seconds
Started Jan 17 01:01:45 PM PST 24
Finished Jan 17 01:01:47 PM PST 24
Peak memory 195036 kb
Host smart-3f659c9d-4eb6-4661-a867-f0b386683dda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2371705871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2371705871
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3085406333
Short name T186
Test name
Test status
Simulation time 69885771 ps
CPU time 1.37 seconds
Started Jan 17 01:01:39 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196104 kb
Host smart-8fe03ddd-35da-477d-80fb-1281947adad2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085406333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3085406333
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1333296402
Short name T181
Test name
Test status
Simulation time 112644871 ps
CPU time 1.09 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:47 PM PST 24
Peak memory 196132 kb
Host smart-1d3e3ef0-bfad-44ff-8018-2815039315b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1333296402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1333296402
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.6561816
Short name T164
Test name
Test status
Simulation time 296295902 ps
CPU time 1.09 seconds
Started Jan 17 01:01:46 PM PST 24
Finished Jan 17 01:01:48 PM PST 24
Peak memory 196052 kb
Host smart-de860c42-cc49-4d3d-856c-0c2ccc5aa27f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6561816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.6561816
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1858831700
Short name T201
Test name
Test status
Simulation time 111964044 ps
CPU time 0.73 seconds
Started Jan 17 01:01:24 PM PST 24
Finished Jan 17 01:01:26 PM PST 24
Peak memory 194888 kb
Host smart-d8bfba3d-572e-4c59-914f-557b1489bf9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1858831700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1858831700
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3199871542
Short name T131
Test name
Test status
Simulation time 37627645 ps
CPU time 0.99 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:26 PM PST 24
Peak memory 197628 kb
Host smart-3131b7a9-ee4d-4601-9c6c-2f3ae7888b4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199871542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3199871542
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1648768899
Short name T137
Test name
Test status
Simulation time 56678861 ps
CPU time 1.04 seconds
Started Jan 17 01:01:41 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196156 kb
Host smart-c96ec200-8bc1-4923-992c-e1be697bebf3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1648768899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1648768899
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1469468614
Short name T154
Test name
Test status
Simulation time 46945342 ps
CPU time 1.05 seconds
Started Jan 17 01:01:41 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196088 kb
Host smart-f00ab9f8-6c0c-4316-b00c-ce51c0eb33e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469468614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1469468614
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3022113756
Short name T138
Test name
Test status
Simulation time 163537277 ps
CPU time 1.19 seconds
Started Jan 17 01:01:41 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197552 kb
Host smart-a2a6daf5-73dc-42b7-a67f-525e1cd716a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3022113756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3022113756
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3364254103
Short name T132
Test name
Test status
Simulation time 62097613 ps
CPU time 1.36 seconds
Started Jan 17 01:01:42 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 196532 kb
Host smart-c66fd220-1a5a-409a-9851-3349010e0e40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364254103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3364254103
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749113151
Short name T196
Test name
Test status
Simulation time 446495443 ps
CPU time 0.89 seconds
Started Jan 17 01:01:49 PM PST 24
Finished Jan 17 01:01:50 PM PST 24
Peak memory 197124 kb
Host smart-743edf43-ee5f-4dd3-92d2-3ad05c9ec9e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749113151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749113151
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2397281669
Short name T182
Test name
Test status
Simulation time 72111416 ps
CPU time 1.13 seconds
Started Jan 17 01:01:43 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 197668 kb
Host smart-bcd7492c-1a33-43cb-ab11-d644fc07af4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2397281669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2397281669
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1862146809
Short name T140
Test name
Test status
Simulation time 139599563 ps
CPU time 1 seconds
Started Jan 17 01:01:43 PM PST 24
Finished Jan 17 01:01:46 PM PST 24
Peak memory 195596 kb
Host smart-4553c085-0597-4e0d-9765-29de6638bd40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862146809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1862146809
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2637628554
Short name T163
Test name
Test status
Simulation time 58812790 ps
CPU time 1.37 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:48 PM PST 24
Peak memory 196332 kb
Host smart-c623a2c8-78c5-40c4-a5ee-da6e5c4c26c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2637628554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2637628554
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1700652636
Short name T171
Test name
Test status
Simulation time 129358589 ps
CPU time 1.09 seconds
Started Jan 17 01:01:48 PM PST 24
Finished Jan 17 01:01:50 PM PST 24
Peak memory 195572 kb
Host smart-852be569-fac3-49d7-9e98-2e3cd64c955a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700652636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1700652636
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4125617646
Short name T169
Test name
Test status
Simulation time 551024745 ps
CPU time 1.37 seconds
Started Jan 17 01:01:44 PM PST 24
Finished Jan 17 01:01:47 PM PST 24
Peak memory 197772 kb
Host smart-a58c9f99-5616-4ec6-857c-b0ef79a1941b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4125617646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4125617646
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2102062989
Short name T153
Test name
Test status
Simulation time 144198025 ps
CPU time 1.39 seconds
Started Jan 17 01:01:49 PM PST 24
Finished Jan 17 01:01:51 PM PST 24
Peak memory 196420 kb
Host smart-d42f9be1-92b1-46b8-a099-1e4c817ac80b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102062989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2102062989
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2440833115
Short name T194
Test name
Test status
Simulation time 52924872 ps
CPU time 1.17 seconds
Started Jan 17 01:01:52 PM PST 24
Finished Jan 17 01:01:54 PM PST 24
Peak memory 197680 kb
Host smart-3947f826-f074-43e8-ae75-9616a6df9f30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2440833115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2440833115
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2533931295
Short name T159
Test name
Test status
Simulation time 62760593 ps
CPU time 1.06 seconds
Started Jan 17 01:01:52 PM PST 24
Finished Jan 17 01:01:54 PM PST 24
Peak memory 195452 kb
Host smart-b1fbc533-4793-4284-b2d6-9541c76297aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533931295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2533931295
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2422883045
Short name T156
Test name
Test status
Simulation time 140484725 ps
CPU time 1.43 seconds
Started Jan 17 01:01:53 PM PST 24
Finished Jan 17 01:01:56 PM PST 24
Peak memory 196496 kb
Host smart-86983102-9702-476c-b59f-0f8724769db3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2422883045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2422883045
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1452731520
Short name T167
Test name
Test status
Simulation time 40537033 ps
CPU time 1.06 seconds
Started Jan 17 01:01:50 PM PST 24
Finished Jan 17 01:01:52 PM PST 24
Peak memory 196472 kb
Host smart-9109e81e-781f-401c-84ad-b63376387bc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452731520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1452731520
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.767174574
Short name T165
Test name
Test status
Simulation time 188637929 ps
CPU time 0.87 seconds
Started Jan 17 01:01:50 PM PST 24
Finished Jan 17 01:01:52 PM PST 24
Peak memory 195852 kb
Host smart-58546eb1-367d-4593-ba8a-5c15bc9a7983
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=767174574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.767174574
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.459079458
Short name T136
Test name
Test status
Simulation time 213108341 ps
CPU time 1.16 seconds
Started Jan 17 01:01:49 PM PST 24
Finished Jan 17 01:01:51 PM PST 24
Peak memory 195328 kb
Host smart-a2470d1c-b0b8-4ce1-aa50-f849533109b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459079458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.459079458
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3346417140
Short name T166
Test name
Test status
Simulation time 109857667 ps
CPU time 0.94 seconds
Started Jan 17 01:01:48 PM PST 24
Finished Jan 17 01:01:50 PM PST 24
Peak memory 196252 kb
Host smart-9a6dc981-75b1-4bb7-b62b-83e1b6055459
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3346417140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3346417140
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2670388463
Short name T149
Test name
Test status
Simulation time 44438537 ps
CPU time 0.98 seconds
Started Jan 17 01:01:56 PM PST 24
Finished Jan 17 01:01:57 PM PST 24
Peak memory 196204 kb
Host smart-1730cbaf-faff-4695-9385-e83c56b309c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670388463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2670388463
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2536845314
Short name T50
Test name
Test status
Simulation time 249825982 ps
CPU time 1.38 seconds
Started Jan 17 01:01:24 PM PST 24
Finished Jan 17 01:01:26 PM PST 24
Peak memory 197708 kb
Host smart-5b087814-129c-4848-a850-3334e768af1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2536845314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2536845314
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122943330
Short name T193
Test name
Test status
Simulation time 246656854 ps
CPU time 1.26 seconds
Started Jan 17 01:01:20 PM PST 24
Finished Jan 17 01:01:22 PM PST 24
Peak memory 197712 kb
Host smart-c88de7db-043f-4ba7-a04a-e7bddea24431
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122943330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1122943330
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3050885308
Short name T198
Test name
Test status
Simulation time 53099848 ps
CPU time 0.84 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196316 kb
Host smart-461a8232-089f-451e-b087-dd4b7888d9ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3050885308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3050885308
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2354134882
Short name T207
Test name
Test status
Simulation time 96378094 ps
CPU time 1.31 seconds
Started Jan 17 01:01:26 PM PST 24
Finished Jan 17 01:01:28 PM PST 24
Peak memory 197792 kb
Host smart-2f346a3f-89fb-4097-946d-cef61baaefe1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354134882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2354134882
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1987840612
Short name T187
Test name
Test status
Simulation time 324644946 ps
CPU time 1.34 seconds
Started Jan 17 01:01:21 PM PST 24
Finished Jan 17 01:01:23 PM PST 24
Peak memory 196488 kb
Host smart-8f779071-ee49-4cf4-8a03-06c3e1c30a9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1987840612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1987840612
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2621371515
Short name T205
Test name
Test status
Simulation time 381981261 ps
CPU time 1.25 seconds
Started Jan 17 01:01:22 PM PST 24
Finished Jan 17 01:01:24 PM PST 24
Peak memory 197716 kb
Host smart-343bd4ed-8764-421c-82ac-8bdb4e94b9ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621371515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2621371515
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3244620346
Short name T209
Test name
Test status
Simulation time 58840591 ps
CPU time 1.17 seconds
Started Jan 17 01:01:21 PM PST 24
Finished Jan 17 01:01:23 PM PST 24
Peak memory 196280 kb
Host smart-cdf46b1f-30df-4c78-8d1f-c6c2000eed7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3244620346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3244620346
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1647712786
Short name T147
Test name
Test status
Simulation time 105962227 ps
CPU time 1.53 seconds
Started Jan 17 01:01:22 PM PST 24
Finished Jan 17 01:01:24 PM PST 24
Peak memory 196612 kb
Host smart-5c7fd675-81d6-4298-8e5e-85fff3675c7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647712786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1647712786
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3899791916
Short name T152
Test name
Test status
Simulation time 46867941 ps
CPU time 1.06 seconds
Started Jan 17 01:01:22 PM PST 24
Finished Jan 17 01:01:24 PM PST 24
Peak memory 196304 kb
Host smart-d7305b44-7bd9-415d-8924-38696ed6a49d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3899791916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3899791916
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1871052992
Short name T52
Test name
Test status
Simulation time 58042711 ps
CPU time 1.03 seconds
Started Jan 17 01:01:25 PM PST 24
Finished Jan 17 01:01:27 PM PST 24
Peak memory 196248 kb
Host smart-4db7c667-7826-40b5-be79-ac3212dda705
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871052992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1871052992
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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