Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	22802056	1			T22	21		T23	21		T24	5
all_values[1]	22802056	1			T22	21		T23	21		T24	5
all_values[2]	22802056	1			T22	21		T23	21		T24	5
all_values[3]	22802056	1			T22	21		T23	21		T24	5
all_values[4]	22802056	1			T22	21		T23	21		T24	5
all_values[5]	22802056	1			T22	21		T23	21		T24	5
all_values[6]	22802056	1			T22	21		T23	21		T24	5
all_values[7]	22802056	1			T22	21		T23	21		T24	5
all_values[8]	22802056	1			T22	21		T23	21		T24	5
all_values[9]	22802056	1			T22	21		T23	21		T24	5
all_values[10]	22802056	1			T22	21		T23	21		T24	5
all_values[11]	22802056	1			T22	21		T23	21		T24	5
all_values[12]	22802056	1			T22	21		T23	21		T24	5
all_values[13]	22802056	1			T22	21		T23	21		T24	5
all_values[14]	22802056	1			T22	21		T23	21		T24	5
all_values[15]	22802056	1			T22	21		T23	21		T24	5
all_values[16]	22802056	1			T22	21		T23	21		T24	5
all_values[17]	22802056	1			T22	21		T23	21		T24	5
all_values[18]	22802056	1			T22	21		T23	21		T24	5
all_values[19]	22802056	1			T22	21		T23	21		T24	5
all_values[20]	22802056	1			T22	21		T23	21		T24	5
all_values[21]	22802056	1			T22	21		T23	21		T24	5
all_values[22]	22802056	1			T22	21		T23	21		T24	5
all_values[23]	22802056	1			T22	21		T23	21		T24	5
all_values[24]	22802056	1			T22	21		T23	21		T24	5
all_values[25]	22802056	1			T22	21		T23	21		T24	5
all_values[26]	22802056	1			T22	21		T23	21		T24	5
all_values[27]	22802056	1			T22	21		T23	21		T24	5
all_values[28]	22802056	1			T22	21		T23	21		T24	5
all_values[29]	22802056	1			T22	21		T23	21		T24	5
all_values[30]	22802056	1			T22	21		T23	21		T24	5
all_values[31]	22802056	1			T22	21		T23	21		T24	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

398689916

1

T22

561

T23

372

T24

127

auto[1]

330975876

1

T22

111

T23

300

T24

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128582370

1

T22

554

T23

321

T24

122

auto[1]

601083422

1

T22

118

T23

351

T24

38

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3064106	1			T22	17		T23	2		T24	3
all_values[0]	auto[0]	auto[1]	9394376	1			T22	1		T23	19		T24	1
all_values[0]	auto[1]	auto[0]	967325	1			T22	2		T24	1		T1	2
all_values[0]	auto[1]	auto[1]	9376249	1			T22	1		T12	4		T13	4
all_values[1]	auto[0]	auto[0]	3062294	1			T22	15		T23	13		T24	3
all_values[1]	auto[0]	auto[1]	9383454	1			T22	2		T23	8		T24	1
all_values[1]	auto[1]	auto[0]	952896	1			T22	3		T1	2		T12	9
all_values[1]	auto[1]	auto[1]	9403412	1			T22	1		T24	1		T12	2
all_values[2]	auto[0]	auto[0]	3061193	1			T22	16		T23	14		T24	4
all_values[2]	auto[0]	auto[1]	9408242	1			T22	2		T23	7		T24	1
all_values[2]	auto[1]	auto[0]	943913	1			T22	1		T12	3		T13	7
all_values[2]	auto[1]	auto[1]	9388708	1			T22	2		T1	1		T12	2
all_values[3]	auto[0]	auto[0]	3060596	1			T22	15		T23	1		T24	4
all_values[3]	auto[0]	auto[1]	9427834	1			T22	2		T23	20		T24	1
all_values[3]	auto[1]	auto[0]	958350	1			T22	1		T12	5		T13	4
all_values[3]	auto[1]	auto[1]	9355276	1			T22	3		T1	3		T12	1
all_values[4]	auto[0]	auto[0]	3068655	1			T22	16		T23	1		T24	3
all_values[4]	auto[0]	auto[1]	9377372	1			T22	4		T24	2		T1	2
all_values[4]	auto[1]	auto[0]	959010	1			T22	1		T23	12		T12	4
all_values[4]	auto[1]	auto[1]	9397019	1			T23	8		T1	1		T12	3
all_values[5]	auto[0]	auto[0]	3060384	1			T22	15		T23	1		T24	3
all_values[5]	auto[0]	auto[1]	9418384	1			T22	3		T12	7		T13	2
all_values[5]	auto[1]	auto[0]	967035	1			T22	1		T23	13		T24	1
all_values[5]	auto[1]	auto[1]	9356253	1			T22	2		T23	7		T24	1
all_values[6]	auto[0]	auto[0]	3063358	1			T22	15		T23	1		T24	3
all_values[6]	auto[0]	auto[1]	9410507	1			T22	3		T1	1		T12	9
all_values[6]	auto[1]	auto[0]	965839	1			T22	2		T23	20		T12	5
all_values[6]	auto[1]	auto[1]	9362352	1			T22	1		T24	2		T1	2
all_values[7]	auto[0]	auto[0]	3061450	1			T22	14		T23	13		T24	3
all_values[7]	auto[0]	auto[1]	9346436	1			T22	2		T23	8		T24	1
all_values[7]	auto[1]	auto[0]	971180	1			T22	4		T12	4		T13	7
all_values[7]	auto[1]	auto[1]	9422990	1			T22	1		T24	1		T1	3
all_values[8]	auto[0]	auto[0]	3058580	1			T22	14		T23	1		T24	3
all_values[8]	auto[0]	auto[1]	9387675	1			T22	3		T12	7		T13	2
all_values[8]	auto[1]	auto[0]	948634	1			T22	3		T23	20		T24	1
all_values[8]	auto[1]	auto[1]	9407167	1			T22	1		T24	1		T12	1
all_values[9]	auto[0]	auto[0]	3057600	1			T22	14		T23	1		T24	3
all_values[9]	auto[0]	auto[1]	9399530	1			T22	3		T1	1		T12	8
all_values[9]	auto[1]	auto[0]	954155	1			T22	3		T24	2		T12	5
all_values[9]	auto[1]	auto[1]	9390771	1			T22	1		T23	20		T1	2
all_values[10]	auto[0]	auto[0]	3071842	1			T22	17		T23	1		T24	4
all_values[10]	auto[0]	auto[1]	9457846	1			T22	2		T1	1		T12	6
all_values[10]	auto[1]	auto[0]	958066	1			T22	2		T23	12		T12	3
all_values[10]	auto[1]	auto[1]	9314302	1			T23	8		T24	1		T1	2
all_values[11]	auto[0]	auto[0]	3062946	1			T22	16		T23	1		T24	4
all_values[11]	auto[0]	auto[1]	9404949	1			T22	3		T23	20		T1	2
all_values[11]	auto[1]	auto[0]	954010	1			T22	1		T24	1		T12	6
all_values[11]	auto[1]	auto[1]	9380151	1			T22	1		T12	4		T13	5
all_values[12]	auto[0]	auto[0]	3060440	1			T22	15		T23	21		T24	3
all_values[12]	auto[0]	auto[1]	9380147	1			T22	1		T12	11		T13	4
all_values[12]	auto[1]	auto[0]	954755	1			T22	2		T12	6		T13	7
all_values[12]	auto[1]	auto[1]	9406714	1			T22	3		T24	2		T1	3
all_values[13]	auto[0]	auto[0]	3055510	1			T22	14		T23	1		T24	4
all_values[13]	auto[0]	auto[1]	9397447	1			T22	2		T1	2		T12	5
all_values[13]	auto[1]	auto[0]	953967	1			T22	3		T24	1		T12	6
all_values[13]	auto[1]	auto[1]	9395132	1			T22	2		T23	20		T1	1
all_values[14]	auto[0]	auto[0]	3063928	1			T22	13		T23	14		T24	3
all_values[14]	auto[0]	auto[1]	9383731	1			T22	4		T23	7		T24	2
all_values[14]	auto[1]	auto[0]	953724	1			T22	4		T12	7		T13	5
all_values[14]	auto[1]	auto[1]	9400673	1			T1	1		T12	3		T13	5
all_values[15]	auto[0]	auto[0]	3064386	1			T22	18		T23	13		T24	3
all_values[15]	auto[0]	auto[1]	9393256	1			T23	8		T24	1		T1	3
all_values[15]	auto[1]	auto[0]	961376	1			T22	2		T24	1		T12	8
all_values[15]	auto[1]	auto[1]	9383038	1			T22	1		T12	4		T13	5
all_values[16]	auto[0]	auto[0]	3068556	1			T22	14		T23	1		T24	4
all_values[16]	auto[0]	auto[1]	9402214	1			T22	3		T24	1		T1	1
all_values[16]	auto[1]	auto[0]	954548	1			T22	3		T23	12		T12	6
all_values[16]	auto[1]	auto[1]	9376738	1			T22	1		T23	8		T1	1
all_values[17]	auto[0]	auto[0]	3078203	1			T22	14		T23	3		T24	3
all_values[17]	auto[0]	auto[1]	9389076	1			T22	1		T23	18		T24	1
all_values[17]	auto[1]	auto[0]	956796	1			T22	3		T12	5		T13	3
all_values[17]	auto[1]	auto[1]	9377981	1			T22	3		T24	1		T12	5
all_values[18]	auto[0]	auto[0]	3051247	1			T22	19		T23	13		T24	3
all_values[18]	auto[0]	auto[1]	9400586	1			T23	8		T24	1		T12	11
all_values[18]	auto[1]	auto[0]	962714	1			T24	1		T1	2		T12	2
all_values[18]	auto[1]	auto[1]	9387509	1			T22	2		T12	2		T13	3
all_values[19]	auto[0]	auto[0]	3053973	1			T22	15		T23	1		T24	3
all_values[19]	auto[0]	auto[1]	9407532	1			T22	3		T1	2		T12	8
all_values[19]	auto[1]	auto[0]	953033	1			T22	2		T23	12		T24	2
all_values[19]	auto[1]	auto[1]	9387518	1			T22	1		T23	8		T1	1
all_values[20]	auto[0]	auto[0]	3061971	1			T22	13		T23	1		T24	3
all_values[20]	auto[0]	auto[1]	9407706	1			T22	4		T24	1		T1	3
all_values[20]	auto[1]	auto[0]	957511	1			T22	3		T23	6		T12	5
all_values[20]	auto[1]	auto[1]	9374868	1			T22	1		T23	14		T24	1
all_values[21]	auto[0]	auto[0]	3051370	1			T22	14		T23	1		T24	4
all_values[21]	auto[0]	auto[1]	9437511	1			T22	3		T1	3		T12	8
all_values[21]	auto[1]	auto[0]	951192	1			T22	3		T23	12		T12	3
all_values[21]	auto[1]	auto[1]	9361983	1			T22	1		T23	8		T24	1
all_values[22]	auto[0]	auto[0]	3052073	1			T22	15		T23	1		T24	3
all_values[22]	auto[0]	auto[1]	9412838	1			T24	1		T12	8		T13	5
all_values[22]	auto[1]	auto[0]	953666	1			T22	6		T23	20		T1	3
all_values[22]	auto[1]	auto[1]	9383479	1			T24	1		T12	5		T13	5
all_values[23]	auto[0]	auto[0]	3057629	1			T22	17		T23	1		T24	3
all_values[23]	auto[0]	auto[1]	9379664	1			T24	1		T12	7		T13	6
all_values[23]	auto[1]	auto[0]	961128	1			T22	2		T12	4		T13	3
all_values[23]	auto[1]	auto[1]	9403635	1			T22	2		T23	20		T24	1
all_values[24]	auto[0]	auto[0]	3061617	1			T22	16		T23	5		T24	3
all_values[24]	auto[0]	auto[1]	9406424	1			T22	3		T23	16		T24	1
all_values[24]	auto[1]	auto[0]	957167	1			T22	1		T24	1		T1	3
all_values[24]	auto[1]	auto[1]	9376848	1			T22	1		T12	3		T13	3
all_values[25]	auto[0]	auto[0]	3060027	1			T22	15		T23	13		T24	3
all_values[25]	auto[0]	auto[1]	9394566	1			T22	3		T23	8		T24	1
all_values[25]	auto[1]	auto[0]	959320	1			T22	3		T12	6		T13	6
all_values[25]	auto[1]	auto[1]	9388143	1			T24	1		T12	3		T13	4
all_values[26]	auto[0]	auto[0]	3060985	1			T22	16		T23	1		T24	4
all_values[26]	auto[0]	auto[1]	9411120	1			T22	3		T24	1		T12	7
all_values[26]	auto[1]	auto[0]	953739	1			T22	1		T23	20		T12	4
all_values[26]	auto[1]	auto[1]	9376212	1			T22	1		T1	3		T12	4
all_values[27]	auto[0]	auto[0]	3048704	1			T22	14		T23	3		T24	3
all_values[27]	auto[0]	auto[1]	9318194	1			T22	4		T23	18		T1	2
all_values[27]	auto[1]	auto[0]	962635	1			T22	1		T24	2		T12	7
all_values[27]	auto[1]	auto[1]	9472523	1			T22	2		T1	1		T12	3
all_values[28]	auto[0]	auto[0]	3053036	1			T22	14		T23	2		T24	4
all_values[28]	auto[0]	auto[1]	9400299	1			T22	3		T23	19		T1	2
all_values[28]	auto[1]	auto[0]	963324	1			T22	2		T24	1		T12	3
all_values[28]	auto[1]	auto[1]	9385397	1			T22	2		T1	1		T12	3
all_values[29]	auto[0]	auto[0]	3062726	1			T22	15		T23	13		T24	3
all_values[29]	auto[0]	auto[1]	9402229	1			T22	3		T23	8		T1	1
all_values[29]	auto[1]	auto[0]	953742	1			T22	2		T24	1		T12	9
all_values[29]	auto[1]	auto[1]	9383359	1			T22	1		T24	1		T1	2
all_values[30]	auto[0]	auto[0]	3059325	1			T22	13		T23	2		T24	3
all_values[30]	auto[0]	auto[1]	9392778	1			T22	5		T23	19		T24	1
all_values[30]	auto[1]	auto[0]	962796	1			T22	3		T24	1		T12	8
all_values[30]	auto[1]	auto[1]	9387157	1			T12	8		T13	3		T15	1
all_values[31]	auto[0]	auto[0]	3063458	1			T22	15		T23	1		T24	3
all_values[31]	auto[0]	auto[1]	9413825	1			T22	3		T24	2		T1	3
all_values[31]	auto[1]	auto[0]	952656	1			T22	1		T23	1		T12	8
all_values[31]	auto[1]	auto[1]	9372117	1			T22	2		T23	19		T12	2