Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6858624	1			T22	28		T23	16		T24	9
all_pins[1]	6858624	1			T22	28		T23	16		T24	9
all_pins[2]	6858624	1			T22	28		T23	16		T24	9
all_pins[3]	6858624	1			T22	28		T23	16		T24	9
all_pins[4]	6858624	1			T22	28		T23	16		T24	9
all_pins[5]	6858624	1			T22	28		T23	16		T24	9
all_pins[6]	6858624	1			T22	28		T23	16		T24	9
all_pins[7]	6858624	1			T22	28		T23	16		T24	9
all_pins[8]	6858624	1			T22	28		T23	16		T24	9
all_pins[9]	6858624	1			T22	28		T23	16		T24	9
all_pins[10]	6858624	1			T22	28		T23	16		T24	9
all_pins[11]	6858624	1			T22	28		T23	16		T24	9
all_pins[12]	6858624	1			T22	28		T23	16		T24	9
all_pins[13]	6858624	1			T22	28		T23	16		T24	9
all_pins[14]	6858624	1			T22	28		T23	16		T24	9
all_pins[15]	6858624	1			T22	28		T23	16		T24	9
all_pins[16]	6858624	1			T22	28		T23	16		T24	9
all_pins[17]	6858624	1			T22	28		T23	16		T24	9
all_pins[18]	6858624	1			T22	28		T23	16		T24	9
all_pins[19]	6858624	1			T22	28		T23	16		T24	9
all_pins[20]	6858624	1			T22	28		T23	16		T24	9
all_pins[21]	6858624	1			T22	28		T23	16		T24	9
all_pins[22]	6858624	1			T22	28		T23	16		T24	9
all_pins[23]	6858624	1			T22	28		T23	16		T24	9
all_pins[24]	6858624	1			T22	28		T23	16		T24	9
all_pins[25]	6858624	1			T22	28		T23	16		T24	9
all_pins[26]	6858624	1			T22	28		T23	16		T24	9
all_pins[27]	6858624	1			T22	28		T23	16		T24	9
all_pins[28]	6858624	1			T22	28		T23	16		T24	9
all_pins[29]	6858624	1			T22	28		T23	16		T24	9
all_pins[30]	6858624	1			T22	28		T23	16		T24	9
all_pins[31]	6858624	1			T22	28		T23	16		T24	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	136021645	1			T22	769		T23	328		T24	245
values[0x1]	83454323	1			T22	127		T23	184		T24	43
transitions[0x0=>0x1]	49917898	1			T22	90		T23	108		T24	38
transitions[0x1=>0x0]	49917748	1			T22	90		T23	108		T24	38

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4251467	1			T22	25		T23	12		T24	9
all_pins[0]	values[0x1]	2607157	1			T22	3		T23	4		T12	11
all_pins[0]	transitions[0x0=>0x1]	1611769	1			T22	3		T12	10		T13	9
all_pins[0]	transitions[0x1=>0x0]	1611879	1			T22	5		T23	8		T12	13
all_pins[1]	values[0x0]	4248559	1			T22	27		T23	12		T24	6
all_pins[1]	values[0x1]	2610065	1			T22	1		T23	4		T24	3
all_pins[1]	transitions[0x0=>0x1]	1558411	1			T22	1		T23	1		T24	3
all_pins[1]	transitions[0x1=>0x0]	1555503	1			T22	3		T23	1		T12	9
all_pins[2]	values[0x0]	4251146	1			T22	22		T23	14		T24	9
all_pins[2]	values[0x1]	2607478	1			T22	6		T23	2		T1	1
all_pins[2]	transitions[0x0=>0x1]	1553770	1			T22	6		T23	1		T1	1
all_pins[2]	transitions[0x1=>0x0]	1556357	1			T22	1		T23	3		T24	3
all_pins[3]	values[0x0]	4251743	1			T22	22		T23	12		T24	9
all_pins[3]	values[0x1]	2606881	1			T22	6		T23	4		T1	3
all_pins[3]	transitions[0x0=>0x1]	1555161	1			T22	4		T23	3		T1	2
all_pins[3]	transitions[0x1=>0x0]	1555758	1			T22	4		T23	1		T12	8
all_pins[4]	values[0x0]	4253485	1			T22	24		T23	10		T24	9
all_pins[4]	values[0x1]	2605139	1			T22	4		T23	6		T1	1
all_pins[4]	transitions[0x0=>0x1]	1556121	1			T22	4		T23	4		T12	8
all_pins[4]	transitions[0x1=>0x0]	1557863	1			T22	6		T23	2		T1	2
all_pins[5]	values[0x0]	4249881	1			T22	20		T23	15		T24	6
all_pins[5]	values[0x1]	2608743	1			T22	8		T23	1		T24	3
all_pins[5]	transitions[0x0=>0x1]	1563202	1			T22	4		T24	3		T12	12
all_pins[5]	transitions[0x1=>0x0]	1559598	1			T23	5		T1	1		T12	7
all_pins[6]	values[0x0]	4248161	1			T22	25		T23	8		T24	5
all_pins[6]	values[0x1]	2610463	1			T22	3		T23	8		T24	4
all_pins[6]	transitions[0x0=>0x1]	1559578	1			T22	1		T23	7		T24	3
all_pins[6]	transitions[0x1=>0x0]	1557858	1			T22	6		T24	2		T12	13
all_pins[7]	values[0x0]	4245562	1			T22	23		T23	11		T24	6
all_pins[7]	values[0x1]	2613062	1			T22	5		T23	5		T24	3
all_pins[7]	transitions[0x0=>0x1]	1563916	1			T22	4		T23	2		T1	1
all_pins[7]	transitions[0x1=>0x0]	1561317	1			T22	2		T23	5		T24	1
all_pins[8]	values[0x0]	4252658	1			T22	23		T23	9		T24	6
all_pins[8]	values[0x1]	2605966	1			T22	5		T23	7		T24	3
all_pins[8]	transitions[0x0=>0x1]	1554080	1			T22	2		T23	5		T24	3
all_pins[8]	transitions[0x1=>0x0]	1561176	1			T22	2		T23	3		T24	3
all_pins[9]	values[0x0]	4246769	1			T22	23		T23	5		T24	9
all_pins[9]	values[0x1]	2611855	1			T22	5		T23	11		T1	2
all_pins[9]	transitions[0x0=>0x1]	1562418	1			T22	4		T23	6		T1	2
all_pins[9]	transitions[0x1=>0x0]	1556529	1			T22	4		T23	2		T24	3
all_pins[10]	values[0x0]	4256064	1			T22	27		T23	8		T24	6
all_pins[10]	values[0x1]	2602560	1			T22	1		T23	8		T24	3
all_pins[10]	transitions[0x0=>0x1]	1552506	1			T23	3		T24	3		T12	21
all_pins[10]	transitions[0x1=>0x0]	1561801	1			T22	4		T23	6		T12	6
all_pins[11]	values[0x0]	4255007	1			T22	24		T23	12		T24	9
all_pins[11]	values[0x1]	2603617	1			T22	4		T23	4		T12	12
all_pins[11]	transitions[0x0=>0x1]	1558840	1			T22	4		T23	2		T12	2
all_pins[11]	transitions[0x1=>0x0]	1557783	1			T22	1		T23	6		T24	3
all_pins[12]	values[0x0]	4252229	1			T22	20		T23	14		T24	5
all_pins[12]	values[0x1]	2606395	1			T22	8		T23	2		T24	4
all_pins[12]	transitions[0x0=>0x1]	1562674	1			T22	6		T23	1		T24	4
all_pins[12]	transitions[0x1=>0x0]	1559896	1			T22	2		T23	3		T12	8
all_pins[13]	values[0x0]	4246914	1			T22	22		T23	3		T24	9
all_pins[13]	values[0x1]	2611710	1			T22	6		T23	13		T1	1
all_pins[13]	transitions[0x0=>0x1]	1560346	1			T22	2		T23	11		T12	11
all_pins[13]	transitions[0x1=>0x0]	1555031	1			T22	4		T24	4		T1	2
all_pins[14]	values[0x0]	4250436	1			T22	27		T23	12		T24	9
all_pins[14]	values[0x1]	2608188	1			T22	1		T23	4		T1	1
all_pins[14]	transitions[0x0=>0x1]	1556686	1			T23	2		T12	10		T13	11
all_pins[14]	transitions[0x1=>0x0]	1560208	1			T22	5		T23	11		T12	9
all_pins[15]	values[0x0]	4253111	1			T22	27		T23	11		T24	9
all_pins[15]	values[0x1]	2605513	1			T22	1		T23	5		T12	10
all_pins[15]	transitions[0x0=>0x1]	1556059	1			T22	1		T23	2		T12	5
all_pins[15]	transitions[0x1=>0x0]	1558734	1			T22	1		T23	1		T1	1
all_pins[16]	values[0x0]	4256955	1			T22	26		T23	7		T24	9
all_pins[16]	values[0x1]	2601669	1			T22	2		T23	9		T1	1
all_pins[16]	transitions[0x0=>0x1]	1554911	1			T22	2		T23	6		T1	1
all_pins[16]	transitions[0x1=>0x0]	1558755	1			T22	1		T23	2		T12	9
all_pins[17]	values[0x0]	4256603	1			T22	23		T23	14		T24	6
all_pins[17]	values[0x1]	2602021	1			T22	5		T23	2		T24	3
all_pins[17]	transitions[0x0=>0x1]	1557875	1			T22	4		T24	3		T12	15
all_pins[17]	transitions[0x1=>0x0]	1557523	1			T22	1		T23	7		T1	1
all_pins[18]	values[0x0]	4245060	1			T22	24		T23	11		T24	9
all_pins[18]	values[0x1]	2613564	1			T22	4		T23	5		T12	8
all_pins[18]	transitions[0x0=>0x1]	1563347	1			T23	4		T12	6		T13	7
all_pins[18]	transitions[0x1=>0x0]	1551804	1			T22	1		T23	1		T24	3
all_pins[19]	values[0x0]	4248548	1			T22	26		T23	8		T24	9
all_pins[19]	values[0x1]	2610076	1			T22	2		T23	8		T1	1
all_pins[19]	transitions[0x0=>0x1]	1559162	1			T22	2		T23	6		T1	1
all_pins[19]	transitions[0x1=>0x0]	1562650	1			T22	4		T23	3		T12	4
all_pins[20]	values[0x0]	4250001	1			T22	26		T23	7		T24	6
all_pins[20]	values[0x1]	2608623	1			T22	2		T23	9		T24	3
all_pins[20]	transitions[0x0=>0x1]	1557392	1			T22	2		T23	2		T24	3
all_pins[20]	transitions[0x1=>0x0]	1558845	1			T22	2		T23	1		T1	1
all_pins[21]	values[0x0]	4251906	1			T22	25		T23	9		T24	8
all_pins[21]	values[0x1]	2606718	1			T22	3		T23	7		T24	1
all_pins[21]	transitions[0x0=>0x1]	1555889	1			T22	3		T23	3		T24	1
all_pins[21]	transitions[0x1=>0x0]	1557794	1			T22	2		T23	5		T24	3
all_pins[22]	values[0x0]	4249931	1			T22	25		T23	10		T24	7
all_pins[22]	values[0x1]	2608693	1			T22	3		T23	6		T24	2
all_pins[22]	transitions[0x0=>0x1]	1557442	1			T22	2		T23	2		T24	1
all_pins[22]	transitions[0x1=>0x0]	1555467	1			T22	2		T23	3		T12	12
all_pins[23]	values[0x0]	4252733	1			T22	24		T23	5		T24	7
all_pins[23]	values[0x1]	2605891	1			T22	4		T23	11		T24	2
all_pins[23]	transitions[0x0=>0x1]	1552729	1			T22	4		T23	8		T24	2
all_pins[23]	transitions[0x1=>0x0]	1555531	1			T22	3		T23	3		T24	2
all_pins[24]	values[0x0]	4248175	1			T22	27		T23	13		T24	9
all_pins[24]	values[0x1]	2610449	1			T22	1		T23	3		T12	16
all_pins[24]	transitions[0x0=>0x1]	1562342	1			T22	1		T23	1		T12	8
all_pins[24]	transitions[0x1=>0x0]	1557784	1			T22	4		T23	9		T24	2
all_pins[25]	values[0x0]	4250908	1			T22	24		T23	14		T24	6
all_pins[25]	values[0x1]	2607716	1			T22	4		T23	2		T24	3
all_pins[25]	transitions[0x0=>0x1]	1559416	1			T22	4		T23	1		T24	3
all_pins[25]	transitions[0x1=>0x0]	1562149	1			T22	1		T23	2		T12	7
all_pins[26]	values[0x0]	4249325	1			T22	23		T23	8		T24	9
all_pins[26]	values[0x1]	2609299	1			T22	5		T23	8		T1	2
all_pins[26]	transitions[0x0=>0x1]	1560411	1			T22	3		T23	7		T1	2
all_pins[26]	transitions[0x1=>0x0]	1558828	1			T22	2		T23	1		T24	3
all_pins[27]	values[0x0]	4247341	1			T22	23		T23	11		T24	9
all_pins[27]	values[0x1]	2611283	1			T22	5		T23	5		T1	1
all_pins[27]	transitions[0x0=>0x1]	1558657	1			T22	4		T23	4		T12	10
all_pins[27]	transitions[0x1=>0x0]	1556673	1			T22	4		T23	7		T1	1
all_pins[28]	values[0x0]	4255833	1			T22	23		T23	13		T24	9
all_pins[28]	values[0x1]	2602791	1			T22	5		T23	3		T1	1
all_pins[28]	transitions[0x0=>0x1]	1554437	1			T22	4		T23	1		T12	8
all_pins[28]	transitions[0x1=>0x0]	1562929	1			T22	4		T23	3		T12	8
all_pins[29]	values[0x0]	4243942	1			T22	22		T23	14		T24	3
all_pins[29]	values[0x1]	2614682	1			T22	6		T23	2		T24	6
all_pins[29]	transitions[0x0=>0x1]	1563125	1			T22	3		T23	1		T24	6
all_pins[29]	transitions[0x1=>0x0]	1551234	1			T22	2		T23	2		T1	1
all_pins[30]	values[0x0]	4249985	1			T22	24		T23	12		T24	9
all_pins[30]	values[0x1]	2608639	1			T22	4		T23	4		T12	23
all_pins[30]	transitions[0x0=>0x1]	1558824	1			T22	2		T23	2		T12	18
all_pins[30]	transitions[0x1=>0x0]	1564867	1			T22	4		T24	6		T1	2
all_pins[31]	values[0x0]	4251207	1			T22	23		T23	4		T24	9
all_pins[31]	values[0x1]	2607417	1			T22	5		T23	12		T12	14
all_pins[31]	transitions[0x0=>0x1]	1556402	1			T22	4		T23	10		T12	12
all_pins[31]	transitions[0x1=>0x0]	1557624	1			T22	3		T23	2		T12	21