Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	22802056	1			T22	21		T23	21		T24	5
all_values[1]	22802056	1			T22	21		T23	21		T24	5
all_values[2]	22802056	1			T22	21		T23	21		T24	5
all_values[3]	22802056	1			T22	21		T23	21		T24	5
all_values[4]	22802056	1			T22	21		T23	21		T24	5
all_values[5]	22802056	1			T22	21		T23	21		T24	5
all_values[6]	22802056	1			T22	21		T23	21		T24	5
all_values[7]	22802056	1			T22	21		T23	21		T24	5
all_values[8]	22802056	1			T22	21		T23	21		T24	5
all_values[9]	22802056	1			T22	21		T23	21		T24	5
all_values[10]	22802056	1			T22	21		T23	21		T24	5
all_values[11]	22802056	1			T22	21		T23	21		T24	5
all_values[12]	22802056	1			T22	21		T23	21		T24	5
all_values[13]	22802056	1			T22	21		T23	21		T24	5
all_values[14]	22802056	1			T22	21		T23	21		T24	5
all_values[15]	22802056	1			T22	21		T23	21		T24	5
all_values[16]	22802056	1			T22	21		T23	21		T24	5
all_values[17]	22802056	1			T22	21		T23	21		T24	5
all_values[18]	22802056	1			T22	21		T23	21		T24	5
all_values[19]	22802056	1			T22	21		T23	21		T24	5
all_values[20]	22802056	1			T22	21		T23	21		T24	5
all_values[21]	22802056	1			T22	21		T23	21		T24	5
all_values[22]	22802056	1			T22	21		T23	21		T24	5
all_values[23]	22802056	1			T22	21		T23	21		T24	5
all_values[24]	22802056	1			T22	21		T23	21		T24	5
all_values[25]	22802056	1			T22	21		T23	21		T24	5
all_values[26]	22802056	1			T22	21		T23	21		T24	5
all_values[27]	22802056	1			T22	21		T23	21		T24	5
all_values[28]	22802056	1			T22	21		T23	21		T24	5
all_values[29]	22802056	1			T22	21		T23	21		T24	5
all_values[30]	22802056	1			T22	21		T23	21		T24	5
all_values[31]	22802056	1			T22	21		T23	21		T24	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

398689916

1

T22

561

T23

372

T24

127

auto[1]

330975876

1

T22

111

T23

300

T24

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128582370

1

T22

554

T23

321

T24

122

auto[1]

601083422

1

T22

118

T23

351

T24

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721225397

1

T22

672

T23

672

T24

160

auto[1]

8440395

1

T17

86

T19

96

T25

90

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3064106	1			T22	17		T23	2		T24	3
all_values[0]	auto[0]	auto[0]	auto[1]	9262198	1			T22	1		T23	19		T24	1
all_values[0]	auto[0]	auto[1]	auto[0]	967325	1			T22	2		T24	1		T1	2
all_values[0]	auto[0]	auto[1]	auto[1]	9244404	1			T22	1		T12	4		T13	4
all_values[0]	auto[1]	auto[0]	auto[1]	132178	1			T25	2		T116	4		T117	2
all_values[0]	auto[1]	auto[1]	auto[1]	131845	1			T17	3		T19	3		T110	1
all_values[1]	auto[0]	auto[0]	auto[0]	3062294	1			T22	15		T23	13		T24	3
all_values[1]	auto[0]	auto[0]	auto[1]	9251069	1			T22	2		T23	8		T24	1
all_values[1]	auto[0]	auto[1]	auto[0]	952896	1			T22	3		T1	2		T12	9
all_values[1]	auto[0]	auto[1]	auto[1]	9271828	1			T22	1		T24	1		T12	2
all_values[1]	auto[1]	auto[0]	auto[1]	132385	1			T19	1		T25	1		T111	1
all_values[1]	auto[1]	auto[1]	auto[1]	131584	1			T17	1		T19	3		T25	3
all_values[2]	auto[0]	auto[0]	auto[0]	3061193	1			T22	16		T23	14		T24	4
all_values[2]	auto[0]	auto[0]	auto[1]	9276217	1			T22	2		T23	7		T24	1
all_values[2]	auto[0]	auto[1]	auto[0]	943913	1			T22	1		T12	3		T13	7
all_values[2]	auto[0]	auto[1]	auto[1]	9256839	1			T22	2		T1	1		T12	2
all_values[2]	auto[1]	auto[0]	auto[1]	132025	1			T17	1		T19	2		T110	1
all_values[2]	auto[1]	auto[1]	auto[1]	131869	1			T19	1		T25	1		T116	2
all_values[3]	auto[0]	auto[0]	auto[0]	3060596	1			T22	15		T23	1		T24	4
all_values[3]	auto[0]	auto[0]	auto[1]	9295410	1			T22	2		T23	20		T24	1
all_values[3]	auto[0]	auto[1]	auto[0]	958350	1			T22	1		T12	5		T13	4
all_values[3]	auto[0]	auto[1]	auto[1]	9223322	1			T22	3		T1	3		T12	1
all_values[3]	auto[1]	auto[0]	auto[1]	132424	1			T17	2		T19	2		T25	1
all_values[3]	auto[1]	auto[1]	auto[1]	131954	1			T17	1		T25	3		T116	3
all_values[4]	auto[0]	auto[0]	auto[0]	3068655	1			T22	16		T23	1		T24	3
all_values[4]	auto[0]	auto[0]	auto[1]	9245288	1			T22	4		T24	2		T1	2
all_values[4]	auto[0]	auto[1]	auto[0]	959010	1			T22	1		T23	12		T12	4
all_values[4]	auto[0]	auto[1]	auto[1]	9265883	1			T23	8		T1	1		T12	3
all_values[4]	auto[1]	auto[0]	auto[1]	132084	1			T17	1		T19	1		T25	2
all_values[4]	auto[1]	auto[1]	auto[1]	131136	1			T17	1		T19	1		T25	1
all_values[5]	auto[0]	auto[0]	auto[0]	3060384	1			T22	15		T23	1		T24	3
all_values[5]	auto[0]	auto[0]	auto[1]	9286172	1			T22	3		T12	7		T13	2
all_values[5]	auto[0]	auto[1]	auto[0]	967035	1			T22	1		T23	13		T24	1
all_values[5]	auto[0]	auto[1]	auto[1]	9224487	1			T22	2		T23	7		T24	1
all_values[5]	auto[1]	auto[0]	auto[1]	132212	1			T17	1		T19	3		T25	1
all_values[5]	auto[1]	auto[1]	auto[1]	131766	1			T17	2		T25	3		T116	2
all_values[6]	auto[0]	auto[0]	auto[0]	3063358	1			T22	15		T23	1		T24	3
all_values[6]	auto[0]	auto[0]	auto[1]	9277506	1			T22	3		T1	1		T12	9
all_values[6]	auto[0]	auto[1]	auto[0]	965839	1			T22	2		T23	20		T12	5
all_values[6]	auto[0]	auto[1]	auto[1]	9231002	1			T22	1		T24	2		T1	2
all_values[6]	auto[1]	auto[0]	auto[1]	133001	1			T17	1		T19	1		T25	1
all_values[6]	auto[1]	auto[1]	auto[1]	131350	1			T25	2		T110	1		T116	4
all_values[7]	auto[0]	auto[0]	auto[0]	3061450	1			T22	14		T23	13		T24	3
all_values[7]	auto[0]	auto[0]	auto[1]	9214885	1			T22	2		T23	8		T24	1
all_values[7]	auto[0]	auto[1]	auto[0]	971180	1			T22	4		T12	4		T13	7
all_values[7]	auto[0]	auto[1]	auto[1]	9291363	1			T22	1		T24	1		T1	3
all_values[7]	auto[1]	auto[0]	auto[1]	131551	1			T17	1		T19	1		T25	2
all_values[7]	auto[1]	auto[1]	auto[1]	131627	1			T17	3		T19	4		T25	1
all_values[8]	auto[0]	auto[0]	auto[0]	3058580	1			T22	14		T23	1		T24	3
all_values[8]	auto[0]	auto[0]	auto[1]	9255218	1			T22	3		T12	7		T13	2
all_values[8]	auto[0]	auto[1]	auto[0]	948634	1			T22	3		T23	20		T24	1
all_values[8]	auto[0]	auto[1]	auto[1]	9275646	1			T22	1		T24	1		T12	1
all_values[8]	auto[1]	auto[0]	auto[1]	132457	1			T17	3		T25	2		T110	1
all_values[8]	auto[1]	auto[1]	auto[1]	131521	1			T19	4		T111	2		T116	2
all_values[9]	auto[0]	auto[0]	auto[0]	3057600	1			T22	14		T23	1		T24	3
all_values[9]	auto[0]	auto[0]	auto[1]	9267693	1			T22	3		T1	1		T12	8
all_values[9]	auto[0]	auto[1]	auto[0]	954155	1			T22	3		T24	2		T12	5
all_values[9]	auto[0]	auto[1]	auto[1]	9259103	1			T22	1		T23	20		T1	2
all_values[9]	auto[1]	auto[0]	auto[1]	131837	1			T17	2		T19	3		T25	1
all_values[9]	auto[1]	auto[1]	auto[1]	131668	1			T17	1		T25	1		T110	1
all_values[10]	auto[0]	auto[0]	auto[0]	3071842	1			T22	17		T23	1		T24	4
all_values[10]	auto[0]	auto[0]	auto[1]	9325637	1			T22	2		T1	1		T12	6
all_values[10]	auto[0]	auto[1]	auto[0]	958066	1			T22	2		T23	12		T12	3
all_values[10]	auto[0]	auto[1]	auto[1]	9182344	1			T23	8		T24	1		T1	2
all_values[10]	auto[1]	auto[0]	auto[1]	132209	1			T19	1		T25	2		T110	1
all_values[10]	auto[1]	auto[1]	auto[1]	131958	1			T17	3		T19	2		T25	3
all_values[11]	auto[0]	auto[0]	auto[0]	3062946	1			T22	16		T23	1		T24	4
all_values[11]	auto[0]	auto[0]	auto[1]	9272917	1			T22	3		T23	20		T1	2
all_values[11]	auto[0]	auto[1]	auto[0]	954010	1			T22	1		T24	1		T12	6
all_values[11]	auto[0]	auto[1]	auto[1]	9248381	1			T22	1		T12	4		T13	5
all_values[11]	auto[1]	auto[0]	auto[1]	132032	1			T17	1		T19	1		T25	2
all_values[11]	auto[1]	auto[1]	auto[1]	131770	1			T17	1		T110	1		T111	1
all_values[12]	auto[0]	auto[0]	auto[0]	3060440	1			T22	15		T23	21		T24	3
all_values[12]	auto[0]	auto[0]	auto[1]	9247833	1			T22	1		T12	11		T13	4
all_values[12]	auto[0]	auto[1]	auto[0]	954755	1			T22	2		T12	6		T13	7
all_values[12]	auto[0]	auto[1]	auto[1]	9275057	1			T22	3		T24	2		T1	3
all_values[12]	auto[1]	auto[0]	auto[1]	132314	1			T17	1		T19	1		T25	1
all_values[12]	auto[1]	auto[1]	auto[1]	131657	1			T17	1		T19	1		T25	3
all_values[13]	auto[0]	auto[0]	auto[0]	3055510	1			T22	14		T23	1		T24	4
all_values[13]	auto[0]	auto[0]	auto[1]	9265819	1			T22	2		T1	2		T12	5
all_values[13]	auto[0]	auto[1]	auto[0]	953967	1			T22	3		T24	1		T12	6
all_values[13]	auto[0]	auto[1]	auto[1]	9263007	1			T22	2		T23	20		T1	1
all_values[13]	auto[1]	auto[0]	auto[1]	131628	1			T17	3		T19	3		T110	2
all_values[13]	auto[1]	auto[1]	auto[1]	132125	1			T17	3		T25	3		T118	2
all_values[14]	auto[0]	auto[0]	auto[0]	3063928	1			T22	13		T23	14		T24	3
all_values[14]	auto[0]	auto[0]	auto[1]	9251508	1			T22	4		T23	7		T24	2
all_values[14]	auto[0]	auto[1]	auto[0]	953724	1			T22	4		T12	7		T13	5
all_values[14]	auto[0]	auto[1]	auto[1]	9269231	1			T1	1		T12	3		T13	5
all_values[14]	auto[1]	auto[0]	auto[1]	132223	1			T17	1		T25	3		T110	3
all_values[14]	auto[1]	auto[1]	auto[1]	131442	1			T17	1		T19	2		T25	1
all_values[15]	auto[0]	auto[0]	auto[0]	3064386	1			T22	18		T23	13		T24	3
all_values[15]	auto[0]	auto[0]	auto[1]	9261326	1			T23	8		T24	1		T1	3
all_values[15]	auto[0]	auto[1]	auto[0]	961376	1			T22	2		T24	1		T12	8
all_values[15]	auto[0]	auto[1]	auto[1]	9251259	1			T22	1		T12	4		T13	5
all_values[15]	auto[1]	auto[0]	auto[1]	131930	1			T17	1		T19	4		T110	2
all_values[15]	auto[1]	auto[1]	auto[1]	131779	1			T17	2		T19	1		T111	2
all_values[16]	auto[0]	auto[0]	auto[0]	3068556	1			T22	14		T23	1		T24	4
all_values[16]	auto[0]	auto[0]	auto[1]	9270147	1			T22	3		T24	1		T1	1
all_values[16]	auto[0]	auto[1]	auto[0]	954548	1			T22	3		T23	12		T12	6
all_values[16]	auto[0]	auto[1]	auto[1]	9245764	1			T22	1		T23	8		T1	1
all_values[16]	auto[1]	auto[0]	auto[1]	132067	1			T17	2		T19	1		T110	1
all_values[16]	auto[1]	auto[1]	auto[1]	130974	1			T17	1		T19	3		T25	1
all_values[17]	auto[0]	auto[0]	auto[0]	3078203	1			T22	14		T23	3		T24	3
all_values[17]	auto[0]	auto[0]	auto[1]	9256110	1			T22	1		T23	18		T24	1
all_values[17]	auto[0]	auto[1]	auto[0]	956796	1			T22	3		T12	5		T13	3
all_values[17]	auto[0]	auto[1]	auto[1]	9247073	1			T22	3		T24	1		T12	5
all_values[17]	auto[1]	auto[0]	auto[1]	132966	1			T17	2		T25	2		T110	2
all_values[17]	auto[1]	auto[1]	auto[1]	130908	1			T17	2		T19	2		T25	3
all_values[18]	auto[0]	auto[0]	auto[0]	3051247	1			T22	19		T23	13		T24	3
all_values[18]	auto[0]	auto[0]	auto[1]	9268752	1			T23	8		T24	1		T12	11
all_values[18]	auto[0]	auto[1]	auto[0]	962714	1			T24	1		T1	2		T12	2
all_values[18]	auto[0]	auto[1]	auto[1]	9255759	1			T22	2		T12	2		T13	3
all_values[18]	auto[1]	auto[0]	auto[1]	131834	1			T17	1		T19	2		T110	1
all_values[18]	auto[1]	auto[1]	auto[1]	131750	1			T17	2		T19	1		T25	2
all_values[19]	auto[0]	auto[0]	auto[0]	3053973	1			T22	15		T23	1		T24	3
all_values[19]	auto[0]	auto[0]	auto[1]	9275464	1			T22	3		T1	2		T12	8
all_values[19]	auto[0]	auto[1]	auto[0]	953033	1			T22	2		T23	12		T24	2
all_values[19]	auto[0]	auto[1]	auto[1]	9256248	1			T22	1		T23	8		T1	1
all_values[19]	auto[1]	auto[0]	auto[1]	132068	1			T17	2		T19	2		T25	2
all_values[19]	auto[1]	auto[1]	auto[1]	131270	1			T19	2		T116	2		T118	1
all_values[20]	auto[0]	auto[0]	auto[0]	3061971	1			T22	13		T23	1		T24	3
all_values[20]	auto[0]	auto[0]	auto[1]	9275553	1			T22	4		T24	1		T1	3
all_values[20]	auto[0]	auto[1]	auto[0]	957511	1			T22	3		T23	6		T12	5
all_values[20]	auto[0]	auto[1]	auto[1]	9243417	1			T22	1		T23	14		T24	1
all_values[20]	auto[1]	auto[0]	auto[1]	132153	1			T17	1		T19	3		T25	2
all_values[20]	auto[1]	auto[1]	auto[1]	131451	1			T25	2		T110	2		T111	2
all_values[21]	auto[0]	auto[0]	auto[0]	3051370	1			T22	14		T23	1		T24	4
all_values[21]	auto[0]	auto[0]	auto[1]	9304863	1			T22	3		T1	3		T12	8
all_values[21]	auto[0]	auto[1]	auto[0]	951192	1			T22	3		T23	12		T12	3
all_values[21]	auto[0]	auto[1]	auto[1]	9230248	1			T22	1		T23	8		T24	1
all_values[21]	auto[1]	auto[0]	auto[1]	132648	1			T19	1		T25	1		T110	1
all_values[21]	auto[1]	auto[1]	auto[1]	131735	1			T17	4		T19	2		T25	2
all_values[22]	auto[0]	auto[0]	auto[0]	3052073	1			T22	15		T23	1		T24	3
all_values[22]	auto[0]	auto[0]	auto[1]	9280287	1			T24	1		T12	8		T13	5
all_values[22]	auto[0]	auto[1]	auto[0]	953666	1			T22	6		T23	20		T1	3
all_values[22]	auto[0]	auto[1]	auto[1]	9252395	1			T24	1		T12	5		T13	5
all_values[22]	auto[1]	auto[0]	auto[1]	132551	1			T17	3		T19	2		T25	2
all_values[22]	auto[1]	auto[1]	auto[1]	131084	1			T17	1		T19	1		T25	1
all_values[23]	auto[0]	auto[0]	auto[0]	3057629	1			T22	17		T23	1		T24	3
all_values[23]	auto[0]	auto[0]	auto[1]	9246775	1			T24	1		T12	7		T13	6
all_values[23]	auto[0]	auto[1]	auto[0]	961128	1			T22	2		T12	4		T13	3
all_values[23]	auto[0]	auto[1]	auto[1]	9272344	1			T22	2		T23	20		T24	1
all_values[23]	auto[1]	auto[0]	auto[1]	132889	1			T17	1		T19	3		T111	1
all_values[23]	auto[1]	auto[1]	auto[1]	131291	1			T17	3		T19	1		T25	1
all_values[24]	auto[0]	auto[0]	auto[0]	3061617	1			T22	16		T23	5		T24	3
all_values[24]	auto[0]	auto[0]	auto[1]	9274492	1			T22	3		T23	16		T24	1
all_values[24]	auto[0]	auto[1]	auto[0]	957167	1			T22	1		T24	1		T1	3
all_values[24]	auto[0]	auto[1]	auto[1]	9245246	1			T22	1		T12	3		T13	3
all_values[24]	auto[1]	auto[0]	auto[1]	131932	1			T25	1		T111	2		T116	2
all_values[24]	auto[1]	auto[1]	auto[1]	131602	1			T19	3		T25	1		T116	5
all_values[25]	auto[0]	auto[0]	auto[0]	3060027	1			T22	15		T23	13		T24	3
all_values[25]	auto[0]	auto[0]	auto[1]	9262912	1			T22	3		T23	8		T24	1
all_values[25]	auto[0]	auto[1]	auto[0]	959320	1			T22	3		T12	6		T13	6
all_values[25]	auto[0]	auto[1]	auto[1]	9256736	1			T24	1		T12	3		T13	4
all_values[25]	auto[1]	auto[0]	auto[1]	131654	1			T19	3		T25	1		T110	1
all_values[25]	auto[1]	auto[1]	auto[1]	131407	1			T17	3		T25	1		T111	1
all_values[26]	auto[0]	auto[0]	auto[0]	3060985	1			T22	16		T23	1		T24	4
all_values[26]	auto[0]	auto[0]	auto[1]	9278850	1			T22	3		T24	1		T12	7
all_values[26]	auto[0]	auto[1]	auto[0]	953739	1			T22	1		T23	20		T12	4
all_values[26]	auto[0]	auto[1]	auto[1]	9244845	1			T22	1		T1	3		T12	4
all_values[26]	auto[1]	auto[0]	auto[1]	132270	1			T17	1		T19	1		T110	2
all_values[26]	auto[1]	auto[1]	auto[1]	131367	1			T17	1		T19	3		T25	3
all_values[27]	auto[0]	auto[0]	auto[0]	3048704	1			T22	14		T23	3		T24	3
all_values[27]	auto[0]	auto[0]	auto[1]	9185877	1			T22	4		T23	18		T1	2
all_values[27]	auto[0]	auto[1]	auto[0]	962635	1			T22	1		T24	2		T12	7
all_values[27]	auto[0]	auto[1]	auto[1]	9340926	1			T22	2		T1	1		T12	3
all_values[27]	auto[1]	auto[0]	auto[1]	132317	1			T25	4		T110	2		T111	1
all_values[27]	auto[1]	auto[1]	auto[1]	131597	1			T17	1		T19	2		T111	1
all_values[28]	auto[0]	auto[0]	auto[0]	3053036	1			T22	14		T23	2		T24	4
all_values[28]	auto[0]	auto[0]	auto[1]	9268380	1			T22	3		T23	19		T1	2
all_values[28]	auto[0]	auto[1]	auto[0]	963324	1			T22	2		T24	1		T12	3
all_values[28]	auto[0]	auto[1]	auto[1]	9253561	1			T22	2		T1	1		T12	3
all_values[28]	auto[1]	auto[0]	auto[1]	131919	1			T17	2		T19	3		T25	3
all_values[28]	auto[1]	auto[1]	auto[1]	131836	1			T17	1		T19	1		T111	1
all_values[29]	auto[0]	auto[0]	auto[0]	3062726	1			T22	15		T23	13		T24	3
all_values[29]	auto[0]	auto[0]	auto[1]	9270232	1			T22	3		T23	8		T1	1
all_values[29]	auto[0]	auto[1]	auto[0]	953742	1			T22	2		T24	1		T12	9
all_values[29]	auto[0]	auto[1]	auto[1]	9251287	1			T22	1		T24	1		T1	2
all_values[29]	auto[1]	auto[0]	auto[1]	131997	1			T17	2		T19	2		T25	2
all_values[29]	auto[1]	auto[1]	auto[1]	132072	1			T17	3		T19	1		T25	1
all_values[30]	auto[0]	auto[0]	auto[0]	3059325	1			T22	13		T23	2		T24	3
all_values[30]	auto[0]	auto[0]	auto[1]	9261039	1			T22	5		T23	19		T24	1
all_values[30]	auto[0]	auto[1]	auto[0]	962796	1			T22	3		T24	1		T12	8
all_values[30]	auto[0]	auto[1]	auto[1]	9255356	1			T12	8		T13	3		T15	1
all_values[30]	auto[1]	auto[0]	auto[1]	131739	1			T19	2		T25	1		T116	1
all_values[30]	auto[1]	auto[1]	auto[1]	131801	1			T17	2		T19	1		T25	1
all_values[31]	auto[0]	auto[0]	auto[0]	3063458	1			T22	15		T23	1		T24	3
all_values[31]	auto[0]	auto[0]	auto[1]	9282046	1			T22	3		T24	2		T1	3
all_values[31]	auto[0]	auto[1]	auto[0]	952656	1			T22	1		T23	1		T12	8
all_values[31]	auto[0]	auto[1]	auto[1]	9240191	1			T22	2		T23	19		T12	2
all_values[31]	auto[1]	auto[0]	auto[1]	131779	1			T17	2		T25	3		T110	1
all_values[31]	auto[1]	auto[1]	auto[1]	131926	1			T17	1		T19	2		T25	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal