Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[1]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[2]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[3]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[4]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[5]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[6]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[7]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[8]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[9]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[10]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[11]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[12]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[13]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[14]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[15]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[16]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[17]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[18]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[19]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[20]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[21]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[22]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[23]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[24]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[25]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[26]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[27]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[28]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[29]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[30]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[31]	22479479	1			T22	21		T23	21		T24	5

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443982451

1

T22

672

T23

672

T24

160

auto[1]

275360877

1

T40

1920

T41

2398

T42

19287

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

569840909

1

T22

672

T23

672

T24

160

auto[1]

149502419

1

T40

1575

T41

2559

T42

10818

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

525932771

1

T22

672

T23

672

T24

160

auto[1]

193410557

1

T40

1648

T41

2630

T42

11058

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	8373418	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5702592	1			T40	28		T41	35		T42	209
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2357240	1			T40	18		T41	18		T42	167
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	3144549	1			T40	28		T41	54		T52	170
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	569521	1			T42	186		T53	19		T55	55
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2332159	1			T40	31		T41	30		T42	202
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	8378167	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5710508	1			T40	31		T41	39		T42	246
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2351505	1			T40	22		T41	48		T42	199
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	3143554	1			T40	24		T41	32		T52	166
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	563737	1			T42	178		T53	24		T55	51
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2332008	1			T40	23		T41	32		T42	150
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	8376730	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5709074	1			T40	35		T41	30		T42	244
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2351440	1			T40	14		T41	43		T42	182
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	3143317	1			T40	40		T41	34		T52	128
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	565660	1			T42	166		T53	22		T55	74
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2333258	1			T40	31		T41	46		T42	182
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	8377711	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5718779	1			T40	34		T41	36		T42	253
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2349137	1			T40	31		T41	48		T42	187
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	3143637	1			T40	22		T41	31		T52	156
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	561662	1			T42	166		T53	12		T55	82
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2328553	1			T40	22		T41	40		T42	162
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	8383020	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5701977	1			T40	34		T41	34		T42	249
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2345949	1			T40	28		T41	44		T42	176
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	3147493	1			T40	22		T41	28		T52	172
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	567430	1			T42	179		T53	22		T55	66
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2333610	1			T40	29		T41	36		T42	172
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	8380682	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5711113	1			T40	31		T41	37		T42	263
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2349857	1			T40	30		T41	28		T42	156
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	3146799	1			T40	25		T41	44		T52	156
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	567004	1			T42	212		T53	24		T55	60
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2324024	1			T40	14		T41	36		T42	140
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	8382652	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5704844	1			T40	32		T41	34		T42	288
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2347548	1			T40	34		T41	56		T42	144
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	3150654	1			T40	20		T41	32		T52	162
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	568426	1			T42	190		T53	24		T55	31
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2325355	1			T40	15		T41	44		T42	157
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	8384463	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5707270	1			T40	35		T41	34		T42	267
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2350257	1			T40	20		T41	40		T42	134
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	3146413	1			T40	16		T41	52		T52	190
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	563442	1			T42	205		T53	28		T55	54
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2327634	1			T40	36		T41	32		T42	166
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	8361314	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5710573	1			T40	43		T41	32		T42	245
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2343851	1			T40	16		T41	28		T42	135
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	3162193	1			T40	20		T41	51		T52	192
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	567663	1			T42	170		T53	22		T55	81
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2333885	1			T40	16		T41	48		T42	226
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	8377722	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5706287	1			T40	33		T41	41		T42	273
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2351234	1			T40	18		T41	30		T42	168
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	3141951	1			T40	30		T41	60		T52	185
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	568612	1			T42	176		T53	22		T55	70
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2333673	1			T40	26		T41	39		T42	160
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	8386521	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5706164	1			T40	28		T41	25		T42	240
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2348967	1			T40	34		T41	40		T42	212
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	3149061	1			T40	22		T41	35		T52	164
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	565406	1			T42	162		T53	16		T55	65
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2323360	1			T40	22		T41	44		T42	153
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	8364712	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5714606	1			T40	36		T41	36		T42	262
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2351201	1			T40	22		T41	34		T42	143
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	3145788	1			T40	25		T41	46		T52	164
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	567626	1			T42	194		T53	30		T55	60
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2335546	1			T40	38		T41	30		T42	166
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	8352838	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5719306	1			T40	27		T41	25		T42	277
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2352400	1			T40	32		T41	30		T42	174
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	3156377	1			T40	18		T41	41		T52	134
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	570149	1			T42	165		T53	14		T55	60
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2328409	1			T40	33		T41	54		T42	162
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	8391712	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5703328	1			T40	31		T41	36		T42	253
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2350095	1			T40	28		T41	44		T42	160
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	3140918	1			T40	18		T41	39		T52	172
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	566398	1			T42	168		T53	17		T55	56
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2327028	1			T40	29		T41	32		T42	196
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	8376902	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5709096	1			T40	34		T41	25		T42	257
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2350130	1			T40	27		T41	50		T42	167
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	3147776	1			T40	34		T41	46		T52	171
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	569795	1			T42	182		T53	14		T55	68
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2325780	1			T40	18		T41	38		T42	162
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	8374299	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5712010	1			T40	38		T41	30		T42	264
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2352839	1			T40	8		T41	46		T42	191
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	3141476	1			T40	35		T41	53		T52	164
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	566447	1			T42	154		T53	19		T55	61
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2332408	1			T40	40		T41	38		T42	162
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	8376610	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5719829	1			T40	24		T41	42		T42	256
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2337187	1			T40	17		T41	55		T42	188
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	3159940	1			T40	16		T41	42		T52	148
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	565892	1			T42	179		T53	18		T55	66
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2320021	1			T40	40		T41	38		T42	152
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	8379699	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5715080	1			T40	36		T41	36		T42	253
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2345227	1			T40	26		T41	36		T42	176
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	3151085	1			T40	17		T41	38		T52	145
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	567085	1			T42	160		T53	27		T55	56
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2321303	1			T40	30		T41	37		T42	184
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	8374235	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5714026	1			T40	36		T41	31		T42	266
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2346162	1			T40	14		T41	36		T42	149
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	3147341	1			T40	34		T41	36		T52	200
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	568748	1			T42	196		T53	34		T55	67
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2328967	1			T40	10		T41	44		T42	160
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	8384774	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5716377	1			T40	28		T41	33		T42	254
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2339065	1			T40	17		T41	35		T42	153
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	3148197	1			T40	28		T41	42		T52	160
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	567611	1			T42	204		T53	42		T55	90
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2323455	1			T40	24		T41	62		T42	160
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	8368661	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5716718	1			T40	35		T41	31		T42	237
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2340243	1			T40	30		T41	28		T42	188
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	3156282	1			T40	22		T41	48		T52	164
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	569392	1			T42	150		T53	18		T55	84
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2328183	1			T40	26		T41	44		T42	193
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	8382944	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5708459	1			T40	31		T41	31		T42	263
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2340903	1			T40	14		T41	32		T42	204
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	3153718	1			T40	20		T41	42		T52	184
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	567830	1			T42	122		T53	24		T55	66
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2325625	1			T40	27		T41	49		T42	181
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	8370388	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5725439	1			T40	34		T41	34		T42	269
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2346589	1			T40	15		T41	38		T42	157
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	3153050	1			T40	34		T41	50		T52	142
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	564863	1			T42	196		T53	19		T55	53
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2319150	1			T40	26		T41	34		T42	148
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	8373765	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5721114	1			T40	34		T41	34		T42	272
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2342548	1			T40	12		T41	42		T42	198
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3154767	1			T40	30		T41	38		T52	162
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	567388	1			T42	158		T53	27		T55	65
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2319897	1			T40	33		T41	34		T42	154
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	8374295	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5715059	1			T40	31		T41	31		T42	295
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2339339	1			T40	21		T41	27		T42	168
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	3161002	1			T40	24		T41	38		T52	148
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	567485	1			T42	163		T53	28		T55	84
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2322299	1			T40	24		T41	54		T42	140
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	8391063	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5701691	1			T40	34		T41	29		T42	256
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2341800	1			T40	32		T41	32		T42	134
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	3151482	1			T40	14		T41	34		T52	209
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	570129	1			T42	184		T53	22		T55	32
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2323314	1			T40	41		T41	73		T42	191
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	8379012	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5717454	1			T40	33		T41	40		T42	244
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2343444	1			T40	22		T41	65		T42	192
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	3155282	1			T40	22		T41	28		T52	162
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	566816	1			T42	162		T53	24		T55	62
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2317471	1			T40	22		T41	36		T42	169
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	8382297	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5708355	1			T40	35		T41	37		T42	288
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2339051	1			T40	26		T41	49		T42	188
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	3157917	1			T40	18		T41	44		T52	126
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	567518	1			T42	171		T53	22		T55	42
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2324341	1			T40	34		T41	36		T42	136
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	8396245	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5697830	1			T40	34		T41	34		T42	263
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2335344	1			T40	14		T41	34		T42	156
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	3153772	1			T40	25		T41	50		T52	188
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	571346	1			T42	215		T53	11		T55	64
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2324942	1			T40	42		T41	38		T42	148
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	8387940	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5707458	1			T40	34		T41	49		T42	256
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2337751	1			T40	25		T41	42		T42	144
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	3153330	1			T40	32		T41	46		T52	173
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	570342	1			T42	186		T53	10		T55	76
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2322658	1			T40	16		T41	22		T42	185
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	8384761	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5716773	1			T40	31		T41	46		T42	223
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2344757	1			T40	26		T41	27		T42	141
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	3149210	1			T40	32		T41	42		T52	164
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	566248	1			T42	216		T53	37		T55	79
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2317730	1			T40	31		T41	50		T42	188
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	8373381	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5716316	1			T40	37		T41	27		T42	244
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2341273	1			T40	19		T41	50		T42	200
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	3156854	1			T40	18		T41	30		T52	172
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	569615	1			T42	156		T53	20		T55	72
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2322040	1			T40	14		T41	34		T42	180

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal