Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[1]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[2]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[3]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[4]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[5]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[6]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[7]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[8]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[9]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[10]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[11]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[12]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[13]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[14]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[15]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[16]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[17]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[18]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[19]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[20]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[21]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[22]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[23]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[24]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[25]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[26]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[27]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[28]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[29]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[30]	22479479	1			T22	21		T23	21		T24	5
bins_for_gpio_bits[31]	22479479	1			T22	21		T23	21		T24	5

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443982451

1

T22

672

T23

672

T24

160

auto[1]

275360877

1

T40

1920

T41

2398

T42

19287

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

443973866

1

T22

598

T23

476

T24

142

auto[1]

275369462

1

T22

74

T23

196

T24

18

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	13457878	1			T22	20		T23	10		T24	5
bins_for_gpio_bits[0]	auto[0]	auto[1]	417059	1			T40	7		T41	7		T42	45
bins_for_gpio_bits[0]	auto[1]	auto[0]	417329	1			T22	1		T23	11		T12	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	8187213	1			T40	52		T41	58		T42	552
bins_for_gpio_bits[1]	auto[0]	auto[0]	13456877	1			T22	19		T23	16		T24	4
bins_for_gpio_bits[1]	auto[0]	auto[1]	416078	1			T40	4		T41	10		T42	44
bins_for_gpio_bits[1]	auto[1]	auto[0]	416349	1			T22	2		T23	5		T24	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	8190175	1			T40	50		T41	61		T42	530
bins_for_gpio_bits[2]	auto[0]	auto[0]	13455196	1			T22	16		T23	12		T24	5
bins_for_gpio_bits[2]	auto[0]	auto[1]	415990	1			T40	9		T41	9		T42	40
bins_for_gpio_bits[2]	auto[1]	auto[0]	416291	1			T22	5		T23	9		T1	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	8192002	1			T40	57		T41	67		T42	552
bins_for_gpio_bits[3]	auto[0]	auto[0]	13453992	1			T22	20		T23	14		T24	4
bins_for_gpio_bits[3]	auto[0]	auto[1]	416218	1			T40	5		T41	11		T42	44
bins_for_gpio_bits[3]	auto[1]	auto[0]	416493	1			T22	1		T23	7		T24	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	8192776	1			T40	51		T41	65		T42	537
bins_for_gpio_bits[4]	auto[0]	auto[0]	13458886	1			T22	17		T23	17		T24	5
bins_for_gpio_bits[4]	auto[0]	auto[1]	417291	1			T40	4		T41	8		T42	41
bins_for_gpio_bits[4]	auto[1]	auto[0]	417576	1			T22	4		T23	4		T12	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	8185726	1			T40	59		T41	62		T42	559
bins_for_gpio_bits[5]	auto[0]	auto[0]	13461226	1			T22	18		T23	11		T24	5
bins_for_gpio_bits[5]	auto[0]	auto[1]	415801	1			T40	5		T41	9		T42	36
bins_for_gpio_bits[5]	auto[1]	auto[0]	416112	1			T22	3		T23	10		T12	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	8186340	1			T40	40		T41	64		T42	579
bins_for_gpio_bits[6]	auto[0]	auto[0]	13464953	1			T22	19		T23	13		T24	3
bins_for_gpio_bits[6]	auto[0]	auto[1]	415628	1			T40	5		T41	12		T42	38
bins_for_gpio_bits[6]	auto[1]	auto[0]	415901	1			T22	2		T23	8		T24	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	8182997	1			T40	42		T41	66		T42	597
bins_for_gpio_bits[7]	auto[0]	auto[0]	13464976	1			T22	19		T23	15		T24	5
bins_for_gpio_bits[7]	auto[0]	auto[1]	415902	1			T40	5		T41	10		T42	41
bins_for_gpio_bits[7]	auto[1]	auto[0]	416157	1			T22	2		T23	6		T1	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	8182444	1			T40	66		T41	56		T42	597
bins_for_gpio_bits[8]	auto[0]	auto[0]	13450093	1			T22	17		T23	16		T24	4
bins_for_gpio_bits[8]	auto[0]	auto[1]	417008	1			T40	2		T41	11		T42	32
bins_for_gpio_bits[8]	auto[1]	auto[0]	417265	1			T22	4		T23	5		T24	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	8195113	1			T40	57		T41	69		T42	609
bins_for_gpio_bits[9]	auto[0]	auto[0]	13453738	1			T22	19		T23	14		T24	5
bins_for_gpio_bits[9]	auto[0]	auto[1]	416929	1			T40	5		T41	11		T42	44
bins_for_gpio_bits[9]	auto[1]	auto[0]	417169	1			T22	2		T23	7		T12	6
bins_for_gpio_bits[9]	auto[1]	auto[1]	8191643	1			T40	54		T41	69		T42	565
bins_for_gpio_bits[10]	auto[0]	auto[0]	13468878	1			T22	21		T23	19		T24	4
bins_for_gpio_bits[10]	auto[0]	auto[1]	415415	1			T40	7		T41	14		T42	39
bins_for_gpio_bits[10]	auto[1]	auto[0]	415671	1			T23	2		T24	1		T12	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	8179515	1			T40	43		T41	55		T42	516
bins_for_gpio_bits[11]	auto[0]	auto[0]	13445115	1			T22	19		T23	12		T24	5
bins_for_gpio_bits[11]	auto[0]	auto[1]	416305	1			T40	7		T41	8		T42	39
bins_for_gpio_bits[11]	auto[1]	auto[0]	416586	1			T22	2		T23	9		T1	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	8201473	1			T40	67		T41	58		T42	583
bins_for_gpio_bits[12]	auto[0]	auto[0]	13445453	1			T22	19		T23	21		T24	4
bins_for_gpio_bits[12]	auto[0]	auto[1]	415913	1			T40	6		T41	13		T42	43
bins_for_gpio_bits[12]	auto[1]	auto[0]	416162	1			T22	2		T24	1		T1	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	8201951	1			T40	54		T41	66		T42	561
bins_for_gpio_bits[13]	auto[0]	auto[0]	13466762	1			T22	18		T23	10		T24	4
bins_for_gpio_bits[13]	auto[0]	auto[1]	415630	1			T40	7		T41	10		T42	44
bins_for_gpio_bits[13]	auto[1]	auto[0]	415963	1			T22	3		T23	11		T24	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	8181124	1			T40	53		T41	58		T42	573
bins_for_gpio_bits[14]	auto[0]	auto[0]	13458278	1			T22	19		T23	10		T24	4
bins_for_gpio_bits[14]	auto[0]	auto[1]	416263	1			T40	7		T41	9		T42	39
bins_for_gpio_bits[14]	auto[1]	auto[0]	416530	1			T22	2		T23	11		T24	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	8188408	1			T40	45		T41	54		T42	562
bins_for_gpio_bits[15]	auto[0]	auto[0]	13452239	1			T22	20		T23	15		T24	4
bins_for_gpio_bits[15]	auto[0]	auto[1]	416070	1			T40	7		T41	11		T42	38
bins_for_gpio_bits[15]	auto[1]	auto[0]	416375	1			T22	1		T23	6		T24	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	8194795	1			T40	71		T41	57		T42	542
bins_for_gpio_bits[16]	auto[0]	auto[0]	13457389	1			T22	17		T23	20		T24	5
bins_for_gpio_bits[16]	auto[0]	auto[1]	416117	1			T40	7		T41	11		T42	47
bins_for_gpio_bits[16]	auto[1]	auto[0]	416348	1			T22	4		T23	1		T1	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	8189625	1			T40	57		T41	69		T42	540
bins_for_gpio_bits[17]	auto[0]	auto[0]	13459090	1			T22	19		T23	16		T24	5
bins_for_gpio_bits[17]	auto[0]	auto[1]	416612	1			T40	7		T41	11		T42	48
bins_for_gpio_bits[17]	auto[1]	auto[0]	416921	1			T22	2		T23	5		T1	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	8186856	1			T40	59		T41	62		T42	549
bins_for_gpio_bits[18]	auto[0]	auto[0]	13450793	1			T22	20		T23	20		T24	4
bins_for_gpio_bits[18]	auto[0]	auto[1]	416682	1			T40	3		T41	10		T42	42
bins_for_gpio_bits[18]	auto[1]	auto[0]	416945	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	8195059	1			T40	43		T41	65		T42	580
bins_for_gpio_bits[19]	auto[0]	auto[0]	13455324	1			T22	18		T23	14		T24	4
bins_for_gpio_bits[19]	auto[0]	auto[1]	416465	1			T40	6		T41	12		T42	40
bins_for_gpio_bits[19]	auto[1]	auto[0]	416712	1			T22	3		T23	7		T24	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	8190978	1			T40	46		T41	83		T42	578
bins_for_gpio_bits[20]	auto[0]	auto[0]	13448677	1			T22	19		T23	15		T24	5
bins_for_gpio_bits[20]	auto[0]	auto[1]	416252	1			T40	7		T41	9		T42	45
bins_for_gpio_bits[20]	auto[1]	auto[0]	416509	1			T22	2		T23	6		T1	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	8198041	1			T40	54		T41	66		T42	535
bins_for_gpio_bits[21]	auto[0]	auto[0]	13460268	1			T22	18		T23	18		T24	4
bins_for_gpio_bits[21]	auto[0]	auto[1]	416997	1			T40	5		T41	11		T42	57
bins_for_gpio_bits[21]	auto[1]	auto[0]	417297	1			T22	3		T23	3		T24	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	8184917	1			T40	53		T41	69		T42	509
bins_for_gpio_bits[22]	auto[0]	auto[0]	13452566	1			T22	19		T23	21		T24	4
bins_for_gpio_bits[22]	auto[0]	auto[1]	417199	1			T40	6		T41	12		T42	44
bins_for_gpio_bits[22]	auto[1]	auto[0]	417461	1			T22	2		T24	1		T1	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	8192253	1			T40	54		T41	56		T42	569
bins_for_gpio_bits[23]	auto[0]	auto[0]	13454059	1			T22	18		T23	11		T24	4
bins_for_gpio_bits[23]	auto[0]	auto[1]	416725	1			T40	6		T41	11		T42	47
bins_for_gpio_bits[23]	auto[1]	auto[0]	417021	1			T22	3		T23	10		T24	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	8191674	1			T40	61		T41	57		T42	537
bins_for_gpio_bits[24]	auto[0]	auto[0]	13457791	1			T22	20		T23	11		T24	5
bins_for_gpio_bits[24]	auto[0]	auto[1]	416581	1			T40	5		T41	10		T42	39
bins_for_gpio_bits[24]	auto[1]	auto[0]	416845	1			T22	1		T23	10		T12	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	8188262	1			T40	50		T41	75		T42	559
bins_for_gpio_bits[25]	auto[0]	auto[0]	13467265	1			T22	18		T23	18		T24	5
bins_for_gpio_bits[25]	auto[0]	auto[1]	416827	1			T40	6		T41	9		T42	37
bins_for_gpio_bits[25]	auto[1]	auto[0]	417080	1			T22	3		T23	3		T1	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	8178307	1			T40	69		T41	93		T42	594
bins_for_gpio_bits[26]	auto[0]	auto[0]	13461893	1			T22	19		T23	21		T24	4
bins_for_gpio_bits[26]	auto[0]	auto[1]	415597	1			T40	7		T41	10		T42	39
bins_for_gpio_bits[26]	auto[1]	auto[0]	415845	1			T22	2		T24	1		T1	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	8186144	1			T40	48		T41	66		T42	536
bins_for_gpio_bits[27]	auto[0]	auto[0]	13461913	1			T22	19		T23	15		T24	4
bins_for_gpio_bits[27]	auto[0]	auto[1]	417085	1			T40	8		T41	10		T42	36
bins_for_gpio_bits[27]	auto[1]	auto[0]	417352	1			T22	2		T23	6		T24	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	8183129	1			T40	61		T41	63		T42	559
bins_for_gpio_bits[28]	auto[0]	auto[0]	13468828	1			T22	20		T23	6		T24	5
bins_for_gpio_bits[28]	auto[0]	auto[1]	416307	1			T40	5		T41	8		T42	44
bins_for_gpio_bits[28]	auto[1]	auto[0]	416533	1			T22	1		T23	15		T1	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	8177811	1			T40	71		T41	64		T42	582
bins_for_gpio_bits[29]	auto[0]	auto[0]	13461739	1			T22	20		T23	16		T24	4
bins_for_gpio_bits[29]	auto[0]	auto[1]	417022	1			T40	7		T41	7		T42	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	417282	1			T22	1		T23	5		T24	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	8183436	1			T40	43		T41	64		T42	587
bins_for_gpio_bits[30]	auto[0]	auto[0]	13462075	1			T22	17		T23	14		T24	5
bins_for_gpio_bits[30]	auto[0]	auto[1]	416424	1			T40	8		T41	10		T42	38
bins_for_gpio_bits[30]	auto[1]	auto[0]	416653	1			T22	4		T23	7		T1	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	8184327	1			T40	54		T41	86		T42	589
bins_for_gpio_bits[31]	auto[0]	auto[0]	13455066	1			T22	17		T23	15		T24	5
bins_for_gpio_bits[31]	auto[0]	auto[1]	416198	1			T40	4		T41	8		T42	40
bins_for_gpio_bits[31]	auto[1]	auto[0]	416442	1			T22	4		T23	6		T1	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	8191773	1			T40	47		T41	53		T42	540