Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12458482 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10343574 |
1 |
|
|
T22 |
3 |
|
T24 |
1 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21462510 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1339546 |
1 |
|
|
T51 |
4115 |
|
T113 |
3 |
|
T112 |
1568 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12445513 |
1 |
|
|
T22 |
20 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10356543 |
1 |
|
|
T22 |
1 |
|
T12 |
9 |
|
T13 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4509781 |
1 |
|
|
T12 |
6 |
|
T13 |
5 |
|
T15 |
1 |
| auto[1] |
auto[0] |
auto[1] |
669487 |
1 |
|
|
T51 |
2166 |
|
T113 |
1 |
|
T112 |
676 |
| auto[1] |
auto[1] |
auto[0] |
4507216 |
1 |
|
|
T22 |
1 |
|
T12 |
3 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[1] |
670059 |
1 |
|
|
T51 |
1949 |
|
T113 |
2 |
|
T112 |
892 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12445748 |
1 |
|
|
T22 |
17 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10356308 |
1 |
|
|
T22 |
4 |
|
T24 |
1 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21458459 |
1 |
|
|
T22 |
21 |
|
T23 |
19 |
|
T24 |
5 |
| auto[1] |
1343597 |
1 |
|
|
T23 |
2 |
|
T51 |
3901 |
|
T113 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12428234 |
1 |
|
|
T22 |
16 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10373822 |
1 |
|
|
T22 |
5 |
|
T23 |
20 |
|
T1 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4510102 |
1 |
|
|
T22 |
3 |
|
T23 |
18 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
671162 |
1 |
|
|
T23 |
2 |
|
T51 |
2038 |
|
T113 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4520123 |
1 |
|
|
T22 |
2 |
|
T1 |
2 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
672435 |
1 |
|
|
T51 |
1863 |
|
T113 |
3 |
|
T112 |
630 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12529688 |
1 |
|
|
T22 |
19 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10272368 |
1 |
|
|
T22 |
2 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21462165 |
1 |
|
|
T22 |
21 |
|
T23 |
20 |
|
T24 |
5 |
| auto[1] |
1339891 |
1 |
|
|
T23 |
1 |
|
T84 |
1 |
|
T10 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12447132 |
1 |
|
|
T22 |
19 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10354924 |
1 |
|
|
T22 |
2 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4530856 |
1 |
|
|
T22 |
1 |
|
T12 |
5 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
674661 |
1 |
|
|
T10 |
1 |
|
T20 |
4 |
|
T51 |
1871 |
| auto[1] |
auto[1] |
auto[0] |
4484177 |
1 |
|
|
T22 |
1 |
|
T23 |
19 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
665230 |
1 |
|
|
T23 |
1 |
|
T84 |
1 |
|
T78 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12467895 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10334161 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21466749 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1335307 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12468056 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10334000 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4508560 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
670780 |
1 |
|
|
T1 |
1 |
|
T8 |
1 |
|
T119 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4490133 |
1 |
|
|
T12 |
2 |
|
T13 |
5 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
664527 |
1 |
|
|
T15 |
1 |
|
T75 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12440587 |
1 |
|
|
T22 |
16 |
|
T23 |
21 |
|
T24 |
3 |
| auto[1] |
10361469 |
1 |
|
|
T22 |
5 |
|
T24 |
2 |
|
T1 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21466015 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1336041 |
1 |
|
|
T16 |
1 |
|
T75 |
1 |
|
T84 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12469317 |
1 |
|
|
T22 |
17 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10332739 |
1 |
|
|
T22 |
4 |
|
T24 |
1 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4508934 |
1 |
|
|
T22 |
2 |
|
T12 |
4 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
669045 |
1 |
|
|
T16 |
1 |
|
T84 |
1 |
|
T51 |
2177 |
| auto[1] |
auto[1] |
auto[0] |
4487764 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[1] |
666996 |
1 |
|
|
T75 |
1 |
|
T8 |
1 |
|
T51 |
1969 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12452957 |
1 |
|
|
T22 |
16 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10349099 |
1 |
|
|
T22 |
5 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21469642 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1332414 |
1 |
|
|
T1 |
1 |
|
T75 |
1 |
|
T8 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12481333 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10320723 |
1 |
|
|
T22 |
3 |
|
T1 |
1 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4474075 |
1 |
|
|
T22 |
2 |
|
T12 |
3 |
|
T13 |
5 |
| auto[1] |
auto[0] |
auto[1] |
662804 |
1 |
|
|
T75 |
1 |
|
T8 |
1 |
|
T51 |
2055 |
| auto[1] |
auto[1] |
auto[0] |
4514234 |
1 |
|
|
T22 |
1 |
|
T12 |
4 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[1] |
669610 |
1 |
|
|
T1 |
1 |
|
T76 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12447659 |
1 |
|
|
T22 |
17 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10354397 |
1 |
|
|
T22 |
4 |
|
T1 |
1 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21461280 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1340776 |
1 |
|
|
T75 |
3 |
|
T84 |
1 |
|
T20 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12431430 |
1 |
|
|
T22 |
16 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10370626 |
1 |
|
|
T22 |
5 |
|
T24 |
1 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4532796 |
1 |
|
|
T22 |
3 |
|
T24 |
1 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
673119 |
1 |
|
|
T20 |
4 |
|
T119 |
1 |
|
T51 |
1880 |
| auto[1] |
auto[1] |
auto[0] |
4497054 |
1 |
|
|
T22 |
2 |
|
T12 |
2 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[1] |
667657 |
1 |
|
|
T75 |
3 |
|
T84 |
1 |
|
T107 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12457642 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10344414 |
1 |
|
|
T22 |
3 |
|
T24 |
1 |
|
T12 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21470293 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1331763 |
1 |
|
|
T1 |
1 |
|
T16 |
1 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12490029 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10312027 |
1 |
|
|
T22 |
2 |
|
T1 |
2 |
|
T12 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4501747 |
1 |
|
|
T22 |
2 |
|
T1 |
1 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
669286 |
1 |
|
|
T1 |
1 |
|
T107 |
1 |
|
T51 |
1761 |
| auto[1] |
auto[1] |
auto[0] |
4478517 |
1 |
|
|
T12 |
3 |
|
T13 |
6 |
|
T15 |
3 |
| auto[1] |
auto[1] |
auto[1] |
662477 |
1 |
|
|
T16 |
1 |
|
T75 |
1 |
|
T84 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12470770 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10331286 |
1 |
|
|
T22 |
4 |
|
T23 |
20 |
|
T1 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21466903 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1335153 |
1 |
|
|
T1 |
1 |
|
T20 |
1 |
|
T78 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12448754 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10353302 |
1 |
|
|
T22 |
3 |
|
T1 |
1 |
|
T12 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4525665 |
1 |
|
|
T22 |
2 |
|
T12 |
3 |
|
T13 |
4 |
| auto[1] |
auto[0] |
auto[1] |
670567 |
1 |
|
|
T20 |
1 |
|
T78 |
1 |
|
T51 |
1906 |
| auto[1] |
auto[1] |
auto[0] |
4492484 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
664586 |
1 |
|
|
T1 |
1 |
|
T51 |
2096 |
|
T113 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12467279 |
1 |
|
|
T22 |
15 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10334777 |
1 |
|
|
T22 |
6 |
|
T24 |
1 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21472760 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1329296 |
1 |
|
|
T84 |
1 |
|
T20 |
1 |
|
T77 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12500993 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10301063 |
1 |
|
|
T22 |
3 |
|
T24 |
1 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4495450 |
1 |
|
|
T22 |
1 |
|
T1 |
2 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
665455 |
1 |
|
|
T84 |
1 |
|
T20 |
1 |
|
T107 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4476317 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
663841 |
1 |
|
|
T77 |
1 |
|
T51 |
2098 |
|
T113 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12451833 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10350223 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T1 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21465057 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1336999 |
1 |
|
|
T75 |
1 |
|
T84 |
1 |
|
T8 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12449926 |
1 |
|
|
T22 |
15 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10352130 |
1 |
|
|
T22 |
6 |
|
T1 |
3 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4514716 |
1 |
|
|
T22 |
5 |
|
T1 |
1 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
670832 |
1 |
|
|
T75 |
1 |
|
T84 |
1 |
|
T51 |
1988 |
| auto[1] |
auto[1] |
auto[0] |
4500415 |
1 |
|
|
T22 |
1 |
|
T1 |
2 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
666167 |
1 |
|
|
T8 |
1 |
|
T20 |
2 |
|
T107 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12461505 |
1 |
|
|
T22 |
18 |
|
T23 |
1 |
|
T24 |
3 |
| auto[1] |
10340551 |
1 |
|
|
T22 |
3 |
|
T23 |
20 |
|
T24 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21465828 |
1 |
|
|
T22 |
21 |
|
T23 |
20 |
|
T24 |
5 |
| auto[1] |
1336228 |
1 |
|
|
T23 |
1 |
|
T75 |
1 |
|
T84 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12474672 |
1 |
|
|
T22 |
18 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10327384 |
1 |
|
|
T22 |
3 |
|
T23 |
20 |
|
T1 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4501746 |
1 |
|
|
T22 |
2 |
|
T1 |
2 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
669099 |
1 |
|
|
T75 |
1 |
|
T84 |
1 |
|
T20 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4489410 |
1 |
|
|
T22 |
1 |
|
T23 |
19 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
667129 |
1 |
|
|
T23 |
1 |
|
T119 |
1 |
|
T51 |
1753 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12469435 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10332621 |
1 |
|
|
T22 |
3 |
|
T1 |
1 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21460760 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1341296 |
1 |
|
|
T8 |
1 |
|
T10 |
1 |
|
T20 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12424813 |
1 |
|
|
T22 |
20 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10377243 |
1 |
|
|
T22 |
1 |
|
T12 |
8 |
|
T13 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4510368 |
1 |
|
|
T22 |
1 |
|
T12 |
7 |
|
T13 |
5 |
| auto[1] |
auto[0] |
auto[1] |
669182 |
1 |
|
|
T8 |
1 |
|
T10 |
1 |
|
T77 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4525579 |
1 |
|
|
T12 |
1 |
|
T13 |
4 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
672114 |
1 |
|
|
T20 |
2 |
|
T51 |
2204 |
|
T113 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12469677 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10332379 |
1 |
|
|
T22 |
4 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21465810 |
1 |
|
|
T22 |
21 |
|
T23 |
18 |
|
T24 |
5 |
| auto[1] |
1336246 |
1 |
|
|
T23 |
3 |
|
T15 |
1 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12464610 |
1 |
|
|
T22 |
20 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10337446 |
1 |
|
|
T22 |
1 |
|
T23 |
20 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4512347 |
1 |
|
|
T1 |
1 |
|
T12 |
3 |
|
T13 |
4 |
| auto[1] |
auto[0] |
auto[1] |
669949 |
1 |
|
|
T15 |
1 |
|
T75 |
1 |
|
T51 |
2308 |
| auto[1] |
auto[1] |
auto[0] |
4488853 |
1 |
|
|
T22 |
1 |
|
T23 |
17 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
666297 |
1 |
|
|
T23 |
3 |
|
T51 |
2106 |
|
T113 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12488881 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10313175 |
1 |
|
|
T22 |
4 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21465741 |
1 |
|
|
T22 |
21 |
|
T23 |
20 |
|
T24 |
5 |
| auto[1] |
1336315 |
1 |
|
|
T23 |
1 |
|
T1 |
1 |
|
T75 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12466832 |
1 |
|
|
T22 |
20 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10335224 |
1 |
|
|
T22 |
1 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4512705 |
1 |
|
|
T22 |
1 |
|
T24 |
1 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
670426 |
1 |
|
|
T1 |
1 |
|
T119 |
1 |
|
T78 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4486204 |
1 |
|
|
T23 |
19 |
|
T12 |
2 |
|
T13 |
5 |
| auto[1] |
auto[1] |
auto[1] |
665889 |
1 |
|
|
T23 |
1 |
|
T75 |
3 |
|
T8 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12464911 |
1 |
|
|
T22 |
15 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10337145 |
1 |
|
|
T22 |
6 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21458905 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1343151 |
1 |
|
|
T8 |
1 |
|
T20 |
2 |
|
T77 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418055 |
1 |
|
|
T22 |
18 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10384001 |
1 |
|
|
T22 |
3 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4517020 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
671207 |
1 |
|
|
T8 |
1 |
|
T51 |
1958 |
|
T113 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4523830 |
1 |
|
|
T22 |
1 |
|
T23 |
20 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
671944 |
1 |
|
|
T20 |
2 |
|
T77 |
2 |
|
T119 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12437293 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
4 |
| auto[1] |
10364763 |
1 |
|
|
T22 |
4 |
|
T23 |
20 |
|
T24 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21467621 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1334435 |
1 |
|
|
T105 |
1 |
|
T78 |
1 |
|
T51 |
4035 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12464652 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10337404 |
1 |
|
|
T22 |
2 |
|
T1 |
1 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4506299 |
1 |
|
|
T22 |
2 |
|
T12 |
5 |
|
T13 |
6 |
| auto[1] |
auto[0] |
auto[1] |
668086 |
1 |
|
|
T51 |
2102 |
|
T113 |
3 |
|
T112 |
777 |
| auto[1] |
auto[1] |
auto[0] |
4496670 |
1 |
|
|
T1 |
1 |
|
T12 |
3 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[1] |
666349 |
1 |
|
|
T105 |
1 |
|
T78 |
1 |
|
T51 |
1933 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12468041 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10334015 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T1 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21466204 |
1 |
|
|
T22 |
21 |
|
T23 |
17 |
|
T24 |
5 |
| auto[1] |
1335852 |
1 |
|
|
T23 |
4 |
|
T75 |
4 |
|
T105 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12470035 |
1 |
|
|
T22 |
16 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10332021 |
1 |
|
|
T22 |
5 |
|
T23 |
20 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4494038 |
1 |
|
|
T22 |
4 |
|
T23 |
16 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
668342 |
1 |
|
|
T23 |
4 |
|
T75 |
4 |
|
T51 |
2160 |
| auto[1] |
auto[1] |
auto[0] |
4502131 |
1 |
|
|
T22 |
1 |
|
T1 |
2 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
667510 |
1 |
|
|
T105 |
1 |
|
T51 |
1928 |
|
T113 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12454593 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10347463 |
1 |
|
|
T22 |
3 |
|
T24 |
1 |
|
T12 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21468477 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1333579 |
1 |
|
|
T84 |
1 |
|
T20 |
1 |
|
T51 |
4049 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12484712 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
10317344 |
1 |
|
|
T22 |
2 |
|
T1 |
1 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4508622 |
1 |
|
|
T22 |
2 |
|
T1 |
1 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
670436 |
1 |
|
|
T84 |
1 |
|
T20 |
1 |
|
T51 |
2148 |
| auto[1] |
auto[1] |
auto[0] |
4475143 |
1 |
|
|
T12 |
3 |
|
T13 |
4 |
|
T16 |
4 |
| auto[1] |
auto[1] |
auto[1] |
663143 |
1 |
|
|
T51 |
1901 |
|
T113 |
3 |
|
T112 |
796 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12472105 |
1 |
|
|
T22 |
19 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10329951 |
1 |
|
|
T22 |
2 |
|
T23 |
20 |
|
T1 |
3 |