Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12446255 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
3 |
| auto[1] |
10355801 |
1 |
|
|
T22 |
4 |
|
T23 |
20 |
|
T24 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21466177 |
1 |
|
|
T22 |
21 |
|
T23 |
21 |
|
T24 |
5 |
| auto[1] |
1335879 |
1 |
|
|
T75 |
2 |
|
T84 |
1 |
|
T8 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12461714 |
1 |
|
|
T22 |
18 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10340342 |
1 |
|
|
T22 |
3 |
|
T24 |
1 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4504952 |
1 |
|
|
T22 |
3 |
|
T12 |
7 |
|
T13 |
2 |
| auto[1] |
auto[0] |
auto[1] |
668558 |
1 |
|
|
T75 |
2 |
|
T84 |
1 |
|
T8 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4499511 |
1 |
|
|
T24 |
1 |
|
T12 |
1 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[1] |
667321 |
1 |
|
|
T20 |
5 |
|
T51 |
1958 |
|
T113 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |