Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12467895 |
1 |
|
|
T22 |
19 |
|
T23 |
21 |
|
T24 |
4 |
| auto[1] |
10334161 |
1 |
|
|
T22 |
2 |
|
T24 |
1 |
|
T12 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18663629 |
1 |
|
|
T22 |
21 |
|
T23 |
12 |
|
T24 |
5 |
| auto[1] |
4138427 |
1 |
|
|
T23 |
9 |
|
T12 |
3 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12471091 |
1 |
|
|
T22 |
19 |
|
T23 |
1 |
|
T24 |
5 |
| auto[1] |
10330965 |
1 |
|
|
T22 |
2 |
|
T23 |
20 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3099008 |
1 |
|
|
T22 |
1 |
|
T23 |
11 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2070612 |
1 |
|
|
T23 |
9 |
|
T12 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3093530 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[1] |
2067815 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T16 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |