Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 100.00


Total test records in report: 970
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T776 /workspace/coverage/default/49.gpio_intr_rand_pgm.2976581657 Jan 21 04:22:00 PM PST 24 Jan 21 04:22:02 PM PST 24 236046071 ps
T777 /workspace/coverage/default/2.gpio_stress_all.3519392531 Jan 21 03:20:34 PM PST 24 Jan 21 03:21:00 PM PST 24 4154485151 ps
T778 /workspace/coverage/default/45.gpio_smoke.3245997908 Jan 21 03:25:17 PM PST 24 Jan 21 03:25:20 PM PST 24 136484737 ps
T779 /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3107663096 Jan 21 03:23:02 PM PST 24 Jan 21 03:23:03 PM PST 24 49930910 ps
T780 /workspace/coverage/default/16.gpio_intr_rand_pgm.1670530494 Jan 21 03:40:41 PM PST 24 Jan 21 03:40:43 PM PST 24 327714648 ps
T80 /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.438642024 Jan 21 03:25:53 PM PST 24 Jan 21 03:35:29 PM PST 24 39984419110 ps
T94 /workspace/coverage/default/2.gpio_random_dout_din.641575467 Jan 21 03:20:20 PM PST 24 Jan 21 03:20:21 PM PST 24 74917022 ps
T95 /workspace/coverage/default/33.gpio_filter_stress.207507215 Jan 21 03:24:00 PM PST 24 Jan 21 03:24:21 PM PST 24 644479281 ps
T96 /workspace/coverage/default/2.gpio_full_random.3530621061 Jan 21 03:20:29 PM PST 24 Jan 21 03:20:31 PM PST 24 39703058 ps
T97 /workspace/coverage/default/41.gpio_rand_intr_trigger.181451331 Jan 21 03:24:59 PM PST 24 Jan 21 03:25:02 PM PST 24 112184666 ps
T98 /workspace/coverage/default/26.gpio_smoke.2627887398 Jan 21 03:23:05 PM PST 24 Jan 21 03:23:08 PM PST 24 139245782 ps
T99 /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.328256395 Jan 21 03:20:13 PM PST 24 Jan 21 03:20:15 PM PST 24 30287067 ps
T100 /workspace/coverage/default/43.gpio_rand_intr_trigger.3330844362 Jan 21 04:23:54 PM PST 24 Jan 21 04:23:58 PM PST 24 274084253 ps
T101 /workspace/coverage/default/5.gpio_rand_intr_trigger.1682663442 Jan 21 03:20:47 PM PST 24 Jan 21 03:20:58 PM PST 24 50783072 ps
T781 /workspace/coverage/default/26.gpio_intr_rand_pgm.1997187224 Jan 21 03:23:05 PM PST 24 Jan 21 03:23:07 PM PST 24 35195479 ps
T782 /workspace/coverage/default/39.gpio_alert_test.3150312226 Jan 21 03:24:43 PM PST 24 Jan 21 03:24:51 PM PST 24 22408922 ps
T783 /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3679916153 Jan 21 03:47:34 PM PST 24 Jan 21 03:58:54 PM PST 24 204769683173 ps
T784 /workspace/coverage/default/46.gpio_intr_rand_pgm.1635220941 Jan 21 03:49:10 PM PST 24 Jan 21 03:49:14 PM PST 24 61713765 ps
T785 /workspace/coverage/default/28.gpio_rand_intr_trigger.439867710 Jan 21 03:23:12 PM PST 24 Jan 21 03:23:16 PM PST 24 159842620 ps
T786 /workspace/coverage/default/47.gpio_rand_intr_trigger.1998118669 Jan 21 03:25:24 PM PST 24 Jan 21 03:25:27 PM PST 24 231836660 ps
T787 /workspace/coverage/default/27.gpio_random_dout_din.3509411319 Jan 21 03:23:07 PM PST 24 Jan 21 03:23:09 PM PST 24 18801583 ps
T788 /workspace/coverage/default/8.gpio_random_dout_din.3826839054 Jan 21 03:21:00 PM PST 24 Jan 21 03:21:10 PM PST 24 54564833 ps
T789 /workspace/coverage/default/10.gpio_rand_intr_trigger.2888504 Jan 21 03:36:46 PM PST 24 Jan 21 03:36:48 PM PST 24 276177822 ps
T790 /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1345441351 Jan 21 03:21:32 PM PST 24 Jan 21 03:21:51 PM PST 24 2285775431 ps
T791 /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4215942769 Jan 21 03:20:42 PM PST 24 Jan 21 03:20:45 PM PST 24 97699253 ps
T792 /workspace/coverage/default/9.gpio_random_dout_din.3661382313 Jan 21 03:21:08 PM PST 24 Jan 21 03:21:13 PM PST 24 810628537 ps
T793 /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3461828298 Jan 21 03:25:22 PM PST 24 Jan 21 03:25:24 PM PST 24 47696567 ps
T794 /workspace/coverage/default/30.gpio_alert_test.2863503752 Jan 21 03:23:31 PM PST 24 Jan 21 03:23:32 PM PST 24 17121549 ps
T795 /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.596119424 Jan 21 05:13:20 PM PST 24 Jan 21 05:14:31 PM PST 24 90054757 ps
T796 /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3328179784 Jan 21 03:25:26 PM PST 24 Jan 21 03:25:28 PM PST 24 16683583 ps
T797 /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4032922567 Jan 21 03:22:53 PM PST 24 Jan 21 03:41:04 PM PST 24 64649694031 ps
T798 /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2186092199 Jan 21 03:22:24 PM PST 24 Jan 21 03:38:08 PM PST 24 129957288210 ps
T799 /workspace/coverage/default/47.gpio_filter_stress.971912359 Jan 21 03:25:25 PM PST 24 Jan 21 03:25:34 PM PST 24 939802240 ps
T800 /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2876667555 Jan 21 03:23:40 PM PST 24 Jan 21 03:23:42 PM PST 24 85829433 ps
T801 /workspace/coverage/default/27.gpio_smoke.290739026 Jan 21 03:23:06 PM PST 24 Jan 21 03:23:09 PM PST 24 150022964 ps
T802 /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1849687818 Jan 21 03:20:47 PM PST 24 Jan 21 03:20:57 PM PST 24 334114902 ps
T803 /workspace/coverage/default/12.gpio_full_random.2036554873 Jan 21 03:21:28 PM PST 24 Jan 21 03:21:36 PM PST 24 232204095 ps
T804 /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3207262076 Jan 21 03:21:22 PM PST 24 Jan 21 03:21:26 PM PST 24 207728153 ps
T805 /workspace/coverage/default/8.gpio_alert_test.2634281286 Jan 21 03:20:57 PM PST 24 Jan 21 03:21:09 PM PST 24 17900321 ps
T806 /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1562239775 Jan 21 04:09:06 PM PST 24 Jan 21 04:09:10 PM PST 24 28068680 ps
T807 /workspace/coverage/default/38.gpio_smoke.3326895815 Jan 21 03:24:22 PM PST 24 Jan 21 03:24:26 PM PST 24 151915457 ps
T808 /workspace/coverage/default/23.gpio_full_random.3418699460 Jan 21 03:23:00 PM PST 24 Jan 21 03:23:01 PM PST 24 30194081 ps
T809 /workspace/coverage/default/18.gpio_full_random.573333960 Jan 21 03:22:08 PM PST 24 Jan 21 03:22:16 PM PST 24 63142786 ps
T810 /workspace/coverage/default/38.gpio_intr_rand_pgm.1721532932 Jan 21 03:24:26 PM PST 24 Jan 21 03:24:29 PM PST 24 52767595 ps
T811 /workspace/coverage/default/12.gpio_stress_all.213412221 Jan 21 03:21:34 PM PST 24 Jan 21 03:24:12 PM PST 24 14006780574 ps
T812 /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4267080655 Jan 21 03:22:10 PM PST 24 Jan 21 03:22:17 PM PST 24 127219723 ps
T813 /workspace/coverage/default/25.gpio_smoke.196772851 Jan 21 03:23:02 PM PST 24 Jan 21 03:23:04 PM PST 24 370527995 ps
T814 /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1349628971 Jan 21 03:21:52 PM PST 24 Jan 21 03:22:00 PM PST 24 58489657 ps
T815 /workspace/coverage/default/25.gpio_random_dout_din.1095626057 Jan 21 03:22:55 PM PST 24 Jan 21 03:22:57 PM PST 24 73142069 ps
T816 /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3754705557 Jan 21 03:21:18 PM PST 24 Jan 21 03:21:20 PM PST 24 43306818 ps
T817 /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1185580218 Jan 21 03:20:09 PM PST 24 Jan 21 03:20:12 PM PST 24 42211697 ps
T818 /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2765001138 Jan 21 03:21:03 PM PST 24 Jan 21 03:25:46 PM PST 24 17119563427 ps
T819 /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.803239205 Jan 21 03:23:00 PM PST 24 Jan 21 03:39:23 PM PST 24 151943049331 ps
T820 /workspace/coverage/default/30.gpio_full_random.2321390389 Jan 21 03:23:33 PM PST 24 Jan 21 03:23:34 PM PST 24 80568613 ps
T821 /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3614150328 Jan 21 03:25:25 PM PST 24 Jan 21 03:25:27 PM PST 24 207482503 ps
T822 /workspace/coverage/default/7.gpio_smoke.3164572181 Jan 21 03:20:49 PM PST 24 Jan 21 03:20:59 PM PST 24 339128932 ps
T823 /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.785139197 Jan 21 03:24:26 PM PST 24 Jan 21 03:24:28 PM PST 24 45010007 ps
T824 /workspace/coverage/default/48.gpio_full_random.3396413315 Jan 21 03:25:35 PM PST 24 Jan 21 03:25:37 PM PST 24 248078106 ps
T825 /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3616808236 Jan 21 03:20:44 PM PST 24 Jan 21 03:20:47 PM PST 24 139926976 ps
T826 /workspace/coverage/default/2.gpio_filter_stress.1986238319 Jan 21 03:20:20 PM PST 24 Jan 21 03:20:38 PM PST 24 1802185189 ps
T827 /workspace/coverage/default/26.gpio_full_random.296484938 Jan 21 03:38:47 PM PST 24 Jan 21 03:38:48 PM PST 24 29391595 ps
T828 /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2920697603 Jan 21 03:25:54 PM PST 24 Jan 21 03:25:58 PM PST 24 55913166 ps
T829 /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3787406048 Jan 21 03:23:05 PM PST 24 Jan 21 03:23:07 PM PST 24 29375286 ps
T830 /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3684814374 Jan 21 03:23:30 PM PST 24 Jan 21 03:23:33 PM PST 24 1224912467 ps
T831 /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1434837061 Jan 21 03:22:37 PM PST 24 Jan 21 03:22:41 PM PST 24 1295900819 ps
T832 /workspace/coverage/default/27.gpio_intr_rand_pgm.3541729600 Jan 21 03:36:11 PM PST 24 Jan 21 03:36:13 PM PST 24 359966560 ps
T833 /workspace/coverage/default/42.gpio_smoke.599211575 Jan 21 03:25:00 PM PST 24 Jan 21 03:25:03 PM PST 24 55899221 ps
T834 /workspace/coverage/default/29.gpio_rand_intr_trigger.1631887543 Jan 21 05:20:55 PM PST 24 Jan 21 05:20:58 PM PST 24 93371504 ps
T835 /workspace/coverage/default/46.gpio_stress_all.1967602155 Jan 21 03:25:25 PM PST 24 Jan 21 03:27:14 PM PST 24 3658830425 ps
T836 /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2777099021 Jan 21 03:25:07 PM PST 24 Jan 21 03:25:09 PM PST 24 44605523 ps
T837 /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.884147248 Jan 21 03:24:15 PM PST 24 Jan 21 03:27:47 PM PST 24 57949751201 ps
T838 /workspace/coverage/default/42.gpio_stress_all.2730255386 Jan 21 03:25:03 PM PST 24 Jan 21 03:25:42 PM PST 24 5043876122 ps
T839 /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3458335585 Jan 21 04:31:41 PM PST 24 Jan 21 04:31:47 PM PST 24 124073106 ps
T840 /workspace/coverage/default/30.gpio_intr_rand_pgm.1020246378 Jan 21 03:23:33 PM PST 24 Jan 21 03:23:35 PM PST 24 311261619 ps
T841 /workspace/coverage/default/31.gpio_intr_rand_pgm.4041709700 Jan 21 03:23:38 PM PST 24 Jan 21 03:23:40 PM PST 24 72758538 ps
T842 /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3126423854 Jan 21 03:24:53 PM PST 24 Jan 21 03:24:59 PM PST 24 526794768 ps
T843 /workspace/coverage/default/35.gpio_stress_all.2024495769 Jan 21 03:24:06 PM PST 24 Jan 21 03:26:49 PM PST 24 5869636107 ps
T844 /workspace/coverage/default/23.gpio_rand_intr_trigger.2670198873 Jan 21 03:22:54 PM PST 24 Jan 21 03:22:56 PM PST 24 137539649 ps
T845 /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2999812175 Jan 21 03:25:07 PM PST 24 Jan 21 03:25:12 PM PST 24 606330772 ps
T846 /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1425531569 Jan 21 03:24:22 PM PST 24 Jan 21 03:24:26 PM PST 24 46362836 ps
T847 /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2495447283 Jan 21 03:21:07 PM PST 24 Jan 21 03:21:13 PM PST 24 36734927 ps
T848 /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3407304380 Jan 21 03:22:55 PM PST 24 Jan 21 03:22:57 PM PST 24 132130009 ps
T849 /workspace/coverage/default/44.gpio_rand_intr_trigger.1355254243 Jan 21 03:25:23 PM PST 24 Jan 21 03:25:26 PM PST 24 154812661 ps
T850 /workspace/coverage/default/7.gpio_alert_test.3673741144 Jan 21 03:20:55 PM PST 24 Jan 21 03:21:07 PM PST 24 40785255 ps
T851 /workspace/coverage/default/47.gpio_full_random.2482196269 Jan 21 03:25:42 PM PST 24 Jan 21 03:25:44 PM PST 24 231929886 ps
T852 /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2563711873 Jan 21 03:25:25 PM PST 24 Jan 21 03:25:27 PM PST 24 37927017 ps
T853 /workspace/coverage/default/14.gpio_smoke.2869573368 Jan 21 03:21:35 PM PST 24 Jan 21 03:21:52 PM PST 24 266331821 ps
T854 /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2866514267 Jan 21 03:24:01 PM PST 24 Jan 21 03:24:11 PM PST 24 125973218 ps
T855 /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4157280729 Jan 21 03:20:22 PM PST 24 Jan 21 03:20:23 PM PST 24 37761645 ps
T856 /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3678235259 Jan 21 03:21:20 PM PST 24 Jan 21 03:21:25 PM PST 24 52988662 ps
T857 /workspace/coverage/default/31.gpio_full_random.369308861 Jan 21 03:23:41 PM PST 24 Jan 21 03:23:42 PM PST 24 86785857 ps
T858 /workspace/coverage/default/39.gpio_stress_all.1896330100 Jan 21 03:24:38 PM PST 24 Jan 21 03:25:25 PM PST 24 3604803803 ps
T859 /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1423185294 Jan 21 03:21:24 PM PST 24 Jan 21 03:45:34 PM PST 24 326556844464 ps
T860 /workspace/coverage/default/18.gpio_stress_all.2543152505 Jan 21 03:22:14 PM PST 24 Jan 21 03:24:53 PM PST 24 22653784186 ps
T861 /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.282380984 Jan 21 03:23:25 PM PST 24 Jan 21 03:23:26 PM PST 24 102468141 ps
T862 /workspace/coverage/default/3.gpio_full_random.2220997194 Jan 21 03:20:37 PM PST 24 Jan 21 03:20:39 PM PST 24 231196174 ps
T863 /workspace/coverage/default/4.gpio_rand_intr_trigger.1703941517 Jan 21 03:20:39 PM PST 24 Jan 21 03:20:44 PM PST 24 89394476 ps
T864 /workspace/coverage/default/12.gpio_alert_test.3237887029 Jan 21 03:21:27 PM PST 24 Jan 21 03:21:33 PM PST 24 43040697 ps
T865 /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2947304126 Jan 21 03:21:27 PM PST 24 Jan 21 03:41:29 PM PST 24 168461918310 ps
T866 /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1664373597 Jan 21 03:22:23 PM PST 24 Jan 21 03:22:25 PM PST 24 301623441 ps
T867 /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1976223864 Jan 21 03:21:03 PM PST 24 Jan 21 03:21:16 PM PST 24 415248411 ps
T868 /workspace/coverage/default/29.gpio_random_dout_din.1568313656 Jan 21 03:23:27 PM PST 24 Jan 21 03:23:29 PM PST 24 110917500 ps
T869 /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1264101608 Jan 21 03:21:54 PM PST 24 Jan 21 03:22:00 PM PST 24 54383597 ps
T870 /workspace/coverage/default/47.gpio_random_dout_din.1501254373 Jan 21 03:25:27 PM PST 24 Jan 21 03:25:29 PM PST 24 30751299 ps
T871 /workspace/coverage/default/20.gpio_full_random.2877636804 Jan 21 03:22:23 PM PST 24 Jan 21 03:22:25 PM PST 24 74120735 ps
T872 /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1518489582 Jan 21 03:23:26 PM PST 24 Jan 21 03:23:33 PM PST 24 508762210 ps
T873 /workspace/coverage/default/8.gpio_smoke.3578252649 Jan 21 03:21:02 PM PST 24 Jan 21 03:21:11 PM PST 24 58281137 ps
T874 /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.217295489 Jan 21 03:24:59 PM PST 24 Jan 21 03:25:02 PM PST 24 21479319 ps
T875 /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.268539287 Jan 21 03:23:11 PM PST 24 Jan 21 03:30:52 PM PST 24 142216780152 ps
T876 /workspace/coverage/default/5.gpio_full_random.321280242 Jan 21 03:20:37 PM PST 24 Jan 21 03:20:39 PM PST 24 46467478 ps
T877 /workspace/coverage/default/10.gpio_stress_all.112322719 Jan 21 03:21:06 PM PST 24 Jan 21 03:22:54 PM PST 24 14148141045 ps
T878 /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.834347007 Jan 21 03:24:14 PM PST 24 Jan 21 03:26:44 PM PST 24 10079039079 ps
T879 /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.393940397 Jan 21 03:23:05 PM PST 24 Jan 21 03:23:07 PM PST 24 200185340 ps
T880 /workspace/coverage/default/8.gpio_rand_intr_trigger.3627928027 Jan 21 03:21:00 PM PST 24 Jan 21 03:21:12 PM PST 24 186752019 ps
T881 /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2237800806 Jan 21 03:24:11 PM PST 24 Jan 21 03:24:18 PM PST 24 46929541 ps
T882 /workspace/coverage/default/40.gpio_filter_stress.3304424621 Jan 21 03:46:53 PM PST 24 Jan 21 03:47:23 PM PST 24 914493793 ps
T883 /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1382087442 Jan 21 03:24:02 PM PST 24 Jan 21 03:24:06 PM PST 24 122496105 ps
T884 /workspace/coverage/default/11.gpio_random_dout_din.2239528163 Jan 21 03:21:19 PM PST 24 Jan 21 03:21:23 PM PST 24 389200774 ps
T885 /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1413658479 Jan 21 03:23:05 PM PST 24 Jan 21 04:02:15 PM PST 24 104558781783 ps
T886 /workspace/coverage/default/12.gpio_random_dout_din.1141467981 Jan 21 03:21:25 PM PST 24 Jan 21 03:21:31 PM PST 24 18446027 ps
T93 /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3437567799 Jan 21 03:25:04 PM PST 24 Jan 21 03:25:07 PM PST 24 29875591 ps
T887 /workspace/coverage/default/13.gpio_rand_intr_trigger.3135986179 Jan 21 03:21:34 PM PST 24 Jan 21 03:21:53 PM PST 24 153269432 ps
T888 /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.676119877 Jan 21 03:21:00 PM PST 24 Jan 21 03:21:12 PM PST 24 323265122 ps
T889 /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3793743100 Jan 21 03:21:54 PM PST 24 Jan 21 03:22:00 PM PST 24 30564350 ps
T890 /workspace/coverage/default/32.gpio_rand_intr_trigger.590864868 Jan 21 04:33:43 PM PST 24 Jan 21 04:33:46 PM PST 24 157970720 ps
T891 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3791441319 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:31 PM PST 24 41330416 ps
T892 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2157833150 Jan 21 09:05:59 PM PST 24 Jan 21 09:06:32 PM PST 24 11095259 ps
T109 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2242272870 Jan 21 09:06:01 PM PST 24 Jan 21 09:06:36 PM PST 24 35394990 ps
T893 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3242741181 Jan 21 09:05:41 PM PST 24 Jan 21 09:06:02 PM PST 24 23082498 ps
T894 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.872418204 Jan 21 09:05:03 PM PST 24 Jan 21 09:05:10 PM PST 24 52819934 ps
T895 /workspace/coverage/cover_reg_top/41.gpio_intr_test.701695916 Jan 21 09:06:00 PM PST 24 Jan 21 09:06:34 PM PST 24 55490972 ps
T896 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2799596745 Jan 21 09:04:45 PM PST 24 Jan 21 09:04:51 PM PST 24 176845335 ps
T897 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.686473514 Jan 21 09:04:44 PM PST 24 Jan 21 09:04:47 PM PST 24 25060380 ps
T115 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2978625999 Jan 21 09:05:04 PM PST 24 Jan 21 09:05:10 PM PST 24 165151631 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.604631379 Jan 21 09:04:47 PM PST 24 Jan 21 09:04:53 PM PST 24 316187310 ps
T898 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.542149340 Jan 21 09:04:57 PM PST 24 Jan 21 09:05:04 PM PST 24 19220053 ps
T899 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3784596688 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:31 PM PST 24 84882409 ps
T82 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2073384498 Jan 21 09:05:16 PM PST 24 Jan 21 09:05:21 PM PST 24 17406918 ps
T900 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1597188919 Jan 21 09:06:11 PM PST 24 Jan 21 09:06:46 PM PST 24 13158915 ps
T901 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2514264079 Jan 21 09:04:46 PM PST 24 Jan 21 09:04:50 PM PST 24 64671948 ps
T902 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2711126752 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:33 PM PST 24 551499908 ps
T903 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3439926853 Jan 21 09:05:56 PM PST 24 Jan 21 09:06:29 PM PST 24 318177926 ps
T904 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2427716009 Jan 21 09:05:57 PM PST 24 Jan 21 09:06:30 PM PST 24 69573919 ps
T905 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2467837930 Jan 21 09:04:57 PM PST 24 Jan 21 09:05:04 PM PST 24 25306398 ps
T906 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1799392462 Jan 21 09:05:57 PM PST 24 Jan 21 09:06:32 PM PST 24 578393946 ps
T907 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.818534170 Jan 21 09:04:56 PM PST 24 Jan 21 09:05:03 PM PST 24 18661433 ps
T908 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3623838902 Jan 21 09:05:24 PM PST 24 Jan 21 09:05:31 PM PST 24 38151337 ps
T102 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2075364984 Jan 21 09:05:27 PM PST 24 Jan 21 09:05:31 PM PST 24 67573582 ps
T909 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3820283950 Jan 21 09:05:27 PM PST 24 Jan 21 09:05:33 PM PST 24 158119019 ps
T910 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2404936392 Jan 21 09:05:04 PM PST 24 Jan 21 09:05:09 PM PST 24 23737187 ps
T911 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2038465209 Jan 21 09:05:37 PM PST 24 Jan 21 09:05:45 PM PST 24 33839326 ps
T912 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1616856057 Jan 21 09:05:04 PM PST 24 Jan 21 09:05:10 PM PST 24 90764144 ps
T913 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4287042111 Jan 21 09:05:41 PM PST 24 Jan 21 09:06:02 PM PST 24 16916013 ps
T914 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1270203188 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:31 PM PST 24 14046897 ps
T915 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.158556642 Jan 21 09:04:47 PM PST 24 Jan 21 09:04:54 PM PST 24 991790545 ps
T916 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1659497195 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:32 PM PST 24 34496212 ps
T917 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.21098645 Jan 21 09:04:46 PM PST 24 Jan 21 09:04:50 PM PST 24 15308951 ps
T918 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1381482255 Jan 21 09:06:00 PM PST 24 Jan 21 09:06:34 PM PST 24 25033057 ps
T919 /workspace/coverage/cover_reg_top/17.gpio_intr_test.608948481 Jan 21 09:05:57 PM PST 24 Jan 21 09:06:31 PM PST 24 30522524 ps
T920 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1575437135 Jan 21 09:05:04 PM PST 24 Jan 21 09:05:09 PM PST 24 17262350 ps
T921 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3958539473 Jan 21 09:04:44 PM PST 24 Jan 21 09:04:46 PM PST 24 178579787 ps
T922 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2482807888 Jan 21 09:05:28 PM PST 24 Jan 21 09:05:33 PM PST 24 41618296 ps
T923 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3179005995 Jan 21 09:05:33 PM PST 24 Jan 21 09:05:38 PM PST 24 41359180 ps
T924 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2045806218 Jan 21 09:05:59 PM PST 24 Jan 21 09:06:33 PM PST 24 30723539 ps
T925 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4096761526 Jan 21 09:05:44 PM PST 24 Jan 21 09:06:09 PM PST 24 137603051 ps
T926 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3300685973 Jan 21 09:05:56 PM PST 24 Jan 21 09:06:30 PM PST 24 104485418 ps
T927 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1612527627 Jan 21 09:04:45 PM PST 24 Jan 21 09:04:48 PM PST 24 325318671 ps
T928 /workspace/coverage/cover_reg_top/18.gpio_intr_test.4141416980 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:31 PM PST 24 14129823 ps
T929 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1433717508 Jan 21 09:04:58 PM PST 24 Jan 21 09:05:06 PM PST 24 461601458 ps
T930 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3111523257 Jan 21 09:05:28 PM PST 24 Jan 21 09:05:33 PM PST 24 53573844 ps
T89 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1347526177 Jan 21 09:04:51 PM PST 24 Jan 21 09:04:56 PM PST 24 12684892 ps
T931 /workspace/coverage/cover_reg_top/22.gpio_intr_test.4169805631 Jan 21 09:06:00 PM PST 24 Jan 21 09:06:35 PM PST 24 45937811 ps
T932 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.6595557 Jan 21 09:05:18 PM PST 24 Jan 21 09:05:26 PM PST 24 67198322 ps
T933 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1721242504 Jan 21 09:05:19 PM PST 24 Jan 21 09:05:28 PM PST 24 143230122 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1744206408 Jan 21 09:04:53 PM PST 24 Jan 21 09:05:00 PM PST 24 33720861 ps
T83 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.423538179 Jan 21 09:05:17 PM PST 24 Jan 21 09:05:24 PM PST 24 111700324 ps
T91 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4234232384 Jan 21 09:05:39 PM PST 24 Jan 21 09:05:56 PM PST 24 59026678 ps
T934 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2459468933 Jan 21 09:05:57 PM PST 24 Jan 21 09:06:30 PM PST 24 22062963 ps
T935 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.63157750 Jan 21 09:05:39 PM PST 24 Jan 21 09:05:57 PM PST 24 597804751 ps
T936 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2415676505 Jan 21 09:05:36 PM PST 24 Jan 21 09:05:41 PM PST 24 27664166 ps
T937 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2440103615 Jan 21 09:05:21 PM PST 24 Jan 21 09:05:28 PM PST 24 42711930 ps
T938 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.409901285 Jan 21 09:05:03 PM PST 24 Jan 21 09:05:10 PM PST 24 81154866 ps
T939 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1823858843 Jan 21 09:05:20 PM PST 24 Jan 21 09:05:27 PM PST 24 14403768 ps
T940 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.662669268 Jan 21 09:04:56 PM PST 24 Jan 21 09:05:04 PM PST 24 16205659 ps
T941 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.324826800 Jan 21 09:05:50 PM PST 24 Jan 21 09:06:18 PM PST 24 18782471 ps
T33 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1309174214 Jan 21 09:05:01 PM PST 24 Jan 21 09:05:08 PM PST 24 308459254 ps
T942 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2231972682 Jan 21 09:06:01 PM PST 24 Jan 21 09:06:36 PM PST 24 41364590 ps
T943 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.574376902 Jan 21 09:04:56 PM PST 24 Jan 21 09:05:03 PM PST 24 25879299 ps
T944 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3849312573 Jan 21 09:06:11 PM PST 24 Jan 21 09:06:46 PM PST 24 24670681 ps
T945 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1940422960 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:31 PM PST 24 14444768 ps
T946 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2104118363 Jan 21 09:04:43 PM PST 24 Jan 21 09:04:46 PM PST 24 22676534 ps
T947 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.10697814 Jan 21 09:04:49 PM PST 24 Jan 21 09:04:53 PM PST 24 116945436 ps
T103 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4230984051 Jan 21 09:04:45 PM PST 24 Jan 21 09:04:49 PM PST 24 21461830 ps
T948 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3619667576 Jan 21 09:04:44 PM PST 24 Jan 21 09:04:47 PM PST 24 22035923 ps
T949 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2461719447 Jan 21 09:04:58 PM PST 24 Jan 21 09:05:05 PM PST 24 19267311 ps
T92 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.667292372 Jan 21 09:05:00 PM PST 24 Jan 21 09:05:07 PM PST 24 61665177 ps
T950 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1455549883 Jan 21 09:06:11 PM PST 24 Jan 21 09:06:46 PM PST 24 16866373 ps
T951 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3152241478 Jan 21 09:05:43 PM PST 24 Jan 21 09:06:08 PM PST 24 40734559 ps
T952 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1448029195 Jan 21 09:04:43 PM PST 24 Jan 21 09:04:46 PM PST 24 254110054 ps
T953 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3399281660 Jan 21 09:04:56 PM PST 24 Jan 21 09:05:03 PM PST 24 117249601 ps
T36 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1832945607 Jan 21 09:05:43 PM PST 24 Jan 21 09:06:08 PM PST 24 388913970 ps
T954 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3699769322 Jan 21 09:04:55 PM PST 24 Jan 21 09:05:02 PM PST 24 29714341 ps
T955 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1211569468 Jan 21 09:05:37 PM PST 24 Jan 21 09:05:45 PM PST 24 417825086 ps
T37 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4261303252 Jan 21 09:05:26 PM PST 24 Jan 21 09:05:32 PM PST 24 455324703 ps
T956 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3886626545 Jan 21 09:20:25 PM PST 24 Jan 21 09:20:28 PM PST 24 31773029 ps
T957 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1060637077 Jan 21 09:05:55 PM PST 24 Jan 21 09:06:30 PM PST 24 59772068 ps
T958 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2552366282 Jan 21 09:05:38 PM PST 24 Jan 21 09:05:53 PM PST 24 1148177159 ps
T959 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2902720118 Jan 21 09:05:56 PM PST 24 Jan 21 09:06:31 PM PST 24 216904069 ps
T960 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3408586458 Jan 21 09:05:18 PM PST 24 Jan 21 09:05:24 PM PST 24 41690209 ps
T961 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2327842305 Jan 21 09:06:12 PM PST 24 Jan 21 09:06:46 PM PST 24 15732869 ps
T962 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2798097017 Jan 21 09:05:25 PM PST 24 Jan 21 09:05:30 PM PST 24 25881470 ps
T963 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.791357035 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:32 PM PST 24 270888310 ps
T964 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2313262172 Jan 21 09:04:58 PM PST 24 Jan 21 09:05:05 PM PST 24 46160961 ps
T38 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1770345172 Jan 21 09:05:41 PM PST 24 Jan 21 09:06:01 PM PST 24 295922547 ps
T965 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2213630020 Jan 21 09:05:19 PM PST 24 Jan 21 09:05:27 PM PST 24 466515960 ps
T966 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3133426373 Jan 21 09:06:11 PM PST 24 Jan 21 09:06:46 PM PST 24 74248270 ps
T967 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4016423413 Jan 21 09:05:58 PM PST 24 Jan 21 09:06:31 PM PST 24 24145719 ps
T968 /workspace/coverage/cover_reg_top/12.gpio_intr_test.329037696 Jan 21 09:05:42 PM PST 24 Jan 21 09:06:05 PM PST 24 29529674 ps
T969 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3242066108 Jan 21 09:05:19 PM PST 24 Jan 21 09:05:27 PM PST 24 51094887 ps
T970 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2541952194 Jan 21 09:05:02 PM PST 24 Jan 21 09:05:08 PM PST 24 34142454 ps

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1513841962
Short name T22
Test name
Test status
Simulation time 184561642 ps
CPU time 0.91 seconds
Started Jan 21 09:04:45 PM PST 24
Finished Jan 21 09:04:49 PM PST 24
Peak memory 198108 kb
Host smart-6def3e1d-926c-4fb5-afa9-d64e900273c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513841962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1513841962
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.728290658
Short name T55
Test name
Test status
Simulation time 71609168 ps
CPU time 1.11 seconds
Started Jan 21 08:56:08 PM PST 24
Finished Jan 21 08:56:42 PM PST 24
Peak memory 191240 kb
Host smart-9b160b62-8777-43d0-b22d-472d2bb05a33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=728290658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.728290658
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2430600470
Short name T43
Test name
Test status
Simulation time 90192246 ps
CPU time 3.5 seconds
Started Jan 21 03:23:58 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 196560 kb
Host smart-28824421-cc13-45fb-b368-211c4d084d10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430600470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2430600470
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2610813937
Short name T51
Test name
Test status
Simulation time 107799742358 ps
CPU time 144.78 seconds
Started Jan 21 03:21:25 PM PST 24
Finished Jan 21 03:23:56 PM PST 24
Peak memory 198248 kb
Host smart-7447fc71-0314-4fc0-a793-14e1c44bff1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610813937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2610813937
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.197960889
Short name T2
Test name
Test status
Simulation time 154583072 ps
CPU time 1.2 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:11 PM PST 24
Peak memory 198260 kb
Host smart-7745b9fb-2124-4efa-a0d9-f2e307b96aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197960889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.197960889
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2094822439
Short name T12
Test name
Test status
Simulation time 1389422569 ps
CPU time 1.35 seconds
Started Jan 21 09:05:34 PM PST 24
Finished Jan 21 09:05:39 PM PST 24
Peak memory 198324 kb
Host smart-edc94caf-2efd-4e09-a85d-dbbfedb72eba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094822439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2094822439
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2678593558
Short name T4
Test name
Test status
Simulation time 555369449 ps
CPU time 3.32 seconds
Started Jan 21 09:05:00 PM PST 24
Finished Jan 21 09:05:10 PM PST 24
Peak memory 197072 kb
Host smart-e1a2d8fa-ca21-4cd1-89ed-110b974dc1e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678593558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2678593558
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3884215699
Short name T34
Test name
Test status
Simulation time 2112788462 ps
CPU time 3.18 seconds
Started Jan 21 09:05:40 PM PST 24
Finished Jan 21 09:06:02 PM PST 24
Peak memory 198300 kb
Host smart-d14388e8-ac48-411a-b98b-11249a33f9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884215699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3884215699
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3884451889
Short name T17
Test name
Test status
Simulation time 24241912 ps
CPU time 0.6 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 193952 kb
Host smart-0cdfa199-5836-4049-958f-aff2fa489415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884451889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3884451889
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.88203600
Short name T28
Test name
Test status
Simulation time 254127323 ps
CPU time 0.89 seconds
Started Jan 21 03:44:24 PM PST 24
Finished Jan 21 03:44:26 PM PST 24
Peak memory 213640 kb
Host smart-c9c25ff0-f02f-4964-a4c6-6b84045d9fd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88203600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.88203600
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1680301850
Short name T349
Test name
Test status
Simulation time 34634132 ps
CPU time 0.62 seconds
Started Jan 21 03:21:24 PM PST 24
Finished Jan 21 03:21:31 PM PST 24
Peak memory 194700 kb
Host smart-760d8bbc-9623-4323-bcc5-7461de8ea723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680301850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1680301850
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3480159487
Short name T143
Test name
Test status
Simulation time 42277972 ps
CPU time 1.24 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191384 kb
Host smart-d028d41d-76ac-4b1a-9fb9-4a83c39ab2cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3480159487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3480159487
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2234746633
Short name T75
Test name
Test status
Simulation time 24745427 ps
CPU time 0.89 seconds
Started Jan 21 09:05:22 PM PST 24
Finished Jan 21 09:05:28 PM PST 24
Peak memory 197680 kb
Host smart-456e29af-bb5c-4980-a1d9-8ecf9a3d489c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234746633 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2234746633
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3919800292
Short name T78
Test name
Test status
Simulation time 37081530 ps
CPU time 0.9 seconds
Started Jan 21 09:04:49 PM PST 24
Finished Jan 21 09:04:52 PM PST 24
Peak memory 196384 kb
Host smart-cec41951-a58c-4b02-a102-d5f825132899
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919800292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3919800292
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1832945607
Short name T36
Test name
Test status
Simulation time 388913970 ps
CPU time 1.46 seconds
Started Jan 21 09:05:43 PM PST 24
Finished Jan 21 09:06:08 PM PST 24
Peak memory 198292 kb
Host smart-35b96c5d-5c66-4f37-ab64-b04de89543a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832945607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1832945607
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3920751034
Short name T70
Test name
Test status
Simulation time 75474165967 ps
CPU time 896.58 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:36:56 PM PST 24
Peak memory 198336 kb
Host smart-4fb150f4-b338-4a94-a96f-b1912cc37094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3920751034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3920751034
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1044426504
Short name T116
Test name
Test status
Simulation time 15423263 ps
CPU time 0.66 seconds
Started Jan 21 09:04:45 PM PST 24
Finished Jan 21 09:04:49 PM PST 24
Peak memory 194640 kb
Host smart-fe501bf8-d25b-4020-8d19-78a8565666e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044426504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1044426504
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2795599393
Short name T3
Test name
Test status
Simulation time 126519826 ps
CPU time 1.18 seconds
Started Jan 21 09:05:40 PM PST 24
Finished Jan 21 09:05:58 PM PST 24
Peak memory 198292 kb
Host smart-0590c6cb-e314-402f-8782-3db52b82bda7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795599393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2795599393
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1974501377
Short name T133
Test name
Test status
Simulation time 112645262 ps
CPU time 1.46 seconds
Started Jan 21 09:04:51 PM PST 24
Finished Jan 21 09:04:57 PM PST 24
Peak memory 198236 kb
Host smart-e7b23d73-7ec6-4224-b686-b3564df3c586
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974501377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1974501377
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.466348373
Short name T125
Test name
Test status
Simulation time 36415649 ps
CPU time 0.64 seconds
Started Jan 21 09:05:42 PM PST 24
Finished Jan 21 09:06:05 PM PST 24
Peak memory 194576 kb
Host smart-ccd63bb5-2b24-4ed8-a973-53fbe9d019d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466348373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.466348373
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.852761526
Short name T1
Test name
Test status
Simulation time 114363995 ps
CPU time 0.77 seconds
Started Jan 21 09:04:43 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 196564 kb
Host smart-eb4ad275-42fe-4ab1-9fee-c0080cd49df1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852761526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.852761526
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2799596745
Short name T896
Test name
Test status
Simulation time 176845335 ps
CPU time 2.46 seconds
Started Jan 21 09:04:45 PM PST 24
Finished Jan 21 09:04:51 PM PST 24
Peak memory 198264 kb
Host smart-eae95fa2-aa64-4527-801d-5af97e0179eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799596745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2799596745
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2514264079
Short name T901
Test name
Test status
Simulation time 64671948 ps
CPU time 0.72 seconds
Started Jan 21 09:04:46 PM PST 24
Finished Jan 21 09:04:50 PM PST 24
Peak memory 195344 kb
Host smart-0180d7cf-6e00-46ab-ae71-b32d1ce84b33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514264079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2514264079
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1612527627
Short name T927
Test name
Test status
Simulation time 325318671 ps
CPU time 0.78 seconds
Started Jan 21 09:04:45 PM PST 24
Finished Jan 21 09:04:48 PM PST 24
Peak memory 198108 kb
Host smart-24981140-14ff-48df-95c3-99e4cb4353f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612527627 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1612527627
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.796145278
Short name T76
Test name
Test status
Simulation time 50619112 ps
CPU time 0.66 seconds
Started Jan 21 09:04:37 PM PST 24
Finished Jan 21 09:04:42 PM PST 24
Peak memory 194912 kb
Host smart-f48c46a5-c1f0-41c4-bbb7-82efe7805b5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796145278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.796145278
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2494607471
Short name T108
Test name
Test status
Simulation time 47783105 ps
CPU time 0.61 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:47 PM PST 24
Peak memory 195064 kb
Host smart-9eee7ec7-f5c3-489a-89bd-865e5dec3307
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494607471 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2494607471
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3907659180
Short name T88
Test name
Test status
Simulation time 95627837 ps
CPU time 1.01 seconds
Started Jan 21 09:04:52 PM PST 24
Finished Jan 21 09:04:59 PM PST 24
Peak memory 198036 kb
Host smart-b5556887-3640-4ea9-be42-8adfc1495524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907659180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3907659180
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1448029195
Short name T952
Test name
Test status
Simulation time 254110054 ps
CPU time 1.14 seconds
Started Jan 21 09:04:43 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 198244 kb
Host smart-0740ac3d-e4d8-485d-be54-c98a4192c568
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448029195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1448029195
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.604631379
Short name T81
Test name
Test status
Simulation time 316187310 ps
CPU time 3.15 seconds
Started Jan 21 09:04:47 PM PST 24
Finished Jan 21 09:04:53 PM PST 24
Peak memory 198244 kb
Host smart-621e3aab-59e0-4973-8cd7-332fbc1738e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604631379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.604631379
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1152081788
Short name T14
Test name
Test status
Simulation time 42707388 ps
CPU time 0.67 seconds
Started Jan 21 09:04:45 PM PST 24
Finished Jan 21 09:04:48 PM PST 24
Peak memory 194988 kb
Host smart-dffb6300-d655-445a-9e98-81d2ac4838fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152081788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1152081788
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2761455847
Short name T18
Test name
Test status
Simulation time 28031060 ps
CPU time 1.38 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:47 PM PST 24
Peak memory 198320 kb
Host smart-a7750e37-f975-46f1-9035-d9afa72081c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761455847 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2761455847
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2104118363
Short name T946
Test name
Test status
Simulation time 22676534 ps
CPU time 0.59 seconds
Started Jan 21 09:04:43 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 194964 kb
Host smart-cc0f2e8c-c670-41c2-b7e7-f5c500e0f461
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104118363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2104118363
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3619667576
Short name T948
Test name
Test status
Simulation time 22035923 ps
CPU time 0.58 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:47 PM PST 24
Peak memory 193912 kb
Host smart-c2a0b2aa-082d-429a-83f9-8974de6defd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619667576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3619667576
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.686473514
Short name T897
Test name
Test status
Simulation time 25060380 ps
CPU time 0.75 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:47 PM PST 24
Peak memory 196932 kb
Host smart-dd7df00e-d810-47aa-bf46-8ab0085bb77a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686473514 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.686473514
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2865596893
Short name T11
Test name
Test status
Simulation time 153420906 ps
CPU time 1.22 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:48 PM PST 24
Peak memory 198304 kb
Host smart-5f2d0512-60d5-4506-b574-551da2619aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865596893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2865596893
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2038465209
Short name T911
Test name
Test status
Simulation time 33839326 ps
CPU time 1.04 seconds
Started Jan 21 09:05:37 PM PST 24
Finished Jan 21 09:05:45 PM PST 24
Peak memory 198052 kb
Host smart-65c55a9c-b75f-43c5-a0c3-284bf75d58f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038465209 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2038465209
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.423538179
Short name T83
Test name
Test status
Simulation time 111700324 ps
CPU time 0.69 seconds
Started Jan 21 09:05:17 PM PST 24
Finished Jan 21 09:05:24 PM PST 24
Peak memory 195768 kb
Host smart-a27e533a-7444-4c3e-bffc-9e8773984bc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423538179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.423538179
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3111523257
Short name T930
Test name
Test status
Simulation time 53573844 ps
CPU time 0.62 seconds
Started Jan 21 09:05:28 PM PST 24
Finished Jan 21 09:05:33 PM PST 24
Peak memory 194036 kb
Host smart-1270a1e0-719e-43a4-902d-fa6169077f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111523257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3111523257
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.962511870
Short name T16
Test name
Test status
Simulation time 50883734 ps
CPU time 0.73 seconds
Started Jan 21 09:05:33 PM PST 24
Finished Jan 21 09:05:37 PM PST 24
Peak memory 195176 kb
Host smart-57287e57-097b-4d84-b8e5-c1d11c8daad8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962511870 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.962511870
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3820283950
Short name T909
Test name
Test status
Simulation time 158119019 ps
CPU time 2.47 seconds
Started Jan 21 09:05:27 PM PST 24
Finished Jan 21 09:05:33 PM PST 24
Peak memory 198260 kb
Host smart-824a8f81-daf1-4eb0-8ea2-c36b366caba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820283950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3820283950
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4261303252
Short name T37
Test name
Test status
Simulation time 455324703 ps
CPU time 1.42 seconds
Started Jan 21 09:05:26 PM PST 24
Finished Jan 21 09:05:32 PM PST 24
Peak memory 198320 kb
Host smart-06f6799d-0300-4f06-846e-90917c3373c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261303252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4261303252
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1040954222
Short name T120
Test name
Test status
Simulation time 97877111 ps
CPU time 0.97 seconds
Started Jan 21 09:05:37 PM PST 24
Finished Jan 21 09:05:45 PM PST 24
Peak memory 198116 kb
Host smart-9ef3b160-29bc-4d3d-9d0b-f4e743ebb80f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040954222 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1040954222
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2075364984
Short name T102
Test name
Test status
Simulation time 67573582 ps
CPU time 0.67 seconds
Started Jan 21 09:05:27 PM PST 24
Finished Jan 21 09:05:31 PM PST 24
Peak memory 195088 kb
Host smart-ebb9d157-8b42-4d4b-97c2-ec1f6d0edea8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075364984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2075364984
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2415676505
Short name T936
Test name
Test status
Simulation time 27664166 ps
CPU time 0.58 seconds
Started Jan 21 09:05:36 PM PST 24
Finished Jan 21 09:05:41 PM PST 24
Peak memory 193872 kb
Host smart-6357728b-3b79-484c-b0d1-4881df86b0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415676505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2415676505
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2482807888
Short name T922
Test name
Test status
Simulation time 41618296 ps
CPU time 0.85 seconds
Started Jan 21 09:05:28 PM PST 24
Finished Jan 21 09:05:33 PM PST 24
Peak memory 196656 kb
Host smart-4d815823-671b-4faf-b40f-95d4a6c705b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482807888 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2482807888
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3179005995
Short name T923
Test name
Test status
Simulation time 41359180 ps
CPU time 1.19 seconds
Started Jan 21 09:05:33 PM PST 24
Finished Jan 21 09:05:38 PM PST 24
Peak memory 198244 kb
Host smart-dd4fe2ce-beea-4732-bb91-ffdbd425eca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179005995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3179005995
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3717773217
Short name T124
Test name
Test status
Simulation time 34846872 ps
CPU time 1.72 seconds
Started Jan 21 09:05:29 PM PST 24
Finished Jan 21 09:05:35 PM PST 24
Peak memory 198288 kb
Host smart-bdf8dd6c-9de8-4fb7-8cf9-05dbca1aa3b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717773217 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3717773217
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2849539377
Short name T7
Test name
Test status
Simulation time 14924186 ps
CPU time 0.59 seconds
Started Jan 21 09:05:28 PM PST 24
Finished Jan 21 09:05:32 PM PST 24
Peak memory 193508 kb
Host smart-a8e4591b-66c6-481d-ae40-90eeb6badcb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849539377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2849539377
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.329037696
Short name T968
Test name
Test status
Simulation time 29529674 ps
CPU time 0.6 seconds
Started Jan 21 09:05:42 PM PST 24
Finished Jan 21 09:06:05 PM PST 24
Peak memory 193932 kb
Host smart-49aca80d-0818-4013-a5dc-ab3ec61aa1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329037696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.329037696
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2798097017
Short name T962
Test name
Test status
Simulation time 25881470 ps
CPU time 0.76 seconds
Started Jan 21 09:05:25 PM PST 24
Finished Jan 21 09:05:30 PM PST 24
Peak memory 197044 kb
Host smart-f7dd3e5f-5ba2-429f-9332-c28fe938a98c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798097017 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2798097017
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.486917920
Short name T137
Test name
Test status
Simulation time 139028394 ps
CPU time 2.88 seconds
Started Jan 21 09:05:40 PM PST 24
Finished Jan 21 09:05:59 PM PST 24
Peak memory 198308 kb
Host smart-3779d400-e597-442d-a822-04847512ef89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486917920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.486917920
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1211569468
Short name T955
Test name
Test status
Simulation time 417825086 ps
CPU time 1.26 seconds
Started Jan 21 09:05:37 PM PST 24
Finished Jan 21 09:05:45 PM PST 24
Peak memory 198288 kb
Host smart-90cce222-7794-4a9b-9e12-3608f8e6294e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211569468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1211569468
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3152241478
Short name T951
Test name
Test status
Simulation time 40734559 ps
CPU time 0.82 seconds
Started Jan 21 09:05:43 PM PST 24
Finished Jan 21 09:06:08 PM PST 24
Peak memory 198064 kb
Host smart-a8d93d98-d886-481a-8b11-58330a21005a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152241478 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3152241478
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4234232384
Short name T91
Test name
Test status
Simulation time 59026678 ps
CPU time 0.63 seconds
Started Jan 21 09:05:39 PM PST 24
Finished Jan 21 09:05:56 PM PST 24
Peak memory 195068 kb
Host smart-5e1c5129-cbb9-4c8a-ac96-5dd5b0b06f4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234232384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4234232384
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.4198189614
Short name T132
Test name
Test status
Simulation time 22698770 ps
CPU time 0.62 seconds
Started Jan 21 09:05:45 PM PST 24
Finished Jan 21 09:06:13 PM PST 24
Peak memory 193948 kb
Host smart-fc966902-20d1-44b6-babe-b00fc068dff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198189614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.4198189614
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.904745868
Short name T20
Test name
Test status
Simulation time 77029181 ps
CPU time 0.9 seconds
Started Jan 21 09:05:43 PM PST 24
Finished Jan 21 09:06:08 PM PST 24
Peak memory 196748 kb
Host smart-85f89970-0727-46a3-a384-82a8e39f237b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904745868 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.904745868
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.398189943
Short name T130
Test name
Test status
Simulation time 164615359 ps
CPU time 0.84 seconds
Started Jan 21 09:05:45 PM PST 24
Finished Jan 21 09:06:16 PM PST 24
Peak memory 198060 kb
Host smart-4bfc1187-1ee3-4967-81ff-c5faba4a8557
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398189943 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.398189943
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1717862940
Short name T15
Test name
Test status
Simulation time 51848292 ps
CPU time 0.6 seconds
Started Jan 21 09:05:42 PM PST 24
Finished Jan 21 09:06:05 PM PST 24
Peak memory 194800 kb
Host smart-34400230-675b-4e2b-be40-21f1dfc18680
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717862940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1717862940
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3703601388
Short name T23
Test name
Test status
Simulation time 33354783 ps
CPU time 0.82 seconds
Started Jan 21 09:05:41 PM PST 24
Finished Jan 21 09:06:02 PM PST 24
Peak memory 196892 kb
Host smart-c580d9b2-5a64-49ba-a965-cecf8b6c5613
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703601388 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3703601388
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.63157750
Short name T935
Test name
Test status
Simulation time 597804751 ps
CPU time 2.34 seconds
Started Jan 21 09:05:39 PM PST 24
Finished Jan 21 09:05:57 PM PST 24
Peak memory 198296 kb
Host smart-af8385dc-326d-4d6e-b778-e9075f10f42d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63157750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.63157750
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1770345172
Short name T38
Test name
Test status
Simulation time 295922547 ps
CPU time 1.14 seconds
Started Jan 21 09:05:41 PM PST 24
Finished Jan 21 09:06:01 PM PST 24
Peak memory 198284 kb
Host smart-d31ce0d3-fabd-4055-a3b9-73a60ce8f1e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770345172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1770345172
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3691597735
Short name T39
Test name
Test status
Simulation time 22158697 ps
CPU time 1.1 seconds
Started Jan 21 09:05:44 PM PST 24
Finished Jan 21 09:06:09 PM PST 24
Peak memory 198084 kb
Host smart-708d8683-f8f3-42b7-aec4-b28efaf542c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691597735 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3691597735
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2270626765
Short name T77
Test name
Test status
Simulation time 23153117 ps
CPU time 0.61 seconds
Started Jan 21 09:05:40 PM PST 24
Finished Jan 21 09:05:58 PM PST 24
Peak memory 195020 kb
Host smart-404301a6-0732-45e7-a3ae-319ca68ed7b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270626765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2270626765
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4287042111
Short name T913
Test name
Test status
Simulation time 16916013 ps
CPU time 0.61 seconds
Started Jan 21 09:05:41 PM PST 24
Finished Jan 21 09:06:02 PM PST 24
Peak memory 193884 kb
Host smart-4e6a441c-66ce-4bd4-ac70-4f36df84cd26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287042111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4287042111
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.919324453
Short name T105
Test name
Test status
Simulation time 51963646 ps
CPU time 0.79 seconds
Started Jan 21 09:05:45 PM PST 24
Finished Jan 21 09:06:15 PM PST 24
Peak memory 197120 kb
Host smart-de419e88-402b-4cab-b704-30e4a3f47f0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919324453 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.919324453
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2552366282
Short name T958
Test name
Test status
Simulation time 1148177159 ps
CPU time 2.19 seconds
Started Jan 21 09:05:38 PM PST 24
Finished Jan 21 09:05:53 PM PST 24
Peak memory 198276 kb
Host smart-62b0fd59-fa7b-476c-85c7-454cfb876b18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552366282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2552366282
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3941991963
Short name T26
Test name
Test status
Simulation time 364678243 ps
CPU time 1.41 seconds
Started Jan 21 09:05:45 PM PST 24
Finished Jan 21 09:06:16 PM PST 24
Peak memory 198256 kb
Host smart-ccdb29d6-d94a-45d7-a347-1e10947ac007
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941991963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3941991963
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3242741181
Short name T893
Test name
Test status
Simulation time 23082498 ps
CPU time 1.2 seconds
Started Jan 21 09:05:41 PM PST 24
Finished Jan 21 09:06:02 PM PST 24
Peak memory 198116 kb
Host smart-fc0e6d9c-4612-4f03-87d1-b9552a3bb12c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242741181 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3242741181
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3292166804
Short name T119
Test name
Test status
Simulation time 14176752 ps
CPU time 0.63 seconds
Started Jan 21 09:05:45 PM PST 24
Finished Jan 21 09:06:15 PM PST 24
Peak memory 195640 kb
Host smart-b12961ee-4732-4396-bed8-466741d20866
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292166804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3292166804
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1940422960
Short name T945
Test name
Test status
Simulation time 14444768 ps
CPU time 0.64 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 193996 kb
Host smart-ed38a3fc-b186-44e9-a977-267c8859efdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940422960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1940422960
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4096761526
Short name T925
Test name
Test status
Simulation time 137603051 ps
CPU time 0.84 seconds
Started Jan 21 09:05:44 PM PST 24
Finished Jan 21 09:06:09 PM PST 24
Peak memory 197108 kb
Host smart-51cc18e7-6d2e-459c-ae90-baa86fa0df34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096761526 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4096761526
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1060637077
Short name T957
Test name
Test status
Simulation time 59772068 ps
CPU time 1.98 seconds
Started Jan 21 09:05:55 PM PST 24
Finished Jan 21 09:06:30 PM PST 24
Peak memory 198304 kb
Host smart-295979e6-80a1-4df2-970b-bdd35a60a8f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060637077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1060637077
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.324826800
Short name T941
Test name
Test status
Simulation time 18782471 ps
CPU time 0.72 seconds
Started Jan 21 09:05:50 PM PST 24
Finished Jan 21 09:06:18 PM PST 24
Peak memory 198136 kb
Host smart-b12def48-cfd7-4f49-9806-bc06d6ed0559
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324826800 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.324826800
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3643302830
Short name T138
Test name
Test status
Simulation time 12614331 ps
CPU time 0.6 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 193544 kb
Host smart-ff41ae0e-0ade-4b83-b9fe-dd258befd48b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643302830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3643302830
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.608948481
Short name T919
Test name
Test status
Simulation time 30522524 ps
CPU time 0.6 seconds
Started Jan 21 09:05:57 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 194204 kb
Host smart-5f70b6f1-afcb-4778-9a21-01f8542a0bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608948481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.608948481
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2242272870
Short name T109
Test name
Test status
Simulation time 35394990 ps
CPU time 0.83 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 196680 kb
Host smart-ccecbb07-53ff-4695-89a8-ff0bb950d302
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242272870 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2242272870
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2902720118
Short name T959
Test name
Test status
Simulation time 216904069 ps
CPU time 2.32 seconds
Started Jan 21 09:05:56 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 198212 kb
Host smart-8c1a309f-8266-41ca-b8d9-d1f0a1fc3c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902720118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2902720118
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.791357035
Short name T963
Test name
Test status
Simulation time 270888310 ps
CPU time 1.14 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:32 PM PST 24
Peak memory 197948 kb
Host smart-53043079-072e-4e40-8e73-f95a972beb87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791357035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.791357035
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3439926853
Short name T903
Test name
Test status
Simulation time 318177926 ps
CPU time 0.93 seconds
Started Jan 21 09:05:56 PM PST 24
Finished Jan 21 09:06:29 PM PST 24
Peak memory 198152 kb
Host smart-5dec59eb-c08d-44ca-bf13-f4b506dfefe6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439926853 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3439926853
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2941060579
Short name T10
Test name
Test status
Simulation time 15503934 ps
CPU time 0.64 seconds
Started Jan 21 09:05:52 PM PST 24
Finished Jan 21 09:06:21 PM PST 24
Peak memory 195736 kb
Host smart-7b57e3d8-24e2-40b0-a32f-dc44a22c30d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941060579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2941060579
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4141416980
Short name T928
Test name
Test status
Simulation time 14129823 ps
CPU time 0.66 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 193956 kb
Host smart-af1b4cde-1bc1-47c9-a1fb-2846d19da019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141416980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4141416980
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2427716009
Short name T904
Test name
Test status
Simulation time 69573919 ps
CPU time 0.89 seconds
Started Jan 21 09:05:57 PM PST 24
Finished Jan 21 09:06:30 PM PST 24
Peak memory 197260 kb
Host smart-8b9399b4-bbae-4991-ad10-5de72ea5a8da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427716009 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2427716009
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2711126752
Short name T902
Test name
Test status
Simulation time 551499908 ps
CPU time 2.76 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:33 PM PST 24
Peak memory 198332 kb
Host smart-4c186690-4e12-4a1c-b8c0-117ce4435933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711126752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2711126752
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3784596688
Short name T899
Test name
Test status
Simulation time 84882409 ps
CPU time 0.87 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 198152 kb
Host smart-0bb844fb-4196-4623-84c9-04f148f0d631
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784596688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3784596688
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3300685973
Short name T926
Test name
Test status
Simulation time 104485418 ps
CPU time 0.9 seconds
Started Jan 21 09:05:56 PM PST 24
Finished Jan 21 09:06:30 PM PST 24
Peak memory 198172 kb
Host smart-51092809-d9f7-4bf3-a869-72e7d8d2fd46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300685973 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3300685973
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1381482255
Short name T918
Test name
Test status
Simulation time 25033057 ps
CPU time 0.58 seconds
Started Jan 21 09:06:00 PM PST 24
Finished Jan 21 09:06:34 PM PST 24
Peak memory 193552 kb
Host smart-834cb0be-ce29-452a-918d-a89d6d2e67c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381482255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1381482255
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3207719368
Short name T85
Test name
Test status
Simulation time 22980582 ps
CPU time 0.63 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 193928 kb
Host smart-0d21899d-e24d-45b8-8155-ba61e8b04392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207719368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3207719368
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4016423413
Short name T967
Test name
Test status
Simulation time 24145719 ps
CPU time 0.75 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 197016 kb
Host smart-16a90ac9-5fac-4375-bbf0-a24177415104
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016423413 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.4016423413
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1799392462
Short name T906
Test name
Test status
Simulation time 578393946 ps
CPU time 2.72 seconds
Started Jan 21 09:05:57 PM PST 24
Finished Jan 21 09:06:32 PM PST 24
Peak memory 198264 kb
Host smart-4289d029-3de2-4fc4-9034-d02398a3cd7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799392462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1799392462
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1543398924
Short name T114
Test name
Test status
Simulation time 555699645 ps
CPU time 1.09 seconds
Started Jan 21 09:05:52 PM PST 24
Finished Jan 21 09:06:21 PM PST 24
Peak memory 198264 kb
Host smart-bcd184fa-92c7-458c-bdc5-90d70d59f110
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543398924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1543398924
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4230984051
Short name T103
Test name
Test status
Simulation time 21461830 ps
CPU time 0.68 seconds
Started Jan 21 09:04:45 PM PST 24
Finished Jan 21 09:04:49 PM PST 24
Peak memory 194916 kb
Host smart-ecaa498b-c47e-4f43-add2-c34bcb8ab4bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230984051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4230984051
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.158556642
Short name T915
Test name
Test status
Simulation time 991790545 ps
CPU time 3.43 seconds
Started Jan 21 09:04:47 PM PST 24
Finished Jan 21 09:04:54 PM PST 24
Peak memory 198252 kb
Host smart-2d148ae3-2fa4-43ed-a873-0f777fa9eb2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158556642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.158556642
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3958539473
Short name T921
Test name
Test status
Simulation time 178579787 ps
CPU time 0.58 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 195552 kb
Host smart-f0a549c8-f56a-4840-bd03-df621962055a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958539473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3958539473
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.21098645
Short name T917
Test name
Test status
Simulation time 15308951 ps
CPU time 0.7 seconds
Started Jan 21 09:04:46 PM PST 24
Finished Jan 21 09:04:50 PM PST 24
Peak memory 197996 kb
Host smart-9e24cf1f-0865-4535-b448-96aeae448ccd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21098645 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.21098645
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1347526177
Short name T89
Test name
Test status
Simulation time 12684892 ps
CPU time 0.6 seconds
Started Jan 21 09:04:51 PM PST 24
Finished Jan 21 09:04:56 PM PST 24
Peak memory 194996 kb
Host smart-07b8420a-5b00-4dc2-9de6-5f82d2d86f93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347526177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1347526177
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2074290855
Short name T131
Test name
Test status
Simulation time 14429339 ps
CPU time 0.62 seconds
Started Jan 21 09:04:44 PM PST 24
Finished Jan 21 09:04:46 PM PST 24
Peak memory 194028 kb
Host smart-132eed53-9c4a-4d45-822f-aaed5a912c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074290855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2074290855
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.173706879
Short name T106
Test name
Test status
Simulation time 41562326 ps
CPU time 0.7 seconds
Started Jan 21 09:04:51 PM PST 24
Finished Jan 21 09:04:56 PM PST 24
Peak memory 194652 kb
Host smart-65bf8ac9-41af-4b6b-9cad-819f163c3d63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173706879 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.173706879
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.10697814
Short name T947
Test name
Test status
Simulation time 116945436 ps
CPU time 1.79 seconds
Started Jan 21 09:04:49 PM PST 24
Finished Jan 21 09:04:53 PM PST 24
Peak memory 198276 kb
Host smart-c845c864-a236-47f7-849d-3b3c35c28eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10697814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.10697814
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2422044228
Short name T21
Test name
Test status
Simulation time 49364719 ps
CPU time 0.57 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 194108 kb
Host smart-678abfcc-3e57-4671-840c-4b48f4c0f416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422044228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2422044228
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3791441319
Short name T891
Test name
Test status
Simulation time 41330416 ps
CPU time 0.6 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 194512 kb
Host smart-7e81ec6e-cab3-499b-b1a2-0cb3d269be8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791441319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3791441319
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4169805631
Short name T931
Test name
Test status
Simulation time 45937811 ps
CPU time 0.59 seconds
Started Jan 21 09:06:00 PM PST 24
Finished Jan 21 09:06:35 PM PST 24
Peak memory 194032 kb
Host smart-319f2c64-236c-4135-8eb3-42d7e9d49fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169805631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4169805631
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2045806218
Short name T924
Test name
Test status
Simulation time 30723539 ps
CPU time 0.64 seconds
Started Jan 21 09:05:59 PM PST 24
Finished Jan 21 09:06:33 PM PST 24
Peak memory 194016 kb
Host smart-eab5f681-530a-4a26-9ef9-500cc800abe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045806218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2045806218
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3934840395
Short name T135
Test name
Test status
Simulation time 43942770 ps
CPU time 0.61 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 194528 kb
Host smart-e55f984e-cc1c-419c-9c0e-88674f98ebca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934840395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3934840395
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.755562868
Short name T139
Test name
Test status
Simulation time 70793030 ps
CPU time 0.61 seconds
Started Jan 21 09:05:56 PM PST 24
Finished Jan 21 09:06:29 PM PST 24
Peak memory 194560 kb
Host smart-4b03e125-fdff-40cb-8394-8ba39d4122c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755562868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.755562868
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2459468933
Short name T934
Test name
Test status
Simulation time 22062963 ps
CPU time 0.59 seconds
Started Jan 21 09:05:57 PM PST 24
Finished Jan 21 09:06:30 PM PST 24
Peak memory 194648 kb
Host smart-e3262eb9-3e5a-4e6b-909e-a824320e96db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459468933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2459468933
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.368981789
Short name T110
Test name
Test status
Simulation time 14586555 ps
CPU time 0.58 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 193872 kb
Host smart-1bcf5a54-dcd6-467b-a91d-f67ac4254b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368981789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.368981789
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1659497195
Short name T916
Test name
Test status
Simulation time 34496212 ps
CPU time 0.57 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:32 PM PST 24
Peak memory 194536 kb
Host smart-ac6ff67b-c8e0-4686-8267-9888213a7383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659497195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1659497195
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4127428856
Short name T134
Test name
Test status
Simulation time 46471105 ps
CPU time 0.58 seconds
Started Jan 21 09:06:02 PM PST 24
Finished Jan 21 09:06:37 PM PST 24
Peak memory 193964 kb
Host smart-5c23f558-711e-4e63-b8cf-a218cfd346e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127428856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4127428856
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3399281660
Short name T953
Test name
Test status
Simulation time 117249601 ps
CPU time 0.86 seconds
Started Jan 21 09:04:56 PM PST 24
Finished Jan 21 09:05:03 PM PST 24
Peak memory 196404 kb
Host smart-b1feb997-0aa1-4848-9de8-7ffc9af8cbc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399281660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3399281660
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1154102812
Short name T31
Test name
Test status
Simulation time 68971880 ps
CPU time 0.65 seconds
Started Jan 21 09:04:54 PM PST 24
Finished Jan 21 09:05:01 PM PST 24
Peak memory 194632 kb
Host smart-883f2b41-96c0-4d30-97e1-5a5c820d9905
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154102812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1154102812
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3699769322
Short name T954
Test name
Test status
Simulation time 29714341 ps
CPU time 0.66 seconds
Started Jan 21 09:04:55 PM PST 24
Finished Jan 21 09:05:02 PM PST 24
Peak memory 196924 kb
Host smart-6614eb71-8b4e-40e5-b273-e58cf9bac223
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699769322 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3699769322
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.662669268
Short name T940
Test name
Test status
Simulation time 16205659 ps
CPU time 0.67 seconds
Started Jan 21 09:04:56 PM PST 24
Finished Jan 21 09:05:04 PM PST 24
Peak memory 195204 kb
Host smart-d2155d63-0143-4fb2-888b-ff9403dc8792
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662669268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.662669268
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3044572570
Short name T86
Test name
Test status
Simulation time 38043203 ps
CPU time 0.56 seconds
Started Jan 21 09:04:52 PM PST 24
Finished Jan 21 09:04:59 PM PST 24
Peak memory 193904 kb
Host smart-893079b6-e8f4-4607-bdf7-c746290438c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044572570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3044572570
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.574376902
Short name T943
Test name
Test status
Simulation time 25879299 ps
CPU time 0.74 seconds
Started Jan 21 09:04:56 PM PST 24
Finished Jan 21 09:05:03 PM PST 24
Peak memory 195344 kb
Host smart-dd6a5cee-0ef7-46bf-aeda-2cfbb1c3b839
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574376902 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.574376902
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.806124869
Short name T74
Test name
Test status
Simulation time 62576153 ps
CPU time 1.02 seconds
Started Jan 21 09:04:57 PM PST 24
Finished Jan 21 09:05:04 PM PST 24
Peak memory 198040 kb
Host smart-2f17e70a-617a-41f0-ac75-bf2e9241560d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806124869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.806124869
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1309174214
Short name T33
Test name
Test status
Simulation time 308459254 ps
CPU time 1.26 seconds
Started Jan 21 09:05:01 PM PST 24
Finished Jan 21 09:05:08 PM PST 24
Peak memory 198244 kb
Host smart-5b7d051a-79db-41f1-8c1e-19f0ddde461d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309174214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1309174214
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1597188919
Short name T900
Test name
Test status
Simulation time 13158915 ps
CPU time 0.61 seconds
Started Jan 21 09:06:11 PM PST 24
Finished Jan 21 09:06:46 PM PST 24
Peak memory 193940 kb
Host smart-ad89237d-8df7-41f6-bd8b-cbf41e11127c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597188919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1597188919
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2167998011
Short name T126
Test name
Test status
Simulation time 16963754 ps
CPU time 0.56 seconds
Started Jan 21 09:06:00 PM PST 24
Finished Jan 21 09:06:35 PM PST 24
Peak memory 193924 kb
Host smart-9f1df1dc-5812-4c73-9210-6900dd4118df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167998011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2167998011
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4232954816
Short name T127
Test name
Test status
Simulation time 31616735 ps
CPU time 0.56 seconds
Started Jan 21 09:06:06 PM PST 24
Finished Jan 21 09:06:41 PM PST 24
Peak memory 193920 kb
Host smart-9b9f2800-54ae-4406-8929-7d6073a42a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232954816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4232954816
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2327842305
Short name T961
Test name
Test status
Simulation time 15732869 ps
CPU time 0.63 seconds
Started Jan 21 09:06:12 PM PST 24
Finished Jan 21 09:06:46 PM PST 24
Peak memory 194000 kb
Host smart-32d88333-331f-42c1-b3ed-ef14e19d124a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327842305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2327842305
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1270203188
Short name T914
Test name
Test status
Simulation time 14046897 ps
CPU time 0.57 seconds
Started Jan 21 09:05:58 PM PST 24
Finished Jan 21 09:06:31 PM PST 24
Peak memory 194104 kb
Host smart-a2b7ece1-e23d-4d3e-8d81-ee88342a5b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270203188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1270203188
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1461261488
Short name T136
Test name
Test status
Simulation time 18992535 ps
CPU time 0.58 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 193828 kb
Host smart-1b0abf3c-9390-4f9b-9beb-811fe5624b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461261488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1461261488
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2061843669
Short name T25
Test name
Test status
Simulation time 15415224 ps
CPU time 0.59 seconds
Started Jan 21 09:05:57 PM PST 24
Finished Jan 21 09:06:30 PM PST 24
Peak memory 193940 kb
Host smart-40ad2c90-c3f3-489b-b77a-cb45a9eec0bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061843669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2061843669
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1318626914
Short name T117
Test name
Test status
Simulation time 13346257 ps
CPU time 0.59 seconds
Started Jan 21 09:06:00 PM PST 24
Finished Jan 21 09:06:35 PM PST 24
Peak memory 193860 kb
Host smart-b74211e6-1577-43cc-ac41-0ed295e08dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318626914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1318626914
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2615944819
Short name T87
Test name
Test status
Simulation time 12581353 ps
CPU time 0.58 seconds
Started Jan 21 09:06:00 PM PST 24
Finished Jan 21 09:06:34 PM PST 24
Peak memory 193960 kb
Host smart-1f040a2c-cbc9-4ea8-8aea-ce6b95908a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615944819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2615944819
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2380596582
Short name T111
Test name
Test status
Simulation time 11568715 ps
CPU time 0.59 seconds
Started Jan 21 09:06:02 PM PST 24
Finished Jan 21 09:06:37 PM PST 24
Peak memory 194560 kb
Host smart-70133611-1409-445c-aa61-f97f02415cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380596582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2380596582
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.667292372
Short name T92
Test name
Test status
Simulation time 61665177 ps
CPU time 0.88 seconds
Started Jan 21 09:05:00 PM PST 24
Finished Jan 21 09:05:07 PM PST 24
Peak memory 198008 kb
Host smart-5eb21e78-eae9-496c-be6a-e871f535a1f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667292372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.667292372
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1433717508
Short name T929
Test name
Test status
Simulation time 461601458 ps
CPU time 1.48 seconds
Started Jan 21 09:04:58 PM PST 24
Finished Jan 21 09:05:06 PM PST 24
Peak memory 198188 kb
Host smart-6b340400-ce48-40ef-9f7d-daf190e125da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433717508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1433717508
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.542149340
Short name T898
Test name
Test status
Simulation time 19220053 ps
CPU time 0.73 seconds
Started Jan 21 09:04:57 PM PST 24
Finished Jan 21 09:05:04 PM PST 24
Peak memory 195840 kb
Host smart-90f8205b-44b3-4edd-899b-9471dec8b6fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542149340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.542149340
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1031228241
Short name T24
Test name
Test status
Simulation time 31497601 ps
CPU time 0.93 seconds
Started Jan 21 09:04:57 PM PST 24
Finished Jan 21 09:05:04 PM PST 24
Peak memory 198052 kb
Host smart-bee7e473-d7e5-4b83-a734-ac6fea750b2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031228241 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1031228241
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1744206408
Short name T90
Test name
Test status
Simulation time 33720861 ps
CPU time 0.59 seconds
Started Jan 21 09:04:53 PM PST 24
Finished Jan 21 09:05:00 PM PST 24
Peak memory 194448 kb
Host smart-73ed79ea-e9b9-4a53-a1b8-8848cc18db0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744206408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1744206408
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2313262172
Short name T964
Test name
Test status
Simulation time 46160961 ps
CPU time 0.61 seconds
Started Jan 21 09:04:58 PM PST 24
Finished Jan 21 09:05:05 PM PST 24
Peak memory 193880 kb
Host smart-256d8237-0090-4f73-abaf-982425d6537e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313262172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2313262172
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2467837930
Short name T905
Test name
Test status
Simulation time 25306398 ps
CPU time 0.66 seconds
Started Jan 21 09:04:57 PM PST 24
Finished Jan 21 09:05:04 PM PST 24
Peak memory 195572 kb
Host smart-3a4a445f-9dbc-4de5-8cf6-0215ebf47363
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467837930 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2467837930
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.978781343
Short name T9
Test name
Test status
Simulation time 177266669 ps
CPU time 3 seconds
Started Jan 21 09:04:57 PM PST 24
Finished Jan 21 09:05:06 PM PST 24
Peak memory 198272 kb
Host smart-cadd9fb4-6fd9-4cff-98f0-bf015cbe9e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978781343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.978781343
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.158908042
Short name T13
Test name
Test status
Simulation time 2899717268 ps
CPU time 1.24 seconds
Started Jan 21 09:04:58 PM PST 24
Finished Jan 21 09:05:05 PM PST 24
Peak memory 198628 kb
Host smart-e064a814-feb2-4ec4-a148-92d50dd29e9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158908042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.158908042
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1455549883
Short name T950
Test name
Test status
Simulation time 16866373 ps
CPU time 0.66 seconds
Started Jan 21 09:06:11 PM PST 24
Finished Jan 21 09:06:46 PM PST 24
Peak memory 194008 kb
Host smart-a937e5cc-926f-4a85-8335-6627e274e1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455549883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1455549883
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.701695916
Short name T895
Test name
Test status
Simulation time 55490972 ps
CPU time 0.64 seconds
Started Jan 21 09:06:00 PM PST 24
Finished Jan 21 09:06:34 PM PST 24
Peak memory 193952 kb
Host smart-3a88c05e-9c07-4129-9376-9b37c9a5b219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701695916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.701695916
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2157833150
Short name T892
Test name
Test status
Simulation time 11095259 ps
CPU time 0.61 seconds
Started Jan 21 09:05:59 PM PST 24
Finished Jan 21 09:06:32 PM PST 24
Peak memory 194640 kb
Host smart-15e70b5d-3048-4534-ac1a-24cd42448412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157833150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2157833150
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4018169478
Short name T123
Test name
Test status
Simulation time 21012125 ps
CPU time 0.6 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 193968 kb
Host smart-4b17ca4d-464c-44af-8736-23cebff45547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018169478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4018169478
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3133426373
Short name T966
Test name
Test status
Simulation time 74248270 ps
CPU time 0.66 seconds
Started Jan 21 09:06:11 PM PST 24
Finished Jan 21 09:06:46 PM PST 24
Peak memory 193320 kb
Host smart-e17f66c1-8349-45ea-b42d-b9d62ccaba73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133426373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3133426373
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3886626545
Short name T956
Test name
Test status
Simulation time 31773029 ps
CPU time 0.57 seconds
Started Jan 21 09:20:25 PM PST 24
Finished Jan 21 09:20:28 PM PST 24
Peak memory 193964 kb
Host smart-c6696d11-3417-47ca-abf8-f1af4f1f21e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886626545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3886626545
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2231972682
Short name T942
Test name
Test status
Simulation time 41364590 ps
CPU time 0.6 seconds
Started Jan 21 09:06:01 PM PST 24
Finished Jan 21 09:06:36 PM PST 24
Peak memory 194020 kb
Host smart-1e873eeb-0ad8-454e-b5ac-982e81879957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231972682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2231972682
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.199576025
Short name T19
Test name
Test status
Simulation time 74264056 ps
CPU time 0.64 seconds
Started Jan 21 09:06:11 PM PST 24
Finished Jan 21 09:06:46 PM PST 24
Peak memory 193484 kb
Host smart-18dbf152-73fb-4bbb-ae22-016726c6097e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199576025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.199576025
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3849312573
Short name T944
Test name
Test status
Simulation time 24670681 ps
CPU time 0.6 seconds
Started Jan 21 09:06:11 PM PST 24
Finished Jan 21 09:06:46 PM PST 24
Peak memory 194576 kb
Host smart-53790699-b6d1-4796-81b6-7be53ce0ce3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849312573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3849312573
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2461719447
Short name T949
Test name
Test status
Simulation time 19267311 ps
CPU time 0.8 seconds
Started Jan 21 09:04:58 PM PST 24
Finished Jan 21 09:05:05 PM PST 24
Peak memory 198368 kb
Host smart-264d95f9-bc6b-46c8-8934-de184ebb7a09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461719447 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2461719447
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1684955204
Short name T84
Test name
Test status
Simulation time 15676718 ps
CPU time 0.64 seconds
Started Jan 21 09:04:59 PM PST 24
Finished Jan 21 09:05:06 PM PST 24
Peak memory 195216 kb
Host smart-eabeaaf7-e586-42b3-833b-f9d6eb6c9281
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684955204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1684955204
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.789854100
Short name T128
Test name
Test status
Simulation time 22043991 ps
CPU time 0.62 seconds
Started Jan 21 09:05:02 PM PST 24
Finished Jan 21 09:05:09 PM PST 24
Peak memory 193960 kb
Host smart-43e286dc-e8a3-4fe8-8db6-2362d24cbfb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789854100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.789854100
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.818534170
Short name T907
Test name
Test status
Simulation time 18661433 ps
CPU time 0.78 seconds
Started Jan 21 09:04:56 PM PST 24
Finished Jan 21 09:05:03 PM PST 24
Peak memory 196372 kb
Host smart-a46f4082-c7c7-401f-96dc-895ccfded6cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818534170 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.818534170
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.872418204
Short name T894
Test name
Test status
Simulation time 52819934 ps
CPU time 1.39 seconds
Started Jan 21 09:05:03 PM PST 24
Finished Jan 21 09:05:10 PM PST 24
Peak memory 198276 kb
Host smart-0a0cd4be-1c64-4e2a-ba89-ecf30328cc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872418204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.872418204
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2978625999
Short name T115
Test name
Test status
Simulation time 165151631 ps
CPU time 0.9 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:10 PM PST 24
Peak memory 197180 kb
Host smart-19179006-ecee-40cd-a4bb-3995e64f7baf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978625999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2978625999
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1575437135
Short name T920
Test name
Test status
Simulation time 17262350 ps
CPU time 0.67 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:09 PM PST 24
Peak memory 197012 kb
Host smart-0f09ad82-3145-4c91-9f93-a0c63bd87213
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575437135 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1575437135
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2541952194
Short name T970
Test name
Test status
Simulation time 34142454 ps
CPU time 0.65 seconds
Started Jan 21 09:05:02 PM PST 24
Finished Jan 21 09:05:08 PM PST 24
Peak memory 194728 kb
Host smart-5fc3fe13-17b3-4d0f-ac80-4ee937017977
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541952194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2541952194
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.60887818
Short name T118
Test name
Test status
Simulation time 26960630 ps
CPU time 0.6 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:09 PM PST 24
Peak memory 193876 kb
Host smart-ca755ddc-b579-49a2-aae3-d3f599522b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60887818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.60887818
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.409901285
Short name T938
Test name
Test status
Simulation time 81154866 ps
CPU time 0.84 seconds
Started Jan 21 09:05:03 PM PST 24
Finished Jan 21 09:05:10 PM PST 24
Peak memory 197588 kb
Host smart-f994b4d7-e19b-4a0a-9140-829a235ee2c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409901285 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.409901285
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3890262829
Short name T35
Test name
Test status
Simulation time 352156458 ps
CPU time 1.18 seconds
Started Jan 21 09:05:05 PM PST 24
Finished Jan 21 09:05:11 PM PST 24
Peak memory 198200 kb
Host smart-af6263f3-566c-4b6b-8d6b-ce19966441e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890262829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3890262829
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1616856057
Short name T912
Test name
Test status
Simulation time 90764144 ps
CPU time 0.86 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:10 PM PST 24
Peak memory 198096 kb
Host smart-04f53071-7f09-425d-bea2-9bb71e8c2884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616856057 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1616856057
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2404936392
Short name T910
Test name
Test status
Simulation time 23737187 ps
CPU time 0.61 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:09 PM PST 24
Peak memory 195680 kb
Host smart-6202659f-ce7c-4525-a98a-6488bbfb522e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404936392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2404936392
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3408586458
Short name T960
Test name
Test status
Simulation time 41690209 ps
CPU time 0.62 seconds
Started Jan 21 09:05:18 PM PST 24
Finished Jan 21 09:05:24 PM PST 24
Peak memory 193960 kb
Host smart-68b97b49-011f-4f7b-b0f3-bca68fdeec3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408586458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3408586458
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2135806384
Short name T8
Test name
Test status
Simulation time 56901845 ps
CPU time 0.82 seconds
Started Jan 21 09:05:05 PM PST 24
Finished Jan 21 09:05:11 PM PST 24
Peak memory 197088 kb
Host smart-a7feae7d-fb93-4338-987f-77347cc84902
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135806384 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2135806384
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.108183081
Short name T129
Test name
Test status
Simulation time 147560501 ps
CPU time 2.52 seconds
Started Jan 21 09:05:17 PM PST 24
Finished Jan 21 09:05:24 PM PST 24
Peak memory 198236 kb
Host smart-fbe7e682-59a1-4bd0-979f-0781115c1fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108183081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.108183081
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1123935404
Short name T6
Test name
Test status
Simulation time 383481251 ps
CPU time 1.23 seconds
Started Jan 21 09:05:04 PM PST 24
Finished Jan 21 09:05:11 PM PST 24
Peak memory 198260 kb
Host smart-5fac2bcf-272c-47c3-86b1-6e5443144911
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123935404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1123935404
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.6595557
Short name T932
Test name
Test status
Simulation time 67198322 ps
CPU time 0.89 seconds
Started Jan 21 09:05:18 PM PST 24
Finished Jan 21 09:05:26 PM PST 24
Peak memory 198116 kb
Host smart-19c4bffb-62a4-4809-b2bd-7ae64b144212
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6595557 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.6595557
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2073384498
Short name T82
Test name
Test status
Simulation time 17406918 ps
CPU time 0.61 seconds
Started Jan 21 09:05:16 PM PST 24
Finished Jan 21 09:05:21 PM PST 24
Peak memory 195156 kb
Host smart-dac80d75-8486-4436-b0ae-a17db7a4da42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073384498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2073384498
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3242066108
Short name T969
Test name
Test status
Simulation time 51094887 ps
CPU time 0.64 seconds
Started Jan 21 09:05:19 PM PST 24
Finished Jan 21 09:05:27 PM PST 24
Peak memory 193944 kb
Host smart-b769c407-faa2-4472-a281-8fb220a752af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242066108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3242066108
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3623838902
Short name T908
Test name
Test status
Simulation time 38151337 ps
CPU time 1.99 seconds
Started Jan 21 09:05:24 PM PST 24
Finished Jan 21 09:05:31 PM PST 24
Peak memory 198256 kb
Host smart-c0cb6ce3-7dbc-4136-b6e2-40cb3dd74b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623838902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3623838902
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2213630020
Short name T965
Test name
Test status
Simulation time 466515960 ps
CPU time 1.43 seconds
Started Jan 21 09:05:19 PM PST 24
Finished Jan 21 09:05:27 PM PST 24
Peak memory 198304 kb
Host smart-28e7e7d1-5fe7-4a14-88a4-6a77ede2c603
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213630020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2213630020
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1124043256
Short name T5
Test name
Test status
Simulation time 55892374 ps
CPU time 0.93 seconds
Started Jan 21 09:05:24 PM PST 24
Finished Jan 21 09:05:30 PM PST 24
Peak memory 198096 kb
Host smart-a5965fc8-9d9e-4f08-b08f-bf624e9f98b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124043256 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1124043256
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1823858843
Short name T939
Test name
Test status
Simulation time 14403768 ps
CPU time 0.62 seconds
Started Jan 21 09:05:20 PM PST 24
Finished Jan 21 09:05:27 PM PST 24
Peak memory 194632 kb
Host smart-2653ef97-7f56-461b-98bf-b92fc6175592
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823858843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1823858843
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2440103615
Short name T937
Test name
Test status
Simulation time 42711930 ps
CPU time 0.65 seconds
Started Jan 21 09:05:21 PM PST 24
Finished Jan 21 09:05:28 PM PST 24
Peak memory 193940 kb
Host smart-09ad5728-1236-4858-9ae6-adedf5c834ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440103615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2440103615
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4093555989
Short name T107
Test name
Test status
Simulation time 102636977 ps
CPU time 0.77 seconds
Started Jan 21 09:05:20 PM PST 24
Finished Jan 21 09:05:27 PM PST 24
Peak memory 196780 kb
Host smart-16b582cd-2ea1-4fe0-9653-920ca177c1f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093555989 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4093555989
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1721242504
Short name T933
Test name
Test status
Simulation time 143230122 ps
CPU time 2.09 seconds
Started Jan 21 09:05:19 PM PST 24
Finished Jan 21 09:05:28 PM PST 24
Peak memory 198284 kb
Host smart-ebb8b595-d1e4-4a21-92f1-5b0d663c1a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721242504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1721242504
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2379404478
Short name T30
Test name
Test status
Simulation time 150640427 ps
CPU time 1.23 seconds
Started Jan 21 09:05:22 PM PST 24
Finished Jan 21 09:05:29 PM PST 24
Peak memory 197836 kb
Host smart-7cf2d2fe-663f-4ef7-a3d5-d7b132928290
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379404478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2379404478
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4023823840
Short name T400
Test name
Test status
Simulation time 34708127 ps
CPU time 0.56 seconds
Started Jan 21 03:20:14 PM PST 24
Finished Jan 21 03:20:15 PM PST 24
Peak memory 194000 kb
Host smart-8461f514-7a1b-452d-a25c-22cf734243af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023823840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4023823840
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.13213008
Short name T558
Test name
Test status
Simulation time 31023216 ps
CPU time 0.93 seconds
Started Jan 21 03:20:05 PM PST 24
Finished Jan 21 03:20:07 PM PST 24
Peak memory 196852 kb
Host smart-dcd11e2b-b61a-4780-9d37-f84814214948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13213008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.13213008
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2273977533
Short name T763
Test name
Test status
Simulation time 1241914028 ps
CPU time 11.5 seconds
Started Jan 21 03:20:09 PM PST 24
Finished Jan 21 03:20:22 PM PST 24
Peak memory 197144 kb
Host smart-a7901541-ea3b-45d2-b3fd-b52b47febee1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273977533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2273977533
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1448475452
Short name T325
Test name
Test status
Simulation time 88798540 ps
CPU time 1.32 seconds
Started Jan 21 05:11:20 PM PST 24
Finished Jan 21 05:11:25 PM PST 24
Peak memory 197844 kb
Host smart-24e1344a-e009-4b51-a25c-6750059030ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448475452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1448475452
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3442621922
Short name T471
Test name
Test status
Simulation time 283265044 ps
CPU time 1.26 seconds
Started Jan 21 03:20:08 PM PST 24
Finished Jan 21 03:20:10 PM PST 24
Peak memory 196128 kb
Host smart-d12ec764-a888-45f0-b8c4-b958255eb9c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442621922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3442621922
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.423525276
Short name T595
Test name
Test status
Simulation time 146773214 ps
CPU time 1.57 seconds
Started Jan 21 03:20:10 PM PST 24
Finished Jan 21 03:20:13 PM PST 24
Peak memory 196904 kb
Host smart-ad2790a9-0e37-44bc-8b64-2d6de83b0f7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423525276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.423525276
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4250022567
Short name T391
Test name
Test status
Simulation time 59023260 ps
CPU time 1.12 seconds
Started Jan 21 03:20:09 PM PST 24
Finished Jan 21 03:20:11 PM PST 24
Peak memory 195876 kb
Host smart-9da908b7-8100-469b-8854-f780281a1706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250022567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4250022567
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4132365083
Short name T563
Test name
Test status
Simulation time 38789683 ps
CPU time 0.97 seconds
Started Jan 21 03:20:06 PM PST 24
Finished Jan 21 03:20:08 PM PST 24
Peak memory 196032 kb
Host smart-f771e133-b815-472e-87e8-a8b643b2bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132365083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4132365083
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.855152594
Short name T258
Test name
Test status
Simulation time 62224341 ps
CPU time 0.65 seconds
Started Jan 21 03:20:08 PM PST 24
Finished Jan 21 03:20:09 PM PST 24
Peak memory 194348 kb
Host smart-ff438b72-a985-4e19-aa16-8f4df0e68717
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855152594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.855152594
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1185580218
Short name T817
Test name
Test status
Simulation time 42211697 ps
CPU time 1.9 seconds
Started Jan 21 03:20:09 PM PST 24
Finished Jan 21 03:20:12 PM PST 24
Peak memory 198108 kb
Host smart-21c792a4-f25e-486e-b943-beeb4cd3421c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185580218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1185580218
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1990118152
Short name T398
Test name
Test status
Simulation time 238052530 ps
CPU time 1.12 seconds
Started Jan 21 03:20:06 PM PST 24
Finished Jan 21 03:20:08 PM PST 24
Peak memory 196352 kb
Host smart-b9edbc0a-0447-4b5f-8855-f1280091fb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990118152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1990118152
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1631910343
Short name T615
Test name
Test status
Simulation time 167117871 ps
CPU time 1.32 seconds
Started Jan 21 03:20:08 PM PST 24
Finished Jan 21 03:20:10 PM PST 24
Peak memory 197068 kb
Host smart-125ecd5f-d1a9-4ac4-bc6d-a521ccf68af5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631910343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1631910343
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3999156148
Short name T468
Test name
Test status
Simulation time 4327836677 ps
CPU time 67.63 seconds
Started Jan 21 03:38:32 PM PST 24
Finished Jan 21 03:39:41 PM PST 24
Peak memory 198292 kb
Host smart-3aec2373-ff3a-4cd9-9b1c-de3dc98badf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999156148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3999156148
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1861083408
Short name T642
Test name
Test status
Simulation time 417456585860 ps
CPU time 1118.98 seconds
Started Jan 21 03:20:08 PM PST 24
Finished Jan 21 03:38:48 PM PST 24
Peak memory 198344 kb
Host smart-71fcd232-241f-4fdc-9576-cff708fb4161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1861083408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1861083408
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3190855987
Short name T580
Test name
Test status
Simulation time 27219311 ps
CPU time 0.56 seconds
Started Jan 21 03:36:32 PM PST 24
Finished Jan 21 03:36:39 PM PST 24
Peak memory 193932 kb
Host smart-626c1aad-a2a0-4c1f-97a1-bf5ed25ae4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190855987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3190855987
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2444335477
Short name T505
Test name
Test status
Simulation time 167158290 ps
CPU time 0.84 seconds
Started Jan 21 03:20:38 PM PST 24
Finished Jan 21 03:20:40 PM PST 24
Peak memory 195368 kb
Host smart-038d47f8-e01e-4f82-aafc-d81f034b11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444335477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2444335477
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2216051576
Short name T334
Test name
Test status
Simulation time 2055967993 ps
CPU time 27.21 seconds
Started Jan 21 03:20:11 PM PST 24
Finished Jan 21 03:20:39 PM PST 24
Peak memory 197104 kb
Host smart-1a86c709-a278-49f0-ac4f-7a03fe7c9fcb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216051576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2216051576
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3856389082
Short name T416
Test name
Test status
Simulation time 159447117 ps
CPU time 0.85 seconds
Started Jan 21 03:47:32 PM PST 24
Finished Jan 21 03:47:34 PM PST 24
Peak memory 196880 kb
Host smart-6329a3c6-a9de-4aa0-b379-5970de357d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856389082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3856389082
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3810601638
Short name T310
Test name
Test status
Simulation time 104448692 ps
CPU time 0.88 seconds
Started Jan 21 03:20:21 PM PST 24
Finished Jan 21 03:20:23 PM PST 24
Peak memory 196880 kb
Host smart-fef6e6c7-c369-4b5a-8c1e-0b56b34cbb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810601638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3810601638
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.156860429
Short name T488
Test name
Test status
Simulation time 71369823 ps
CPU time 2.89 seconds
Started Jan 21 03:20:13 PM PST 24
Finished Jan 21 03:20:17 PM PST 24
Peak memory 198144 kb
Host smart-420101ff-1c8a-4dcb-8b74-d803a8cda5fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156860429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.156860429
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3107788670
Short name T529
Test name
Test status
Simulation time 55049894 ps
CPU time 1.45 seconds
Started Jan 21 03:28:37 PM PST 24
Finished Jan 21 03:28:39 PM PST 24
Peak memory 196116 kb
Host smart-e1fba92d-84d2-458f-91bb-1519e160ced3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107788670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3107788670
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2811814014
Short name T750
Test name
Test status
Simulation time 44643956 ps
CPU time 0.75 seconds
Started Jan 21 03:20:16 PM PST 24
Finished Jan 21 03:20:17 PM PST 24
Peak memory 195460 kb
Host smart-6ef7c177-2f27-43ef-89c0-53133f1dc4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811814014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2811814014
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.328256395
Short name T99
Test name
Test status
Simulation time 30287067 ps
CPU time 1.35 seconds
Started Jan 21 03:20:13 PM PST 24
Finished Jan 21 03:20:15 PM PST 24
Peak memory 196008 kb
Host smart-87add13c-c90c-4db7-9c90-23d4094803dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328256395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.328256395
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3112198406
Short name T396
Test name
Test status
Simulation time 283419836 ps
CPU time 4.13 seconds
Started Jan 21 03:20:20 PM PST 24
Finished Jan 21 03:20:26 PM PST 24
Peak memory 198092 kb
Host smart-6c64f9fb-54eb-4fcc-9d36-12884deef77f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112198406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3112198406
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3288479724
Short name T60
Test name
Test status
Simulation time 216596119 ps
CPU time 0.87 seconds
Started Jan 21 03:20:11 PM PST 24
Finished Jan 21 03:20:13 PM PST 24
Peak memory 213720 kb
Host smart-20f27a89-353a-443c-8a1d-8c2f436d4410
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288479724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3288479724
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2455009207
Short name T339
Test name
Test status
Simulation time 523736972 ps
CPU time 1.4 seconds
Started Jan 21 03:48:05 PM PST 24
Finished Jan 21 03:48:08 PM PST 24
Peak memory 195720 kb
Host smart-4b44d9a7-e259-4717-a80c-0a41de05263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455009207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2455009207
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1935047403
Short name T687
Test name
Test status
Simulation time 27654580 ps
CPU time 0.94 seconds
Started Jan 21 03:20:16 PM PST 24
Finished Jan 21 03:20:18 PM PST 24
Peak memory 195696 kb
Host smart-dc7b82bd-563a-479f-9363-31f32f66891e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935047403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1935047403
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1635860643
Short name T616
Test name
Test status
Simulation time 5230438384 ps
CPU time 127.93 seconds
Started Jan 21 03:36:21 PM PST 24
Finished Jan 21 03:38:30 PM PST 24
Peak memory 198348 kb
Host smart-42a24a8e-070d-410c-a500-25007ec859a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635860643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1635860643
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3679916153
Short name T783
Test name
Test status
Simulation time 204769683173 ps
CPU time 678.57 seconds
Started Jan 21 03:47:34 PM PST 24
Finished Jan 21 03:58:54 PM PST 24
Peak memory 198396 kb
Host smart-1e7f563b-d85f-4e93-8e48-b3976ec410f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3679916153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3679916153
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3559811435
Short name T729
Test name
Test status
Simulation time 13787409 ps
CPU time 0.58 seconds
Started Jan 21 03:21:19 PM PST 24
Finished Jan 21 03:21:20 PM PST 24
Peak memory 193980 kb
Host smart-c1ce4e38-1679-4ff7-a402-9b4ccb02830a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559811435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3559811435
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.158714410
Short name T435
Test name
Test status
Simulation time 48888920 ps
CPU time 0.75 seconds
Started Jan 21 03:35:12 PM PST 24
Finished Jan 21 03:35:15 PM PST 24
Peak memory 195364 kb
Host smart-acc3ea93-d6d1-4118-8a18-6421178c1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158714410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.158714410
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2644966881
Short name T233
Test name
Test status
Simulation time 199738519 ps
CPU time 10.62 seconds
Started Jan 21 03:21:10 PM PST 24
Finished Jan 21 03:21:25 PM PST 24
Peak memory 198088 kb
Host smart-65c164c9-690c-41ec-823a-766ed0e97275
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644966881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2644966881
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2376351281
Short name T566
Test name
Test status
Simulation time 49888072 ps
CPU time 0.81 seconds
Started Jan 21 03:21:09 PM PST 24
Finished Jan 21 03:21:13 PM PST 24
Peak memory 195876 kb
Host smart-f56b2678-435d-4c08-a460-260048061bfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376351281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2376351281
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3203673293
Short name T331
Test name
Test status
Simulation time 73818718 ps
CPU time 1.19 seconds
Started Jan 21 03:21:08 PM PST 24
Finished Jan 21 03:21:13 PM PST 24
Peak memory 196652 kb
Host smart-818da3a0-76ee-45ac-9470-dcd9fc8b391c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203673293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3203673293
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1937875015
Short name T122
Test name
Test status
Simulation time 453947610 ps
CPU time 2.44 seconds
Started Jan 21 03:31:41 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 196604 kb
Host smart-f43d2d24-fdbe-4458-8947-1e40203d6df7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937875015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1937875015
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2888504
Short name T789
Test name
Test status
Simulation time 276177822 ps
CPU time 0.91 seconds
Started Jan 21 03:36:46 PM PST 24
Finished Jan 21 03:36:48 PM PST 24
Peak memory 194548 kb
Host smart-c2639d46-a4f8-4215-9543-79891aed3950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.2888504
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3397206501
Short name T265
Test name
Test status
Simulation time 23973134 ps
CPU time 0.67 seconds
Started Jan 21 03:40:34 PM PST 24
Finished Jan 21 03:40:36 PM PST 24
Peak memory 194300 kb
Host smart-e88d0705-4202-490d-be60-d4531fc0540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397206501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3397206501
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2609232665
Short name T517
Test name
Test status
Simulation time 53481634 ps
CPU time 0.73 seconds
Started Jan 21 03:51:53 PM PST 24
Finished Jan 21 03:51:54 PM PST 24
Peak memory 195540 kb
Host smart-78ba7f2e-6736-462e-b9d9-7a8352d69499
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609232665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2609232665
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3224762370
Short name T359
Test name
Test status
Simulation time 435006975 ps
CPU time 2.22 seconds
Started Jan 21 03:21:05 PM PST 24
Finished Jan 21 03:21:12 PM PST 24
Peak memory 198024 kb
Host smart-9bf6238d-6745-4c92-8a46-1f57c701bceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224762370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3224762370
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.326780749
Short name T235
Test name
Test status
Simulation time 41156390 ps
CPU time 1.19 seconds
Started Jan 21 03:21:12 PM PST 24
Finished Jan 21 03:21:16 PM PST 24
Peak memory 196000 kb
Host smart-adedc5eb-6388-45f6-9c33-7acf4a1fa7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326780749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.326780749
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.635044147
Short name T665
Test name
Test status
Simulation time 202189594 ps
CPU time 1.11 seconds
Started Jan 21 03:39:25 PM PST 24
Finished Jan 21 03:39:29 PM PST 24
Peak memory 196016 kb
Host smart-9c46d29d-73af-463b-9829-bf868cba39ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635044147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.635044147
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.112322719
Short name T877
Test name
Test status
Simulation time 14148141045 ps
CPU time 103.64 seconds
Started Jan 21 03:21:06 PM PST 24
Finished Jan 21 03:22:54 PM PST 24
Peak memory 198248 kb
Host smart-6dced2cb-4539-4c25-b967-e751b477fd47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112322719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.112322719
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1105933046
Short name T621
Test name
Test status
Simulation time 28913757853 ps
CPU time 388.21 seconds
Started Jan 21 03:21:06 PM PST 24
Finished Jan 21 03:27:39 PM PST 24
Peak memory 198392 kb
Host smart-0dbbae38-804e-4ceb-b143-77ce61ce268f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1105933046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1105933046
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3754705557
Short name T816
Test name
Test status
Simulation time 43306818 ps
CPU time 0.74 seconds
Started Jan 21 03:21:18 PM PST 24
Finished Jan 21 03:21:20 PM PST 24
Peak memory 194240 kb
Host smart-16957928-2609-492c-b117-fd1f446a0999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754705557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3754705557
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1945854344
Short name T509
Test name
Test status
Simulation time 413254178 ps
CPU time 7.5 seconds
Started Jan 21 03:21:22 PM PST 24
Finished Jan 21 03:21:31 PM PST 24
Peak memory 198348 kb
Host smart-b13a7b94-ebaa-40a6-9e12-bcafa04d8177
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945854344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1945854344
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.4269407356
Short name T464
Test name
Test status
Simulation time 47817957 ps
CPU time 0.96 seconds
Started Jan 21 03:21:25 PM PST 24
Finished Jan 21 03:21:32 PM PST 24
Peak memory 196792 kb
Host smart-1c6a5cfa-0ec4-47e8-919f-b60daf70233e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269407356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4269407356
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.933600152
Short name T679
Test name
Test status
Simulation time 131813654 ps
CPU time 1.02 seconds
Started Jan 21 03:21:19 PM PST 24
Finished Jan 21 03:21:21 PM PST 24
Peak memory 196056 kb
Host smart-59043b11-4407-4dc2-9839-ba1a17f34a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933600152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.933600152
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3207262076
Short name T804
Test name
Test status
Simulation time 207728153 ps
CPU time 2.17 seconds
Started Jan 21 03:21:22 PM PST 24
Finished Jan 21 03:21:26 PM PST 24
Peak memory 198060 kb
Host smart-90242b82-2d68-423e-a18a-57305c6f0dec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207262076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3207262076
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3822079175
Short name T721
Test name
Test status
Simulation time 114508057 ps
CPU time 3.5 seconds
Started Jan 21 03:21:22 PM PST 24
Finished Jan 21 03:21:27 PM PST 24
Peak memory 197480 kb
Host smart-84dad2d8-5ddb-4eca-b8fa-c9cf3e1fe26e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822079175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3822079175
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2239528163
Short name T884
Test name
Test status
Simulation time 389200774 ps
CPU time 1.2 seconds
Started Jan 21 03:21:19 PM PST 24
Finished Jan 21 03:21:23 PM PST 24
Peak memory 196016 kb
Host smart-30ba59d1-2cc7-43ec-8d49-93762e0007b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239528163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2239528163
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.765350839
Short name T379
Test name
Test status
Simulation time 80293999 ps
CPU time 1.15 seconds
Started Jan 21 03:21:24 PM PST 24
Finished Jan 21 03:21:28 PM PST 24
Peak memory 196296 kb
Host smart-89e26f52-4f18-4226-8021-0ee44839c197
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765350839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.765350839
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3678235259
Short name T856
Test name
Test status
Simulation time 52988662 ps
CPU time 2.26 seconds
Started Jan 21 03:21:20 PM PST 24
Finished Jan 21 03:21:25 PM PST 24
Peak memory 198192 kb
Host smart-c1e79095-7552-46dd-b1df-05e01d8d94ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678235259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3678235259
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1348063759
Short name T361
Test name
Test status
Simulation time 133621376 ps
CPU time 1.22 seconds
Started Jan 21 03:21:20 PM PST 24
Finished Jan 21 03:21:23 PM PST 24
Peak memory 195828 kb
Host smart-f5e02ea3-5d87-4953-9845-b2a3f1b70a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348063759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1348063759
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3295530776
Short name T303
Test name
Test status
Simulation time 181592905 ps
CPU time 1.39 seconds
Started Jan 21 03:21:24 PM PST 24
Finished Jan 21 03:21:32 PM PST 24
Peak memory 198144 kb
Host smart-93dc6898-3716-4de1-a357-7c2e54eaeaf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295530776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3295530776
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1423185294
Short name T859
Test name
Test status
Simulation time 326556844464 ps
CPU time 1443.1 seconds
Started Jan 21 03:21:24 PM PST 24
Finished Jan 21 03:45:34 PM PST 24
Peak memory 198368 kb
Host smart-e4606271-0aed-4a5a-bc60-4039cf3cde68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1423185294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1423185294
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3237887029
Short name T864
Test name
Test status
Simulation time 43040697 ps
CPU time 0.56 seconds
Started Jan 21 03:21:27 PM PST 24
Finished Jan 21 03:21:33 PM PST 24
Peak memory 194000 kb
Host smart-5ec05d4c-d945-4b7d-8f46-407381f93930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237887029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3237887029
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3060736412
Short name T769
Test name
Test status
Simulation time 425797154 ps
CPU time 0.74 seconds
Started Jan 21 03:21:26 PM PST 24
Finished Jan 21 03:21:33 PM PST 24
Peak memory 195316 kb
Host smart-1932aea8-7be1-4b3f-9e0d-07c854e174a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060736412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3060736412
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2838931526
Short name T544
Test name
Test status
Simulation time 212847149 ps
CPU time 7.77 seconds
Started Jan 21 03:21:26 PM PST 24
Finished Jan 21 03:21:40 PM PST 24
Peak memory 196832 kb
Host smart-c9fa7671-cce7-485d-b1a1-17728c15a141
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838931526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2838931526
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2036554873
Short name T803
Test name
Test status
Simulation time 232204095 ps
CPU time 0.85 seconds
Started Jan 21 03:21:28 PM PST 24
Finished Jan 21 03:21:36 PM PST 24
Peak memory 196172 kb
Host smart-f1507b5c-d46e-4783-b058-152f62760cbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036554873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2036554873
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3081857656
Short name T253
Test name
Test status
Simulation time 391601265 ps
CPU time 1.49 seconds
Started Jan 21 03:21:27 PM PST 24
Finished Jan 21 03:21:34 PM PST 24
Peak memory 196980 kb
Host smart-3d11734c-b005-4e9b-a962-b5af1d7dbe6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081857656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3081857656
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2492524383
Short name T46
Test name
Test status
Simulation time 699382699 ps
CPU time 3.27 seconds
Started Jan 21 03:21:22 PM PST 24
Finished Jan 21 03:21:27 PM PST 24
Peak memory 198128 kb
Host smart-2a12e645-6919-4d1c-9d68-ece8849ea179
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492524383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2492524383
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3208142502
Short name T627
Test name
Test status
Simulation time 315442186 ps
CPU time 2.57 seconds
Started Jan 21 03:21:28 PM PST 24
Finished Jan 21 03:21:37 PM PST 24
Peak memory 197016 kb
Host smart-19c5df3a-e4bd-4a65-b9e4-f717b0e9ead2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208142502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3208142502
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1141467981
Short name T886
Test name
Test status
Simulation time 18446027 ps
CPU time 0.81 seconds
Started Jan 21 03:21:25 PM PST 24
Finished Jan 21 03:21:31 PM PST 24
Peak memory 196332 kb
Host smart-71902bd9-0a93-490d-ad2a-72a120e3f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141467981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1141467981
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3825458432
Short name T719
Test name
Test status
Simulation time 36661034 ps
CPU time 0.92 seconds
Started Jan 21 03:21:28 PM PST 24
Finished Jan 21 03:21:36 PM PST 24
Peak memory 196712 kb
Host smart-96c1abd5-3174-47f4-99f4-9fb3f07ce17a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825458432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3825458432
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1928618560
Short name T623
Test name
Test status
Simulation time 50274555 ps
CPU time 2.43 seconds
Started Jan 21 03:21:27 PM PST 24
Finished Jan 21 03:21:35 PM PST 24
Peak memory 198096 kb
Host smart-2a0d3e8f-8ab1-4341-924b-bc2252c502ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928618560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1928618560
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.962347606
Short name T252
Test name
Test status
Simulation time 37532094 ps
CPU time 1.06 seconds
Started Jan 21 03:21:26 PM PST 24
Finished Jan 21 03:21:33 PM PST 24
Peak memory 195836 kb
Host smart-a2ddd2d8-f707-4455-ad3d-f2aa96f15384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962347606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.962347606
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1184200080
Short name T369
Test name
Test status
Simulation time 341208988 ps
CPU time 1.39 seconds
Started Jan 21 03:21:24 PM PST 24
Finished Jan 21 03:21:32 PM PST 24
Peak memory 197284 kb
Host smart-57866919-a7d5-4071-a260-a43693f1ce22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184200080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1184200080
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.213412221
Short name T811
Test name
Test status
Simulation time 14006780574 ps
CPU time 143.32 seconds
Started Jan 21 03:21:34 PM PST 24
Finished Jan 21 03:24:12 PM PST 24
Peak memory 198268 kb
Host smart-78f0890e-8bb0-4719-994e-f6bcf4a3a2c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213412221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.213412221
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2947304126
Short name T865
Test name
Test status
Simulation time 168461918310 ps
CPU time 1194.83 seconds
Started Jan 21 03:21:27 PM PST 24
Finished Jan 21 03:41:29 PM PST 24
Peak memory 198432 kb
Host smart-a5669872-909c-42d5-8d86-68168a6de669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2947304126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2947304126
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1695710086
Short name T555
Test name
Test status
Simulation time 20237506 ps
CPU time 0.57 seconds
Started Jan 21 03:21:34 PM PST 24
Finished Jan 21 03:21:49 PM PST 24
Peak memory 194676 kb
Host smart-cd9986a0-ef9c-4d71-8b7c-cc6482b4d049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695710086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1695710086
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3769851787
Short name T364
Test name
Test status
Simulation time 140294237 ps
CPU time 0.75 seconds
Started Jan 21 03:21:33 PM PST 24
Finished Jan 21 03:21:49 PM PST 24
Peak memory 194908 kb
Host smart-0f2d2741-a713-4599-8767-0bd35bae36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769851787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3769851787
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.569044455
Short name T276
Test name
Test status
Simulation time 2225135457 ps
CPU time 14.3 seconds
Started Jan 21 03:21:35 PM PST 24
Finished Jan 21 03:22:06 PM PST 24
Peak memory 195840 kb
Host smart-62575f1c-f936-47a8-b985-06ccc9a9c6b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569044455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.569044455
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1670383560
Short name T596
Test name
Test status
Simulation time 56435269 ps
CPU time 0.69 seconds
Started Jan 21 03:29:58 PM PST 24
Finished Jan 21 03:30:08 PM PST 24
Peak memory 195360 kb
Host smart-1095ed67-9264-4b81-ac32-249aee177ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670383560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1670383560
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.403558556
Short name T461
Test name
Test status
Simulation time 55253998 ps
CPU time 1.13 seconds
Started Jan 21 03:21:34 PM PST 24
Finished Jan 21 03:21:51 PM PST 24
Peak memory 196064 kb
Host smart-cd7d594f-d533-4cd4-8338-9ab73791afa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403558556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.403558556
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.296502666
Short name T285
Test name
Test status
Simulation time 164714677 ps
CPU time 1.75 seconds
Started Jan 21 03:21:35 PM PST 24
Finished Jan 21 03:21:53 PM PST 24
Peak memory 198140 kb
Host smart-c335ffd8-d208-49d8-9dc4-e49454676584
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296502666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.296502666
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3135986179
Short name T887
Test name
Test status
Simulation time 153269432 ps
CPU time 3.37 seconds
Started Jan 21 03:21:34 PM PST 24
Finished Jan 21 03:21:53 PM PST 24
Peak memory 195904 kb
Host smart-80a21bc7-8239-4f76-bdec-3c89afdbc5bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135986179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3135986179
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2996871273
Short name T654
Test name
Test status
Simulation time 15677603 ps
CPU time 0.71 seconds
Started Jan 21 03:21:24 PM PST 24
Finished Jan 21 03:21:28 PM PST 24
Peak memory 195340 kb
Host smart-aa7cb3d7-ca79-419f-be33-7f46acaead24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996871273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2996871273
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3906231838
Short name T257
Test name
Test status
Simulation time 383434690 ps
CPU time 1.04 seconds
Started Jan 21 03:21:30 PM PST 24
Finished Jan 21 03:21:45 PM PST 24
Peak memory 195868 kb
Host smart-8f7713de-b05a-486a-bf26-70427326f219
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906231838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3906231838
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1345441351
Short name T790
Test name
Test status
Simulation time 2285775431 ps
CPU time 4.36 seconds
Started Jan 21 03:21:32 PM PST 24
Finished Jan 21 03:21:51 PM PST 24
Peak memory 198256 kb
Host smart-e6d5896b-a021-4b67-9f2f-5e9af0b81555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345441351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1345441351
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1065518844
Short name T522
Test name
Test status
Simulation time 93819653 ps
CPU time 1.44 seconds
Started Jan 21 03:21:30 PM PST 24
Finished Jan 21 03:21:46 PM PST 24
Peak memory 195608 kb
Host smart-1b377ce5-3839-48df-b81c-0770f8864ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065518844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1065518844
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1180394149
Short name T485
Test name
Test status
Simulation time 38951159 ps
CPU time 1.2 seconds
Started Jan 21 03:21:25 PM PST 24
Finished Jan 21 03:21:31 PM PST 24
Peak memory 198128 kb
Host smart-eab81130-23b4-4b76-b095-92d6397e23a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180394149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1180394149
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3005469604
Short name T734
Test name
Test status
Simulation time 2935319127 ps
CPU time 76.01 seconds
Started Jan 21 03:21:35 PM PST 24
Finished Jan 21 03:23:07 PM PST 24
Peak memory 198328 kb
Host smart-fadda5a9-e26d-4fa3-a35c-3be000a6804f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005469604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3005469604
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2346443927
Short name T510
Test name
Test status
Simulation time 118981966244 ps
CPU time 1551.73 seconds
Started Jan 21 03:21:33 PM PST 24
Finished Jan 21 03:47:40 PM PST 24
Peak memory 198336 kb
Host smart-ceb68e16-e7d7-42b0-b623-c9116ce9d90c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2346443927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2346443927
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3349341585
Short name T561
Test name
Test status
Simulation time 18093869 ps
CPU time 0.59 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 194132 kb
Host smart-79ff2537-dc2b-4740-b72b-bb7a41bc54fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349341585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3349341585
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1286495545
Short name T241
Test name
Test status
Simulation time 18079360 ps
CPU time 0.72 seconds
Started Jan 21 03:21:47 PM PST 24
Finished Jan 21 03:21:56 PM PST 24
Peak memory 194252 kb
Host smart-20b91482-c467-4151-bdc4-68ed4f8bfb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286495545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1286495545
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3358122068
Short name T367
Test name
Test status
Simulation time 198918070 ps
CPU time 10.8 seconds
Started Jan 21 03:21:42 PM PST 24
Finished Jan 21 03:22:03 PM PST 24
Peak memory 196704 kb
Host smart-fc88f73a-0422-4c76-86fd-bb1c234d0e5a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358122068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3358122068
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1760418067
Short name T701
Test name
Test status
Simulation time 74287919 ps
CPU time 0.63 seconds
Started Jan 21 03:21:45 PM PST 24
Finished Jan 21 03:21:54 PM PST 24
Peak memory 194524 kb
Host smart-a74e12b3-2df1-4fcf-8a66-e1c42cb20fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760418067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1760418067
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.169310687
Short name T259
Test name
Test status
Simulation time 49056288 ps
CPU time 0.76 seconds
Started Jan 21 03:21:45 PM PST 24
Finished Jan 21 03:21:54 PM PST 24
Peak memory 195452 kb
Host smart-233d0747-8ec4-455f-afbd-cb0d2bb091ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169310687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.169310687
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3538914609
Short name T338
Test name
Test status
Simulation time 78265666 ps
CPU time 3.06 seconds
Started Jan 21 03:21:44 PM PST 24
Finished Jan 21 03:21:56 PM PST 24
Peak memory 198040 kb
Host smart-b563e265-580d-4eca-9962-857d827b3603
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538914609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3538914609
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3993485601
Short name T498
Test name
Test status
Simulation time 383209518 ps
CPU time 2.39 seconds
Started Jan 21 03:21:44 PM PST 24
Finished Jan 21 03:21:56 PM PST 24
Peak memory 196976 kb
Host smart-08741b72-b9fe-4f49-ad25-2461cd5eacc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993485601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3993485601
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1043065598
Short name T32
Test name
Test status
Simulation time 82587956 ps
CPU time 0.7 seconds
Started Jan 21 03:21:48 PM PST 24
Finished Jan 21 03:21:57 PM PST 24
Peak memory 196076 kb
Host smart-11232321-530e-4465-bcb1-8ae37122f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043065598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1043065598
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2626211325
Short name T581
Test name
Test status
Simulation time 194860024 ps
CPU time 0.98 seconds
Started Jan 21 03:21:42 PM PST 24
Finished Jan 21 03:21:54 PM PST 24
Peak memory 196612 kb
Host smart-2c3f757d-631d-47ef-b824-9123dc8c34f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626211325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2626211325
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3924014402
Short name T524
Test name
Test status
Simulation time 272094830 ps
CPU time 2.53 seconds
Started Jan 21 03:21:45 PM PST 24
Finished Jan 21 03:21:56 PM PST 24
Peak memory 198172 kb
Host smart-a18ee36b-c517-460c-ad68-a4a4d22e5d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924014402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3924014402
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2869573368
Short name T853
Test name
Test status
Simulation time 266331821 ps
CPU time 1.23 seconds
Started Jan 21 03:21:35 PM PST 24
Finished Jan 21 03:21:52 PM PST 24
Peak memory 196748 kb
Host smart-cc1c4780-f30c-4458-a317-3ceaa961502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869573368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2869573368
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2872286120
Short name T697
Test name
Test status
Simulation time 57702909 ps
CPU time 1.06 seconds
Started Jan 21 04:02:29 PM PST 24
Finished Jan 21 04:02:39 PM PST 24
Peak memory 195816 kb
Host smart-8669f99e-95c0-456f-a75f-08a3a6ab2e3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872286120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2872286120
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1019576281
Short name T239
Test name
Test status
Simulation time 106312455603 ps
CPU time 157.09 seconds
Started Jan 21 03:21:44 PM PST 24
Finished Jan 21 03:24:30 PM PST 24
Peak memory 198328 kb
Host smart-a01c56f2-85d7-44a2-a577-2716ebd54cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019576281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1019576281
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3297511892
Short name T470
Test name
Test status
Simulation time 61271601310 ps
CPU time 1554.7 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:47:54 PM PST 24
Peak memory 198364 kb
Host smart-63bd8a94-40ca-4776-9d36-8478a65e434a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3297511892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3297511892
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2205368559
Short name T65
Test name
Test status
Simulation time 32031200 ps
CPU time 0.58 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 194020 kb
Host smart-e5079c24-39f1-4729-af5e-db80f6c2ba34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205368559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2205368559
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1054420483
Short name T741
Test name
Test status
Simulation time 18836823 ps
CPU time 0.65 seconds
Started Jan 21 03:22:02 PM PST 24
Finished Jan 21 03:22:06 PM PST 24
Peak memory 193976 kb
Host smart-3a86f43d-4325-4a90-bb3e-d9cf16668ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054420483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1054420483
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2616441908
Short name T652
Test name
Test status
Simulation time 627051124 ps
CPU time 16.44 seconds
Started Jan 21 03:21:53 PM PST 24
Finished Jan 21 03:22:15 PM PST 24
Peak memory 197052 kb
Host smart-77f648e1-0d69-4e15-a870-516b12a25aba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616441908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2616441908
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3060921905
Short name T268
Test name
Test status
Simulation time 23804481 ps
CPU time 0.64 seconds
Started Jan 21 03:21:53 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 194668 kb
Host smart-c778058d-88e2-4d7c-9444-dde1cce874e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060921905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3060921905
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2335508603
Short name T720
Test name
Test status
Simulation time 295723778 ps
CPU time 0.93 seconds
Started Jan 21 03:22:02 PM PST 24
Finished Jan 21 03:22:06 PM PST 24
Peak memory 197364 kb
Host smart-d8a10486-43d5-4e42-9949-8ac47daf4d77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335508603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2335508603
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3743336094
Short name T383
Test name
Test status
Simulation time 106647359 ps
CPU time 1.88 seconds
Started Jan 21 03:21:51 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 197952 kb
Host smart-9a856740-2513-458b-a1d2-a2d15d21bfce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743336094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3743336094
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1395995024
Short name T492
Test name
Test status
Simulation time 101602895 ps
CPU time 3.23 seconds
Started Jan 21 03:21:53 PM PST 24
Finished Jan 21 03:22:02 PM PST 24
Peak memory 198196 kb
Host smart-19516ec1-ec3c-4956-9539-381e0b15c1df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395995024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1395995024
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.857758133
Short name T261
Test name
Test status
Simulation time 59829703 ps
CPU time 0.71 seconds
Started Jan 21 03:22:03 PM PST 24
Finished Jan 21 03:22:06 PM PST 24
Peak memory 196216 kb
Host smart-066c379b-04af-456d-8d4b-82194280c437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857758133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.857758133
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3793743100
Short name T889
Test name
Test status
Simulation time 30564350 ps
CPU time 1.12 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 195948 kb
Host smart-0961c9a8-cc30-48a3-85bf-1b26924e2b8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793743100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3793743100
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3464962954
Short name T548
Test name
Test status
Simulation time 444653109 ps
CPU time 5.25 seconds
Started Jan 21 03:22:02 PM PST 24
Finished Jan 21 03:22:11 PM PST 24
Peak memory 198112 kb
Host smart-a90894b3-20b6-4b80-9db9-2a3bb76c85c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464962954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3464962954
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3051194437
Short name T418
Test name
Test status
Simulation time 68182566 ps
CPU time 1.17 seconds
Started Jan 21 03:21:51 PM PST 24
Finished Jan 21 03:21:59 PM PST 24
Peak memory 195788 kb
Host smart-1cb3299b-bea8-41fd-acf1-ddcd44c69832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051194437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3051194437
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1340166937
Short name T771
Test name
Test status
Simulation time 40856745 ps
CPU time 0.88 seconds
Started Jan 21 03:22:02 PM PST 24
Finished Jan 21 03:22:06 PM PST 24
Peak memory 195248 kb
Host smart-6bb44866-1a79-43f1-b8cc-823c975a1408
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340166937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1340166937
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1048352125
Short name T354
Test name
Test status
Simulation time 7723425373 ps
CPU time 197.47 seconds
Started Jan 21 03:21:52 PM PST 24
Finished Jan 21 03:25:16 PM PST 24
Peak memory 198216 kb
Host smart-48c31395-d537-45c0-82e8-c155d258eccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048352125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1048352125
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2783123910
Short name T401
Test name
Test status
Simulation time 138995311 ps
CPU time 0.57 seconds
Started Jan 21 03:22:14 PM PST 24
Finished Jan 21 03:22:20 PM PST 24
Peak memory 193896 kb
Host smart-59285b85-6e0e-473d-86b7-ba589dc45e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783123910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2783123910
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1264101608
Short name T869
Test name
Test status
Simulation time 54383597 ps
CPU time 0.76 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 195376 kb
Host smart-3559316f-7679-487f-8341-8495ada65e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264101608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1264101608
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3410096276
Short name T44
Test name
Test status
Simulation time 466633778 ps
CPU time 16.54 seconds
Started Jan 21 03:21:53 PM PST 24
Finished Jan 21 03:22:15 PM PST 24
Peak memory 198184 kb
Host smart-d8f9a1b9-0311-495b-96f8-23277cc751fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410096276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3410096276
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2193719539
Short name T575
Test name
Test status
Simulation time 324964485 ps
CPU time 1.05 seconds
Started Jan 21 03:22:02 PM PST 24
Finished Jan 21 03:22:06 PM PST 24
Peak memory 197920 kb
Host smart-d2ab1225-89c5-44dd-a56b-cf1a237bbff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193719539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2193719539
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1670530494
Short name T780
Test name
Test status
Simulation time 327714648 ps
CPU time 1.41 seconds
Started Jan 21 03:40:41 PM PST 24
Finished Jan 21 03:40:43 PM PST 24
Peak memory 197320 kb
Host smart-b44d8f42-5884-4944-b281-912950dd358d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670530494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1670530494
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1299535676
Short name T319
Test name
Test status
Simulation time 142234483 ps
CPU time 2.92 seconds
Started Jan 21 03:49:19 PM PST 24
Finished Jan 21 03:49:24 PM PST 24
Peak memory 198148 kb
Host smart-6d9411d9-e0e3-4e25-847d-09cd2ef5d681
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299535676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1299535676
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1769589227
Short name T320
Test name
Test status
Simulation time 182281043 ps
CPU time 3.42 seconds
Started Jan 21 03:21:54 PM PST 24
Finished Jan 21 03:22:03 PM PST 24
Peak memory 196948 kb
Host smart-44657901-5326-4b72-aa49-c77f05f8970b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769589227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1769589227
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2799415245
Short name T407
Test name
Test status
Simulation time 27236104 ps
CPU time 0.77 seconds
Started Jan 21 03:21:58 PM PST 24
Finished Jan 21 03:22:02 PM PST 24
Peak memory 196000 kb
Host smart-cf318e94-c7ef-4f96-8ce6-efc5fffdfa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799415245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2799415245
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1349628971
Short name T814
Test name
Test status
Simulation time 58489657 ps
CPU time 1.13 seconds
Started Jan 21 03:21:52 PM PST 24
Finished Jan 21 03:22:00 PM PST 24
Peak memory 196148 kb
Host smart-e31ced7f-27cb-4850-a97e-8bbe241c9fbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349628971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1349628971
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3298955823
Short name T465
Test name
Test status
Simulation time 329640996 ps
CPU time 4.04 seconds
Started Jan 21 03:21:53 PM PST 24
Finished Jan 21 03:22:03 PM PST 24
Peak memory 198056 kb
Host smart-8e7ee790-446a-4c99-8de3-541cd24aadf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298955823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3298955823
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3458456378
Short name T323
Test name
Test status
Simulation time 147912008 ps
CPU time 1.22 seconds
Started Jan 21 03:22:03 PM PST 24
Finished Jan 21 03:22:07 PM PST 24
Peak memory 195976 kb
Host smart-4ab33231-ad02-4225-a7dd-115af34adad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458456378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3458456378
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3748196596
Short name T288
Test name
Test status
Simulation time 165770308 ps
CPU time 1.27 seconds
Started Jan 21 03:21:58 PM PST 24
Finished Jan 21 03:22:02 PM PST 24
Peak memory 195584 kb
Host smart-4b7ac83b-89b5-4cf8-9acb-37add7d21a14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748196596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3748196596
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.241478998
Short name T611
Test name
Test status
Simulation time 14053916476 ps
CPU time 151.82 seconds
Started Jan 21 03:21:58 PM PST 24
Finished Jan 21 03:24:33 PM PST 24
Peak memory 198196 kb
Host smart-2a9b2422-ff96-41d8-841e-4963e729332a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241478998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.241478998
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.273513795
Short name T676
Test name
Test status
Simulation time 609684663618 ps
CPU time 755.31 seconds
Started Jan 21 03:22:07 PM PST 24
Finished Jan 21 03:34:51 PM PST 24
Peak memory 198284 kb
Host smart-1ab8b240-4338-4dfe-bece-e01ba9dc4841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=273513795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.273513795
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3602365105
Short name T240
Test name
Test status
Simulation time 15236273 ps
CPU time 0.63 seconds
Started Jan 21 03:22:06 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 194092 kb
Host smart-f7ab2251-2dbe-44c8-aa0d-554b9c72e052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602365105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3602365105
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3660139305
Short name T341
Test name
Test status
Simulation time 60222535 ps
CPU time 0.82 seconds
Started Jan 21 03:22:03 PM PST 24
Finished Jan 21 03:22:07 PM PST 24
Peak memory 195388 kb
Host smart-9d29761c-7372-497e-9538-f60d569d1187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660139305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3660139305
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3602690516
Short name T749
Test name
Test status
Simulation time 133650218 ps
CPU time 6.67 seconds
Started Jan 21 03:47:02 PM PST 24
Finished Jan 21 03:47:14 PM PST 24
Peak memory 195628 kb
Host smart-c30c8657-5d8e-404f-8e60-47b33e2e1d36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602690516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3602690516
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2760769385
Short name T267
Test name
Test status
Simulation time 94743643 ps
CPU time 1.09 seconds
Started Jan 21 03:22:04 PM PST 24
Finished Jan 21 03:22:13 PM PST 24
Peak memory 197876 kb
Host smart-c1c15279-d50e-4b93-a8b0-18a81aa720f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760769385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2760769385
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3178680527
Short name T582
Test name
Test status
Simulation time 346391654 ps
CPU time 1.16 seconds
Started Jan 21 03:22:14 PM PST 24
Finished Jan 21 03:22:21 PM PST 24
Peak memory 195816 kb
Host smart-a5c09e3d-3239-4afb-a2aa-c665c09a3eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178680527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3178680527
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.409900556
Short name T402
Test name
Test status
Simulation time 289640923 ps
CPU time 2.83 seconds
Started Jan 21 03:22:05 PM PST 24
Finished Jan 21 03:22:15 PM PST 24
Peak memory 198348 kb
Host smart-8bfa6a00-a778-4123-90bb-e4799704feba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409900556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.409900556
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.923369664
Short name T631
Test name
Test status
Simulation time 289446006 ps
CPU time 1.72 seconds
Started Jan 21 03:22:14 PM PST 24
Finished Jan 21 03:22:21 PM PST 24
Peak memory 196160 kb
Host smart-9273b10b-2844-43aa-bbc5-1c5f52f26c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923369664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
923369664
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1323759232
Short name T552
Test name
Test status
Simulation time 31781835 ps
CPU time 1.22 seconds
Started Jan 21 03:22:03 PM PST 24
Finished Jan 21 03:22:12 PM PST 24
Peak memory 195964 kb
Host smart-046d8ebd-f1e8-4071-ad70-68616a44362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323759232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1323759232
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4267080655
Short name T812
Test name
Test status
Simulation time 127219723 ps
CPU time 1.14 seconds
Started Jan 21 03:22:10 PM PST 24
Finished Jan 21 03:22:17 PM PST 24
Peak memory 195804 kb
Host smart-926d58a5-e1df-43c1-9df3-93a1ec49cd26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267080655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4267080655
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1200338851
Short name T473
Test name
Test status
Simulation time 69046704 ps
CPU time 3.29 seconds
Started Jan 21 03:22:05 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 198056 kb
Host smart-dfb81edd-54be-4089-a740-715fa676b101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200338851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1200338851
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2321064463
Short name T725
Test name
Test status
Simulation time 100354562 ps
CPU time 1.34 seconds
Started Jan 21 03:22:10 PM PST 24
Finished Jan 21 03:22:17 PM PST 24
Peak memory 195640 kb
Host smart-2b4b5d87-1245-4498-8b59-0b7ffcbcec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321064463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2321064463
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1552394925
Short name T617
Test name
Test status
Simulation time 49834727 ps
CPU time 1.33 seconds
Started Jan 21 03:22:10 PM PST 24
Finished Jan 21 03:22:17 PM PST 24
Peak memory 196852 kb
Host smart-bada8357-5bef-4dcd-9022-66bd46ed2545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552394925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1552394925
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1094694852
Short name T644
Test name
Test status
Simulation time 37228429668 ps
CPU time 134.33 seconds
Started Jan 21 03:22:04 PM PST 24
Finished Jan 21 03:24:26 PM PST 24
Peak memory 198340 kb
Host smart-1ea123c9-dbf8-4214-afa8-f63d64445312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094694852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1094694852
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2480808073
Short name T680
Test name
Test status
Simulation time 331381210351 ps
CPU time 1135.73 seconds
Started Jan 21 03:22:05 PM PST 24
Finished Jan 21 03:41:08 PM PST 24
Peak memory 206504 kb
Host smart-f590019d-db51-475c-a29f-f38286e714e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2480808073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2480808073
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2436110692
Short name T673
Test name
Test status
Simulation time 35613446 ps
CPU time 0.56 seconds
Started Jan 21 03:22:06 PM PST 24
Finished Jan 21 03:22:15 PM PST 24
Peak memory 194004 kb
Host smart-721a1029-7e25-42cc-92a3-46a651505d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436110692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2436110692
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.314598571
Short name T445
Test name
Test status
Simulation time 44061345 ps
CPU time 0.89 seconds
Started Jan 21 03:22:07 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 196512 kb
Host smart-fee31d3d-10d5-402b-8a93-270c5a3bd67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314598571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.314598571
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4259852265
Short name T463
Test name
Test status
Simulation time 556144889 ps
CPU time 4.21 seconds
Started Jan 21 03:22:09 PM PST 24
Finished Jan 21 03:22:20 PM PST 24
Peak memory 195928 kb
Host smart-b5230d33-a499-4c3d-8933-1d5e0c394cd8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259852265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4259852265
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.573333960
Short name T809
Test name
Test status
Simulation time 63142786 ps
CPU time 0.71 seconds
Started Jan 21 03:22:08 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 194624 kb
Host smart-98d7dba1-40bc-471c-932a-e9a834dd6acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573333960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.573333960
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.272857423
Short name T480
Test name
Test status
Simulation time 33771563 ps
CPU time 0.99 seconds
Started Jan 21 03:22:05 PM PST 24
Finished Jan 21 03:22:13 PM PST 24
Peak memory 196156 kb
Host smart-de5c3f10-250a-4ec2-b24e-345cb9e4c7b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272857423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.272857423
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2236342370
Short name T568
Test name
Test status
Simulation time 47914182 ps
CPU time 2.06 seconds
Started Jan 21 03:22:06 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 198060 kb
Host smart-5f673071-8212-41c0-b73a-3574c1591930
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236342370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2236342370
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.336775937
Short name T274
Test name
Test status
Simulation time 60106269 ps
CPU time 1.83 seconds
Started Jan 21 03:22:06 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 196784 kb
Host smart-d200a169-0dde-4af8-855f-6f47347cb8ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336775937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
336775937
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3302479671
Short name T440
Test name
Test status
Simulation time 132334578 ps
CPU time 1.03 seconds
Started Jan 21 03:22:03 PM PST 24
Finished Jan 21 03:22:11 PM PST 24
Peak memory 196712 kb
Host smart-49304c58-ef62-4c4d-8811-591a8966ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302479671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3302479671
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1562239775
Short name T806
Test name
Test status
Simulation time 28068680 ps
CPU time 0.81 seconds
Started Jan 21 04:09:06 PM PST 24
Finished Jan 21 04:09:10 PM PST 24
Peak memory 196336 kb
Host smart-79d701fb-40bc-4c19-8aac-ad090b677424
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562239775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1562239775
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3138942346
Short name T426
Test name
Test status
Simulation time 487401412 ps
CPU time 5.8 seconds
Started Jan 21 03:22:04 PM PST 24
Finished Jan 21 03:22:17 PM PST 24
Peak memory 198168 kb
Host smart-81dbf3bc-8d23-4672-85f5-e2944a9ff0fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138942346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3138942346
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1990344821
Short name T262
Test name
Test status
Simulation time 95781630 ps
CPU time 0.74 seconds
Started Jan 21 03:22:07 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 195352 kb
Host smart-42627d39-9320-432a-ae9c-eedd88a48294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990344821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1990344821
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2530890942
Short name T381
Test name
Test status
Simulation time 40664502 ps
CPU time 0.95 seconds
Started Jan 21 03:22:07 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 195904 kb
Host smart-d1e707e2-6b05-4dd5-90a6-9bb4bb8180fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530890942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2530890942
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2543152505
Short name T860
Test name
Test status
Simulation time 22653784186 ps
CPU time 153.35 seconds
Started Jan 21 03:22:14 PM PST 24
Finished Jan 21 03:24:53 PM PST 24
Peak memory 198232 kb
Host smart-555658b1-ab34-4021-b134-2cc33f553d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543152505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2543152505
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.4009045270
Short name T282
Test name
Test status
Simulation time 875368277574 ps
CPU time 1349.3 seconds
Started Jan 21 03:22:06 PM PST 24
Finished Jan 21 03:44:45 PM PST 24
Peak memory 198372 kb
Host smart-91c7710c-9f7c-4bfc-ae32-a2284bc7b98a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4009045270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.4009045270
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1682396591
Short name T717
Test name
Test status
Simulation time 20062283 ps
CPU time 0.62 seconds
Started Jan 21 03:22:26 PM PST 24
Finished Jan 21 03:22:28 PM PST 24
Peak memory 194976 kb
Host smart-db3268a1-db3a-402c-856c-fe479c5a1699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682396591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1682396591
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.934844477
Short name T668
Test name
Test status
Simulation time 36268256 ps
CPU time 0.85 seconds
Started Jan 21 03:22:09 PM PST 24
Finished Jan 21 03:22:16 PM PST 24
Peak memory 195540 kb
Host smart-366f8863-ae30-482b-84ad-c5e827a51b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934844477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.934844477
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1380531220
Short name T238
Test name
Test status
Simulation time 203579208 ps
CPU time 6.71 seconds
Started Jan 21 03:39:37 PM PST 24
Finished Jan 21 03:39:46 PM PST 24
Peak memory 195696 kb
Host smart-a58cc98c-5cc6-426a-a6e3-fe00f066d247
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380531220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1380531220
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.895509402
Short name T340
Test name
Test status
Simulation time 123055959 ps
CPU time 1.01 seconds
Started Jan 21 03:22:26 PM PST 24
Finished Jan 21 03:22:28 PM PST 24
Peak memory 196752 kb
Host smart-c6b337d1-729c-4b57-8085-2dfb24efe821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895509402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.895509402
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.710253811
Short name T638
Test name
Test status
Simulation time 278144934 ps
CPU time 1.23 seconds
Started Jan 21 03:22:10 PM PST 24
Finished Jan 21 03:22:17 PM PST 24
Peak memory 196668 kb
Host smart-dcd0c89a-70a5-4698-928f-8649f8687ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710253811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.710253811
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3560716370
Short name T448
Test name
Test status
Simulation time 138678840 ps
CPU time 3.08 seconds
Started Jan 21 03:22:07 PM PST 24
Finished Jan 21 03:22:18 PM PST 24
Peak memory 198136 kb
Host smart-bdf02316-2fd4-4519-b22d-346f915e6fef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560716370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3560716370
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3091677530
Short name T300
Test name
Test status
Simulation time 288093884 ps
CPU time 2.67 seconds
Started Jan 21 03:38:08 PM PST 24
Finished Jan 21 03:38:11 PM PST 24
Peak memory 197540 kb
Host smart-d8e7b55a-3af5-4f56-9cbe-1d65fcef77ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091677530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3091677530
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2251583280
Short name T692
Test name
Test status
Simulation time 106385081 ps
CPU time 1.18 seconds
Started Jan 21 03:22:07 PM PST 24
Finished Jan 21 03:22:17 PM PST 24
Peak memory 195868 kb
Host smart-298509f7-e83c-4413-a537-5e05a45e4c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251583280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2251583280
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2801167345
Short name T352
Test name
Test status
Simulation time 445936684 ps
CPU time 0.79 seconds
Started Jan 21 03:40:39 PM PST 24
Finished Jan 21 03:40:40 PM PST 24
Peak memory 195480 kb
Host smart-8bc201a7-125f-40ca-93d1-ac54b9a4c89e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801167345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2801167345
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3228157723
Short name T650
Test name
Test status
Simulation time 119909018 ps
CPU time 5.59 seconds
Started Jan 21 03:22:09 PM PST 24
Finished Jan 21 03:22:21 PM PST 24
Peak memory 198152 kb
Host smart-d6fde262-d626-4c85-b9a1-1c0559940399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228157723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3228157723
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.106409966
Short name T662
Test name
Test status
Simulation time 38211262 ps
CPU time 1.15 seconds
Started Jan 21 03:22:04 PM PST 24
Finished Jan 21 03:22:13 PM PST 24
Peak memory 196840 kb
Host smart-0dfae11a-c1f8-4d78-9809-1319cc8dfb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106409966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.106409966
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4086740410
Short name T629
Test name
Test status
Simulation time 76797092 ps
CPU time 1.51 seconds
Started Jan 21 03:22:03 PM PST 24
Finished Jan 21 03:22:12 PM PST 24
Peak memory 195632 kb
Host smart-0e67d906-8bbf-45af-ab0d-59365afbb136
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086740410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4086740410
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1930070561
Short name T569
Test name
Test status
Simulation time 31906729448 ps
CPU time 206.64 seconds
Started Jan 21 03:22:24 PM PST 24
Finished Jan 21 03:25:52 PM PST 24
Peak memory 198348 kb
Host smart-6c7c9cff-4471-48be-801a-ca68abf18427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930070561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1930070561
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1700643672
Short name T71
Test name
Test status
Simulation time 192619629064 ps
CPU time 1387.56 seconds
Started Jan 21 03:22:27 PM PST 24
Finished Jan 21 03:45:36 PM PST 24
Peak memory 198364 kb
Host smart-3a6416ff-2b4b-469d-8a1f-46dd3c8c6d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1700643672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1700643672
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1533584746
Short name T537
Test name
Test status
Simulation time 108845032 ps
CPU time 0.62 seconds
Started Jan 21 03:20:34 PM PST 24
Finished Jan 21 03:20:35 PM PST 24
Peak memory 194696 kb
Host smart-385c794f-7ac6-4992-b4ee-f44fdbf969e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533584746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1533584746
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4157280729
Short name T855
Test name
Test status
Simulation time 37761645 ps
CPU time 0.94 seconds
Started Jan 21 03:20:22 PM PST 24
Finished Jan 21 03:20:23 PM PST 24
Peak memory 197316 kb
Host smart-8ae44d51-d43f-4a68-8bef-e4a01bb28817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157280729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4157280729
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1986238319
Short name T826
Test name
Test status
Simulation time 1802185189 ps
CPU time 15.83 seconds
Started Jan 21 03:20:20 PM PST 24
Finished Jan 21 03:20:38 PM PST 24
Peak memory 198112 kb
Host smart-c48106a5-ddda-47e9-97c7-da1c4921dbcc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986238319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1986238319
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3530621061
Short name T96
Test name
Test status
Simulation time 39703058 ps
CPU time 0.84 seconds
Started Jan 21 03:20:29 PM PST 24
Finished Jan 21 03:20:31 PM PST 24
Peak memory 196720 kb
Host smart-09e95eb4-4011-46cf-a818-7bc3ffb4b9d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530621061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3530621061
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2635419431
Short name T768
Test name
Test status
Simulation time 30979619 ps
CPU time 0.98 seconds
Started Jan 21 03:41:06 PM PST 24
Finished Jan 21 03:41:07 PM PST 24
Peak memory 196080 kb
Host smart-100d4303-e77b-49e7-ad66-5acaeeae4ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635419431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2635419431
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4070685174
Short name T630
Test name
Test status
Simulation time 76193049 ps
CPU time 3.06 seconds
Started Jan 21 03:20:28 PM PST 24
Finished Jan 21 03:20:32 PM PST 24
Peak memory 198156 kb
Host smart-1b7c9329-2207-4a49-908a-976e47e8415f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070685174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4070685174
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3392083055
Short name T242
Test name
Test status
Simulation time 254357208 ps
CPU time 2.54 seconds
Started Jan 21 03:20:20 PM PST 24
Finished Jan 21 03:20:24 PM PST 24
Peak memory 196664 kb
Host smart-1e2e94a1-67f0-4f6e-8997-c3c06ce79c07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392083055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3392083055
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.641575467
Short name T94
Test name
Test status
Simulation time 74917022 ps
CPU time 0.87 seconds
Started Jan 21 03:20:20 PM PST 24
Finished Jan 21 03:20:21 PM PST 24
Peak memory 196000 kb
Host smart-de35bd8a-e6ce-4f59-9c25-ae9a079e6fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641575467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.641575467
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2753087789
Short name T459
Test name
Test status
Simulation time 72683109 ps
CPU time 0.75 seconds
Started Jan 21 03:40:38 PM PST 24
Finished Jan 21 03:40:40 PM PST 24
Peak memory 196300 kb
Host smart-9a5fc0b4-081f-4173-b45e-40575052f90e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753087789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2753087789
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1543196093
Short name T373
Test name
Test status
Simulation time 139084557 ps
CPU time 3.32 seconds
Started Jan 21 03:51:34 PM PST 24
Finished Jan 21 03:51:38 PM PST 24
Peak memory 198104 kb
Host smart-e0d74930-4455-4638-896a-14fc41010a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543196093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1543196093
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.869681093
Short name T29
Test name
Test status
Simulation time 224718834 ps
CPU time 0.86 seconds
Started Jan 21 03:20:36 PM PST 24
Finished Jan 21 03:20:37 PM PST 24
Peak memory 213656 kb
Host smart-65298c9b-ca85-42f5-bfef-9234fc68310b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869681093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.869681093
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.286012970
Short name T651
Test name
Test status
Simulation time 92708580 ps
CPU time 1.22 seconds
Started Jan 21 03:20:24 PM PST 24
Finished Jan 21 03:20:26 PM PST 24
Peak memory 195644 kb
Host smart-a6d5f3ce-5889-446a-a009-11fed3bf5491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286012970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.286012970
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.335795596
Short name T671
Test name
Test status
Simulation time 166004231 ps
CPU time 1.02 seconds
Started Jan 21 03:20:23 PM PST 24
Finished Jan 21 03:20:25 PM PST 24
Peak memory 195888 kb
Host smart-6723d3b0-9dff-4bdf-844e-d5a99a139a2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335795596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.335795596
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3519392531
Short name T777
Test name
Test status
Simulation time 4154485151 ps
CPU time 24.85 seconds
Started Jan 21 03:20:34 PM PST 24
Finished Jan 21 03:21:00 PM PST 24
Peak memory 198176 kb
Host smart-612e1322-6308-4f87-bc31-c0eb3bf3ab71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519392531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3519392531
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1490159337
Short name T394
Test name
Test status
Simulation time 1003515197267 ps
CPU time 1813.89 seconds
Started Jan 21 03:20:36 PM PST 24
Finished Jan 21 03:50:51 PM PST 24
Peak memory 198344 kb
Host smart-80fb0c55-2650-4784-983f-978b1fab2296
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1490159337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1490159337
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2653611414
Short name T298
Test name
Test status
Simulation time 58500842 ps
CPU time 0.58 seconds
Started Jan 21 03:22:25 PM PST 24
Finished Jan 21 03:22:26 PM PST 24
Peak memory 194700 kb
Host smart-55bde563-7f7c-4a4e-aac2-4d09e36a603c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653611414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2653611414
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.114941678
Short name T251
Test name
Test status
Simulation time 229560528 ps
CPU time 0.92 seconds
Started Jan 21 03:22:21 PM PST 24
Finished Jan 21 03:22:23 PM PST 24
Peak memory 197172 kb
Host smart-41605303-a753-4650-be9f-47a098391c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114941678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.114941678
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1864266115
Short name T591
Test name
Test status
Simulation time 914050934 ps
CPU time 29.03 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:59 PM PST 24
Peak memory 198060 kb
Host smart-4b02e613-827d-4508-a920-960539785fd7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864266115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1864266115
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2877636804
Short name T871
Test name
Test status
Simulation time 74120735 ps
CPU time 1.1 seconds
Started Jan 21 03:22:23 PM PST 24
Finished Jan 21 03:22:25 PM PST 24
Peak memory 196624 kb
Host smart-fc7af3be-ab89-45b0-9a4f-eafbb7d6e1f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877636804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2877636804
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1253595001
Short name T413
Test name
Test status
Simulation time 438723314 ps
CPU time 1.4 seconds
Started Jan 21 03:22:24 PM PST 24
Finished Jan 21 03:22:27 PM PST 24
Peak memory 197028 kb
Host smart-53d98585-674e-4eaa-8549-42ba26446a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253595001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1253595001
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.791972388
Short name T476
Test name
Test status
Simulation time 89545415 ps
CPU time 3.47 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:33 PM PST 24
Peak memory 196368 kb
Host smart-568175c1-fa5d-4f33-a928-4b12ccc43f10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791972388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.791972388
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4036268048
Short name T250
Test name
Test status
Simulation time 127147748 ps
CPU time 2.1 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:32 PM PST 24
Peak memory 196884 kb
Host smart-a6f9da4f-34c4-49a3-82cc-90daf291d05f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036268048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4036268048
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3895962421
Short name T457
Test name
Test status
Simulation time 53105870 ps
CPU time 0.69 seconds
Started Jan 21 03:22:22 PM PST 24
Finished Jan 21 03:22:24 PM PST 24
Peak memory 195068 kb
Host smart-5e62f330-ca3b-4728-9054-3d90b9ba17e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895962421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3895962421
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2637383708
Short name T269
Test name
Test status
Simulation time 21919157 ps
CPU time 0.89 seconds
Started Jan 21 03:22:23 PM PST 24
Finished Jan 21 03:22:25 PM PST 24
Peak memory 196648 kb
Host smart-0718ccbb-873c-4031-8ebd-1665c0e32a06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637383708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2637383708
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3262544030
Short name T358
Test name
Test status
Simulation time 204432141 ps
CPU time 3.45 seconds
Started Jan 21 03:22:30 PM PST 24
Finished Jan 21 03:22:36 PM PST 24
Peak memory 198012 kb
Host smart-d9438e9b-9e2d-4960-a1d4-e6584c8f5479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262544030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3262544030
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2383966652
Short name T755
Test name
Test status
Simulation time 83220323 ps
CPU time 1.17 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:30 PM PST 24
Peak memory 195872 kb
Host smart-3e212616-b417-4f69-a548-67327721961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383966652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2383966652
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1664373597
Short name T866
Test name
Test status
Simulation time 301623441 ps
CPU time 1.35 seconds
Started Jan 21 03:22:23 PM PST 24
Finished Jan 21 03:22:25 PM PST 24
Peak memory 196848 kb
Host smart-aaa4f9d4-f7c2-4df3-ba0f-d6b58009f281
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664373597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1664373597
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1505461252
Short name T287
Test name
Test status
Simulation time 75095812496 ps
CPU time 147.07 seconds
Started Jan 21 03:22:21 PM PST 24
Finished Jan 21 03:24:49 PM PST 24
Peak memory 198292 kb
Host smart-8d0feed0-8463-4dde-b9c5-9a0f1d5abfc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505461252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1505461252
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2186092199
Short name T798
Test name
Test status
Simulation time 129957288210 ps
CPU time 942.73 seconds
Started Jan 21 03:22:24 PM PST 24
Finished Jan 21 03:38:08 PM PST 24
Peak memory 198384 kb
Host smart-6ada1df0-63e3-4098-9b26-2b49be602fa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2186092199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2186092199
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1907071870
Short name T513
Test name
Test status
Simulation time 15732923 ps
CPU time 0.6 seconds
Started Jan 21 03:22:39 PM PST 24
Finished Jan 21 03:22:41 PM PST 24
Peak memory 194200 kb
Host smart-4b976db9-edc0-4762-a788-e559810306ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907071870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1907071870
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4279872811
Short name T232
Test name
Test status
Simulation time 149757295 ps
CPU time 0.69 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:30 PM PST 24
Peak memory 194868 kb
Host smart-b06d8314-7df3-4210-bbfb-ed2847cc0ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279872811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4279872811
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1241564805
Short name T541
Test name
Test status
Simulation time 2442919647 ps
CPU time 20.75 seconds
Started Jan 21 03:22:31 PM PST 24
Finished Jan 21 03:22:53 PM PST 24
Peak memory 197064 kb
Host smart-e6fc163f-9828-4b7a-a8a3-70b0f1430ae4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241564805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1241564805
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2892875456
Short name T293
Test name
Test status
Simulation time 34934775 ps
CPU time 0.8 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:30 PM PST 24
Peak memory 196592 kb
Host smart-77f5d53e-a0e4-4ae2-a393-61b5e4db068d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892875456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2892875456
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.423235056
Short name T246
Test name
Test status
Simulation time 39037968 ps
CPU time 1.1 seconds
Started Jan 21 03:22:32 PM PST 24
Finished Jan 21 03:22:34 PM PST 24
Peak memory 196156 kb
Host smart-a87ebefd-dc4e-42fe-9e4c-40ef8b98b890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423235056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.423235056
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.973411496
Short name T295
Test name
Test status
Simulation time 41749183 ps
CPU time 1.81 seconds
Started Jan 21 03:22:30 PM PST 24
Finished Jan 21 03:22:34 PM PST 24
Peak memory 198224 kb
Host smart-e19d8dc0-4bd9-4616-8528-d74e5c87f8bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973411496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.973411496
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2457634775
Short name T520
Test name
Test status
Simulation time 112403036 ps
CPU time 2.6 seconds
Started Jan 21 03:22:30 PM PST 24
Finished Jan 21 03:22:35 PM PST 24
Peak memory 197324 kb
Host smart-89519942-786a-49fd-a7bd-87acdbc422dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457634775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2457634775
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.58854593
Short name T760
Test name
Test status
Simulation time 70883950 ps
CPU time 0.84 seconds
Started Jan 21 03:22:21 PM PST 24
Finished Jan 21 03:22:23 PM PST 24
Peak memory 196612 kb
Host smart-12d099aa-8982-4097-9ae3-87fe50300c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58854593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.58854593
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1738920909
Short name T518
Test name
Test status
Simulation time 35656920 ps
CPU time 0.69 seconds
Started Jan 21 03:22:30 PM PST 24
Finished Jan 21 03:22:32 PM PST 24
Peak memory 194472 kb
Host smart-4aa8ec44-accc-4fac-a032-06f3cf13bb7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738920909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1738920909
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.549260550
Short name T761
Test name
Test status
Simulation time 400917700 ps
CPU time 3.79 seconds
Started Jan 21 03:22:36 PM PST 24
Finished Jan 21 03:22:41 PM PST 24
Peak memory 198048 kb
Host smart-284915fc-c963-4c96-babe-aa38b5edae67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549260550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.549260550
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.537906866
Short name T314
Test name
Test status
Simulation time 106424146 ps
CPU time 0.74 seconds
Started Jan 21 03:22:28 PM PST 24
Finished Jan 21 03:22:31 PM PST 24
Peak memory 195204 kb
Host smart-c84c2e8f-f6e1-4ec0-b4f7-deff2d13e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537906866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.537906866
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3216995629
Short name T411
Test name
Test status
Simulation time 283069630 ps
CPU time 1.31 seconds
Started Jan 21 03:22:30 PM PST 24
Finished Jan 21 03:22:33 PM PST 24
Peak memory 198148 kb
Host smart-09b331a0-da62-4ce0-8250-2f1f254f24d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216995629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3216995629
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1469477321
Short name T348
Test name
Test status
Simulation time 3998943971 ps
CPU time 51.52 seconds
Started Jan 21 03:22:29 PM PST 24
Finished Jan 21 03:23:22 PM PST 24
Peak memory 198312 kb
Host smart-5c6ae26e-1cdc-4d76-9330-77688e90edbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469477321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1469477321
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3589833136
Short name T609
Test name
Test status
Simulation time 81419056255 ps
CPU time 1429.97 seconds
Started Jan 21 03:22:39 PM PST 24
Finished Jan 21 03:46:31 PM PST 24
Peak memory 198428 kb
Host smart-af1ab4e9-7ab9-4fc3-9311-159e98e526d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3589833136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3589833136
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2050858037
Short name T351
Test name
Test status
Simulation time 15859172 ps
CPU time 0.6 seconds
Started Jan 21 03:22:57 PM PST 24
Finished Jan 21 03:22:59 PM PST 24
Peak memory 194184 kb
Host smart-926cf4ea-65cc-4cff-a1f9-141ed5778e5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050858037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2050858037
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1675723715
Short name T475
Test name
Test status
Simulation time 72899686 ps
CPU time 0.88 seconds
Started Jan 21 03:22:40 PM PST 24
Finished Jan 21 03:22:42 PM PST 24
Peak memory 196216 kb
Host smart-2e0be6ba-56ed-46dd-ac5f-88db24886701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675723715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1675723715
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1731830842
Short name T66
Test name
Test status
Simulation time 508387533 ps
CPU time 25.97 seconds
Started Jan 21 03:22:38 PM PST 24
Finished Jan 21 03:23:05 PM PST 24
Peak memory 196940 kb
Host smart-7a20764b-0e85-433d-a90d-52ce2d86b382
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731830842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1731830842
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3736921707
Short name T601
Test name
Test status
Simulation time 89870772 ps
CPU time 1.16 seconds
Started Jan 21 03:22:53 PM PST 24
Finished Jan 21 03:22:55 PM PST 24
Peak memory 197792 kb
Host smart-53bbcba0-2e48-4400-8b3b-67d04f29937f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736921707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3736921707
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.410411653
Short name T663
Test name
Test status
Simulation time 214486058 ps
CPU time 1.44 seconds
Started Jan 21 03:22:41 PM PST 24
Finished Jan 21 03:22:43 PM PST 24
Peak memory 195864 kb
Host smart-ac2a00ab-0452-4149-ac4f-b20f1fd90786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410411653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.410411653
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.488154667
Short name T698
Test name
Test status
Simulation time 94689715 ps
CPU time 3.95 seconds
Started Jan 21 03:22:40 PM PST 24
Finished Jan 21 03:22:45 PM PST 24
Peak memory 198152 kb
Host smart-2ab073d7-d83c-47f6-964b-b6444ea5aa3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488154667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.488154667
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3508814525
Short name T543
Test name
Test status
Simulation time 60200679 ps
CPU time 1.47 seconds
Started Jan 21 03:22:42 PM PST 24
Finished Jan 21 03:22:45 PM PST 24
Peak memory 196728 kb
Host smart-a25b84b0-174c-4cca-99fa-757f1404a328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508814525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3508814525
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3614186525
Short name T640
Test name
Test status
Simulation time 66546863 ps
CPU time 0.86 seconds
Started Jan 21 03:33:48 PM PST 24
Finished Jan 21 03:33:54 PM PST 24
Peak memory 197460 kb
Host smart-8c4dfc9c-1433-452f-8fa3-1d03ad2bbfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614186525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3614186525
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1546467270
Short name T415
Test name
Test status
Simulation time 190917129 ps
CPU time 1.11 seconds
Started Jan 21 03:22:40 PM PST 24
Finished Jan 21 03:22:43 PM PST 24
Peak memory 196872 kb
Host smart-a9483bcc-6d86-4c7d-8c50-8a797858f71d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546467270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1546467270
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1434837061
Short name T831
Test name
Test status
Simulation time 1295900819 ps
CPU time 3.41 seconds
Started Jan 21 03:22:37 PM PST 24
Finished Jan 21 03:22:41 PM PST 24
Peak memory 198156 kb
Host smart-05614d13-e070-44a5-a7ed-664de07d1437
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434837061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1434837061
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1309047958
Short name T244
Test name
Test status
Simulation time 181952222 ps
CPU time 0.93 seconds
Started Jan 21 03:22:40 PM PST 24
Finished Jan 21 03:22:42 PM PST 24
Peak memory 195508 kb
Host smart-fa435921-361e-4481-a4ad-367399166ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309047958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1309047958
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.422494149
Short name T584
Test name
Test status
Simulation time 159401181 ps
CPU time 0.92 seconds
Started Jan 21 03:22:41 PM PST 24
Finished Jan 21 03:22:42 PM PST 24
Peak memory 196392 kb
Host smart-62b315c0-a9be-4fc6-b9e5-58b9b8ea1518
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422494149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.422494149
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4088204989
Short name T68
Test name
Test status
Simulation time 14477181945 ps
CPU time 190.78 seconds
Started Jan 21 03:22:48 PM PST 24
Finished Jan 21 03:26:00 PM PST 24
Peak memory 198368 kb
Host smart-0ed15464-4b51-442e-b6c3-a74abddf7c9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088204989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4088204989
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.803239205
Short name T819
Test name
Test status
Simulation time 151943049331 ps
CPU time 981.75 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:39:23 PM PST 24
Peak memory 206548 kb
Host smart-bb18060b-21e9-48ee-98fa-557f01a7a3f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=803239205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.803239205
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1159711967
Short name T500
Test name
Test status
Simulation time 48232830 ps
CPU time 0.58 seconds
Started Jan 21 03:22:49 PM PST 24
Finished Jan 21 03:22:50 PM PST 24
Peak memory 194068 kb
Host smart-22fdda8c-0e69-4959-b654-2759a315b09f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159711967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1159711967
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2527954085
Short name T660
Test name
Test status
Simulation time 452938808 ps
CPU time 0.75 seconds
Started Jan 21 03:22:53 PM PST 24
Finished Jan 21 03:22:54 PM PST 24
Peak memory 196116 kb
Host smart-c7b94e74-5a4d-4ae9-afdc-39f3f144e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527954085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2527954085
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.201092846
Short name T104
Test name
Test status
Simulation time 367613839 ps
CPU time 12.85 seconds
Started Jan 21 03:22:55 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 196444 kb
Host smart-6f37cc58-a6ff-4236-98eb-ab958b50dc1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201092846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.201092846
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3418699460
Short name T808
Test name
Test status
Simulation time 30194081 ps
CPU time 0.69 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:23:01 PM PST 24
Peak memory 194424 kb
Host smart-f28b3597-ad0f-4733-9149-aa3e7f470354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418699460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3418699460
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.570071401
Short name T254
Test name
Test status
Simulation time 47040875 ps
CPU time 1.34 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:23:02 PM PST 24
Peak memory 197316 kb
Host smart-d45d2c31-9795-4dc9-9159-bcc933d866b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570071401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.570071401
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3878442429
Short name T395
Test name
Test status
Simulation time 222395527 ps
CPU time 2.7 seconds
Started Jan 21 03:22:53 PM PST 24
Finished Jan 21 03:22:57 PM PST 24
Peak memory 198016 kb
Host smart-c965dbd7-ea5d-40b4-9aa1-83fae9d6afb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878442429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3878442429
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2670198873
Short name T844
Test name
Test status
Simulation time 137539649 ps
CPU time 1.25 seconds
Started Jan 21 03:22:54 PM PST 24
Finished Jan 21 03:22:56 PM PST 24
Peak memory 196976 kb
Host smart-9ef7b3e1-b9ba-4f4a-95bc-14860ba3ccc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670198873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2670198873
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.36657615
Short name T699
Test name
Test status
Simulation time 39654207 ps
CPU time 0.99 seconds
Started Jan 21 03:22:52 PM PST 24
Finished Jan 21 03:22:54 PM PST 24
Peak memory 195932 kb
Host smart-0e8df376-c5e8-40c7-9c77-acb4d01734a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36657615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.36657615
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2493571422
Short name T327
Test name
Test status
Simulation time 110324947 ps
CPU time 1.19 seconds
Started Jan 21 03:22:56 PM PST 24
Finished Jan 21 03:22:58 PM PST 24
Peak memory 197112 kb
Host smart-5ea7a09e-e285-4fad-82f9-38d33eca3f5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493571422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2493571422
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1641687667
Short name T452
Test name
Test status
Simulation time 868208173 ps
CPU time 2.86 seconds
Started Jan 21 03:22:48 PM PST 24
Finished Jan 21 03:22:51 PM PST 24
Peak memory 198128 kb
Host smart-717a8e2b-4de6-4230-88ab-386d2efcf423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641687667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1641687667
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.835568405
Short name T607
Test name
Test status
Simulation time 79100736 ps
CPU time 1.33 seconds
Started Jan 21 03:22:49 PM PST 24
Finished Jan 21 03:22:51 PM PST 24
Peak memory 198112 kb
Host smart-bd5e038b-7721-4c46-b52c-70c61389b325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835568405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.835568405
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.829231443
Short name T645
Test name
Test status
Simulation time 44811678 ps
CPU time 0.96 seconds
Started Jan 21 03:22:50 PM PST 24
Finished Jan 21 03:22:52 PM PST 24
Peak memory 196428 kb
Host smart-ff6d2ce6-24e2-49f5-8b26-7c776b87aadf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829231443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.829231443
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3809235520
Short name T248
Test name
Test status
Simulation time 28737721586 ps
CPU time 154.83 seconds
Started Jan 21 03:22:49 PM PST 24
Finished Jan 21 03:25:25 PM PST 24
Peak memory 198612 kb
Host smart-96caf189-50cf-41e2-9834-25fa05afa260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809235520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3809235520
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4032922567
Short name T797
Test name
Test status
Simulation time 64649694031 ps
CPU time 1090.65 seconds
Started Jan 21 03:22:53 PM PST 24
Finished Jan 21 03:41:04 PM PST 24
Peak memory 198228 kb
Host smart-1c7679c9-365f-42b5-8c4d-82438554476f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4032922567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4032922567
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2337077540
Short name T312
Test name
Test status
Simulation time 30934947 ps
CPU time 0.62 seconds
Started Jan 21 03:22:54 PM PST 24
Finished Jan 21 03:22:56 PM PST 24
Peak memory 194068 kb
Host smart-619b5b6b-2978-49f8-96d6-9d010300b8ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337077540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2337077540
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3107663096
Short name T779
Test name
Test status
Simulation time 49930910 ps
CPU time 0.69 seconds
Started Jan 21 03:23:02 PM PST 24
Finished Jan 21 03:23:03 PM PST 24
Peak memory 194748 kb
Host smart-3284b718-2d42-47af-ae45-cc1326e63871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107663096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3107663096
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3852605202
Short name T708
Test name
Test status
Simulation time 177056336 ps
CPU time 5.18 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:10 PM PST 24
Peak memory 196736 kb
Host smart-6028742d-53c6-4a91-95c6-d80430dbe33d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852605202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3852605202
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4032466469
Short name T335
Test name
Test status
Simulation time 71742129 ps
CPU time 1.06 seconds
Started Jan 21 03:22:56 PM PST 24
Finished Jan 21 03:22:58 PM PST 24
Peak memory 197192 kb
Host smart-e200d8ad-9212-46d2-959f-6b2f5b1b3928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032466469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4032466469
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1861216063
Short name T597
Test name
Test status
Simulation time 308231761 ps
CPU time 1.04 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:06 PM PST 24
Peak memory 195908 kb
Host smart-0194a021-2b9d-43dd-a206-bbd1dbb82b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861216063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1861216063
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.86557262
Short name T508
Test name
Test status
Simulation time 81469453 ps
CPU time 3.32 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:23:04 PM PST 24
Peak memory 198184 kb
Host smart-5101562f-063a-4047-a569-c9af3365241e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86557262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.gpio_intr_with_filter_rand_intr_event.86557262
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2252623110
Short name T299
Test name
Test status
Simulation time 171173407 ps
CPU time 2.45 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:08 PM PST 24
Peak memory 197272 kb
Host smart-3f4935cf-64d6-490a-b276-90824d5704fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252623110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2252623110
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4103735691
Short name T752
Test name
Test status
Simulation time 66961261 ps
CPU time 1.44 seconds
Started Jan 21 03:22:54 PM PST 24
Finished Jan 21 03:22:56 PM PST 24
Peak memory 196600 kb
Host smart-2ef1c571-0d5b-4d96-9868-21bab3c7106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103735691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4103735691
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2050723668
Short name T256
Test name
Test status
Simulation time 65269780 ps
CPU time 0.65 seconds
Started Jan 21 03:22:56 PM PST 24
Finished Jan 21 03:22:57 PM PST 24
Peak memory 194396 kb
Host smart-fcd75ac1-16a2-4d5f-b594-14a040e0bff1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050723668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2050723668
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1173594395
Short name T266
Test name
Test status
Simulation time 350396496 ps
CPU time 2.7 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:08 PM PST 24
Peak memory 198132 kb
Host smart-90be81a3-d5e2-4a0a-b6e8-25c287d99884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173594395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1173594395
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4214994510
Short name T585
Test name
Test status
Simulation time 160233378 ps
CPU time 1.51 seconds
Started Jan 21 03:22:48 PM PST 24
Finished Jan 21 03:22:50 PM PST 24
Peak memory 198056 kb
Host smart-d3532fb9-4a19-493c-ad2b-a2ec78f82c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214994510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4214994510
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1114807724
Short name T371
Test name
Test status
Simulation time 259125570 ps
CPU time 1.04 seconds
Started Jan 21 03:22:54 PM PST 24
Finished Jan 21 03:22:55 PM PST 24
Peak memory 195832 kb
Host smart-232831c8-32fe-4610-89a1-4fb3cd357c9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114807724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1114807724
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.959288831
Short name T62
Test name
Test status
Simulation time 7413427685 ps
CPU time 111.34 seconds
Started Jan 21 03:23:02 PM PST 24
Finished Jan 21 03:24:54 PM PST 24
Peak memory 198260 kb
Host smart-b5251855-1ea9-44ec-a396-a316144c9049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959288831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.959288831
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1493266940
Short name T599
Test name
Test status
Simulation time 12934723405 ps
CPU time 295.04 seconds
Started Jan 21 03:22:54 PM PST 24
Finished Jan 21 03:27:50 PM PST 24
Peak memory 198284 kb
Host smart-0861726b-f3eb-4d68-ae41-6926f6ea14af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1493266940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1493266940
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3094184620
Short name T436
Test name
Test status
Simulation time 129287225 ps
CPU time 0.58 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:05 PM PST 24
Peak memory 194692 kb
Host smart-ae81fa0e-33a4-40f0-9c8f-0bdc8b8d6690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094184620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3094184620
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3407304380
Short name T848
Test name
Test status
Simulation time 132130009 ps
CPU time 0.81 seconds
Started Jan 21 03:22:55 PM PST 24
Finished Jan 21 03:22:57 PM PST 24
Peak memory 196160 kb
Host smart-baf3fefd-0b34-443d-85e0-2de775bf2a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407304380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3407304380
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2013369159
Short name T280
Test name
Test status
Simulation time 863037227 ps
CPU time 7.04 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:12 PM PST 24
Peak memory 197164 kb
Host smart-0221eaa1-e27e-4138-9414-1e711f9bfd29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013369159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2013369159
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.608040714
Short name T714
Test name
Test status
Simulation time 37897206 ps
CPU time 0.73 seconds
Started Jan 21 03:23:05 PM PST 24
Finished Jan 21 03:23:06 PM PST 24
Peak memory 195408 kb
Host smart-9d861c37-b94d-440f-b121-744ed605014e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608040714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.608040714
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2146596621
Short name T432
Test name
Test status
Simulation time 50825755 ps
CPU time 1.48 seconds
Started Jan 21 03:23:07 PM PST 24
Finished Jan 21 03:23:10 PM PST 24
Peak memory 196740 kb
Host smart-8ee1c240-89e8-4795-97ba-fb643d47dff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146596621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2146596621
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1005621817
Short name T579
Test name
Test status
Simulation time 53192239 ps
CPU time 1.32 seconds
Started Jan 21 03:23:07 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 198032 kb
Host smart-948a186b-f79e-4240-99a8-74d3110c4952
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005621817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1005621817
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4269681075
Short name T308
Test name
Test status
Simulation time 1268717096 ps
CPU time 1.9 seconds
Started Jan 21 03:23:02 PM PST 24
Finished Jan 21 03:23:05 PM PST 24
Peak memory 195968 kb
Host smart-ec8c65e0-a463-4bc8-bede-d7be90357874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269681075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4269681075
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1095626057
Short name T815
Test name
Test status
Simulation time 73142069 ps
CPU time 1.2 seconds
Started Jan 21 03:22:55 PM PST 24
Finished Jan 21 03:22:57 PM PST 24
Peak memory 196620 kb
Host smart-973ed2db-6c6d-483d-99a9-b5ff8a1063bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095626057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1095626057
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4030790175
Short name T590
Test name
Test status
Simulation time 39277643 ps
CPU time 1.01 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:06 PM PST 24
Peak memory 196848 kb
Host smart-19303fae-9de5-4d55-b364-86094beb230b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030790175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4030790175
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1813862509
Short name T746
Test name
Test status
Simulation time 146042375 ps
CPU time 2.33 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 198088 kb
Host smart-dd439ac1-a6c1-46ce-90cb-4e5231bcdb30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813862509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1813862509
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.196772851
Short name T813
Test name
Test status
Simulation time 370527995 ps
CPU time 1.52 seconds
Started Jan 21 03:23:02 PM PST 24
Finished Jan 21 03:23:04 PM PST 24
Peak memory 198044 kb
Host smart-d96113c5-158a-414f-870b-da090ea0de68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196772851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.196772851
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2798756894
Short name T766
Test name
Test status
Simulation time 22959640 ps
CPU time 0.83 seconds
Started Jan 21 03:23:00 PM PST 24
Finished Jan 21 03:23:02 PM PST 24
Peak memory 195936 kb
Host smart-ed1618fb-4ac2-40e3-adbf-fd257db988cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798756894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2798756894
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3530305674
Short name T535
Test name
Test status
Simulation time 79527437822 ps
CPU time 200.08 seconds
Started Jan 21 03:23:11 PM PST 24
Finished Jan 21 03:26:32 PM PST 24
Peak memory 198172 kb
Host smart-97ee98ef-481e-4fc0-9294-aa58dba33a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530305674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3530305674
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1413658479
Short name T885
Test name
Test status
Simulation time 104558781783 ps
CPU time 2349.37 seconds
Started Jan 21 03:23:05 PM PST 24
Finished Jan 21 04:02:15 PM PST 24
Peak memory 198384 kb
Host smart-04bed425-6aa3-4f5d-9823-f73740b7c825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1413658479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1413658479
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2140665813
Short name T745
Test name
Test status
Simulation time 14594696 ps
CPU time 0.64 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:08 PM PST 24
Peak memory 194804 kb
Host smart-244bd7d1-ba1b-4a4a-b016-6489f59635e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140665813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2140665813
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1484369053
Short name T362
Test name
Test status
Simulation time 108653657 ps
CPU time 0.82 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:07 PM PST 24
Peak memory 196020 kb
Host smart-efc1f89b-9471-43f6-b5f8-ebb95e58ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484369053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1484369053
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1061299580
Short name T515
Test name
Test status
Simulation time 871250941 ps
CPU time 19.66 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:27 PM PST 24
Peak memory 198384 kb
Host smart-505a3814-c7be-465f-8e6a-94a4dfc3d5f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061299580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1061299580
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.296484938
Short name T827
Test name
Test status
Simulation time 29391595 ps
CPU time 0.62 seconds
Started Jan 21 03:38:47 PM PST 24
Finished Jan 21 03:38:48 PM PST 24
Peak memory 194572 kb
Host smart-6680fae8-9603-4fa6-8a71-4aee5fd57ba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296484938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.296484938
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1997187224
Short name T781
Test name
Test status
Simulation time 35195479 ps
CPU time 0.86 seconds
Started Jan 21 03:23:05 PM PST 24
Finished Jan 21 03:23:07 PM PST 24
Peak memory 196276 kb
Host smart-054287be-9a49-445d-af54-96d2f52869a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997187224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1997187224
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.956840290
Short name T494
Test name
Test status
Simulation time 96419337 ps
CPU time 2.05 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:23:07 PM PST 24
Peak memory 198240 kb
Host smart-83751255-40aa-4040-b849-f638b4432873
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956840290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.956840290
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1345740156
Short name T501
Test name
Test status
Simulation time 1164124328 ps
CPU time 1.7 seconds
Started Jan 21 03:23:07 PM PST 24
Finished Jan 21 03:23:10 PM PST 24
Peak memory 196168 kb
Host smart-022fb64e-7486-4157-a608-67b70b5fd6ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345740156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1345740156
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3758563104
Short name T528
Test name
Test status
Simulation time 109351489 ps
CPU time 0.7 seconds
Started Jan 21 03:40:42 PM PST 24
Finished Jan 21 03:40:44 PM PST 24
Peak memory 194424 kb
Host smart-a85852e0-2206-4e68-bae4-5f1c7ff624bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758563104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3758563104
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4089060553
Short name T236
Test name
Test status
Simulation time 72945212 ps
CPU time 1.02 seconds
Started Jan 21 03:23:03 PM PST 24
Finished Jan 21 03:23:05 PM PST 24
Peak memory 196844 kb
Host smart-1171e727-2edb-4807-ae38-68660917311b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089060553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4089060553
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2056375051
Short name T514
Test name
Test status
Simulation time 523745432 ps
CPU time 6.11 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:13 PM PST 24
Peak memory 198176 kb
Host smart-83450e7f-1aac-4e75-a28d-82f6b777eecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056375051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2056375051
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2627887398
Short name T98
Test name
Test status
Simulation time 139245782 ps
CPU time 1.29 seconds
Started Jan 21 03:23:05 PM PST 24
Finished Jan 21 03:23:08 PM PST 24
Peak memory 196776 kb
Host smart-2458dabb-7768-4f50-b7e7-f3451b30a9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627887398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2627887398
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.393940397
Short name T879
Test name
Test status
Simulation time 200185340 ps
CPU time 1.18 seconds
Started Jan 21 03:23:05 PM PST 24
Finished Jan 21 03:23:07 PM PST 24
Peak memory 195852 kb
Host smart-4bb12d50-d240-43b2-b4e8-40aa2fd57dc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393940397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.393940397
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3960818071
Short name T724
Test name
Test status
Simulation time 12098203316 ps
CPU time 183.53 seconds
Started Jan 21 03:23:04 PM PST 24
Finished Jan 21 03:26:08 PM PST 24
Peak memory 198380 kb
Host smart-514742bc-2ab8-470b-bfe8-f31cfe61521c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960818071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3960818071
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.268539287
Short name T875
Test name
Test status
Simulation time 142216780152 ps
CPU time 460.02 seconds
Started Jan 21 03:23:11 PM PST 24
Finished Jan 21 03:30:52 PM PST 24
Peak memory 198364 kb
Host smart-99f21ef4-94ab-4c95-be80-f9ca3bc0a446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=268539287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.268539287
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3186226285
Short name T490
Test name
Test status
Simulation time 17143742 ps
CPU time 0.61 seconds
Started Jan 21 03:23:15 PM PST 24
Finished Jan 21 03:23:16 PM PST 24
Peak memory 194224 kb
Host smart-fe7ebfba-564c-40cc-b550-0bce7bdeba41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186226285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3186226285
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3787406048
Short name T829
Test name
Test status
Simulation time 29375286 ps
CPU time 0.79 seconds
Started Jan 21 03:23:05 PM PST 24
Finished Jan 21 03:23:07 PM PST 24
Peak memory 195320 kb
Host smart-63c70309-349e-4217-8815-c390fb514d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787406048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3787406048
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2208329100
Short name T682
Test name
Test status
Simulation time 2784579455 ps
CPU time 20.05 seconds
Started Jan 21 03:23:13 PM PST 24
Finished Jan 21 03:23:34 PM PST 24
Peak memory 197192 kb
Host smart-863f766d-72b9-4e74-abf7-bd56609e6982
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208329100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2208329100
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1516524869
Short name T370
Test name
Test status
Simulation time 115434654 ps
CPU time 0.84 seconds
Started Jan 21 05:23:09 PM PST 24
Finished Jan 21 05:23:10 PM PST 24
Peak memory 196736 kb
Host smart-929d3996-f879-4939-a306-0d684cd9d50d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516524869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1516524869
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3541729600
Short name T832
Test name
Test status
Simulation time 359966560 ps
CPU time 1.11 seconds
Started Jan 21 03:36:11 PM PST 24
Finished Jan 21 03:36:13 PM PST 24
Peak memory 195976 kb
Host smart-5db9a34a-515b-4e6d-9e7b-2cfcbc29e749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541729600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3541729600
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.596119424
Short name T795
Test name
Test status
Simulation time 90054757 ps
CPU time 3.66 seconds
Started Jan 21 05:13:20 PM PST 24
Finished Jan 21 05:14:31 PM PST 24
Peak memory 198128 kb
Host smart-a7ad7701-742d-439a-9a45-9e618286bd2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596119424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.596119424
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.844571827
Short name T705
Test name
Test status
Simulation time 469509354 ps
CPU time 2.52 seconds
Started Jan 21 03:23:03 PM PST 24
Finished Jan 21 03:23:06 PM PST 24
Peak memory 195992 kb
Host smart-fd363305-5348-4f49-a02c-01adb66496f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844571827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
844571827
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3509411319
Short name T787
Test name
Test status
Simulation time 18801583 ps
CPU time 0.74 seconds
Started Jan 21 03:23:07 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 195148 kb
Host smart-12f801b9-bbe7-4a1b-830a-c4499e61a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509411319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3509411319
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1960420148
Short name T605
Test name
Test status
Simulation time 44533692 ps
CPU time 1.19 seconds
Started Jan 21 03:23:11 PM PST 24
Finished Jan 21 03:23:13 PM PST 24
Peak memory 197236 kb
Host smart-c85439c7-5903-447d-b1f8-238918e48dc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960420148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1960420148
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3458335585
Short name T839
Test name
Test status
Simulation time 124073106 ps
CPU time 2.18 seconds
Started Jan 21 04:31:41 PM PST 24
Finished Jan 21 04:31:47 PM PST 24
Peak memory 198140 kb
Host smart-ea54b5e9-7d1b-4bc9-8c3c-74ae442a8d83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458335585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3458335585
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.290739026
Short name T801
Test name
Test status
Simulation time 150022964 ps
CPU time 1.01 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 196464 kb
Host smart-5168b54a-64ce-4449-929a-4b4309173b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290739026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.290739026
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4029276670
Short name T737
Test name
Test status
Simulation time 32037709 ps
CPU time 0.99 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 195944 kb
Host smart-3fc93f87-8e62-4d9c-8710-4843102164dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029276670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4029276670
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2003970141
Short name T516
Test name
Test status
Simulation time 33900752638 ps
CPU time 212.74 seconds
Started Jan 21 04:02:39 PM PST 24
Finished Jan 21 04:06:18 PM PST 24
Peak memory 198344 kb
Host smart-3ebd5791-22a1-4e63-afbe-4f8036a12cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003970141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2003970141
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1197939249
Short name T355
Test name
Test status
Simulation time 118632905763 ps
CPU time 2377.88 seconds
Started Jan 21 04:06:45 PM PST 24
Finished Jan 21 04:46:34 PM PST 24
Peak memory 198336 kb
Host smart-3d9edce1-9183-4391-b49e-632c1206be7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1197939249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1197939249
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3250525388
Short name T730
Test name
Test status
Simulation time 11871272 ps
CPU time 0.58 seconds
Started Jan 21 03:23:26 PM PST 24
Finished Jan 21 03:23:28 PM PST 24
Peak memory 193848 kb
Host smart-b46c549c-06c3-491c-b8bc-1410e84f3726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250525388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3250525388
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3017129916
Short name T61
Test name
Test status
Simulation time 47966739 ps
CPU time 0.95 seconds
Started Jan 21 03:40:58 PM PST 24
Finished Jan 21 03:41:00 PM PST 24
Peak memory 196836 kb
Host smart-dc34e7c4-6487-4d81-b175-e4830075d39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017129916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3017129916
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3510248119
Short name T477
Test name
Test status
Simulation time 113421726 ps
CPU time 5.62 seconds
Started Jan 21 03:23:13 PM PST 24
Finished Jan 21 03:23:19 PM PST 24
Peak memory 196404 kb
Host smart-c88c4aa0-7d40-49c6-9d18-eb5ec41d9e66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510248119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3510248119
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3526820384
Short name T635
Test name
Test status
Simulation time 1127957958 ps
CPU time 1.05 seconds
Started Jan 21 03:23:14 PM PST 24
Finished Jan 21 03:23:15 PM PST 24
Peak memory 196564 kb
Host smart-3d59ae3a-1d03-4d52-b1ce-b3e68b82303b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526820384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3526820384
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2935430787
Short name T357
Test name
Test status
Simulation time 20761468 ps
CPU time 0.74 seconds
Started Jan 21 03:51:36 PM PST 24
Finished Jan 21 03:51:37 PM PST 24
Peak memory 195396 kb
Host smart-c578fda9-77b5-4151-922b-6bbbb9836896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935430787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2935430787
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.442327603
Short name T559
Test name
Test status
Simulation time 38091164 ps
CPU time 0.92 seconds
Started Jan 21 03:23:13 PM PST 24
Finished Jan 21 03:23:15 PM PST 24
Peak memory 196296 kb
Host smart-150f2795-80b3-4f8a-8cc0-76327331027a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442327603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.442327603
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.439867710
Short name T785
Test name
Test status
Simulation time 159842620 ps
CPU time 2.91 seconds
Started Jan 21 03:23:12 PM PST 24
Finished Jan 21 03:23:16 PM PST 24
Peak memory 197300 kb
Host smart-2e4dfc8b-375d-43b2-8296-0381def400fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439867710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
439867710
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2439699019
Short name T69
Test name
Test status
Simulation time 296561082 ps
CPU time 0.91 seconds
Started Jan 21 03:35:59 PM PST 24
Finished Jan 21 03:36:03 PM PST 24
Peak memory 196732 kb
Host smart-7b7ea748-91bd-430f-90a1-a71ce48d85ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439699019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2439699019
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4063268114
Short name T643
Test name
Test status
Simulation time 43041034 ps
CPU time 1 seconds
Started Jan 21 03:23:16 PM PST 24
Finished Jan 21 03:23:18 PM PST 24
Peak memory 196848 kb
Host smart-1d46b858-e1fa-44ff-b3d9-0a5099626cf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063268114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4063268114
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2006779189
Short name T661
Test name
Test status
Simulation time 317908012 ps
CPU time 3.87 seconds
Started Jan 21 03:46:42 PM PST 24
Finished Jan 21 03:46:48 PM PST 24
Peak memory 198096 kb
Host smart-0f84f581-c420-4e61-a05a-56b6519dd6b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006779189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2006779189
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3422031044
Short name T506
Test name
Test status
Simulation time 55719724 ps
CPU time 0.96 seconds
Started Jan 21 03:23:16 PM PST 24
Finished Jan 21 03:23:18 PM PST 24
Peak memory 195868 kb
Host smart-2e5f504d-3844-4348-a945-b985dca7acca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422031044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3422031044
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2728410836
Short name T273
Test name
Test status
Simulation time 133411364 ps
CPU time 1.1 seconds
Started Jan 21 03:23:15 PM PST 24
Finished Jan 21 03:23:17 PM PST 24
Peak memory 195604 kb
Host smart-fd5b307c-6ed1-4fd3-bc26-f3cfd66b13ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728410836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2728410836
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3586902479
Short name T353
Test name
Test status
Simulation time 48889639745 ps
CPU time 85.95 seconds
Started Jan 21 03:23:13 PM PST 24
Finished Jan 21 03:24:40 PM PST 24
Peak memory 198348 kb
Host smart-5be7f495-245e-4349-9128-9144f24d75b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586902479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3586902479
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.423138652
Short name T365
Test name
Test status
Simulation time 68577080827 ps
CPU time 259.21 seconds
Started Jan 21 03:39:39 PM PST 24
Finished Jan 21 03:44:00 PM PST 24
Peak memory 206612 kb
Host smart-da709c68-a0d8-480d-a527-9500dbce2b01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=423138652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.423138652
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.603203854
Short name T765
Test name
Test status
Simulation time 15126972 ps
CPU time 0.6 seconds
Started Jan 21 03:23:26 PM PST 24
Finished Jan 21 03:23:27 PM PST 24
Peak memory 193992 kb
Host smart-8794f6f2-c0d1-4e47-aa1e-a04d8903d3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603203854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.603203854
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.440545904
Short name T747
Test name
Test status
Simulation time 109813185 ps
CPU time 0.91 seconds
Started Jan 21 03:23:25 PM PST 24
Finished Jan 21 03:23:27 PM PST 24
Peak memory 195760 kb
Host smart-11eddd03-168c-4a1e-b57b-e30b3a1d5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440545904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.440545904
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3526168672
Short name T438
Test name
Test status
Simulation time 8430912966 ps
CPU time 28.71 seconds
Started Jan 21 03:23:27 PM PST 24
Finished Jan 21 03:23:56 PM PST 24
Peak memory 197116 kb
Host smart-62cefd45-70df-449c-a670-db14da5fdd81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526168672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3526168672
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3419216101
Short name T374
Test name
Test status
Simulation time 132538093 ps
CPU time 0.99 seconds
Started Jan 21 03:23:26 PM PST 24
Finished Jan 21 03:23:28 PM PST 24
Peak memory 197068 kb
Host smart-671b99d9-3916-4931-87e3-7d39c9fb112e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419216101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3419216101
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1983287020
Short name T634
Test name
Test status
Simulation time 179130806 ps
CPU time 1.29 seconds
Started Jan 21 03:23:21 PM PST 24
Finished Jan 21 03:23:23 PM PST 24
Peak memory 196636 kb
Host smart-66e56c9c-f68f-4964-8f83-bd2a0357b944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983287020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1983287020
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3247591980
Short name T482
Test name
Test status
Simulation time 38006339 ps
CPU time 1.65 seconds
Started Jan 21 03:23:27 PM PST 24
Finished Jan 21 03:23:29 PM PST 24
Peak memory 196716 kb
Host smart-ee9ff912-5c00-4492-9ce3-07393d5bd6fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247591980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3247591980
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1631887543
Short name T834
Test name
Test status
Simulation time 93371504 ps
CPU time 1.71 seconds
Started Jan 21 05:20:55 PM PST 24
Finished Jan 21 05:20:58 PM PST 24
Peak memory 196280 kb
Host smart-1098c657-a596-4742-94fc-d9bad0593a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631887543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1631887543
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1568313656
Short name T868
Test name
Test status
Simulation time 110917500 ps
CPU time 0.9 seconds
Started Jan 21 03:23:27 PM PST 24
Finished Jan 21 03:23:29 PM PST 24
Peak memory 196636 kb
Host smart-340ffb4e-7789-41aa-b511-2ba21bc4ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568313656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1568313656
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.282380984
Short name T861
Test name
Test status
Simulation time 102468141 ps
CPU time 0.76 seconds
Started Jan 21 03:23:25 PM PST 24
Finished Jan 21 03:23:26 PM PST 24
Peak memory 195536 kb
Host smart-87f229eb-ee12-45b1-b234-c50cd4589635
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282380984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.282380984
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1518489582
Short name T872
Test name
Test status
Simulation time 508762210 ps
CPU time 6.22 seconds
Started Jan 21 03:23:26 PM PST 24
Finished Jan 21 03:23:33 PM PST 24
Peak memory 197508 kb
Host smart-7a38df26-8ae0-4e08-bcc8-28c2e0d5124a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518489582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1518489582
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2749740673
Short name T690
Test name
Test status
Simulation time 307550683 ps
CPU time 1.39 seconds
Started Jan 21 03:23:25 PM PST 24
Finished Jan 21 03:23:27 PM PST 24
Peak memory 196992 kb
Host smart-564079b0-885c-4471-ba7c-55118a06db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749740673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2749740673
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1319748358
Short name T441
Test name
Test status
Simulation time 542288822 ps
CPU time 1.46 seconds
Started Jan 21 03:23:28 PM PST 24
Finished Jan 21 03:23:30 PM PST 24
Peak memory 196588 kb
Host smart-135867fe-c1bd-4196-9438-dffe5ec29ab7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319748358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1319748358
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.40477595
Short name T715
Test name
Test status
Simulation time 1660676368 ps
CPU time 29.61 seconds
Started Jan 21 03:23:23 PM PST 24
Finished Jan 21 03:23:53 PM PST 24
Peak memory 198212 kb
Host smart-e11d3bcc-9f2e-4d6e-90d8-4ee163272130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40477595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gp
io_stress_all.40477595
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.971294237
Short name T72
Test name
Test status
Simulation time 382913395763 ps
CPU time 1868.13 seconds
Started Jan 21 03:23:29 PM PST 24
Finished Jan 21 03:54:38 PM PST 24
Peak memory 198412 kb
Host smart-517040ea-df6d-4b99-b05e-c301df69cbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=971294237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.971294237
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2459359665
Short name T332
Test name
Test status
Simulation time 30959610 ps
CPU time 0.59 seconds
Started Jan 21 03:20:35 PM PST 24
Finished Jan 21 03:20:37 PM PST 24
Peak memory 194584 kb
Host smart-f5706048-099c-45a1-9d6a-b28d4b0f1da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459359665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2459359665
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3012061225
Short name T291
Test name
Test status
Simulation time 20737187 ps
CPU time 0.68 seconds
Started Jan 21 03:20:30 PM PST 24
Finished Jan 21 03:20:31 PM PST 24
Peak memory 194864 kb
Host smart-819bb24b-4421-44bc-bf84-6b66d18520a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012061225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3012061225
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1939664792
Short name T447
Test name
Test status
Simulation time 15050226311 ps
CPU time 28.13 seconds
Started Jan 21 03:20:38 PM PST 24
Finished Jan 21 03:21:07 PM PST 24
Peak memory 197616 kb
Host smart-493ff59b-10f1-4cfd-9c1d-75c63295d982
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939664792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1939664792
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2220997194
Short name T862
Test name
Test status
Simulation time 231196174 ps
CPU time 1.04 seconds
Started Jan 21 03:20:37 PM PST 24
Finished Jan 21 03:20:39 PM PST 24
Peak memory 198044 kb
Host smart-97e40ea1-21ba-453a-979f-6bfa59cf42ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220997194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2220997194
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3635345609
Short name T718
Test name
Test status
Simulation time 90872918 ps
CPU time 0.86 seconds
Started Jan 21 03:20:35 PM PST 24
Finished Jan 21 03:20:37 PM PST 24
Peak memory 195760 kb
Host smart-a56c6c6b-fc7a-4845-a228-240e860d41d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635345609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3635345609
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1477551174
Short name T570
Test name
Test status
Simulation time 225547550 ps
CPU time 2.38 seconds
Started Jan 21 03:20:37 PM PST 24
Finished Jan 21 03:20:40 PM PST 24
Peak memory 198152 kb
Host smart-ad811975-f215-487b-bfd4-1d92362bcae2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477551174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1477551174
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1561964141
Short name T657
Test name
Test status
Simulation time 203148909 ps
CPU time 1.47 seconds
Started Jan 21 03:27:52 PM PST 24
Finished Jan 21 03:27:58 PM PST 24
Peak memory 196316 kb
Host smart-5b4663d0-0c18-4180-80d4-839f7c1a7201
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561964141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1561964141
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.377817340
Short name T574
Test name
Test status
Simulation time 165098267 ps
CPU time 0.93 seconds
Started Jan 21 03:20:38 PM PST 24
Finished Jan 21 03:20:40 PM PST 24
Peak memory 196064 kb
Host smart-eed8ed09-ef4b-4495-b22a-693c7790a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377817340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.377817340
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2671394182
Short name T423
Test name
Test status
Simulation time 55455169 ps
CPU time 1.1 seconds
Started Jan 21 03:20:33 PM PST 24
Finished Jan 21 03:20:35 PM PST 24
Peak memory 196120 kb
Host smart-16c6edf3-2e61-432e-b856-fb30415ba469
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671394182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2671394182
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3359023487
Short name T502
Test name
Test status
Simulation time 86674794 ps
CPU time 4.09 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:21:03 PM PST 24
Peak memory 198076 kb
Host smart-3527b86d-f16e-456e-ae85-399a4129bf9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359023487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3359023487
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1020372930
Short name T59
Test name
Test status
Simulation time 1575248516 ps
CPU time 0.95 seconds
Started Jan 21 03:20:35 PM PST 24
Finished Jan 21 03:20:37 PM PST 24
Peak memory 214760 kb
Host smart-1ccf5d68-85bd-4608-b5a7-9c82207da987
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020372930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1020372930
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.966305539
Short name T762
Test name
Test status
Simulation time 107762670 ps
CPU time 0.79 seconds
Started Jan 21 03:20:38 PM PST 24
Finished Jan 21 03:20:40 PM PST 24
Peak memory 195320 kb
Host smart-208d3554-e1f9-44c8-9132-dadf1406fd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966305539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.966305539
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1507681485
Short name T430
Test name
Test status
Simulation time 137408735 ps
CPU time 0.87 seconds
Started Jan 21 03:20:29 PM PST 24
Finished Jan 21 03:20:31 PM PST 24
Peak memory 196348 kb
Host smart-b2c85bfb-7e92-48e7-b449-2cec9dcb3566
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507681485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1507681485
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1145700580
Short name T706
Test name
Test status
Simulation time 13278356526 ps
CPU time 185.55 seconds
Started Jan 21 03:20:36 PM PST 24
Finished Jan 21 03:23:43 PM PST 24
Peak memory 198332 kb
Host smart-15e6f722-b3ce-4fd5-95a7-ca329dc5377c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145700580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1145700580
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1156640401
Short name T691
Test name
Test status
Simulation time 477960950700 ps
CPU time 1382.51 seconds
Started Jan 21 03:35:11 PM PST 24
Finished Jan 21 03:58:17 PM PST 24
Peak memory 198296 kb
Host smart-02f0d81f-8841-49a1-9c20-5a2741fe5dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1156640401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1156640401
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2863503752
Short name T794
Test name
Test status
Simulation time 17121549 ps
CPU time 0.6 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:23:32 PM PST 24
Peak memory 194780 kb
Host smart-b8810dad-163b-47cc-adc7-8b3d00c9cc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863503752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2863503752
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.318187707
Short name T758
Test name
Test status
Simulation time 350809543 ps
CPU time 0.79 seconds
Started Jan 21 03:23:33 PM PST 24
Finished Jan 21 03:23:34 PM PST 24
Peak memory 195976 kb
Host smart-1bc8010b-f6ae-4a08-a3ce-27a956d84a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318187707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.318187707
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1460407363
Short name T523
Test name
Test status
Simulation time 886348520 ps
CPU time 11.6 seconds
Started Jan 21 03:23:34 PM PST 24
Finished Jan 21 03:23:46 PM PST 24
Peak memory 198116 kb
Host smart-5f502b60-d239-46f4-bf49-0b61abc47008
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460407363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1460407363
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2321390389
Short name T820
Test name
Test status
Simulation time 80568613 ps
CPU time 0.87 seconds
Started Jan 21 03:23:33 PM PST 24
Finished Jan 21 03:23:34 PM PST 24
Peak memory 196104 kb
Host smart-305b9ef7-6fa3-46c1-af70-8c6790f379c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321390389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2321390389
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1020246378
Short name T840
Test name
Test status
Simulation time 311261619 ps
CPU time 1.43 seconds
Started Jan 21 03:23:33 PM PST 24
Finished Jan 21 03:23:35 PM PST 24
Peak memory 198228 kb
Host smart-28abf95c-cb72-431f-a90f-6e8e717c2b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020246378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1020246378
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2124033430
Short name T450
Test name
Test status
Simulation time 271739590 ps
CPU time 2.68 seconds
Started Jan 21 03:23:36 PM PST 24
Finished Jan 21 03:23:40 PM PST 24
Peak memory 198044 kb
Host smart-fe94ac42-29fa-43d4-b096-7a8fe3267e8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124033430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2124033430
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2260033196
Short name T646
Test name
Test status
Simulation time 603026828 ps
CPU time 3.52 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:23:36 PM PST 24
Peak memory 198056 kb
Host smart-1c3bb0d9-379b-4556-ae1f-50cc55da0fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260033196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2260033196
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2316985850
Short name T695
Test name
Test status
Simulation time 60826157 ps
CPU time 1.41 seconds
Started Jan 21 03:23:34 PM PST 24
Finished Jan 21 03:23:36 PM PST 24
Peak memory 197072 kb
Host smart-1b2080c5-3289-49af-9152-2e82be341687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316985850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2316985850
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.369713967
Short name T669
Test name
Test status
Simulation time 46663488 ps
CPU time 0.79 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:23:33 PM PST 24
Peak memory 196280 kb
Host smart-aaff06ff-bdb2-4ffd-adfb-786c29d9e7e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369713967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.369713967
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3684814374
Short name T830
Test name
Test status
Simulation time 1224912467 ps
CPU time 2.72 seconds
Started Jan 21 03:23:30 PM PST 24
Finished Jan 21 03:23:33 PM PST 24
Peak memory 198112 kb
Host smart-1d1ddd9e-c748-4d92-b4cb-5a851b7ed908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684814374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3684814374
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2599163570
Short name T727
Test name
Test status
Simulation time 383672260 ps
CPU time 1.03 seconds
Started Jan 21 03:23:26 PM PST 24
Finished Jan 21 03:23:28 PM PST 24
Peak memory 196596 kb
Host smart-0921bc6a-a422-4252-98a4-f02ca7353dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599163570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2599163570
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3939992406
Short name T743
Test name
Test status
Simulation time 162428006 ps
CPU time 1.14 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:23:33 PM PST 24
Peak memory 195960 kb
Host smart-bd152799-9e31-4189-9ba9-7ed5a0efedb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939992406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3939992406
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2036992816
Short name T641
Test name
Test status
Simulation time 6976109815 ps
CPU time 58.4 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:24:30 PM PST 24
Peak memory 198372 kb
Host smart-52279354-bf31-486b-aade-1995c6c05fd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036992816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2036992816
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2235075690
Short name T454
Test name
Test status
Simulation time 22212475560 ps
CPU time 728.55 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:35:40 PM PST 24
Peak memory 198416 kb
Host smart-e35e028b-0472-408a-923e-25d2dad566bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2235075690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2235075690
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.781262734
Short name T649
Test name
Test status
Simulation time 33275467 ps
CPU time 0.57 seconds
Started Jan 21 03:23:53 PM PST 24
Finished Jan 21 03:23:55 PM PST 24
Peak memory 194680 kb
Host smart-f1bdae83-d839-4cb4-8323-3ba87607c3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781262734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.781262734
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3558559932
Short name T497
Test name
Test status
Simulation time 90221354 ps
CPU time 0.95 seconds
Started Jan 21 03:23:40 PM PST 24
Finished Jan 21 03:23:42 PM PST 24
Peak memory 196616 kb
Host smart-730f7a1c-7ce0-487d-8ce0-a53299e72a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558559932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3558559932
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1018441481
Short name T696
Test name
Test status
Simulation time 701650744 ps
CPU time 21.05 seconds
Started Jan 21 03:23:43 PM PST 24
Finished Jan 21 03:24:05 PM PST 24
Peak memory 196832 kb
Host smart-90086cd9-268f-42b2-9364-c50ee5ee7b57
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018441481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1018441481
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.369308861
Short name T857
Test name
Test status
Simulation time 86785857 ps
CPU time 0.63 seconds
Started Jan 21 03:23:41 PM PST 24
Finished Jan 21 03:23:42 PM PST 24
Peak memory 194640 kb
Host smart-35a8a071-3171-48cc-be63-793f9c48b965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369308861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.369308861
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4041709700
Short name T841
Test name
Test status
Simulation time 72758538 ps
CPU time 1.26 seconds
Started Jan 21 03:23:38 PM PST 24
Finished Jan 21 03:23:40 PM PST 24
Peak memory 196936 kb
Host smart-02dec923-a7a4-4ce2-b991-e828541a7602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041709700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4041709700
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.298812065
Short name T694
Test name
Test status
Simulation time 32623221 ps
CPU time 1.49 seconds
Started Jan 21 03:23:40 PM PST 24
Finished Jan 21 03:23:43 PM PST 24
Peak memory 196676 kb
Host smart-8406519b-23d0-43d4-808e-6842ea8e5d0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298812065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.298812065
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1104812241
Short name T753
Test name
Test status
Simulation time 152496005 ps
CPU time 1.17 seconds
Started Jan 21 03:23:44 PM PST 24
Finished Jan 21 03:23:46 PM PST 24
Peak memory 195668 kb
Host smart-49503bdf-ec65-4b62-be6e-e815dceb3275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104812241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1104812241
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.634945675
Short name T491
Test name
Test status
Simulation time 167603000 ps
CPU time 0.98 seconds
Started Jan 21 03:23:43 PM PST 24
Finished Jan 21 03:23:45 PM PST 24
Peak memory 195884 kb
Host smart-d106e9f2-01ce-4031-99a1-a14c75b20c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634945675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.634945675
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3204880600
Short name T592
Test name
Test status
Simulation time 214442501 ps
CPU time 0.96 seconds
Started Jan 21 03:23:40 PM PST 24
Finished Jan 21 03:23:42 PM PST 24
Peak memory 196336 kb
Host smart-82bb102b-aa3a-4c4a-81b8-60fc45b29def
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204880600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3204880600
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.830394076
Short name T556
Test name
Test status
Simulation time 137057353 ps
CPU time 5.89 seconds
Started Jan 21 03:23:38 PM PST 24
Finished Jan 21 03:23:44 PM PST 24
Peak memory 197988 kb
Host smart-f0837203-d7ec-48d0-aeb3-e7c7a12faa23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830394076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.830394076
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2654759101
Short name T376
Test name
Test status
Simulation time 24619553 ps
CPU time 0.78 seconds
Started Jan 21 03:23:31 PM PST 24
Finished Jan 21 03:23:32 PM PST 24
Peak memory 195340 kb
Host smart-bdc71caa-2faf-441e-bd79-045e70f0c6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654759101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2654759101
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2876667555
Short name T800
Test name
Test status
Simulation time 85829433 ps
CPU time 1.05 seconds
Started Jan 21 03:23:40 PM PST 24
Finished Jan 21 03:23:42 PM PST 24
Peak memory 195816 kb
Host smart-e4f66de5-81b4-44f7-b7ea-98ea708e44fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876667555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2876667555
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1165997603
Short name T270
Test name
Test status
Simulation time 20960614206 ps
CPU time 239.18 seconds
Started Jan 21 03:23:54 PM PST 24
Finished Jan 21 03:27:54 PM PST 24
Peak memory 198332 kb
Host smart-78d0bcdb-a79f-4d46-9cce-ef86cc93a0af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165997603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1165997603
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1985392965
Short name T446
Test name
Test status
Simulation time 217669102261 ps
CPU time 3428.93 seconds
Started Jan 21 03:23:55 PM PST 24
Finished Jan 21 04:21:05 PM PST 24
Peak memory 198380 kb
Host smart-f6dba68f-a37a-4f60-82d3-950560f98580
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1985392965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1985392965
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.527205532
Short name T296
Test name
Test status
Simulation time 30797210 ps
CPU time 0.57 seconds
Started Jan 21 03:23:50 PM PST 24
Finished Jan 21 03:23:51 PM PST 24
Peak memory 193968 kb
Host smart-212fa883-24f1-462b-9f32-26c8f0d812bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527205532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.527205532
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2115366360
Short name T368
Test name
Test status
Simulation time 56273820 ps
CPU time 0.67 seconds
Started Jan 21 03:23:50 PM PST 24
Finished Jan 21 03:23:52 PM PST 24
Peak memory 194132 kb
Host smart-3db08df9-6543-449d-85b0-b0b21e0da77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115366360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2115366360
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2086840737
Short name T678
Test name
Test status
Simulation time 1677492503 ps
CPU time 24.05 seconds
Started Jan 21 03:24:17 PM PST 24
Finished Jan 21 03:24:44 PM PST 24
Peak memory 197012 kb
Host smart-0518c2bb-50ac-41b8-8ff5-cd30f55bd9a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086840737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2086840737
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3311563680
Short name T744
Test name
Test status
Simulation time 32232650 ps
CPU time 0.69 seconds
Started Jan 21 03:23:48 PM PST 24
Finished Jan 21 03:23:50 PM PST 24
Peak memory 194616 kb
Host smart-3025878f-61c6-4704-9348-86e71a5e9550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311563680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3311563680
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3464784559
Short name T263
Test name
Test status
Simulation time 111532778 ps
CPU time 0.9 seconds
Started Jan 21 03:23:50 PM PST 24
Finished Jan 21 03:23:52 PM PST 24
Peak memory 197608 kb
Host smart-5e25e5fe-2e7f-4ea1-9eeb-ed43488d607b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464784559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3464784559
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3691268816
Short name T732
Test name
Test status
Simulation time 51423531 ps
CPU time 2.12 seconds
Started Jan 21 03:23:54 PM PST 24
Finished Jan 21 03:23:56 PM PST 24
Peak memory 196608 kb
Host smart-49bc959e-9ef0-40fd-bd3a-0b6932f8aa72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691268816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3691268816
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.590864868
Short name T890
Test name
Test status
Simulation time 157970720 ps
CPU time 2.57 seconds
Started Jan 21 04:33:43 PM PST 24
Finished Jan 21 04:33:46 PM PST 24
Peak memory 198236 kb
Host smart-ac1cf56c-8516-4b95-ab41-28069121836a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590864868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
590864868
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.622177925
Short name T496
Test name
Test status
Simulation time 69788337 ps
CPU time 1.01 seconds
Started Jan 21 03:23:51 PM PST 24
Finished Jan 21 03:23:53 PM PST 24
Peak memory 196152 kb
Host smart-bc1edfe5-ba89-4d28-99d7-d4cec834ea16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622177925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.622177925
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3640650063
Short name T693
Test name
Test status
Simulation time 44186937 ps
CPU time 1.03 seconds
Started Jan 21 03:23:54 PM PST 24
Finished Jan 21 03:23:55 PM PST 24
Peak memory 195928 kb
Host smart-5749c1a2-4715-4f22-9984-b4ef51812067
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640650063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3640650063
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2854730394
Short name T375
Test name
Test status
Simulation time 942434839 ps
CPU time 3.69 seconds
Started Jan 21 03:32:56 PM PST 24
Finished Jan 21 03:33:13 PM PST 24
Peak memory 198092 kb
Host smart-fc9f1405-151b-4880-8d9d-7e1b1bf37ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854730394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2854730394
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4249474891
Short name T324
Test name
Test status
Simulation time 159976165 ps
CPU time 1.36 seconds
Started Jan 21 03:23:53 PM PST 24
Finished Jan 21 03:23:55 PM PST 24
Peak memory 196400 kb
Host smart-d0255d41-a70d-4a0a-b732-d36d7a87b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249474891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4249474891
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.653595110
Short name T481
Test name
Test status
Simulation time 163394006 ps
CPU time 1.19 seconds
Started Jan 21 03:23:48 PM PST 24
Finished Jan 21 03:23:50 PM PST 24
Peak memory 197024 kb
Host smart-a13b601b-8831-4080-8a9d-b12f2f4de409
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653595110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.653595110
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.260279166
Short name T604
Test name
Test status
Simulation time 9637018282 ps
CPU time 154.83 seconds
Started Jan 21 03:23:53 PM PST 24
Finished Jan 21 03:26:29 PM PST 24
Peak memory 198280 kb
Host smart-a458e310-9109-4fe8-a645-2bd13cbc0d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260279166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.260279166
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2322620131
Short name T428
Test name
Test status
Simulation time 133485808602 ps
CPU time 2369.65 seconds
Started Jan 21 03:23:55 PM PST 24
Finished Jan 21 04:03:26 PM PST 24
Peak memory 198360 kb
Host smart-6167462e-9877-47c8-a4b1-0254b951835c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2322620131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2322620131
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1594895464
Short name T636
Test name
Test status
Simulation time 66366316 ps
CPU time 0.56 seconds
Started Jan 21 03:24:00 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 194592 kb
Host smart-4ad4a56a-ba74-44ac-89bc-f858bdbf14d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594895464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1594895464
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2886322779
Short name T712
Test name
Test status
Simulation time 37502268 ps
CPU time 0.88 seconds
Started Jan 21 03:23:52 PM PST 24
Finished Jan 21 03:23:54 PM PST 24
Peak memory 196488 kb
Host smart-62d1e80d-c2dc-4dc9-a3ac-96948b4a08e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886322779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2886322779
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.207507215
Short name T95
Test name
Test status
Simulation time 644479281 ps
CPU time 16.08 seconds
Started Jan 21 03:24:00 PM PST 24
Finished Jan 21 03:24:21 PM PST 24
Peak memory 196964 kb
Host smart-e07af928-7f99-4514-8f27-2124b8257675
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207507215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.207507215
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.217823155
Short name T437
Test name
Test status
Simulation time 77933355 ps
CPU time 0.88 seconds
Started Jan 21 03:24:01 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 197800 kb
Host smart-ab3af9e5-536c-408f-ba48-d102aa79502c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217823155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.217823155
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2093095101
Short name T772
Test name
Test status
Simulation time 145461150 ps
CPU time 0.81 seconds
Started Jan 21 03:23:48 PM PST 24
Finished Jan 21 03:23:49 PM PST 24
Peak memory 195480 kb
Host smart-ba868cc6-9672-402b-add2-62bb6b2b4659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093095101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2093095101
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3230107371
Short name T624
Test name
Test status
Simulation time 188429584 ps
CPU time 2.23 seconds
Started Jan 21 03:23:50 PM PST 24
Finished Jan 21 03:23:53 PM PST 24
Peak memory 198076 kb
Host smart-c3d6b998-0c98-452e-8357-02a8f538d6cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230107371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3230107371
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2381157457
Short name T427
Test name
Test status
Simulation time 106517598 ps
CPU time 3.47 seconds
Started Jan 21 03:23:55 PM PST 24
Finished Jan 21 03:23:59 PM PST 24
Peak memory 197044 kb
Host smart-645d58cc-4319-4c3b-9275-f886e63e5bd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381157457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2381157457
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1065459201
Short name T614
Test name
Test status
Simulation time 64245471 ps
CPU time 1.22 seconds
Started Jan 21 03:23:55 PM PST 24
Finished Jan 21 03:23:57 PM PST 24
Peak memory 196948 kb
Host smart-e7c88079-93bf-4d79-b850-2911ef39671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065459201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1065459201
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.193755093
Short name T542
Test name
Test status
Simulation time 538076204 ps
CPU time 1.4 seconds
Started Jan 21 04:34:59 PM PST 24
Finished Jan 21 04:35:02 PM PST 24
Peak memory 197268 kb
Host smart-9b2d84ac-4b9c-49a8-afd6-3928c59aabfb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193755093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.193755093
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2866514267
Short name T854
Test name
Test status
Simulation time 125973218 ps
CPU time 5.76 seconds
Started Jan 21 03:24:01 PM PST 24
Finished Jan 21 03:24:11 PM PST 24
Peak memory 197504 kb
Host smart-0678acbf-51ee-4b96-a2ec-27e71a800bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866514267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2866514267
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3089038390
Short name T419
Test name
Test status
Simulation time 59243198 ps
CPU time 1.29 seconds
Started Jan 21 03:23:49 PM PST 24
Finished Jan 21 03:23:51 PM PST 24
Peak memory 197016 kb
Host smart-b54db51c-e0ff-4481-872b-26e233c6a634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089038390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3089038390
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2923893667
Short name T573
Test name
Test status
Simulation time 57029531 ps
CPU time 1.01 seconds
Started Jan 21 03:23:52 PM PST 24
Finished Jan 21 03:23:54 PM PST 24
Peak memory 196588 kb
Host smart-260d3ef3-1c0a-41be-872c-2264bb79d8f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923893667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2923893667
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1113862915
Short name T112
Test name
Test status
Simulation time 14586214900 ps
CPU time 43.68 seconds
Started Jan 21 03:24:06 PM PST 24
Finished Jan 21 03:24:56 PM PST 24
Peak memory 198392 kb
Host smart-8c203002-eadd-4a98-bcad-4e39a14d2b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113862915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1113862915
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4284324680
Short name T79
Test name
Test status
Simulation time 608169876314 ps
CPU time 1899.43 seconds
Started Jan 21 03:24:01 PM PST 24
Finished Jan 21 03:55:45 PM PST 24
Peak memory 198344 kb
Host smart-459f5a7c-c9f3-406c-8f85-4d192975df8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4284324680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.4284324680
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.640046001
Short name T608
Test name
Test status
Simulation time 30543550 ps
CPU time 0.58 seconds
Started Jan 21 03:24:03 PM PST 24
Finished Jan 21 03:24:07 PM PST 24
Peak memory 195672 kb
Host smart-26b42e69-43fc-48b6-a955-3dc2a1e2a1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640046001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.640046001
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.871871830
Short name T571
Test name
Test status
Simulation time 24878953 ps
CPU time 0.68 seconds
Started Jan 21 03:23:59 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 194292 kb
Host smart-57f7a45f-adf5-4628-b608-11533900a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871871830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.871871830
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1101396132
Short name T469
Test name
Test status
Simulation time 697533922 ps
CPU time 5.21 seconds
Started Jan 21 03:24:00 PM PST 24
Finished Jan 21 03:24:10 PM PST 24
Peak memory 196248 kb
Host smart-a399156e-9369-4b42-9db4-8dc2e00affd2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101396132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1101396132
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1720443118
Short name T539
Test name
Test status
Simulation time 77168375 ps
CPU time 0.78 seconds
Started Jan 21 03:41:14 PM PST 24
Finished Jan 21 03:41:16 PM PST 24
Peak memory 196012 kb
Host smart-a41d02aa-b9e1-41ed-98b3-da1233eb388d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720443118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1720443118
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.673433812
Short name T460
Test name
Test status
Simulation time 161248601 ps
CPU time 1.15 seconds
Started Jan 21 04:13:31 PM PST 24
Finished Jan 21 04:13:37 PM PST 24
Peak memory 196160 kb
Host smart-6a3eae06-1b8c-45d8-bc04-d81cf50ce378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673433812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.673433812
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2540688087
Short name T618
Test name
Test status
Simulation time 41934188 ps
CPU time 0.96 seconds
Started Jan 21 03:24:05 PM PST 24
Finished Jan 21 03:24:11 PM PST 24
Peak memory 193772 kb
Host smart-86314ea6-fabb-48dd-86ee-0ddb70fca85a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540688087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2540688087
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1465238144
Short name T292
Test name
Test status
Simulation time 62886169 ps
CPU time 1.09 seconds
Started Jan 21 03:24:04 PM PST 24
Finished Jan 21 03:24:10 PM PST 24
Peak memory 195272 kb
Host smart-a8f3ae49-43bd-4765-b3e6-b3ef9da5fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465238144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1465238144
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1225792537
Short name T486
Test name
Test status
Simulation time 53476690 ps
CPU time 0.76 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 195416 kb
Host smart-ba4d6953-d168-493e-8b93-6dee6ab1c966
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225792537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1225792537
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3345125321
Short name T767
Test name
Test status
Simulation time 50275331 ps
CPU time 2.47 seconds
Started Jan 21 03:24:04 PM PST 24
Finished Jan 21 03:24:11 PM PST 24
Peak memory 198184 kb
Host smart-4a3192cc-4d12-4fa5-9107-ddf8322d283e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345125321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3345125321
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3084364379
Short name T511
Test name
Test status
Simulation time 180724503 ps
CPU time 0.95 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 196184 kb
Host smart-1339ebe4-4934-45af-8c2c-efa13a33a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084364379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3084364379
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1331987972
Short name T625
Test name
Test status
Simulation time 36893433 ps
CPU time 1.15 seconds
Started Jan 21 03:24:04 PM PST 24
Finished Jan 21 03:24:11 PM PST 24
Peak memory 195692 kb
Host smart-a0a7d2b5-2125-4b1e-a0c6-2f112c093a88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331987972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1331987972
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.675937086
Short name T670
Test name
Test status
Simulation time 37229682886 ps
CPU time 98.39 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:25:44 PM PST 24
Peak memory 198316 kb
Host smart-5080cf9d-5012-4b8c-9b08-e882de44393c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675937086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.675937086
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1969579419
Short name T626
Test name
Test status
Simulation time 186345054287 ps
CPU time 854.9 seconds
Started Jan 21 03:23:58 PM PST 24
Finished Jan 21 03:38:18 PM PST 24
Peak memory 198428 kb
Host smart-cad9c8c2-20b1-415a-b513-b88f2eff2b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1969579419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1969579419
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2617656148
Short name T478
Test name
Test status
Simulation time 12560108 ps
CPU time 0.59 seconds
Started Jan 21 03:24:05 PM PST 24
Finished Jan 21 03:24:11 PM PST 24
Peak memory 193320 kb
Host smart-c5da3eb4-1127-4c1c-9265-05a32c39c2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617656148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2617656148
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3070130896
Short name T444
Test name
Test status
Simulation time 71983181 ps
CPU time 0.72 seconds
Started Jan 21 03:24:06 PM PST 24
Finished Jan 21 03:24:13 PM PST 24
Peak memory 194984 kb
Host smart-b573e279-abba-40a1-b0e4-fb40d330ef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070130896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3070130896
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3866795029
Short name T622
Test name
Test status
Simulation time 1796432050 ps
CPU time 24.14 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:24:29 PM PST 24
Peak memory 196836 kb
Host smart-7eb704b0-90dc-4b69-9868-1b82fd7ffa12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866795029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3866795029
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2843434972
Short name T484
Test name
Test status
Simulation time 682970373 ps
CPU time 0.78 seconds
Started Jan 21 03:24:00 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 194832 kb
Host smart-48681eab-42a3-4d18-9d16-4f8f046e34f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843434972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2843434972
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3994208239
Short name T588
Test name
Test status
Simulation time 46960299 ps
CPU time 1.34 seconds
Started Jan 21 03:24:04 PM PST 24
Finished Jan 21 03:24:10 PM PST 24
Peak memory 198176 kb
Host smart-36932dc5-a9c9-4005-b3a4-3f0c485e3bdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994208239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3994208239
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1589832822
Short name T564
Test name
Test status
Simulation time 76275097 ps
CPU time 3.13 seconds
Started Jan 21 03:28:04 PM PST 24
Finished Jan 21 03:28:08 PM PST 24
Peak memory 196560 kb
Host smart-31c8cb6c-8666-4585-9b68-bb9965474996
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589832822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1589832822
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1659456567
Short name T751
Test name
Test status
Simulation time 766983903 ps
CPU time 3.03 seconds
Started Jan 21 03:24:03 PM PST 24
Finished Jan 21 03:24:09 PM PST 24
Peak memory 196820 kb
Host smart-07f7655f-4bd8-4bcb-93a3-960c8c616020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659456567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1659456567
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3786203324
Short name T434
Test name
Test status
Simulation time 68059983 ps
CPU time 0.84 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 196356 kb
Host smart-efdb66d6-a426-4a80-9ac0-e4386a07af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786203324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3786203324
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1382087442
Short name T883
Test name
Test status
Simulation time 122496105 ps
CPU time 0.92 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 197096 kb
Host smart-e3baed10-a12f-41a8-9878-5f9e424d273d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382087442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1382087442
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3938189739
Short name T260
Test name
Test status
Simulation time 379540885 ps
CPU time 2.45 seconds
Started Jan 21 03:24:01 PM PST 24
Finished Jan 21 03:24:08 PM PST 24
Peak memory 198124 kb
Host smart-ab79d5eb-7581-4a87-bec8-70a82e394286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938189739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3938189739
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.4280755608
Short name T593
Test name
Test status
Simulation time 70844931 ps
CPU time 1.23 seconds
Started Jan 21 03:24:00 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 196888 kb
Host smart-076c7c62-cda1-48e0-be6d-c82ce02ee895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280755608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4280755608
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3420562084
Short name T723
Test name
Test status
Simulation time 45277114 ps
CPU time 0.94 seconds
Started Jan 21 03:24:01 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 196268 kb
Host smart-a11d9e75-4412-469f-a725-7b3ad32c10ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420562084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3420562084
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2024495769
Short name T843
Test name
Test status
Simulation time 5869636107 ps
CPU time 156.35 seconds
Started Jan 21 03:24:06 PM PST 24
Finished Jan 21 03:26:49 PM PST 24
Peak memory 198348 kb
Host smart-17df4769-28ec-4f23-8489-7743fddedfd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024495769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2024495769
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3052251260
Short name T707
Test name
Test status
Simulation time 90340203480 ps
CPU time 1894.81 seconds
Started Jan 21 03:24:04 PM PST 24
Finished Jan 21 03:55:44 PM PST 24
Peak memory 197724 kb
Host smart-ba63e037-72a4-4318-9439-e527203b08ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3052251260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3052251260
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3347820126
Short name T606
Test name
Test status
Simulation time 41478541 ps
CPU time 0.65 seconds
Started Jan 21 03:24:15 PM PST 24
Finished Jan 21 03:24:20 PM PST 24
Peak memory 194080 kb
Host smart-ab81e02a-24c7-488c-a307-e8c0cbd77ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347820126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3347820126
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2382605375
Short name T275
Test name
Test status
Simulation time 78970722 ps
CPU time 0.65 seconds
Started Jan 21 03:24:14 PM PST 24
Finished Jan 21 03:24:20 PM PST 24
Peak memory 194212 kb
Host smart-9491fe43-ad03-4904-a0d5-e148a0ac1b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382605375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2382605375
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2005759405
Short name T249
Test name
Test status
Simulation time 71420793 ps
CPU time 3.58 seconds
Started Jan 21 03:24:18 PM PST 24
Finished Jan 21 03:24:27 PM PST 24
Peak memory 196132 kb
Host smart-4801678a-620d-48cd-9d40-5f4d7cb6eaee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005759405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2005759405
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3673391162
Short name T775
Test name
Test status
Simulation time 77142684 ps
CPU time 0.73 seconds
Started Jan 21 03:24:19 PM PST 24
Finished Jan 21 03:24:25 PM PST 24
Peak memory 196508 kb
Host smart-00b15a46-02de-473d-9aa9-dcf8349e48a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673391162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3673391162
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2312725269
Short name T659
Test name
Test status
Simulation time 34731885 ps
CPU time 0.8 seconds
Started Jan 21 03:24:11 PM PST 24
Finished Jan 21 03:24:18 PM PST 24
Peak memory 196180 kb
Host smart-e382dde4-b237-41e6-b5e9-722e8ad32017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312725269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2312725269
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2466749135
Short name T532
Test name
Test status
Simulation time 241361640 ps
CPU time 2.22 seconds
Started Jan 21 03:24:15 PM PST 24
Finished Jan 21 03:24:22 PM PST 24
Peak memory 196352 kb
Host smart-8be37aa9-d8ed-40ee-bbb7-b4d6ab18d255
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466749135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2466749135
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2856444554
Short name T658
Test name
Test status
Simulation time 1034961873 ps
CPU time 1.75 seconds
Started Jan 21 03:24:09 PM PST 24
Finished Jan 21 03:24:15 PM PST 24
Peak memory 196324 kb
Host smart-cc8ed07f-73eb-43d7-8ac5-671253e0911b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856444554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2856444554
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2564542340
Short name T313
Test name
Test status
Simulation time 50570017 ps
CPU time 1.21 seconds
Started Jan 21 03:24:19 PM PST 24
Finished Jan 21 03:24:25 PM PST 24
Peak memory 196148 kb
Host smart-91fc7ae6-b3f1-4881-942b-43470e1fbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564542340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2564542340
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.569149603
Short name T774
Test name
Test status
Simulation time 54414468 ps
CPU time 1.13 seconds
Started Jan 21 03:24:15 PM PST 24
Finished Jan 21 03:24:21 PM PST 24
Peak memory 196208 kb
Host smart-ad77b1ee-8fc5-4137-a243-9c48ae968111
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569149603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.569149603
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1739428987
Short name T764
Test name
Test status
Simulation time 609378849 ps
CPU time 4.14 seconds
Started Jan 21 03:24:16 PM PST 24
Finished Jan 21 03:24:24 PM PST 24
Peak memory 198076 kb
Host smart-b571381d-47f3-4b33-b512-dcd1cdf568c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739428987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1739428987
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.493501242
Short name T736
Test name
Test status
Simulation time 34295718 ps
CPU time 0.87 seconds
Started Jan 21 03:24:02 PM PST 24
Finished Jan 21 03:24:06 PM PST 24
Peak memory 194744 kb
Host smart-c9a9f9e1-ffb2-4e6f-bbea-714fe143078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493501242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.493501242
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2237800806
Short name T881
Test name
Test status
Simulation time 46929541 ps
CPU time 0.97 seconds
Started Jan 21 03:24:11 PM PST 24
Finished Jan 21 03:24:18 PM PST 24
Peak memory 195752 kb
Host smart-8c9a52b6-142c-4d73-88a2-6ad058296252
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237800806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2237800806
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2769910285
Short name T443
Test name
Test status
Simulation time 28415712876 ps
CPU time 187.71 seconds
Started Jan 21 03:24:15 PM PST 24
Finished Jan 21 03:27:27 PM PST 24
Peak memory 198280 kb
Host smart-72a577c0-51f2-4bcd-b00f-251f79dee3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769910285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2769910285
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.834347007
Short name T878
Test name
Test status
Simulation time 10079039079 ps
CPU time 144.53 seconds
Started Jan 21 03:24:14 PM PST 24
Finished Jan 21 03:26:44 PM PST 24
Peak memory 198336 kb
Host smart-a7fa1741-0f6b-4f1f-a8ac-e7eb9bebeb89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=834347007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.834347007
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2507500587
Short name T422
Test name
Test status
Simulation time 48109108 ps
CPU time 0.6 seconds
Started Jan 21 03:24:21 PM PST 24
Finished Jan 21 03:24:25 PM PST 24
Peak memory 194144 kb
Host smart-729048c2-0bc9-43e6-95c8-0a493efde435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507500587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2507500587
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.155515334
Short name T576
Test name
Test status
Simulation time 142670784 ps
CPU time 0.9 seconds
Started Jan 21 03:24:20 PM PST 24
Finished Jan 21 03:24:25 PM PST 24
Peak memory 196092 kb
Host smart-52bf6964-7057-4927-b6fb-5310307d782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155515334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.155515334
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.838097122
Short name T534
Test name
Test status
Simulation time 189614190 ps
CPU time 9.34 seconds
Started Jan 21 03:24:18 PM PST 24
Finished Jan 21 03:24:33 PM PST 24
Peak memory 197356 kb
Host smart-5c54085e-e146-4340-8f69-ac004ac24179
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838097122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.838097122
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2777321044
Short name T594
Test name
Test status
Simulation time 62785088 ps
CPU time 0.95 seconds
Started Jan 21 03:24:17 PM PST 24
Finished Jan 21 03:24:22 PM PST 24
Peak memory 197720 kb
Host smart-1926cfa1-dd9f-414a-8473-e841777fbb1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777321044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2777321044
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2292090388
Short name T385
Test name
Test status
Simulation time 53651356 ps
CPU time 1.05 seconds
Started Jan 21 03:24:17 PM PST 24
Finished Jan 21 03:24:21 PM PST 24
Peak memory 196744 kb
Host smart-3a03c5e2-b7a6-421c-acd8-12f06f13d3e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292090388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2292090388
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4059185425
Short name T681
Test name
Test status
Simulation time 73786311 ps
CPU time 1.73 seconds
Started Jan 21 03:24:22 PM PST 24
Finished Jan 21 03:24:27 PM PST 24
Peak memory 198160 kb
Host smart-5f4bd1cf-581a-4c49-a018-1af12e068ed8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059185425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4059185425
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2205893213
Short name T414
Test name
Test status
Simulation time 445711723 ps
CPU time 2.97 seconds
Started Jan 21 03:24:21 PM PST 24
Finished Jan 21 03:24:28 PM PST 24
Peak memory 198164 kb
Host smart-519beaca-d3c6-48ff-b60a-9ec915ba923e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205893213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2205893213
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4187738786
Short name T347
Test name
Test status
Simulation time 49066006 ps
CPU time 1.03 seconds
Started Jan 21 03:24:17 PM PST 24
Finished Jan 21 03:24:22 PM PST 24
Peak memory 196572 kb
Host smart-eb537922-0bda-401b-acf8-57f394884db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187738786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4187738786
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3375375298
Short name T421
Test name
Test status
Simulation time 125765107 ps
CPU time 1.02 seconds
Started Jan 21 03:24:22 PM PST 24
Finished Jan 21 03:24:26 PM PST 24
Peak memory 196168 kb
Host smart-cb0555b0-348e-4d84-8534-3ec78a542807
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375375298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3375375298
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2015087407
Short name T600
Test name
Test status
Simulation time 334808234 ps
CPU time 5.54 seconds
Started Jan 21 03:24:20 PM PST 24
Finished Jan 21 03:24:30 PM PST 24
Peak memory 198036 kb
Host smart-6e7139ef-f9e1-4761-b70d-438ef0da76f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015087407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2015087407
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2213543340
Short name T384
Test name
Test status
Simulation time 213107662 ps
CPU time 1.02 seconds
Started Jan 21 03:24:19 PM PST 24
Finished Jan 21 03:24:25 PM PST 24
Peak memory 195708 kb
Host smart-d92d107c-a8c4-4223-801a-4deb851438e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213543340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2213543340
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.349044038
Short name T565
Test name
Test status
Simulation time 248641727 ps
CPU time 1.11 seconds
Started Jan 21 03:24:22 PM PST 24
Finished Jan 21 03:24:26 PM PST 24
Peak memory 195700 kb
Host smart-7aff34a5-c052-4767-b047-72e889ed8782
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349044038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.349044038
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2967985146
Short name T474
Test name
Test status
Simulation time 9283181425 ps
CPU time 136.71 seconds
Started Jan 21 03:24:18 PM PST 24
Finished Jan 21 03:26:40 PM PST 24
Peak memory 198564 kb
Host smart-8691a18e-daf3-496a-9cd3-88d509681dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967985146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2967985146
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.884147248
Short name T837
Test name
Test status
Simulation time 57949751201 ps
CPU time 207.41 seconds
Started Jan 21 03:24:15 PM PST 24
Finished Jan 21 03:27:47 PM PST 24
Peak memory 206620 kb
Host smart-598bb9bd-6487-4d7b-ac13-44f7f5d9acaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=884147248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.884147248
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2305863141
Short name T409
Test name
Test status
Simulation time 14800414 ps
CPU time 0.59 seconds
Started Jan 21 03:24:29 PM PST 24
Finished Jan 21 03:24:31 PM PST 24
Peak memory 194696 kb
Host smart-715cd4ee-6c19-4be7-b20c-06ed0097dc29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305863141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2305863141
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2456110598
Short name T545
Test name
Test status
Simulation time 180118178 ps
CPU time 0.83 seconds
Started Jan 21 03:24:30 PM PST 24
Finished Jan 21 03:24:32 PM PST 24
Peak memory 195436 kb
Host smart-4a63dd4c-1d68-49df-bc30-88f58ec84a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456110598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2456110598
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1115514339
Short name T711
Test name
Test status
Simulation time 284286372 ps
CPU time 5.1 seconds
Started Jan 21 03:24:30 PM PST 24
Finished Jan 21 03:24:37 PM PST 24
Peak memory 196612 kb
Host smart-4adb944c-00ba-40bc-ab86-b426c47e4a46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115514339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1115514339
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1214267588
Short name T451
Test name
Test status
Simulation time 152728530 ps
CPU time 0.95 seconds
Started Jan 21 03:24:26 PM PST 24
Finished Jan 21 03:24:28 PM PST 24
Peak memory 197204 kb
Host smart-211ed2da-6d7b-4785-9d33-602b3152e6f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214267588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1214267588
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1721532932
Short name T810
Test name
Test status
Simulation time 52767595 ps
CPU time 1.3 seconds
Started Jan 21 03:24:26 PM PST 24
Finished Jan 21 03:24:29 PM PST 24
Peak memory 197248 kb
Host smart-34106f85-9536-410d-ab8b-d674d0d92f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721532932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1721532932
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4031285528
Short name T613
Test name
Test status
Simulation time 85023289 ps
CPU time 1.91 seconds
Started Jan 21 03:24:30 PM PST 24
Finished Jan 21 03:24:33 PM PST 24
Peak memory 198064 kb
Host smart-89c26213-87ac-40e3-b8fd-bff831c2bcd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031285528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4031285528
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3780156937
Short name T483
Test name
Test status
Simulation time 126184926 ps
CPU time 0.99 seconds
Started Jan 21 03:24:29 PM PST 24
Finished Jan 21 03:24:31 PM PST 24
Peak memory 195484 kb
Host smart-e1342a4f-e25d-4a0c-a146-248ad7e8b3b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780156937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3780156937
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3690810898
Short name T479
Test name
Test status
Simulation time 71827784 ps
CPU time 0.82 seconds
Started Jan 21 03:24:15 PM PST 24
Finished Jan 21 03:24:21 PM PST 24
Peak memory 197260 kb
Host smart-114e864e-5ce0-4616-9041-983c717c88e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690810898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3690810898
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3681755301
Short name T322
Test name
Test status
Simulation time 35967009 ps
CPU time 0.7 seconds
Started Jan 21 03:24:25 PM PST 24
Finished Jan 21 03:24:27 PM PST 24
Peak memory 194680 kb
Host smart-effe7eb7-388b-4af5-87ec-6aede419b0c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681755301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3681755301
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4235406260
Short name T229
Test name
Test status
Simulation time 216136460 ps
CPU time 3.67 seconds
Started Jan 21 03:24:29 PM PST 24
Finished Jan 21 03:24:33 PM PST 24
Peak memory 198112 kb
Host smart-e0b71ef0-0240-46f9-9678-240bc4cd1cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235406260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4235406260
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3326895815
Short name T807
Test name
Test status
Simulation time 151915457 ps
CPU time 0.95 seconds
Started Jan 21 03:24:22 PM PST 24
Finished Jan 21 03:24:26 PM PST 24
Peak memory 196580 kb
Host smart-130908a0-ceca-48dc-a7ff-cd4ae7baea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326895815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3326895815
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1425531569
Short name T846
Test name
Test status
Simulation time 46362836 ps
CPU time 0.93 seconds
Started Jan 21 03:24:22 PM PST 24
Finished Jan 21 03:24:26 PM PST 24
Peak memory 196084 kb
Host smart-34713c75-b1d6-43ee-b541-af01b78c4b67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425531569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1425531569
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2023175029
Short name T301
Test name
Test status
Simulation time 23490153308 ps
CPU time 168.13 seconds
Started Jan 21 03:24:30 PM PST 24
Finished Jan 21 03:27:19 PM PST 24
Peak memory 198272 kb
Host smart-b39432e6-188c-49cf-afdc-7b4e3b62d712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023175029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2023175029
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2157588912
Short name T521
Test name
Test status
Simulation time 148594803447 ps
CPU time 1937.17 seconds
Started Jan 21 03:24:28 PM PST 24
Finished Jan 21 03:56:46 PM PST 24
Peak memory 198392 kb
Host smart-1621f666-69f9-4c83-86cd-6e6e611172ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2157588912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2157588912
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3150312226
Short name T782
Test name
Test status
Simulation time 22408922 ps
CPU time 0.55 seconds
Started Jan 21 03:24:43 PM PST 24
Finished Jan 21 03:24:51 PM PST 24
Peak memory 193972 kb
Host smart-10ba15ec-1d67-48eb-a010-a2cf53630811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150312226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3150312226
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2971065352
Short name T647
Test name
Test status
Simulation time 222660129 ps
CPU time 0.81 seconds
Started Jan 21 03:24:39 PM PST 24
Finished Jan 21 03:24:43 PM PST 24
Peak memory 195500 kb
Host smart-1d2037a6-39dc-4e4d-a583-09e5c4451f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971065352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2971065352
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1514949985
Short name T603
Test name
Test status
Simulation time 889395638 ps
CPU time 15.09 seconds
Started Jan 21 03:24:40 PM PST 24
Finished Jan 21 03:24:58 PM PST 24
Peak memory 198064 kb
Host smart-6de4f32e-3f16-4d47-8c0d-e9ce53aa86aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514949985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1514949985
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.559874647
Short name T425
Test name
Test status
Simulation time 70072146 ps
CPU time 0.99 seconds
Started Jan 21 03:24:40 PM PST 24
Finished Jan 21 03:24:44 PM PST 24
Peak memory 197288 kb
Host smart-21795e67-8c23-4b5f-9cd3-310daa6870a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559874647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.559874647
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2994650447
Short name T550
Test name
Test status
Simulation time 47610131 ps
CPU time 0.69 seconds
Started Jan 21 03:24:39 PM PST 24
Finished Jan 21 03:24:42 PM PST 24
Peak memory 194460 kb
Host smart-df42f98c-ce83-4fb4-a881-0a1d99b4d7cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994650447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2994650447
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.998781868
Short name T675
Test name
Test status
Simulation time 110419882 ps
CPU time 3.75 seconds
Started Jan 21 03:46:53 PM PST 24
Finished Jan 21 03:47:03 PM PST 24
Peak memory 198268 kb
Host smart-093ef644-ef45-4b01-9a56-1f6e182bc925
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998781868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.998781868
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.408915842
Short name T403
Test name
Test status
Simulation time 124745488 ps
CPU time 2.77 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:24:44 PM PST 24
Peak memory 197240 kb
Host smart-43199b16-4edf-460e-9124-29ae7fb2fea9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408915842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
408915842
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3010972183
Short name T733
Test name
Test status
Simulation time 89406275 ps
CPU time 0.85 seconds
Started Jan 21 03:47:27 PM PST 24
Finished Jan 21 03:47:30 PM PST 24
Peak memory 195584 kb
Host smart-375b451c-4ade-4de1-8578-a09f7435cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010972183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3010972183
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2711563850
Short name T281
Test name
Test status
Simulation time 24612979 ps
CPU time 0.66 seconds
Started Jan 21 03:24:27 PM PST 24
Finished Jan 21 03:24:29 PM PST 24
Peak memory 195020 kb
Host smart-0833a115-ee96-40e7-a651-df97572984a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711563850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2711563850
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3149807506
Short name T328
Test name
Test status
Simulation time 73915395 ps
CPU time 1.72 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:24:41 PM PST 24
Peak memory 198116 kb
Host smart-8524ed22-f3d1-4c9d-b439-baad0f9bf7bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149807506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3149807506
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.818567790
Short name T271
Test name
Test status
Simulation time 54039713 ps
CPU time 1.42 seconds
Started Jan 21 03:24:30 PM PST 24
Finished Jan 21 03:24:33 PM PST 24
Peak memory 195728 kb
Host smart-b6b90dde-18c3-4f13-a1d1-93ff0bdd134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818567790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.818567790
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.785139197
Short name T823
Test name
Test status
Simulation time 45010007 ps
CPU time 0.98 seconds
Started Jan 21 03:24:26 PM PST 24
Finished Jan 21 03:24:28 PM PST 24
Peak memory 196524 kb
Host smart-0b5b45e0-ee89-4ab0-9ae8-a8779333a3a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785139197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.785139197
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1896330100
Short name T858
Test name
Test status
Simulation time 3604803803 ps
CPU time 44.3 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:25:25 PM PST 24
Peak memory 198188 kb
Host smart-8f72dc9f-f343-4ba0-bc4c-c6b23cf3f9e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896330100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1896330100
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3945698249
Short name T684
Test name
Test status
Simulation time 121248780009 ps
CPU time 802.63 seconds
Started Jan 21 03:24:40 PM PST 24
Finished Jan 21 03:38:06 PM PST 24
Peak memory 198364 kb
Host smart-d88f6398-e67a-4a9f-b30a-759363d23fb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3945698249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3945698249
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1610015041
Short name T738
Test name
Test status
Simulation time 37311464 ps
CPU time 0.57 seconds
Started Jan 21 03:49:13 PM PST 24
Finished Jan 21 03:49:15 PM PST 24
Peak memory 194100 kb
Host smart-ee6231af-e54b-4595-a9a9-3f16d67a8b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610015041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1610015041
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2210072604
Short name T653
Test name
Test status
Simulation time 27370883 ps
CPU time 0.72 seconds
Started Jan 21 03:35:59 PM PST 24
Finished Jan 21 03:36:01 PM PST 24
Peak memory 194264 kb
Host smart-a03fa627-c794-45d5-8b27-06363d271a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210072604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2210072604
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1895384491
Short name T586
Test name
Test status
Simulation time 1493984339 ps
CPU time 21.68 seconds
Started Jan 21 03:20:42 PM PST 24
Finished Jan 21 03:21:06 PM PST 24
Peak memory 197068 kb
Host smart-e9833422-d889-4bbf-98a1-9d58a820d51d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895384491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1895384491
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3008561859
Short name T45
Test name
Test status
Simulation time 101506826 ps
CPU time 0.79 seconds
Started Jan 21 03:20:48 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 196732 kb
Host smart-5bd0bb53-bed5-4de6-996f-2286767d2169
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008561859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3008561859
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2602885457
Short name T113
Test name
Test status
Simulation time 53014101 ps
CPU time 0.95 seconds
Started Jan 21 03:20:45 PM PST 24
Finished Jan 21 03:20:48 PM PST 24
Peak memory 195964 kb
Host smart-021002e1-ae41-4b6d-9f2a-2cca2283b435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602885457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2602885457
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.373903057
Short name T748
Test name
Test status
Simulation time 161752080 ps
CPU time 1.69 seconds
Started Jan 21 03:20:41 PM PST 24
Finished Jan 21 03:20:45 PM PST 24
Peak memory 197116 kb
Host smart-9ace76e4-94d0-49cc-9a3b-0ca75a73f665
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373903057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.373903057
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1703941517
Short name T863
Test name
Test status
Simulation time 89394476 ps
CPU time 2.7 seconds
Started Jan 21 03:20:39 PM PST 24
Finished Jan 21 03:20:44 PM PST 24
Peak memory 196908 kb
Host smart-3d4b2838-0516-43e5-bdbd-e6a70f34b136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703941517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1703941517
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3870956555
Short name T410
Test name
Test status
Simulation time 71580057 ps
CPU time 0.92 seconds
Started Jan 21 03:20:40 PM PST 24
Finished Jan 21 03:20:43 PM PST 24
Peak memory 197468 kb
Host smart-e8d1fa21-3db2-46e3-b3d1-1e63af4f17b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870956555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3870956555
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.279875585
Short name T648
Test name
Test status
Simulation time 157743480 ps
CPU time 0.96 seconds
Started Jan 21 03:20:37 PM PST 24
Finished Jan 21 03:20:39 PM PST 24
Peak memory 196716 kb
Host smart-ad0eb5b7-0076-4e32-b5a9-52189cf52ff7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279875585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.279875585
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.952383729
Short name T412
Test name
Test status
Simulation time 48454726 ps
CPU time 1.32 seconds
Started Jan 21 03:20:48 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 198204 kb
Host smart-595cfc44-d5e3-403b-81b8-8d62cdc97a29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952383729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.952383729
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3164531681
Short name T27
Test name
Test status
Simulation time 147886695 ps
CPU time 0.81 seconds
Started Jan 21 03:20:39 PM PST 24
Finished Jan 21 03:20:42 PM PST 24
Peak memory 213628 kb
Host smart-1373ef72-75e0-4a58-98cd-d23f799e42b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164531681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3164531681
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2107141601
Short name T247
Test name
Test status
Simulation time 73358134 ps
CPU time 1.17 seconds
Started Jan 21 03:20:39 PM PST 24
Finished Jan 21 03:20:42 PM PST 24
Peak memory 196808 kb
Host smart-665d17cd-a569-4f01-9d3e-392e611ab682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107141601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2107141601
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3616808236
Short name T825
Test name
Test status
Simulation time 139926976 ps
CPU time 1.37 seconds
Started Jan 21 03:20:44 PM PST 24
Finished Jan 21 03:20:47 PM PST 24
Peak memory 196892 kb
Host smart-58ae6e18-5131-4789-984d-cc791a87fca7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616808236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3616808236
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3473781784
Short name T63
Test name
Test status
Simulation time 11959353714 ps
CPU time 167.26 seconds
Started Jan 21 03:20:41 PM PST 24
Finished Jan 21 03:23:30 PM PST 24
Peak memory 198308 kb
Host smart-e06fa929-a727-434d-a06c-1476a2513aa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473781784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3473781784
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3527426332
Short name T589
Test name
Test status
Simulation time 28810646532 ps
CPU time 454.29 seconds
Started Jan 21 03:20:45 PM PST 24
Finished Jan 21 03:28:21 PM PST 24
Peak memory 198380 kb
Host smart-8a164f8b-4f65-4fb9-8aa5-820be1fa3002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3527426332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3527426332
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.158777864
Short name T610
Test name
Test status
Simulation time 71913596 ps
CPU time 0.61 seconds
Started Jan 21 03:40:43 PM PST 24
Finished Jan 21 03:40:44 PM PST 24
Peak memory 193940 kb
Host smart-f7e3e783-6a01-401e-a849-9a0a899f6766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158777864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.158777864
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2597970936
Short name T230
Test name
Test status
Simulation time 37288439 ps
CPU time 0.84 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:24:40 PM PST 24
Peak memory 196088 kb
Host smart-225bdd6e-4262-458d-b770-483f91be95ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597970936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2597970936
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3304424621
Short name T882
Test name
Test status
Simulation time 914493793 ps
CPU time 23.27 seconds
Started Jan 21 03:46:53 PM PST 24
Finished Jan 21 03:47:23 PM PST 24
Peak memory 197044 kb
Host smart-b503c798-74f1-49e7-b3ed-9b95d339ec53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304424621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3304424621
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3861412965
Short name T64
Test name
Test status
Simulation time 350012297 ps
CPU time 0.75 seconds
Started Jan 21 03:46:53 PM PST 24
Finished Jan 21 03:47:00 PM PST 24
Peak memory 196252 kb
Host smart-3a452dff-0b82-4f8a-aa98-fc5d6f83ae27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861412965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3861412965
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2026140446
Short name T234
Test name
Test status
Simulation time 247623723 ps
CPU time 1.15 seconds
Started Jan 21 03:24:39 PM PST 24
Finished Jan 21 03:24:43 PM PST 24
Peak memory 196200 kb
Host smart-329441c9-7ed1-425f-b8d0-7074de3257c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026140446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2026140446
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2251775916
Short name T337
Test name
Test status
Simulation time 261369248 ps
CPU time 2.92 seconds
Started Jan 21 03:24:40 PM PST 24
Finished Jan 21 03:24:46 PM PST 24
Peak memory 198132 kb
Host smart-cf0f60cb-8693-449e-b349-8bd886febb11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251775916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2251775916
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3640566638
Short name T307
Test name
Test status
Simulation time 321590720 ps
CPU time 2.83 seconds
Started Jan 21 03:24:40 PM PST 24
Finished Jan 21 03:24:46 PM PST 24
Peak memory 197368 kb
Host smart-6d14139c-4811-43c2-ac45-8e60d13183b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640566638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3640566638
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3537571237
Short name T350
Test name
Test status
Simulation time 333218705 ps
CPU time 1.3 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:24:42 PM PST 24
Peak memory 198168 kb
Host smart-a7917d46-9ad2-4892-9e84-72670e2c7030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537571237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3537571237
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4129470008
Short name T756
Test name
Test status
Simulation time 75094687 ps
CPU time 0.84 seconds
Started Jan 21 03:24:44 PM PST 24
Finished Jan 21 03:24:52 PM PST 24
Peak memory 196756 kb
Host smart-7f1853b2-18b7-4e72-90c8-091663e81bb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129470008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4129470008
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.157563084
Short name T449
Test name
Test status
Simulation time 72812848 ps
CPU time 1.79 seconds
Started Jan 21 03:24:52 PM PST 24
Finished Jan 21 03:24:58 PM PST 24
Peak memory 198156 kb
Host smart-e7247fd5-47c2-4ba1-9971-a09121cbe783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157563084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.157563084
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2014760512
Short name T378
Test name
Test status
Simulation time 113277204 ps
CPU time 0.99 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:24:42 PM PST 24
Peak memory 196576 kb
Host smart-51bf2b19-c6ea-474d-9fb3-b1da11077892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014760512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2014760512
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.889861298
Short name T620
Test name
Test status
Simulation time 181611848 ps
CPU time 1.04 seconds
Started Jan 21 03:24:38 PM PST 24
Finished Jan 21 03:24:42 PM PST 24
Peak memory 196008 kb
Host smart-bb08f273-f1ee-4e7e-9f29-42c748650843
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889861298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.889861298
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3419207724
Short name T578
Test name
Test status
Simulation time 6910852916 ps
CPU time 208.64 seconds
Started Jan 21 03:40:43 PM PST 24
Finished Jan 21 03:44:13 PM PST 24
Peak memory 198360 kb
Host smart-f3f0aa9f-f133-4c36-b9f1-74389bd4852a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419207724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3419207724
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2797962410
Short name T264
Test name
Test status
Simulation time 175448153492 ps
CPU time 2297.57 seconds
Started Jan 21 05:14:29 PM PST 24
Finished Jan 21 05:53:23 PM PST 24
Peak memory 198376 kb
Host smart-c205442b-b568-4bfd-a9a3-f08b8cdd9b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2797962410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2797962410
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2606413154
Short name T279
Test name
Test status
Simulation time 15003805 ps
CPU time 0.62 seconds
Started Jan 21 03:24:59 PM PST 24
Finished Jan 21 03:25:02 PM PST 24
Peak memory 193992 kb
Host smart-4982da9f-aa74-4475-8ff8-b52297e5d3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606413154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2606413154
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3320805382
Short name T294
Test name
Test status
Simulation time 32074976 ps
CPU time 0.91 seconds
Started Jan 21 04:08:07 PM PST 24
Finished Jan 21 04:08:11 PM PST 24
Peak memory 196784 kb
Host smart-521b07de-704c-4897-a591-afb4cb1ed7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320805382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3320805382
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.145497975
Short name T683
Test name
Test status
Simulation time 1290867000 ps
CPU time 9.88 seconds
Started Jan 21 03:24:52 PM PST 24
Finished Jan 21 03:25:06 PM PST 24
Peak memory 197180 kb
Host smart-422726ac-94d3-4057-816a-5c9c2301bfcb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145497975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.145497975
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.37379834
Short name T742
Test name
Test status
Simulation time 81967269 ps
CPU time 1.04 seconds
Started Jan 21 03:25:00 PM PST 24
Finished Jan 21 03:25:03 PM PST 24
Peak memory 198020 kb
Host smart-5270d20e-f254-4753-b6ce-1e41d49af004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37379834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.37379834
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.667047702
Short name T417
Test name
Test status
Simulation time 86013695 ps
CPU time 1.23 seconds
Started Jan 21 03:24:55 PM PST 24
Finished Jan 21 03:24:58 PM PST 24
Peak memory 196204 kb
Host smart-ea9fdd4a-f888-46b4-84be-e7e0dc9de561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667047702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.667047702
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3126423854
Short name T842
Test name
Test status
Simulation time 526794768 ps
CPU time 2.12 seconds
Started Jan 21 03:24:53 PM PST 24
Finished Jan 21 03:24:59 PM PST 24
Peak memory 198168 kb
Host smart-5280034b-e458-497c-b0f4-6a2870ec4eee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126423854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3126423854
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.181451331
Short name T97
Test name
Test status
Simulation time 112184666 ps
CPU time 1.35 seconds
Started Jan 21 03:24:59 PM PST 24
Finished Jan 21 03:25:02 PM PST 24
Peak memory 196940 kb
Host smart-6c358b20-56dd-4cf4-ba1c-4ab9e9a54918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181451331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
181451331
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.677339316
Short name T309
Test name
Test status
Simulation time 130063109 ps
CPU time 1.16 seconds
Started Jan 21 03:24:57 PM PST 24
Finished Jan 21 03:24:59 PM PST 24
Peak memory 197196 kb
Host smart-7bda865a-6861-4722-8e6a-30127dcd9d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677339316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.677339316
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1312513009
Short name T700
Test name
Test status
Simulation time 62319660 ps
CPU time 0.87 seconds
Started Jan 21 03:42:04 PM PST 24
Finished Jan 21 03:42:06 PM PST 24
Peak memory 196676 kb
Host smart-a1c9bf1a-401a-43c2-8274-15597f93b90a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312513009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1312513009
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2565273102
Short name T553
Test name
Test status
Simulation time 119396756 ps
CPU time 5.71 seconds
Started Jan 21 03:24:51 PM PST 24
Finished Jan 21 03:25:01 PM PST 24
Peak memory 198028 kb
Host smart-142663c8-e520-4a84-ad92-556c2d5d1e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565273102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2565273102
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1616061055
Short name T639
Test name
Test status
Simulation time 67069441 ps
CPU time 1.23 seconds
Started Jan 21 03:24:49 PM PST 24
Finished Jan 21 03:24:54 PM PST 24
Peak memory 195668 kb
Host smart-b0580e42-95ba-4479-a557-3653953fa1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616061055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1616061055
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.253936405
Short name T562
Test name
Test status
Simulation time 106534381 ps
CPU time 0.82 seconds
Started Jan 21 03:57:52 PM PST 24
Finished Jan 21 03:57:54 PM PST 24
Peak memory 195376 kb
Host smart-3eb70639-c00c-4102-ab9b-b63b6a6318dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253936405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.253936405
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1555864842
Short name T389
Test name
Test status
Simulation time 20865660711 ps
CPU time 153.06 seconds
Started Jan 21 03:25:02 PM PST 24
Finished Jan 21 03:27:38 PM PST 24
Peak memory 198320 kb
Host smart-a5395fb6-d1a3-41f7-8b0e-e27089ad2b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555864842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1555864842
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.799333608
Short name T554
Test name
Test status
Simulation time 101824228520 ps
CPU time 1213.91 seconds
Started Jan 21 03:25:00 PM PST 24
Finished Jan 21 03:45:16 PM PST 24
Peak memory 198380 kb
Host smart-137036fc-3a3c-41d3-9516-4eddaa11a453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=799333608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.799333608
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2242428835
Short name T713
Test name
Test status
Simulation time 22350542 ps
CPU time 0.56 seconds
Started Jan 21 03:25:03 PM PST 24
Finished Jan 21 03:25:06 PM PST 24
Peak memory 194676 kb
Host smart-c2abff4d-71a5-4a60-93d3-dfc8f36117f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242428835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2242428835
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2777099021
Short name T836
Test name
Test status
Simulation time 44605523 ps
CPU time 0.6 seconds
Started Jan 21 03:25:07 PM PST 24
Finished Jan 21 03:25:09 PM PST 24
Peak memory 194792 kb
Host smart-13656ad7-5afe-4027-8007-05afe904a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777099021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2777099021
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.618803454
Short name T672
Test name
Test status
Simulation time 469626578 ps
CPU time 3.78 seconds
Started Jan 21 03:25:02 PM PST 24
Finished Jan 21 03:25:08 PM PST 24
Peak memory 196808 kb
Host smart-3d8ae18f-17b7-431d-bbfc-5afb162e2ace
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618803454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.618803454
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3216081940
Short name T336
Test name
Test status
Simulation time 236222159 ps
CPU time 1 seconds
Started Jan 21 03:25:00 PM PST 24
Finished Jan 21 03:25:03 PM PST 24
Peak memory 196676 kb
Host smart-54a0c796-887b-45e5-ac6e-5abfc2051dcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216081940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3216081940
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1103118220
Short name T587
Test name
Test status
Simulation time 212144869 ps
CPU time 0.94 seconds
Started Jan 21 03:25:00 PM PST 24
Finished Jan 21 03:25:04 PM PST 24
Peak memory 196516 kb
Host smart-71be8d48-4913-4ce9-904b-eeafb16e5dc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103118220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1103118220
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3437567799
Short name T93
Test name
Test status
Simulation time 29875591 ps
CPU time 1.26 seconds
Started Jan 21 03:25:04 PM PST 24
Finished Jan 21 03:25:07 PM PST 24
Peak memory 197160 kb
Host smart-98ee1fa9-753d-4ae0-a0cd-50c99916cd52
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437567799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3437567799
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3975335661
Short name T360
Test name
Test status
Simulation time 409773194 ps
CPU time 2.19 seconds
Started Jan 21 03:25:03 PM PST 24
Finished Jan 21 03:25:07 PM PST 24
Peak memory 198240 kb
Host smart-fe6ba80b-4c53-41f0-8b7a-38b1f839f809
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975335661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3975335661
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1586158747
Short name T345
Test name
Test status
Simulation time 58855852 ps
CPU time 0.97 seconds
Started Jan 21 03:25:03 PM PST 24
Finished Jan 21 03:25:06 PM PST 24
Peak memory 196900 kb
Host smart-a819801e-1537-4918-aa82-a15168a53bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586158747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1586158747
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.217295489
Short name T874
Test name
Test status
Simulation time 21479319 ps
CPU time 0.94 seconds
Started Jan 21 03:24:59 PM PST 24
Finished Jan 21 03:25:02 PM PST 24
Peak memory 195992 kb
Host smart-259a5bd6-a26c-4da4-8275-f1675af1d4dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217295489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.217295489
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3818485782
Short name T728
Test name
Test status
Simulation time 547701566 ps
CPU time 5 seconds
Started Jan 21 03:24:58 PM PST 24
Finished Jan 21 03:25:05 PM PST 24
Peak memory 198120 kb
Host smart-87db3733-1c88-493a-86e8-b9a247cf3bfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818485782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3818485782
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.599211575
Short name T833
Test name
Test status
Simulation time 55899221 ps
CPU time 1.05 seconds
Started Jan 21 03:25:00 PM PST 24
Finished Jan 21 03:25:03 PM PST 24
Peak memory 195636 kb
Host smart-2055bb67-e7fc-4dae-bc01-8c37a557ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599211575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.599211575
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.175617596
Short name T388
Test name
Test status
Simulation time 222149779 ps
CPU time 1.33 seconds
Started Jan 21 03:25:05 PM PST 24
Finished Jan 21 03:25:08 PM PST 24
Peak memory 197332 kb
Host smart-387139c3-9993-448b-8f0f-1de9f96445f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175617596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.175617596
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2730255386
Short name T838
Test name
Test status
Simulation time 5043876122 ps
CPU time 36.43 seconds
Started Jan 21 03:25:03 PM PST 24
Finished Jan 21 03:25:42 PM PST 24
Peak memory 198344 kb
Host smart-272bb887-acae-4e5f-af56-cc862adbbaea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730255386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2730255386
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.557108893
Short name T536
Test name
Test status
Simulation time 41073679364 ps
CPU time 363.97 seconds
Started Jan 21 03:25:07 PM PST 24
Finished Jan 21 03:31:13 PM PST 24
Peak memory 198364 kb
Host smart-24d432ae-4df1-4155-84c9-3070c605faa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=557108893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.557108893
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3110091271
Short name T716
Test name
Test status
Simulation time 13844549 ps
CPU time 0.56 seconds
Started Jan 21 03:25:09 PM PST 24
Finished Jan 21 03:25:10 PM PST 24
Peak memory 193908 kb
Host smart-0a6bedae-d34a-42f4-a109-3ffa8fbb56bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110091271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3110091271
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2404211486
Short name T664
Test name
Test status
Simulation time 24515639 ps
CPU time 0.88 seconds
Started Jan 21 03:25:07 PM PST 24
Finished Jan 21 03:25:10 PM PST 24
Peak memory 195508 kb
Host smart-4d0bbb6d-8e3b-487f-a086-bfd289997f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404211486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2404211486
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3893496224
Short name T583
Test name
Test status
Simulation time 199184186 ps
CPU time 5.58 seconds
Started Jan 21 03:25:04 PM PST 24
Finished Jan 21 03:25:12 PM PST 24
Peak memory 197184 kb
Host smart-c7e071b3-cac7-4b9f-b6e0-a84630b5c18f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893496224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3893496224
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.132533221
Short name T567
Test name
Test status
Simulation time 150734119 ps
CPU time 0.84 seconds
Started Jan 21 03:25:06 PM PST 24
Finished Jan 21 03:25:08 PM PST 24
Peak memory 195952 kb
Host smart-afe6e1bf-a32c-4d58-9c80-bf454bf75304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132533221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.132533221
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.359516164
Short name T243
Test name
Test status
Simulation time 124545404 ps
CPU time 0.82 seconds
Started Jan 21 04:00:29 PM PST 24
Finished Jan 21 04:00:32 PM PST 24
Peak memory 196368 kb
Host smart-a51fd57b-037b-41a6-8fd7-8298057aba7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359516164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.359516164
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3388677490
Short name T527
Test name
Test status
Simulation time 95725128 ps
CPU time 3.75 seconds
Started Jan 21 03:25:07 PM PST 24
Finished Jan 21 03:25:13 PM PST 24
Peak memory 198176 kb
Host smart-29057d1e-c7b3-4999-a83c-b304af5d56e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388677490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3388677490
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3330844362
Short name T100
Test name
Test status
Simulation time 274084253 ps
CPU time 2.4 seconds
Started Jan 21 04:23:54 PM PST 24
Finished Jan 21 04:23:58 PM PST 24
Peak memory 197372 kb
Host smart-8b3d162d-d403-4701-b908-b0b988a2c995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330844362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3330844362
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2064989916
Short name T316
Test name
Test status
Simulation time 61646978 ps
CPU time 1.24 seconds
Started Jan 21 03:25:01 PM PST 24
Finished Jan 21 03:25:05 PM PST 24
Peak memory 196460 kb
Host smart-171480e7-95ad-4f06-b56f-5b76d7a83db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064989916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2064989916
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.376852784
Short name T283
Test name
Test status
Simulation time 224988208 ps
CPU time 1.15 seconds
Started Jan 21 03:25:05 PM PST 24
Finished Jan 21 03:25:08 PM PST 24
Peak memory 197252 kb
Host smart-6732a627-453b-4712-ab05-c53dd55865b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376852784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.376852784
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2999812175
Short name T845
Test name
Test status
Simulation time 606330772 ps
CPU time 4.04 seconds
Started Jan 21 03:25:07 PM PST 24
Finished Jan 21 03:25:12 PM PST 24
Peak memory 198052 kb
Host smart-3e0f9555-d904-4b41-b1ba-835aa52acc6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999812175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2999812175
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3715899450
Short name T304
Test name
Test status
Simulation time 123668080 ps
CPU time 1 seconds
Started Jan 21 03:25:05 PM PST 24
Finished Jan 21 03:25:08 PM PST 24
Peak memory 196628 kb
Host smart-db0a9e69-81c4-4d54-b7cd-ed61874a69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715899450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3715899450
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1684669656
Short name T311
Test name
Test status
Simulation time 52968941 ps
CPU time 1.24 seconds
Started Jan 21 03:25:07 PM PST 24
Finished Jan 21 03:25:10 PM PST 24
Peak memory 196352 kb
Host smart-7a55ae34-ba50-479d-9aed-452674152d02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684669656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1684669656
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2957160857
Short name T710
Test name
Test status
Simulation time 7357122670 ps
CPU time 182.77 seconds
Started Jan 21 03:25:05 PM PST 24
Finished Jan 21 03:28:10 PM PST 24
Peak memory 198384 kb
Host smart-5a7a40d5-0760-40a1-9bb6-c806fc5e5165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957160857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2957160857
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1350367820
Short name T406
Test name
Test status
Simulation time 30233119883 ps
CPU time 759.05 seconds
Started Jan 21 03:25:05 PM PST 24
Finished Jan 21 03:37:46 PM PST 24
Peak memory 198284 kb
Host smart-063cefd2-eef2-47bb-91b3-270dc9cb9fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1350367820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1350367820
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1568564470
Short name T49
Test name
Test status
Simulation time 17138929 ps
CPU time 0.63 seconds
Started Jan 21 03:25:20 PM PST 24
Finished Jan 21 03:25:22 PM PST 24
Peak memory 193992 kb
Host smart-3ba7f77b-8b25-4d78-ad34-5587bbe2d338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568564470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1568564470
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4092213284
Short name T387
Test name
Test status
Simulation time 89655706 ps
CPU time 0.9 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:25 PM PST 24
Peak memory 196492 kb
Host smart-802ae3f5-798c-492d-8178-4e27549aaee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092213284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4092213284
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4228902202
Short name T363
Test name
Test status
Simulation time 475442950 ps
CPU time 16.84 seconds
Started Jan 21 03:25:15 PM PST 24
Finished Jan 21 03:25:33 PM PST 24
Peak memory 196860 kb
Host smart-0b4d44bf-b53a-47dd-8436-36f55ef69167
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228902202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4228902202
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3940949093
Short name T399
Test name
Test status
Simulation time 61011273 ps
CPU time 0.92 seconds
Started Jan 21 03:25:21 PM PST 24
Finished Jan 21 03:25:23 PM PST 24
Peak memory 195980 kb
Host smart-9a53e70b-a246-438c-bc5b-5f5b68c0a978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940949093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3940949093
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3883165077
Short name T366
Test name
Test status
Simulation time 38655929 ps
CPU time 1.12 seconds
Started Jan 21 03:25:17 PM PST 24
Finished Jan 21 03:25:20 PM PST 24
Peak memory 195904 kb
Host smart-0cd5c400-64a0-421d-a87f-2b190f708c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883165077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3883165077
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1005364939
Short name T405
Test name
Test status
Simulation time 51465461 ps
CPU time 1.09 seconds
Started Jan 21 03:25:21 PM PST 24
Finished Jan 21 03:25:23 PM PST 24
Peak memory 197244 kb
Host smart-4056673d-92be-46f8-8522-84450fefdab0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005364939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1005364939
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1355254243
Short name T849
Test name
Test status
Simulation time 154812661 ps
CPU time 1.74 seconds
Started Jan 21 03:25:23 PM PST 24
Finished Jan 21 03:25:26 PM PST 24
Peak memory 196540 kb
Host smart-4d383cdb-74ee-4b6d-b9ea-9f137454168d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355254243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1355254243
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1117208617
Short name T344
Test name
Test status
Simulation time 260189577 ps
CPU time 1.26 seconds
Started Jan 21 03:25:05 PM PST 24
Finished Jan 21 03:25:08 PM PST 24
Peak memory 197124 kb
Host smart-f7a62914-0ee7-43ad-b61a-eebbfd3d990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117208617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1117208617
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3461828298
Short name T793
Test name
Test status
Simulation time 47696567 ps
CPU time 0.76 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:24 PM PST 24
Peak memory 195528 kb
Host smart-e2853056-8965-4d9d-9f2b-1c7a0cc36a98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461828298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3461828298
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2414468586
Short name T377
Test name
Test status
Simulation time 318335578 ps
CPU time 3.79 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:27 PM PST 24
Peak memory 198020 kb
Host smart-97b7e4e2-4b83-4aab-b953-38671b10a77c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414468586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2414468586
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.74878811
Short name T628
Test name
Test status
Simulation time 46644358 ps
CPU time 1.3 seconds
Started Jan 21 03:47:30 PM PST 24
Finished Jan 21 03:47:32 PM PST 24
Peak memory 197320 kb
Host smart-284d7e28-c180-428b-820a-c49a26d5854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74878811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.74878811
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.538886720
Short name T722
Test name
Test status
Simulation time 323737243 ps
CPU time 1.48 seconds
Started Jan 21 03:25:08 PM PST 24
Finished Jan 21 03:25:11 PM PST 24
Peak memory 195664 kb
Host smart-d4e9c177-24e1-4e9e-aaf4-dd02036af3eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538886720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.538886720
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2349053453
Short name T704
Test name
Test status
Simulation time 13724211000 ps
CPU time 150.89 seconds
Started Jan 21 03:25:21 PM PST 24
Finished Jan 21 03:27:53 PM PST 24
Peak memory 198328 kb
Host smart-86a791a4-9923-4d23-bec7-a101b5b406b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349053453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2349053453
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2502587054
Short name T386
Test name
Test status
Simulation time 107433269364 ps
CPU time 2528.75 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 04:07:32 PM PST 24
Peak memory 198412 kb
Host smart-e0eb6f55-fbbb-40d6-ad29-1eadb387e1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2502587054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2502587054
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.4064977897
Short name T619
Test name
Test status
Simulation time 17212212 ps
CPU time 0.58 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:25 PM PST 24
Peak memory 193888 kb
Host smart-f738e61c-5d43-4b75-92a3-81412b297a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064977897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.4064977897
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3795660463
Short name T602
Test name
Test status
Simulation time 17369683 ps
CPU time 0.67 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:24 PM PST 24
Peak memory 194164 kb
Host smart-5c7e9968-720e-4270-aa59-fff9aa05d351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795660463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3795660463
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.4231643295
Short name T666
Test name
Test status
Simulation time 779593652 ps
CPU time 12.99 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:36 PM PST 24
Peak memory 198184 kb
Host smart-b59994ab-678b-47cf-a590-cc12df2bbb75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231643295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.4231643295
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2204704379
Short name T317
Test name
Test status
Simulation time 48390954 ps
CPU time 0.76 seconds
Started Jan 21 03:25:16 PM PST 24
Finished Jan 21 03:25:17 PM PST 24
Peak memory 195920 kb
Host smart-f2f45d42-0981-4e24-ae98-6748567397c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204704379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2204704379
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2031181707
Short name T121
Test name
Test status
Simulation time 74825784 ps
CPU time 1.16 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:24 PM PST 24
Peak memory 196112 kb
Host smart-6e28b9e1-f8be-44ee-bb9f-0b57b5369919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031181707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2031181707
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.652681390
Short name T632
Test name
Test status
Simulation time 249938220 ps
CPU time 1.34 seconds
Started Jan 21 03:25:18 PM PST 24
Finished Jan 21 03:25:21 PM PST 24
Peak memory 197036 kb
Host smart-d2f81e1a-9603-4c62-8aad-37fd1d64194f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652681390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.652681390
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.579876879
Short name T302
Test name
Test status
Simulation time 353824978 ps
CPU time 3.56 seconds
Started Jan 21 03:25:17 PM PST 24
Finished Jan 21 03:25:22 PM PST 24
Peak memory 197264 kb
Host smart-bf1f6c3c-7c42-4718-9d64-d536de936923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579876879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
579876879
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4231884095
Short name T685
Test name
Test status
Simulation time 39761268 ps
CPU time 0.87 seconds
Started Jan 21 03:25:17 PM PST 24
Finished Jan 21 03:25:19 PM PST 24
Peak memory 195972 kb
Host smart-2007639a-0b64-426f-b65c-69d3078483ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231884095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4231884095
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2188051033
Short name T329
Test name
Test status
Simulation time 83010019 ps
CPU time 1.41 seconds
Started Jan 21 03:25:21 PM PST 24
Finished Jan 21 03:25:24 PM PST 24
Peak memory 196888 kb
Host smart-55a998b4-3a69-4cfa-8d0c-258b75fbb858
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188051033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2188051033
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2709426049
Short name T420
Test name
Test status
Simulation time 490206841 ps
CPU time 5.74 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:30 PM PST 24
Peak memory 197632 kb
Host smart-743ea4a9-6e29-4ac1-85b4-fc139f272e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709426049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2709426049
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3245997908
Short name T778
Test name
Test status
Simulation time 136484737 ps
CPU time 1.21 seconds
Started Jan 21 03:25:17 PM PST 24
Finished Jan 21 03:25:20 PM PST 24
Peak memory 195900 kb
Host smart-a24c9634-c004-4f42-b897-63fa63695e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245997908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3245997908
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2339286722
Short name T487
Test name
Test status
Simulation time 70257002 ps
CPU time 1.05 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:24 PM PST 24
Peak memory 197324 kb
Host smart-da95d583-f973-4b4d-b8c9-6525b4281b8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339286722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2339286722
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2184794389
Short name T612
Test name
Test status
Simulation time 21288800081 ps
CPU time 125.5 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:27:29 PM PST 24
Peak memory 198256 kb
Host smart-939fec08-637e-4747-81cb-446487623c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184794389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2184794389
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.921764429
Short name T466
Test name
Test status
Simulation time 56436641930 ps
CPU time 711.85 seconds
Started Jan 21 03:25:20 PM PST 24
Finished Jan 21 03:37:14 PM PST 24
Peak memory 198416 kb
Host smart-01ac2f04-3a5b-4328-ae97-65549147ebda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=921764429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.921764429
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3331689031
Short name T408
Test name
Test status
Simulation time 16128888 ps
CPU time 0.6 seconds
Started Jan 21 03:25:33 PM PST 24
Finished Jan 21 03:25:35 PM PST 24
Peak memory 194020 kb
Host smart-1fce021b-029c-44bc-ab8d-0ac5fa24530f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331689031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3331689031
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1734654964
Short name T321
Test name
Test status
Simulation time 155170370 ps
CPU time 0.72 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:25 PM PST 24
Peak memory 193632 kb
Host smart-7b3ef7ae-1d64-44e5-afd8-64f1764a6fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734654964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1734654964
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.457571350
Short name T770
Test name
Test status
Simulation time 311721645 ps
CPU time 10.96 seconds
Started Jan 21 03:25:31 PM PST 24
Finished Jan 21 03:25:42 PM PST 24
Peak memory 198140 kb
Host smart-4a275505-746d-4721-bfbc-b94a3b9aaf58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457571350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.457571350
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2648642270
Short name T739
Test name
Test status
Simulation time 97893541 ps
CPU time 0.79 seconds
Started Jan 21 03:25:28 PM PST 24
Finished Jan 21 03:25:30 PM PST 24
Peak memory 195992 kb
Host smart-28085d66-263d-4581-b3b1-f0ced770c4f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648642270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2648642270
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1635220941
Short name T784
Test name
Test status
Simulation time 61713765 ps
CPU time 0.81 seconds
Started Jan 21 03:49:10 PM PST 24
Finished Jan 21 03:49:14 PM PST 24
Peak memory 195660 kb
Host smart-c8526c5e-2215-4034-a6eb-051ab73269e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635220941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1635220941
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2584518081
Short name T551
Test name
Test status
Simulation time 398079950 ps
CPU time 2.22 seconds
Started Jan 21 03:25:27 PM PST 24
Finished Jan 21 03:25:31 PM PST 24
Peak memory 198240 kb
Host smart-d9d543cf-34ac-41d4-b776-3e8b4cd12e87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584518081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2584518081
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.698026903
Short name T284
Test name
Test status
Simulation time 51866282 ps
CPU time 1.64 seconds
Started Jan 21 03:25:25 PM PST 24
Finished Jan 21 03:25:28 PM PST 24
Peak memory 196260 kb
Host smart-73525245-72d1-4f6a-931c-d7a2f05f25b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698026903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
698026903
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.530226065
Short name T390
Test name
Test status
Simulation time 131388587 ps
CPU time 1.2 seconds
Started Jan 21 03:25:16 PM PST 24
Finished Jan 21 03:25:19 PM PST 24
Peak memory 195916 kb
Host smart-7f00b351-af96-4760-8ed5-70aca85d6059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530226065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.530226065
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1738024589
Short name T633
Test name
Test status
Simulation time 59281255 ps
CPU time 1.14 seconds
Started Jan 21 03:25:16 PM PST 24
Finished Jan 21 03:25:18 PM PST 24
Peak memory 196184 kb
Host smart-9356d265-ebd6-481f-9015-d59c211635cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738024589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1738024589
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.659627150
Short name T504
Test name
Test status
Simulation time 98282445 ps
CPU time 1.64 seconds
Started Jan 21 03:25:27 PM PST 24
Finished Jan 21 03:25:30 PM PST 24
Peak memory 197692 kb
Host smart-98c976a3-c38f-4aed-84a2-9578249f6858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659627150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.659627150
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2440448946
Short name T278
Test name
Test status
Simulation time 68227846 ps
CPU time 1.27 seconds
Started Jan 21 03:25:17 PM PST 24
Finished Jan 21 03:25:20 PM PST 24
Peak memory 197480 kb
Host smart-74c9da69-20b5-421a-af97-cd5970e7405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440448946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2440448946
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2960205004
Short name T677
Test name
Test status
Simulation time 29892793 ps
CPU time 0.92 seconds
Started Jan 21 03:25:22 PM PST 24
Finished Jan 21 03:25:24 PM PST 24
Peak memory 197084 kb
Host smart-8311fdcf-42a8-45b7-8bb7-5d1c7f939dfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960205004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2960205004
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1967602155
Short name T835
Test name
Test status
Simulation time 3658830425 ps
CPU time 107.7 seconds
Started Jan 21 03:25:25 PM PST 24
Finished Jan 21 03:27:14 PM PST 24
Peak memory 198328 kb
Host smart-5de21bc8-0be7-4f18-b0b9-a925ff6a8f37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967602155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1967602155
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.355014801
Short name T346
Test name
Test status
Simulation time 27138805538 ps
CPU time 424.11 seconds
Started Jan 21 03:25:26 PM PST 24
Finished Jan 21 03:32:32 PM PST 24
Peak memory 198288 kb
Host smart-905d63fb-e668-4a6b-b731-5b9cb9ea3fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=355014801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.355014801
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2591436846
Short name T503
Test name
Test status
Simulation time 24097986 ps
CPU time 0.57 seconds
Started Jan 21 03:25:37 PM PST 24
Finished Jan 21 03:25:38 PM PST 24
Peak memory 193960 kb
Host smart-96fc38e4-a507-4e22-b3c8-fc9e433e7b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591436846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2591436846
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2563711873
Short name T852
Test name
Test status
Simulation time 37927017 ps
CPU time 0.91 seconds
Started Jan 21 03:25:25 PM PST 24
Finished Jan 21 03:25:27 PM PST 24
Peak memory 195912 kb
Host smart-9eda8ee7-87ec-4d78-b747-2c6f398baf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563711873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2563711873
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.971912359
Short name T799
Test name
Test status
Simulation time 939802240 ps
CPU time 7.83 seconds
Started Jan 21 03:25:25 PM PST 24
Finished Jan 21 03:25:34 PM PST 24
Peak memory 197260 kb
Host smart-69038526-bcdc-4e08-bc59-b0d0e2b4ff25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971912359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.971912359
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2482196269
Short name T851
Test name
Test status
Simulation time 231929886 ps
CPU time 1.13 seconds
Started Jan 21 03:25:42 PM PST 24
Finished Jan 21 03:25:44 PM PST 24
Peak memory 196772 kb
Host smart-be4ed12c-669a-46b8-b6f8-bc7201d31316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482196269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2482196269
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1331568105
Short name T372
Test name
Test status
Simulation time 85613703 ps
CPU time 0.73 seconds
Started Jan 21 03:25:25 PM PST 24
Finished Jan 21 03:25:27 PM PST 24
Peak memory 194572 kb
Host smart-b52df8c2-5b73-423c-ac5f-659ac0d05a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331568105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1331568105
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4083389731
Short name T731
Test name
Test status
Simulation time 201308746 ps
CPU time 2.27 seconds
Started Jan 21 03:25:26 PM PST 24
Finished Jan 21 03:25:30 PM PST 24
Peak memory 198144 kb
Host smart-a4c1f37f-1161-4a3c-85ff-115e2d3780ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083389731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4083389731
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1998118669
Short name T786
Test name
Test status
Simulation time 231836660 ps
CPU time 1.42 seconds
Started Jan 21 03:25:24 PM PST 24
Finished Jan 21 03:25:27 PM PST 24
Peak memory 195928 kb
Host smart-44ae40aa-1c9b-42d6-913b-f395865a46f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998118669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1998118669
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1501254373
Short name T870
Test name
Test status
Simulation time 30751299 ps
CPU time 0.82 seconds
Started Jan 21 03:25:27 PM PST 24
Finished Jan 21 03:25:29 PM PST 24
Peak memory 196200 kb
Host smart-d86311a8-0ab7-44f9-a7d9-9398fae07e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501254373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1501254373
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3328179784
Short name T796
Test name
Test status
Simulation time 16683583 ps
CPU time 0.74 seconds
Started Jan 21 03:25:26 PM PST 24
Finished Jan 21 03:25:28 PM PST 24
Peak memory 195424 kb
Host smart-ffb56c50-1000-40cc-9573-657210a379c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328179784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3328179784
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3700949607
Short name T382
Test name
Test status
Simulation time 58263048 ps
CPU time 2.56 seconds
Started Jan 21 03:25:40 PM PST 24
Finished Jan 21 03:25:44 PM PST 24
Peak memory 198092 kb
Host smart-2b577c82-81ba-45ee-a736-53b27a5d17e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700949607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3700949607
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.458686740
Short name T577
Test name
Test status
Simulation time 24578950 ps
CPU time 0.88 seconds
Started Jan 21 03:25:32 PM PST 24
Finished Jan 21 03:25:34 PM PST 24
Peak memory 197036 kb
Host smart-539e1ad1-4cae-407d-b2e0-04c909177aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458686740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.458686740
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3614150328
Short name T821
Test name
Test status
Simulation time 207482503 ps
CPU time 1.1 seconds
Started Jan 21 03:25:25 PM PST 24
Finished Jan 21 03:25:27 PM PST 24
Peak memory 195648 kb
Host smart-38110d67-9a4c-4f47-a4e1-1b00ba2b19a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614150328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3614150328
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1811301092
Short name T557
Test name
Test status
Simulation time 7411619495 ps
CPU time 59.27 seconds
Started Jan 21 03:43:45 PM PST 24
Finished Jan 21 03:44:45 PM PST 24
Peak memory 198296 kb
Host smart-5d168b60-e960-4981-9b5d-ce3c98898c7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811301092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1811301092
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3142682188
Short name T392
Test name
Test status
Simulation time 33102405920 ps
CPU time 562.59 seconds
Started Jan 21 03:32:08 PM PST 24
Finished Jan 21 03:41:32 PM PST 24
Peak memory 198404 kb
Host smart-bed25ee8-57e8-4da1-9d17-231835704c5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3142682188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3142682188
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3908393628
Short name T397
Test name
Test status
Simulation time 37602835 ps
CPU time 0.56 seconds
Started Jan 21 03:25:35 PM PST 24
Finished Jan 21 03:25:37 PM PST 24
Peak memory 194692 kb
Host smart-1c1e10ca-5e6d-4a62-8180-eca27b34e650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908393628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3908393628
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.160800766
Short name T297
Test name
Test status
Simulation time 66067760 ps
CPU time 0.92 seconds
Started Jan 21 03:25:38 PM PST 24
Finished Jan 21 03:25:40 PM PST 24
Peak memory 196572 kb
Host smart-4d494eda-5f10-47d0-800b-c228f5f84dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160800766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.160800766
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.7938616
Short name T306
Test name
Test status
Simulation time 1157818378 ps
CPU time 25.77 seconds
Started Jan 21 03:25:36 PM PST 24
Finished Jan 21 03:26:03 PM PST 24
Peak memory 197008 kb
Host smart-1ee3f20f-b85b-4630-8013-932bbf7b71b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7938616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress.7938616
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3396413315
Short name T824
Test name
Test status
Simulation time 248078106 ps
CPU time 0.98 seconds
Started Jan 21 03:25:35 PM PST 24
Finished Jan 21 03:25:37 PM PST 24
Peak memory 197944 kb
Host smart-a52bbb2f-9675-4a07-bd9e-d10dba2a2322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396413315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3396413315
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.707882408
Short name T456
Test name
Test status
Simulation time 21481830 ps
CPU time 0.68 seconds
Started Jan 21 03:25:40 PM PST 24
Finished Jan 21 03:25:42 PM PST 24
Peak memory 194424 kb
Host smart-9b721335-e68f-4ce3-8834-caa9bdc25b81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707882408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.707882408
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.386769383
Short name T495
Test name
Test status
Simulation time 59799062 ps
CPU time 2.07 seconds
Started Jan 21 03:25:37 PM PST 24
Finished Jan 21 03:25:40 PM PST 24
Peak memory 197936 kb
Host smart-2306d131-0163-4153-bb88-f6e317b7af04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386769383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.386769383
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3155202926
Short name T598
Test name
Test status
Simulation time 115808347 ps
CPU time 1.39 seconds
Started Jan 21 03:25:34 PM PST 24
Finished Jan 21 03:25:36 PM PST 24
Peak memory 196840 kb
Host smart-7fd3fb69-de66-4b2d-9565-ca7906f234cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155202926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3155202926
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3675675572
Short name T546
Test name
Test status
Simulation time 71646571 ps
CPU time 1.09 seconds
Started Jan 21 03:25:35 PM PST 24
Finished Jan 21 03:25:36 PM PST 24
Peak memory 196144 kb
Host smart-f4858ca8-0975-4f59-8575-2dfea1a1105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675675572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3675675572
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3533241048
Short name T393
Test name
Test status
Simulation time 547176197 ps
CPU time 1.21 seconds
Started Jan 21 03:25:34 PM PST 24
Finished Jan 21 03:25:36 PM PST 24
Peak memory 197240 kb
Host smart-b60d5624-96d5-464a-ab55-5f673a9b76bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533241048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3533241048
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1280068923
Short name T245
Test name
Test status
Simulation time 71072493 ps
CPU time 1.46 seconds
Started Jan 21 04:03:52 PM PST 24
Finished Jan 21 04:03:56 PM PST 24
Peak memory 198116 kb
Host smart-fff42281-c3de-4c19-9e50-76b870ab0033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280068923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1280068923
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.765786321
Short name T472
Test name
Test status
Simulation time 39856580 ps
CPU time 1.09 seconds
Started Jan 21 03:25:41 PM PST 24
Finished Jan 21 03:25:43 PM PST 24
Peak memory 196604 kb
Host smart-b2f987b2-a9ef-4af8-b520-5a2cc6e54e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765786321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.765786321
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2840391218
Short name T773
Test name
Test status
Simulation time 257359964 ps
CPU time 0.67 seconds
Started Jan 21 03:25:35 PM PST 24
Finished Jan 21 03:25:36 PM PST 24
Peak memory 194988 kb
Host smart-74e31630-c468-4c52-9560-109cdc27c436
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840391218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2840391218
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2066947809
Short name T519
Test name
Test status
Simulation time 2570108681 ps
CPU time 69.75 seconds
Started Jan 21 03:25:40 PM PST 24
Finished Jan 21 03:26:51 PM PST 24
Peak memory 198232 kb
Host smart-8fdd8aba-dd2c-42b2-8dfe-a0c4b39b8f3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066947809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2066947809
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2474693708
Short name T526
Test name
Test status
Simulation time 344724803561 ps
CPU time 1173.72 seconds
Started Jan 21 03:25:40 PM PST 24
Finished Jan 21 03:45:15 PM PST 24
Peak memory 206588 kb
Host smart-da7cb3cc-77c3-489f-921a-d527fcd9fd31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2474693708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2474693708
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1999175780
Short name T439
Test name
Test status
Simulation time 32922926 ps
CPU time 0.63 seconds
Started Jan 21 03:26:02 PM PST 24
Finished Jan 21 03:26:04 PM PST 24
Peak memory 194844 kb
Host smart-7eaa5b78-d1ad-4ae9-9d23-3bf89f01b4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999175780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1999175780
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3440150180
Short name T689
Test name
Test status
Simulation time 315687939 ps
CPU time 0.7 seconds
Started Jan 21 03:25:46 PM PST 24
Finished Jan 21 03:25:47 PM PST 24
Peak memory 194220 kb
Host smart-6a94812b-c3b5-4f8b-9b3e-583739187114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440150180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3440150180
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1495547549
Short name T458
Test name
Test status
Simulation time 363329933 ps
CPU time 13.41 seconds
Started Jan 21 03:25:55 PM PST 24
Finished Jan 21 03:26:10 PM PST 24
Peak memory 196880 kb
Host smart-caae5873-10f6-4042-85ce-8d28b6a858f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495547549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1495547549
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1966268751
Short name T686
Test name
Test status
Simulation time 36280618 ps
CPU time 0.77 seconds
Started Jan 21 03:25:52 PM PST 24
Finished Jan 21 03:25:53 PM PST 24
Peak memory 194864 kb
Host smart-157db2c0-cc21-41a3-b768-7f2c86bf012c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966268751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1966268751
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2976581657
Short name T776
Test name
Test status
Simulation time 236046071 ps
CPU time 1.16 seconds
Started Jan 21 04:22:00 PM PST 24
Finished Jan 21 04:22:02 PM PST 24
Peak memory 195912 kb
Host smart-6bc7f4b6-fd1c-44b3-b191-fb0eb6d10b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976581657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2976581657
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.856768082
Short name T433
Test name
Test status
Simulation time 198956268 ps
CPU time 3.11 seconds
Started Jan 21 03:46:37 PM PST 24
Finished Jan 21 03:46:42 PM PST 24
Peak memory 198200 kb
Host smart-90d45b7a-2277-454f-a0db-239229dcec83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856768082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.856768082
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.937009212
Short name T462
Test name
Test status
Simulation time 587116134 ps
CPU time 3.31 seconds
Started Jan 21 03:25:42 PM PST 24
Finished Jan 21 03:25:47 PM PST 24
Peak memory 198256 kb
Host smart-56c721e3-65a9-4cb6-93cf-0afc7550c3fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937009212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
937009212
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2930922100
Short name T560
Test name
Test status
Simulation time 25110158 ps
CPU time 0.78 seconds
Started Jan 21 03:25:45 PM PST 24
Finished Jan 21 03:25:46 PM PST 24
Peak memory 195556 kb
Host smart-487d5d6c-f429-42a1-9f54-bbd5dcff8ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930922100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2930922100
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1556722239
Short name T289
Test name
Test status
Simulation time 196592863 ps
CPU time 0.76 seconds
Started Jan 21 03:25:43 PM PST 24
Finished Jan 21 03:25:44 PM PST 24
Peak memory 195500 kb
Host smart-f740487a-6e0f-48ab-8006-039caa9fd0b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556722239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1556722239
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2920697603
Short name T828
Test name
Test status
Simulation time 55913166 ps
CPU time 2.37 seconds
Started Jan 21 03:25:54 PM PST 24
Finished Jan 21 03:25:58 PM PST 24
Peak memory 198028 kb
Host smart-1290c9f5-8960-466e-aa40-530803a17734
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920697603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2920697603
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3751779589
Short name T67
Test name
Test status
Simulation time 171355428 ps
CPU time 1.01 seconds
Started Jan 21 03:25:55 PM PST 24
Finished Jan 21 03:25:57 PM PST 24
Peak memory 196428 kb
Host smart-5ae54e37-5b37-4935-b955-bc158d07de2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751779589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3751779589
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.384801169
Short name T455
Test name
Test status
Simulation time 70797970 ps
CPU time 1.2 seconds
Started Jan 21 04:56:04 PM PST 24
Finished Jan 21 04:56:06 PM PST 24
Peak memory 195848 kb
Host smart-597fd55b-0ce3-4d78-b6aa-1533285f9e63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384801169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.384801169
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2867264123
Short name T656
Test name
Test status
Simulation time 12639477002 ps
CPU time 190.55 seconds
Started Jan 21 03:25:55 PM PST 24
Finished Jan 21 03:29:06 PM PST 24
Peak memory 198196 kb
Host smart-2f8d8008-0536-4b3a-bde1-32f867a1f475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867264123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2867264123
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.438642024
Short name T80
Test name
Test status
Simulation time 39984419110 ps
CPU time 574.33 seconds
Started Jan 21 03:25:53 PM PST 24
Finished Jan 21 03:35:29 PM PST 24
Peak memory 198260 kb
Host smart-78d512d9-4f18-4664-bab0-1ebc796e32f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=438642024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.438642024
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1336303770
Short name T549
Test name
Test status
Simulation time 50426886 ps
CPU time 0.64 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 193956 kb
Host smart-4fe995a2-12f1-4641-a38d-3804182e6ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336303770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1336303770
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3598582793
Short name T330
Test name
Test status
Simulation time 109227276 ps
CPU time 0.73 seconds
Started Jan 21 03:20:45 PM PST 24
Finished Jan 21 03:20:47 PM PST 24
Peak memory 194404 kb
Host smart-5b2c8548-b8a1-42c8-a892-b6abded14fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598582793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3598582793
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2236482496
Short name T703
Test name
Test status
Simulation time 467243476 ps
CPU time 5.52 seconds
Started Jan 21 03:20:41 PM PST 24
Finished Jan 21 03:20:48 PM PST 24
Peak memory 195648 kb
Host smart-cc9d1463-814a-49f2-97eb-aa50270b103a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236482496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2236482496
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.321280242
Short name T876
Test name
Test status
Simulation time 46467478 ps
CPU time 0.69 seconds
Started Jan 21 03:20:37 PM PST 24
Finished Jan 21 03:20:39 PM PST 24
Peak memory 195468 kb
Host smart-8854a40a-191e-466b-b6e8-ac82bb5fc01d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321280242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.321280242
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.330960658
Short name T726
Test name
Test status
Simulation time 40430227 ps
CPU time 1.1 seconds
Started Jan 21 03:20:39 PM PST 24
Finished Jan 21 03:20:42 PM PST 24
Peak memory 195932 kb
Host smart-37f55f51-07ba-4984-b250-8eda7eef3d3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330960658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.330960658
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4215942769
Short name T791
Test name
Test status
Simulation time 97699253 ps
CPU time 1.04 seconds
Started Jan 21 03:20:42 PM PST 24
Finished Jan 21 03:20:45 PM PST 24
Peak memory 196172 kb
Host smart-a8242dec-724f-42b0-9aba-664d636ca4c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215942769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4215942769
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1682663442
Short name T101
Test name
Test status
Simulation time 50783072 ps
CPU time 1.01 seconds
Started Jan 21 03:20:47 PM PST 24
Finished Jan 21 03:20:58 PM PST 24
Peak memory 195756 kb
Host smart-17e2c900-850d-4939-9b60-91c6d39e7087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682663442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1682663442
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.4063713358
Short name T467
Test name
Test status
Simulation time 46118457 ps
CPU time 0.98 seconds
Started Jan 21 03:20:45 PM PST 24
Finished Jan 21 03:20:48 PM PST 24
Peak memory 196164 kb
Host smart-8d611f1b-6497-4b97-b660-3799eec070f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063713358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.4063713358
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1849687818
Short name T802
Test name
Test status
Simulation time 334114902 ps
CPU time 0.72 seconds
Started Jan 21 03:20:47 PM PST 24
Finished Jan 21 03:20:57 PM PST 24
Peak memory 196260 kb
Host smart-87903846-6e6a-4985-85f2-8a6d5cda08e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849687818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1849687818
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.4122261632
Short name T286
Test name
Test status
Simulation time 685169096 ps
CPU time 4.5 seconds
Started Jan 21 03:20:41 PM PST 24
Finished Jan 21 03:20:47 PM PST 24
Peak memory 198128 kb
Host smart-266d75b8-97a9-41d7-8be8-6ed6aa0f45bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122261632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.4122261632
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3192012434
Short name T305
Test name
Test status
Simulation time 34712346 ps
CPU time 1.03 seconds
Started Jan 21 03:20:44 PM PST 24
Finished Jan 21 03:20:47 PM PST 24
Peak memory 195760 kb
Host smart-a7153256-17f0-462c-8d43-f14eddcdb937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192012434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3192012434
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2379684686
Short name T637
Test name
Test status
Simulation time 225511061 ps
CPU time 1.11 seconds
Started Jan 21 03:20:38 PM PST 24
Finished Jan 21 03:20:41 PM PST 24
Peak memory 196184 kb
Host smart-eb47f26a-de7a-4d33-a76a-46d07d5fac49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379684686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2379684686
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2626012056
Short name T667
Test name
Test status
Simulation time 13517721023 ps
CPU time 53.28 seconds
Started Jan 21 03:20:51 PM PST 24
Finished Jan 21 03:21:52 PM PST 24
Peak memory 198328 kb
Host smart-241c3021-0bb3-4f01-a0d7-ecf0dccb2dd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626012056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2626012056
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1536373621
Short name T489
Test name
Test status
Simulation time 351246587522 ps
CPU time 1127.67 seconds
Started Jan 21 03:20:51 PM PST 24
Finished Jan 21 03:39:46 PM PST 24
Peak memory 206592 kb
Host smart-40b6274d-5a14-4e35-8960-2288d76a897b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1536373621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1536373621
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3541362916
Short name T47
Test name
Test status
Simulation time 64120108 ps
CPU time 0.6 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 193948 kb
Host smart-492a1a17-0e21-457b-9f55-88c74fd24c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541362916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3541362916
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.144148799
Short name T333
Test name
Test status
Simulation time 81167003 ps
CPU time 0.89 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 196204 kb
Host smart-8358b8ec-bca1-4172-a660-77d4495d4444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144148799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.144148799
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3123945245
Short name T431
Test name
Test status
Simulation time 3089698493 ps
CPU time 23.72 seconds
Started Jan 21 03:20:52 PM PST 24
Finished Jan 21 03:21:22 PM PST 24
Peak memory 196828 kb
Host smart-ea1dd268-5a09-4ee0-9685-e5183f527e35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123945245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3123945245
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4080394
Short name T356
Test name
Test status
Simulation time 54275173 ps
CPU time 0.64 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 194972 kb
Host smart-a678367b-aff7-4c7d-8d69-0ea96d9f8fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4080394
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3450371313
Short name T380
Test name
Test status
Simulation time 516537653 ps
CPU time 1.08 seconds
Started Jan 21 03:20:47 PM PST 24
Finished Jan 21 03:21:00 PM PST 24
Peak memory 196052 kb
Host smart-888a61bc-eea7-4d3f-b817-48dc2ef41c02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450371313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3450371313
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2549400246
Short name T735
Test name
Test status
Simulation time 67746315 ps
CPU time 2.62 seconds
Started Jan 21 03:20:49 PM PST 24
Finished Jan 21 03:21:01 PM PST 24
Peak memory 198204 kb
Host smart-a8f4e031-8b77-4369-a71d-b46d794115cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549400246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2549400246
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3216069248
Short name T277
Test name
Test status
Simulation time 401819000 ps
CPU time 2.22 seconds
Started Jan 21 03:20:51 PM PST 24
Finished Jan 21 03:21:01 PM PST 24
Peak memory 196120 kb
Host smart-01d91a1c-7ce5-4c53-8dfe-4e73fa5266ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216069248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3216069248
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2159756670
Short name T290
Test name
Test status
Simulation time 48224587 ps
CPU time 1.08 seconds
Started Jan 21 03:20:51 PM PST 24
Finished Jan 21 03:21:00 PM PST 24
Peak memory 196064 kb
Host smart-f0317293-448d-42aa-92f1-ed6ea5539c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159756670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2159756670
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3114952872
Short name T50
Test name
Test status
Simulation time 149576096 ps
CPU time 1.38 seconds
Started Jan 21 03:20:52 PM PST 24
Finished Jan 21 03:21:00 PM PST 24
Peak memory 197132 kb
Host smart-4655f2f0-0a6b-437c-8ad6-c8ac5e585fc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114952872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3114952872
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2862145066
Short name T533
Test name
Test status
Simulation time 90509375 ps
CPU time 1.13 seconds
Started Jan 21 03:20:49 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 196656 kb
Host smart-2bd00913-aa5f-4b0c-b57e-0a939f65eae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862145066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2862145066
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.450781468
Short name T342
Test name
Test status
Simulation time 35128921 ps
CPU time 1.05 seconds
Started Jan 21 03:20:45 PM PST 24
Finished Jan 21 03:20:53 PM PST 24
Peak memory 195816 kb
Host smart-62833764-15fe-4ee3-9a23-999d37458fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450781468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.450781468
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1828285078
Short name T499
Test name
Test status
Simulation time 545878379 ps
CPU time 1.1 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:21:00 PM PST 24
Peak memory 195932 kb
Host smart-2bbaf089-b1b2-41ec-a43d-ca65074dfc47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828285078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1828285078
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3247418384
Short name T442
Test name
Test status
Simulation time 2371459834 ps
CPU time 34.2 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:21:33 PM PST 24
Peak memory 198172 kb
Host smart-59ec249f-cc57-4173-a127-70222e5e43cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247418384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3247418384
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.705752703
Short name T655
Test name
Test status
Simulation time 258164363494 ps
CPU time 1395.16 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:44:14 PM PST 24
Peak memory 198388 kb
Host smart-bf312793-8c31-482b-bbc4-0fb6a984b9e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=705752703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.705752703
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3673741144
Short name T850
Test name
Test status
Simulation time 40785255 ps
CPU time 0.59 seconds
Started Jan 21 03:20:55 PM PST 24
Finished Jan 21 03:21:07 PM PST 24
Peak memory 194184 kb
Host smart-31eb9746-0ec3-4e12-87bf-b122ff5441aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673741144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3673741144
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4014574794
Short name T507
Test name
Test status
Simulation time 47841699 ps
CPU time 0.77 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 195200 kb
Host smart-dbff86d1-d8f5-446c-9f7c-fc7832c329e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014574794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4014574794
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3278440487
Short name T702
Test name
Test status
Simulation time 762327790 ps
CPU time 21.05 seconds
Started Jan 21 03:21:04 PM PST 24
Finished Jan 21 03:21:31 PM PST 24
Peak memory 196964 kb
Host smart-3978108a-0b62-4474-89e4-03030606f1d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278440487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3278440487
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.892271614
Short name T674
Test name
Test status
Simulation time 329196440 ps
CPU time 1.1 seconds
Started Jan 21 03:21:00 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 196716 kb
Host smart-5b67ed20-b5f0-4bbc-9a80-7f5c3f44192f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892271614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.892271614
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2317541393
Short name T231
Test name
Test status
Simulation time 150676942 ps
CPU time 0.81 seconds
Started Jan 21 03:20:49 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 195320 kb
Host smart-47d9db95-9aee-40d7-b864-fbbd5cee5ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317541393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2317541393
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3663782918
Short name T754
Test name
Test status
Simulation time 164480105 ps
CPU time 1.44 seconds
Started Jan 21 03:21:07 PM PST 24
Finished Jan 21 03:21:13 PM PST 24
Peak memory 196904 kb
Host smart-d25d8d57-88db-43ea-8569-02c56902f7a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663782918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3663782918
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2810668004
Short name T343
Test name
Test status
Simulation time 43331058 ps
CPU time 1.08 seconds
Started Jan 21 03:20:50 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 195740 kb
Host smart-339501ee-4cd3-43f0-b6f4-eeec07b03bb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810668004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2810668004
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3249905616
Short name T538
Test name
Test status
Simulation time 83230562 ps
CPU time 1.12 seconds
Started Jan 21 03:46:51 PM PST 24
Finished Jan 21 03:46:53 PM PST 24
Peak memory 196840 kb
Host smart-85552823-21d5-411f-8cbd-14ffca517e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249905616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3249905616
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2951549022
Short name T237
Test name
Test status
Simulation time 18342005 ps
CPU time 0.77 seconds
Started Jan 21 03:20:49 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 196304 kb
Host smart-0e5ac1d2-42ee-4b50-820c-5543fe83f228
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951549022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2951549022
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1552890370
Short name T688
Test name
Test status
Simulation time 98569560 ps
CPU time 4.85 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:21:14 PM PST 24
Peak memory 198112 kb
Host smart-70e4fff8-abfe-43c8-be0c-1cc834197e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552890370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1552890370
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3164572181
Short name T822
Test name
Test status
Simulation time 339128932 ps
CPU time 0.88 seconds
Started Jan 21 03:20:49 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 195200 kb
Host smart-2984e9d2-2569-4487-9525-a80c790065d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164572181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3164572181
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.830408498
Short name T757
Test name
Test status
Simulation time 55492773 ps
CPU time 1.02 seconds
Started Jan 21 03:20:49 PM PST 24
Finished Jan 21 03:20:59 PM PST 24
Peak memory 196584 kb
Host smart-e8bb70ab-b22b-4bf5-806b-6992792e9b34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830408498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.830408498
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2330336941
Short name T547
Test name
Test status
Simulation time 3557011985 ps
CPU time 92.96 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:22:42 PM PST 24
Peak memory 198288 kb
Host smart-9fc47304-b832-467b-ac46-8cb36a786f20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330336941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2330336941
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2765001138
Short name T818
Test name
Test status
Simulation time 17119563427 ps
CPU time 275.6 seconds
Started Jan 21 03:21:03 PM PST 24
Finished Jan 21 03:25:46 PM PST 24
Peak memory 198276 kb
Host smart-6789c5d3-57c9-4935-a0dd-44938da58501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2765001138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2765001138
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2634281286
Short name T805
Test name
Test status
Simulation time 17900321 ps
CPU time 0.59 seconds
Started Jan 21 03:20:57 PM PST 24
Finished Jan 21 03:21:09 PM PST 24
Peak memory 194608 kb
Host smart-75779107-d21a-4d26-8e80-203cdeee7964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634281286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2634281286
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.459738183
Short name T326
Test name
Test status
Simulation time 130893823 ps
CPU time 0.68 seconds
Started Jan 21 03:21:02 PM PST 24
Finished Jan 21 03:21:11 PM PST 24
Peak memory 194184 kb
Host smart-f8b0f876-eb20-4c3d-b4ec-968d9ced2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459738183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.459738183
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1265548931
Short name T255
Test name
Test status
Simulation time 1934815856 ps
CPU time 17.49 seconds
Started Jan 21 03:21:05 PM PST 24
Finished Jan 21 03:21:28 PM PST 24
Peak memory 196604 kb
Host smart-a15a009c-7507-4d72-9cef-7104b1061f9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265548931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1265548931
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1399663821
Short name T493
Test name
Test status
Simulation time 200094239 ps
CPU time 0.86 seconds
Started Jan 21 03:20:58 PM PST 24
Finished Jan 21 03:21:09 PM PST 24
Peak memory 195976 kb
Host smart-01fbc8ac-5457-4b64-a4fb-c865ded8f9ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399663821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1399663821
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3586073894
Short name T540
Test name
Test status
Simulation time 19812701 ps
CPU time 0.72 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 194276 kb
Host smart-c9493264-b12d-4865-bf85-4c49509ffdf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586073894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3586073894
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3536455340
Short name T525
Test name
Test status
Simulation time 52428655 ps
CPU time 1.08 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 196156 kb
Host smart-de07bd65-188d-4260-b89c-00efd48e131c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536455340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3536455340
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3627928027
Short name T880
Test name
Test status
Simulation time 186752019 ps
CPU time 2.46 seconds
Started Jan 21 03:21:00 PM PST 24
Finished Jan 21 03:21:12 PM PST 24
Peak memory 197176 kb
Host smart-63d71142-4f99-418f-bdf5-865241fe9616
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627928027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3627928027
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3826839054
Short name T788
Test name
Test status
Simulation time 54564833 ps
CPU time 0.69 seconds
Started Jan 21 03:21:00 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 193844 kb
Host smart-ab5461c1-5a0e-4929-af67-78d547be3678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826839054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3826839054
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3175791693
Short name T512
Test name
Test status
Simulation time 111971424 ps
CPU time 1.33 seconds
Started Jan 21 03:21:00 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 197140 kb
Host smart-bc2daf2f-305d-4e83-87dc-78295437cf75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175791693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3175791693
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1976223864
Short name T867
Test name
Test status
Simulation time 415248411 ps
CPU time 5.72 seconds
Started Jan 21 03:21:03 PM PST 24
Finished Jan 21 03:21:16 PM PST 24
Peak memory 198044 kb
Host smart-88e7641c-7588-4d61-b8f8-2a73000f8efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976223864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1976223864
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3578252649
Short name T873
Test name
Test status
Simulation time 58281137 ps
CPU time 0.85 seconds
Started Jan 21 03:21:02 PM PST 24
Finished Jan 21 03:21:11 PM PST 24
Peak memory 195200 kb
Host smart-1bbc997f-4eac-41bf-97a0-cda78483f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578252649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3578252649
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.861033328
Short name T572
Test name
Test status
Simulation time 46998226 ps
CPU time 1.28 seconds
Started Jan 21 03:21:04 PM PST 24
Finished Jan 21 03:21:11 PM PST 24
Peak memory 196400 kb
Host smart-3b73c604-49bd-4217-b678-e3b4085f5eb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861033328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.861033328
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3975478817
Short name T404
Test name
Test status
Simulation time 98879815952 ps
CPU time 155.67 seconds
Started Jan 21 03:20:57 PM PST 24
Finished Jan 21 03:23:44 PM PST 24
Peak memory 198296 kb
Host smart-80602fc8-6e3c-456f-abe2-d7384a9e440d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975478817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3975478817
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.912879507
Short name T424
Test name
Test status
Simulation time 47406652278 ps
CPU time 644.7 seconds
Started Jan 21 03:21:04 PM PST 24
Finished Jan 21 03:31:55 PM PST 24
Peak memory 198048 kb
Host smart-3a65428d-5529-4064-b724-8c4af819911e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=912879507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.912879507
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2414314968
Short name T48
Test name
Test status
Simulation time 12274320 ps
CPU time 0.6 seconds
Started Jan 21 04:51:21 PM PST 24
Finished Jan 21 04:51:23 PM PST 24
Peak memory 194020 kb
Host smart-b08cdd3d-933b-40b4-9f86-ac5d11b4d6a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414314968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2414314968
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.955196704
Short name T740
Test name
Test status
Simulation time 132120399 ps
CPU time 0.81 seconds
Started Jan 21 03:20:56 PM PST 24
Finished Jan 21 03:21:08 PM PST 24
Peak memory 195344 kb
Host smart-6a6d52c8-e33c-468e-b75b-3176a1d28015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955196704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.955196704
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1108484328
Short name T318
Test name
Test status
Simulation time 414126473 ps
CPU time 22.39 seconds
Started Jan 21 04:45:29 PM PST 24
Finished Jan 21 04:45:54 PM PST 24
Peak memory 196700 kb
Host smart-6cfb7fe4-2bf2-490b-a5c5-712c731adc7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108484328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1108484328
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.611336815
Short name T453
Test name
Test status
Simulation time 232628388 ps
CPU time 0.88 seconds
Started Jan 21 03:21:01 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 195988 kb
Host smart-e25bf47a-7607-4edb-bd0f-4b073bb9fd87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611336815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.611336815
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4049394527
Short name T531
Test name
Test status
Simulation time 32424524 ps
CPU time 0.79 seconds
Started Jan 21 03:21:05 PM PST 24
Finished Jan 21 03:21:11 PM PST 24
Peak memory 195624 kb
Host smart-0859319e-4b7f-4f26-b44b-a015721eed44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049394527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4049394527
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.676119877
Short name T888
Test name
Test status
Simulation time 323265122 ps
CPU time 3.12 seconds
Started Jan 21 03:21:00 PM PST 24
Finished Jan 21 03:21:12 PM PST 24
Peak memory 196024 kb
Host smart-26191569-5e83-45bc-b9eb-f92d7a7d3999
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676119877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.676119877
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3956178115
Short name T530
Test name
Test status
Simulation time 148725630 ps
CPU time 3.16 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:21:12 PM PST 24
Peak memory 197116 kb
Host smart-839a1b1d-bb84-4f12-83be-b2407fc691b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956178115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3956178115
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3661382313
Short name T792
Test name
Test status
Simulation time 810628537 ps
CPU time 1.12 seconds
Started Jan 21 03:21:08 PM PST 24
Finished Jan 21 03:21:13 PM PST 24
Peak memory 196776 kb
Host smart-60c7b6cc-c10e-41c2-a344-f72e22747d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661382313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3661382313
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2495447283
Short name T847
Test name
Test status
Simulation time 36734927 ps
CPU time 0.9 seconds
Started Jan 21 03:21:07 PM PST 24
Finished Jan 21 03:21:13 PM PST 24
Peak memory 196668 kb
Host smart-6f33c96c-ec0f-463c-80f9-cf12b750d2cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495447283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2495447283
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1242975178
Short name T709
Test name
Test status
Simulation time 712056877 ps
CPU time 2.24 seconds
Started Jan 21 04:06:06 PM PST 24
Finished Jan 21 04:06:14 PM PST 24
Peak memory 198028 kb
Host smart-b1fc4bed-4ea5-46d5-8cd8-78dd82d775c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242975178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1242975178
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.464159123
Short name T315
Test name
Test status
Simulation time 74616429 ps
CPU time 1.07 seconds
Started Jan 21 03:21:00 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 196556 kb
Host smart-2fb2024c-461a-4af2-a5e5-b516a59d193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464159123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.464159123
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3258149701
Short name T272
Test name
Test status
Simulation time 41266214 ps
CPU time 0.94 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:21:10 PM PST 24
Peak memory 197108 kb
Host smart-acd70053-8484-4df8-acf1-0523b68a503a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258149701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3258149701
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.124229430
Short name T759
Test name
Test status
Simulation time 6200465620 ps
CPU time 173.21 seconds
Started Jan 21 03:20:57 PM PST 24
Finished Jan 21 03:24:01 PM PST 24
Peak memory 198268 kb
Host smart-88c53923-64a2-49df-a0cf-97d07d972da8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124229430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.124229430
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.246818683
Short name T429
Test name
Test status
Simulation time 49218039965 ps
CPU time 1163.74 seconds
Started Jan 21 03:20:59 PM PST 24
Finished Jan 21 03:40:33 PM PST 24
Peak memory 198412 kb
Host smart-7a2274e4-5a49-4064-9d84-243c8563c678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=246818683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.246818683
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.284426418
Short name T140
Test name
Test status
Simulation time 48711880 ps
CPU time 1.01 seconds
Started Jan 21 10:22:23 PM PST 24
Finished Jan 21 10:22:34 PM PST 24
Peak memory 191388 kb
Host smart-0fd0da50-453a-4eb9-8e78-7f62e7034baa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=284426418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.284426418
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393176236
Short name T165
Test name
Test status
Simulation time 31398622 ps
CPU time 1.06 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191352 kb
Host smart-d2542de7-2bd4-441d-ad9d-88891fad6db8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393176236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1393176236
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2007558456
Short name T176
Test name
Test status
Simulation time 67557148 ps
CPU time 1.39 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191320 kb
Host smart-bf03f88a-d6e5-4e03-aef9-dc60cb0d283a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2007558456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2007558456
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.88076310
Short name T162
Test name
Test status
Simulation time 131813313 ps
CPU time 1.16 seconds
Started Jan 21 08:56:08 PM PST 24
Finished Jan 21 08:56:41 PM PST 24
Peak memory 191244 kb
Host smart-1c19203a-91f1-459b-906a-4c9ff65c7fa5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88076310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.88076310
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2666371516
Short name T179
Test name
Test status
Simulation time 738917388 ps
CPU time 1.16 seconds
Started Jan 21 08:56:18 PM PST 24
Finished Jan 21 08:56:57 PM PST 24
Peak memory 191532 kb
Host smart-09afcddc-4102-4bde-9183-e2ae5ac8848d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2666371516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2666371516
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2652363272
Short name T155
Test name
Test status
Simulation time 38965960 ps
CPU time 0.9 seconds
Started Jan 21 08:56:13 PM PST 24
Finished Jan 21 08:56:52 PM PST 24
Peak memory 191096 kb
Host smart-bc03e1d7-7670-4985-ad47-13cd1af89fb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652363272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2652363272
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.189000599
Short name T177
Test name
Test status
Simulation time 80158545 ps
CPU time 0.74 seconds
Started Jan 21 08:56:16 PM PST 24
Finished Jan 21 08:56:56 PM PST 24
Peak memory 191032 kb
Host smart-20ddfafd-30e6-49e5-9474-8ddc06de24ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189000599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.189000599
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4171151899
Short name T227
Test name
Test status
Simulation time 70977364 ps
CPU time 1.25 seconds
Started Jan 21 08:56:16 PM PST 24
Finished Jan 21 08:56:55 PM PST 24
Peak memory 191312 kb
Host smart-0b3cafdb-0a67-49b5-9101-cf46318f0422
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4171151899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4171151899
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2628207685
Short name T184
Test name
Test status
Simulation time 251464014 ps
CPU time 1.18 seconds
Started Jan 21 08:56:16 PM PST 24
Finished Jan 21 08:56:56 PM PST 24
Peak memory 197956 kb
Host smart-4230e08f-b693-4955-848b-c5e4df54cd8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628207685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2628207685
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3522039578
Short name T210
Test name
Test status
Simulation time 153694574 ps
CPU time 1.39 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191364 kb
Host smart-697cd659-7aad-4058-addf-1b64510db3fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3522039578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3522039578
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.250099023
Short name T196
Test name
Test status
Simulation time 36071847 ps
CPU time 1.05 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 197208 kb
Host smart-cb1b2713-7721-43e6-b9e3-47f45be1053c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250099023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.250099023
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2151325613
Short name T148
Test name
Test status
Simulation time 86520469 ps
CPU time 1.1 seconds
Started Jan 21 08:56:15 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191316 kb
Host smart-fe7cebca-aab1-460a-95d3-ad6f7cefa906
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2151325613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2151325613
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217685694
Short name T158
Test name
Test status
Simulation time 63717726 ps
CPU time 1.04 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191332 kb
Host smart-8faa0941-3b9d-42d2-85c4-4102c2217e53
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217685694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1217685694
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4208519293
Short name T151
Test name
Test status
Simulation time 204520304 ps
CPU time 1.13 seconds
Started Jan 21 08:56:17 PM PST 24
Finished Jan 21 08:56:57 PM PST 24
Peak memory 196928 kb
Host smart-b8303a4a-3daa-451f-bad4-d768105022e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4208519293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.4208519293
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1089118290
Short name T183
Test name
Test status
Simulation time 55492164 ps
CPU time 1.76 seconds
Started Jan 21 08:56:18 PM PST 24
Finished Jan 21 08:56:59 PM PST 24
Peak memory 191352 kb
Host smart-fafd169a-10b9-42b4-94f6-e37c5ed96456
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089118290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1089118290
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.71929347
Short name T199
Test name
Test status
Simulation time 249861219 ps
CPU time 1.2 seconds
Started Jan 21 08:56:15 PM PST 24
Finished Jan 21 08:56:54 PM PST 24
Peak memory 191244 kb
Host smart-51a1047b-945e-4b24-8270-7e511e241dd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=71929347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.71929347
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3033154500
Short name T142
Test name
Test status
Simulation time 146714396 ps
CPU time 1.08 seconds
Started Jan 21 09:05:26 PM PST 24
Finished Jan 21 09:05:31 PM PST 24
Peak memory 191236 kb
Host smart-2a820af7-2409-4ba6-8c2e-11606f005952
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033154500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3033154500
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.886766891
Short name T153
Test name
Test status
Simulation time 106071562 ps
CPU time 1.02 seconds
Started Jan 21 10:53:26 PM PST 24
Finished Jan 21 10:53:28 PM PST 24
Peak memory 191476 kb
Host smart-a3c319c2-7d5c-4872-93b6-879996cef247
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=886766891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.886766891
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.442535501
Short name T224
Test name
Test status
Simulation time 129248174 ps
CPU time 1 seconds
Started Jan 21 09:09:03 PM PST 24
Finished Jan 21 09:09:12 PM PST 24
Peak memory 197012 kb
Host smart-307a4bca-d52d-48ae-a549-fdd1fef274b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442535501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.442535501
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.14204059
Short name T149
Test name
Test status
Simulation time 148533818 ps
CPU time 0.9 seconds
Started Jan 21 10:35:48 PM PST 24
Finished Jan 21 10:35:57 PM PST 24
Peak memory 191340 kb
Host smart-0adb435d-5f33-4789-bb5c-bc4425f138c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=14204059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.14204059
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4017537113
Short name T40
Test name
Test status
Simulation time 83334298 ps
CPU time 0.75 seconds
Started Jan 21 09:17:44 PM PST 24
Finished Jan 21 09:17:48 PM PST 24
Peak memory 191128 kb
Host smart-57e0413a-8b8c-4949-bd83-44f8cf5b7784
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017537113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4017537113
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.751142540
Short name T197
Test name
Test status
Simulation time 63065820 ps
CPU time 1.2 seconds
Started Jan 21 08:56:21 PM PST 24
Finished Jan 21 08:57:04 PM PST 24
Peak memory 197660 kb
Host smart-292eba0c-cea1-4bb6-b0c7-3e34c8eee0b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=751142540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.751142540
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4183306121
Short name T168
Test name
Test status
Simulation time 298228316 ps
CPU time 0.8 seconds
Started Jan 21 09:17:29 PM PST 24
Finished Jan 21 09:17:36 PM PST 24
Peak memory 195816 kb
Host smart-daa95247-29cb-4411-aa93-1b5d5ba9e4bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183306121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4183306121
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2994853751
Short name T150
Test name
Test status
Simulation time 40082956 ps
CPU time 1.17 seconds
Started Jan 21 08:56:13 PM PST 24
Finished Jan 21 08:56:52 PM PST 24
Peak memory 197736 kb
Host smart-afbb4510-29cc-4e55-8089-40bea07c6449
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2994853751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2994853751
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3216528037
Short name T154
Test name
Test status
Simulation time 44153188 ps
CPU time 1.21 seconds
Started Jan 21 08:56:11 PM PST 24
Finished Jan 21 08:56:47 PM PST 24
Peak memory 191316 kb
Host smart-5bc58bbf-2bf3-4c4f-90fe-e2264bccca5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216528037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3216528037
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.172486912
Short name T186
Test name
Test status
Simulation time 176249470 ps
CPU time 1.28 seconds
Started Jan 21 09:08:07 PM PST 24
Finished Jan 21 09:08:33 PM PST 24
Peak memory 191340 kb
Host smart-035bcfbc-2614-46f2-b926-116178a19577
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=172486912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.172486912
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.305565965
Short name T194
Test name
Test status
Simulation time 30757908 ps
CPU time 0.91 seconds
Started Jan 21 08:56:20 PM PST 24
Finished Jan 21 08:57:01 PM PST 24
Peak memory 191156 kb
Host smart-1f168b3e-cbb7-4e0b-bf59-598ce876d457
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305565965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.305565965
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4168064114
Short name T159
Test name
Test status
Simulation time 247145171 ps
CPU time 1.1 seconds
Started Jan 21 08:56:20 PM PST 24
Finished Jan 21 08:57:01 PM PST 24
Peak memory 197020 kb
Host smart-c037e8f0-8d9c-4556-8101-12ff8b0a9132
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4168064114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4168064114
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.928544259
Short name T170
Test name
Test status
Simulation time 44089439 ps
CPU time 0.84 seconds
Started Jan 21 08:56:21 PM PST 24
Finished Jan 21 08:57:02 PM PST 24
Peak memory 191108 kb
Host smart-e1266284-d2b5-4c5b-9d43-3b87c7679180
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928544259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.928544259
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2829810415
Short name T216
Test name
Test status
Simulation time 297630626 ps
CPU time 1.45 seconds
Started Jan 21 09:11:50 PM PST 24
Finished Jan 21 09:11:55 PM PST 24
Peak memory 191300 kb
Host smart-863f0916-3784-4c4b-837a-ae1386b2eacd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2829810415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2829810415
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1678309729
Short name T189
Test name
Test status
Simulation time 194401167 ps
CPU time 1.3 seconds
Started Jan 21 08:56:31 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 191292 kb
Host smart-cbe8199a-904b-4652-ab1f-3b2e261709c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678309729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1678309729
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.782315173
Short name T188
Test name
Test status
Simulation time 55252613 ps
CPU time 1.4 seconds
Started Jan 21 08:56:30 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 197720 kb
Host smart-ba69b1b2-e1e8-48e7-a8fb-778f1e78ff00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=782315173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.782315173
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030576509
Short name T160
Test name
Test status
Simulation time 887493013 ps
CPU time 1.29 seconds
Started Jan 21 08:56:34 PM PST 24
Finished Jan 21 08:57:14 PM PST 24
Peak memory 191360 kb
Host smart-3b51e0ca-a895-47a0-a881-046b762da00e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030576509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4030576509
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3988458669
Short name T156
Test name
Test status
Simulation time 71950355 ps
CPU time 1.38 seconds
Started Jan 21 08:56:36 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 197656 kb
Host smart-095350a3-53fd-45db-b05a-9664a9826370
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3988458669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3988458669
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3186726610
Short name T178
Test name
Test status
Simulation time 207446665 ps
CPU time 1.21 seconds
Started Jan 21 08:56:37 PM PST 24
Finished Jan 21 08:57:17 PM PST 24
Peak memory 197656 kb
Host smart-3a5a5704-2c2f-4dbf-96f9-4cf5b96b7fdf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186726610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3186726610
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1616671838
Short name T208
Test name
Test status
Simulation time 126686658 ps
CPU time 1.07 seconds
Started Jan 21 08:56:37 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 191272 kb
Host smart-91d4ec0d-2b65-49d3-89c9-6eb4eb6e0fe0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1616671838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1616671838
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1073814447
Short name T52
Test name
Test status
Simulation time 204590927 ps
CPU time 1.44 seconds
Started Jan 21 08:56:35 PM PST 24
Finished Jan 21 08:57:15 PM PST 24
Peak memory 191280 kb
Host smart-b21983c8-722f-44fe-8d52-094488df8616
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073814447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1073814447
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.677458340
Short name T214
Test name
Test status
Simulation time 198639349 ps
CPU time 1.13 seconds
Started Jan 21 08:56:32 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 191240 kb
Host smart-042e6483-3440-4a00-b34c-8e4bc1df25ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=677458340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.677458340
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.928333273
Short name T166
Test name
Test status
Simulation time 224707935 ps
CPU time 1.19 seconds
Started Jan 21 08:56:33 PM PST 24
Finished Jan 21 08:57:14 PM PST 24
Peak memory 191324 kb
Host smart-5a6d21ea-a4ac-476a-9991-8c8b511ab30f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928333273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.928333273
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2416369414
Short name T164
Test name
Test status
Simulation time 303862665 ps
CPU time 1.32 seconds
Started Jan 21 08:56:36 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 191232 kb
Host smart-a565e747-e5e2-4a94-a1ae-cffe9d798330
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2416369414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2416369414
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1916741088
Short name T217
Test name
Test status
Simulation time 76542207 ps
CPU time 1.31 seconds
Started Jan 21 08:56:29 PM PST 24
Finished Jan 21 08:57:12 PM PST 24
Peak memory 191300 kb
Host smart-da1ed230-5a6d-46fa-a9fd-af7b75447c04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916741088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1916741088
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2627228386
Short name T161
Test name
Test status
Simulation time 53372669 ps
CPU time 1.18 seconds
Started Jan 21 08:56:34 PM PST 24
Finished Jan 21 08:57:14 PM PST 24
Peak memory 197624 kb
Host smart-fed8e4ea-a970-4634-90b5-ad145d3bc729
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2627228386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2627228386
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3088223744
Short name T198
Test name
Test status
Simulation time 164496750 ps
CPU time 0.92 seconds
Started Jan 21 08:56:36 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 191356 kb
Host smart-c02493b2-d8a3-4911-8663-9191e75012b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088223744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3088223744
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2388282662
Short name T212
Test name
Test status
Simulation time 51170695 ps
CPU time 1.42 seconds
Started Jan 21 08:56:35 PM PST 24
Finished Jan 21 08:57:15 PM PST 24
Peak memory 191360 kb
Host smart-049afd85-8b94-4fda-aa24-ff6313a0f270
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2388282662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2388282662
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172897252
Short name T145
Test name
Test status
Simulation time 76429956 ps
CPU time 1.27 seconds
Started Jan 21 08:56:36 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 197652 kb
Host smart-d3fc69f5-c9e8-46f9-9a82-504fe0747e4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172897252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2172897252
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4093224419
Short name T220
Test name
Test status
Simulation time 30453300 ps
CPU time 0.91 seconds
Started Jan 21 08:56:06 PM PST 24
Finished Jan 21 08:56:39 PM PST 24
Peak memory 195812 kb
Host smart-f725d1ea-ee14-4bb1-bd05-d37726d475db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4093224419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.4093224419
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986644258
Short name T202
Test name
Test status
Simulation time 100374717 ps
CPU time 1.05 seconds
Started Jan 21 08:56:08 PM PST 24
Finished Jan 21 08:56:42 PM PST 24
Peak memory 197156 kb
Host smart-94d992f9-db3d-4075-b9ac-d643e6c2dac6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986644258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2986644258
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3647382426
Short name T205
Test name
Test status
Simulation time 593440918 ps
CPU time 1.59 seconds
Started Jan 21 08:56:36 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 191220 kb
Host smart-a3356f48-b04a-4f1b-b86b-626ad801d18f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3647382426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3647382426
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4109662353
Short name T174
Test name
Test status
Simulation time 396649508 ps
CPU time 1.3 seconds
Started Jan 21 08:56:31 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 191336 kb
Host smart-4ac56fea-e204-4c98-a349-94f0ad861d05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109662353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4109662353
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2648525419
Short name T141
Test name
Test status
Simulation time 38417535 ps
CPU time 0.97 seconds
Started Jan 21 08:56:37 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 191112 kb
Host smart-8406683f-a194-4fe2-b8d9-96bb23ab9105
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2648525419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2648525419
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1776170923
Short name T221
Test name
Test status
Simulation time 264876080 ps
CPU time 0.89 seconds
Started Jan 21 09:08:00 PM PST 24
Finished Jan 21 09:08:25 PM PST 24
Peak memory 195820 kb
Host smart-ae3f70b2-64c2-4749-bf22-c3571de6e541
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776170923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1776170923
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1078478500
Short name T57
Test name
Test status
Simulation time 33407353 ps
CPU time 0.99 seconds
Started Jan 21 08:56:32 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 191404 kb
Host smart-36089339-2c4f-4b1f-8905-77fc235cd3a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1078478500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1078478500
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1870461306
Short name T226
Test name
Test status
Simulation time 148517782 ps
CPU time 0.93 seconds
Started Jan 21 08:56:33 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 191280 kb
Host smart-2d86e88d-abc3-4dee-9d50-2244af2e0ce2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870461306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1870461306
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3963671208
Short name T182
Test name
Test status
Simulation time 276972334 ps
CPU time 1.28 seconds
Started Jan 21 08:56:34 PM PST 24
Finished Jan 21 08:57:14 PM PST 24
Peak memory 197596 kb
Host smart-15eae27a-b67c-4b0a-8f95-f793c85dfd95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3963671208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3963671208
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.286345220
Short name T211
Test name
Test status
Simulation time 102102349 ps
CPU time 0.82 seconds
Started Jan 21 08:56:33 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 195788 kb
Host smart-a8228f71-773e-4bf2-b970-8c5d48d4c13c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286345220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.286345220
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2752658673
Short name T190
Test name
Test status
Simulation time 63171567 ps
CPU time 0.71 seconds
Started Jan 21 08:56:32 PM PST 24
Finished Jan 21 08:57:13 PM PST 24
Peak memory 191148 kb
Host smart-2e386b7a-8f24-4672-b06c-4609ca48f7a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2752658673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2752658673
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780726579
Short name T58
Test name
Test status
Simulation time 66961070 ps
CPU time 1.36 seconds
Started Jan 21 08:56:37 PM PST 24
Finished Jan 21 08:57:16 PM PST 24
Peak memory 197708 kb
Host smart-1de68f53-d108-4929-8ccc-9232a66b336f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780726579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.780726579
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.802950229
Short name T42
Test name
Test status
Simulation time 207230785 ps
CPU time 1.4 seconds
Started Jan 21 08:56:42 PM PST 24
Finished Jan 21 08:57:21 PM PST 24
Peak memory 191332 kb
Host smart-91cde43e-5c40-4438-90d8-b8e27591e928
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=802950229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.802950229
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3378144349
Short name T218
Test name
Test status
Simulation time 59240313 ps
CPU time 0.89 seconds
Started Jan 21 08:56:41 PM PST 24
Finished Jan 21 08:57:19 PM PST 24
Peak memory 191108 kb
Host smart-2b3e1b47-5ed1-4dbc-b576-452c9d9044d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378144349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3378144349
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3407212230
Short name T200
Test name
Test status
Simulation time 45448824 ps
CPU time 0.95 seconds
Started Jan 21 08:56:42 PM PST 24
Finished Jan 21 08:57:20 PM PST 24
Peak memory 195944 kb
Host smart-5104191e-19c4-4375-8501-ed4d88798787
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3407212230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3407212230
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132363990
Short name T157
Test name
Test status
Simulation time 66401698 ps
CPU time 1.16 seconds
Started Jan 21 10:20:11 PM PST 24
Finished Jan 21 10:20:18 PM PST 24
Peak memory 191360 kb
Host smart-1e05e4f3-77bb-4ea4-9007-8a15171a8907
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132363990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4132363990
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2498121815
Short name T41
Test name
Test status
Simulation time 92132891 ps
CPU time 0.84 seconds
Started Jan 21 09:23:28 PM PST 24
Finished Jan 21 09:23:40 PM PST 24
Peak memory 191108 kb
Host smart-65e5df2f-425b-4297-8175-bc9f1e85c835
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2498121815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2498121815
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.92643016
Short name T171
Test name
Test status
Simulation time 224356403 ps
CPU time 1.28 seconds
Started Jan 21 09:23:57 PM PST 24
Finished Jan 21 09:24:09 PM PST 24
Peak memory 191232 kb
Host smart-8d9aeb45-3cf5-42c1-b599-40725ca0a3bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92643016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.92643016
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4181064559
Short name T201
Test name
Test status
Simulation time 152273458 ps
CPU time 1.14 seconds
Started Jan 21 08:56:39 PM PST 24
Finished Jan 21 08:57:19 PM PST 24
Peak memory 191280 kb
Host smart-a1dfbd16-db3d-4618-af04-33a94560a022
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4181064559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4181064559
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.872595115
Short name T203
Test name
Test status
Simulation time 131656148 ps
CPU time 0.91 seconds
Started Jan 21 08:56:56 PM PST 24
Finished Jan 21 08:57:29 PM PST 24
Peak memory 197052 kb
Host smart-ac1aa1ae-75f9-4709-a444-d853b083eb6e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872595115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.872595115
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3802266019
Short name T225
Test name
Test status
Simulation time 69024713 ps
CPU time 1.13 seconds
Started Jan 21 08:57:02 PM PST 24
Finished Jan 21 08:57:34 PM PST 24
Peak memory 191300 kb
Host smart-839b2201-c501-4c58-a2fc-da8846781ee1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3802266019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3802266019
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3768615839
Short name T213
Test name
Test status
Simulation time 30017904 ps
CPU time 0.85 seconds
Started Jan 21 08:57:02 PM PST 24
Finished Jan 21 08:57:33 PM PST 24
Peak memory 191328 kb
Host smart-f0598e2b-a208-4245-9284-5ceaa2112045
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768615839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3768615839
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3573880075
Short name T180
Test name
Test status
Simulation time 107125872 ps
CPU time 0.97 seconds
Started Jan 21 10:00:20 PM PST 24
Finished Jan 21 10:00:32 PM PST 24
Peak memory 191340 kb
Host smart-e1807fe7-150d-4e13-8986-266ee1af0779
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3573880075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3573880075
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3743093572
Short name T204
Test name
Test status
Simulation time 277293492 ps
CPU time 1.22 seconds
Started Jan 21 08:56:06 PM PST 24
Finished Jan 21 08:56:40 PM PST 24
Peak memory 191340 kb
Host smart-5d648e4c-0a36-4b9d-b085-6fa1fc7f446c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743093572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3743093572
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2131476958
Short name T219
Test name
Test status
Simulation time 30542375 ps
CPU time 0.79 seconds
Started Jan 21 08:57:01 PM PST 24
Finished Jan 21 08:57:32 PM PST 24
Peak memory 195820 kb
Host smart-c4dc683b-6958-46e2-805b-c4e6da8575b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2131476958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2131476958
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2335780132
Short name T147
Test name
Test status
Simulation time 68025041 ps
CPU time 1.31 seconds
Started Jan 21 08:57:03 PM PST 24
Finished Jan 21 08:57:34 PM PST 24
Peak memory 191304 kb
Host smart-468a041c-fb6f-4abc-aa95-fecc47b05e57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335780132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2335780132
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4194799384
Short name T172
Test name
Test status
Simulation time 33886484 ps
CPU time 1.21 seconds
Started Jan 21 08:57:02 PM PST 24
Finished Jan 21 08:57:33 PM PST 24
Peak memory 197160 kb
Host smart-3d0274fd-e7bf-4caf-a6a8-ae46141d6d9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4194799384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4194799384
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3021163579
Short name T185
Test name
Test status
Simulation time 114161548 ps
CPU time 1.02 seconds
Started Jan 21 08:57:12 PM PST 24
Finished Jan 21 08:57:43 PM PST 24
Peak memory 191324 kb
Host smart-691a47c3-c3d1-4c3b-8be2-7ccb51c6198e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021163579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3021163579
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1720931640
Short name T73
Test name
Test status
Simulation time 704701124 ps
CPU time 1.46 seconds
Started Jan 21 08:57:12 PM PST 24
Finished Jan 21 08:57:43 PM PST 24
Peak memory 197680 kb
Host smart-98e7e38f-02ed-42fb-a5c5-7820022cfff4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1720931640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1720931640
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1710078124
Short name T195
Test name
Test status
Simulation time 85209934 ps
CPU time 1.19 seconds
Started Jan 21 08:57:12 PM PST 24
Finished Jan 21 08:57:44 PM PST 24
Peak memory 197660 kb
Host smart-b881c86e-1121-4f4e-95db-3f203e24e08c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710078124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1710078124
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2896907454
Short name T187
Test name
Test status
Simulation time 91571258 ps
CPU time 1.4 seconds
Started Jan 21 08:57:13 PM PST 24
Finished Jan 21 08:57:45 PM PST 24
Peak memory 191336 kb
Host smart-faeb66a4-a5a1-4f5b-8853-01efe2794d18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2896907454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2896907454
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2081022448
Short name T169
Test name
Test status
Simulation time 201860039 ps
CPU time 1.05 seconds
Started Jan 21 08:57:11 PM PST 24
Finished Jan 21 08:57:42 PM PST 24
Peak memory 191248 kb
Host smart-030ecf14-6378-412f-8320-0e65befb20a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081022448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2081022448
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3532371813
Short name T146
Test name
Test status
Simulation time 149419770 ps
CPU time 1.18 seconds
Started Jan 21 08:57:17 PM PST 24
Finished Jan 21 08:57:48 PM PST 24
Peak memory 197656 kb
Host smart-906bb48f-2f53-494d-a00c-494f3617fff3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3532371813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3532371813
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3014369444
Short name T175
Test name
Test status
Simulation time 189174015 ps
CPU time 1.15 seconds
Started Jan 21 08:57:12 PM PST 24
Finished Jan 21 08:57:44 PM PST 24
Peak memory 197456 kb
Host smart-fff8a081-ff96-4af2-a004-d20d0c4665dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014369444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3014369444
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1052895834
Short name T144
Test name
Test status
Simulation time 49462815 ps
CPU time 1.18 seconds
Started Jan 21 08:57:14 PM PST 24
Finished Jan 21 08:57:46 PM PST 24
Peak memory 191280 kb
Host smart-3b7ab3a7-72c1-49e3-aafe-a219c877cbdb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1052895834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1052895834
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136354172
Short name T181
Test name
Test status
Simulation time 198271350 ps
CPU time 1.24 seconds
Started Jan 21 08:57:16 PM PST 24
Finished Jan 21 08:57:48 PM PST 24
Peak memory 197164 kb
Host smart-cd031953-8ed4-4eba-97ba-806cbd36d0fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136354172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.136354172
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2868857377
Short name T193
Test name
Test status
Simulation time 215323358 ps
CPU time 1.03 seconds
Started Jan 21 08:57:19 PM PST 24
Finished Jan 21 08:57:49 PM PST 24
Peak memory 191336 kb
Host smart-407e7319-83a1-43b1-aff4-fe0311f5bff5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2868857377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2868857377
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2865290600
Short name T228
Test name
Test status
Simulation time 191712838 ps
CPU time 1.25 seconds
Started Jan 21 08:57:13 PM PST 24
Finished Jan 21 08:57:45 PM PST 24
Peak memory 191344 kb
Host smart-d1d30474-cdb8-457a-abb8-a2af1befab0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865290600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2865290600
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.407613083
Short name T206
Test name
Test status
Simulation time 198965405 ps
CPU time 1.1 seconds
Started Jan 21 08:57:11 PM PST 24
Finished Jan 21 08:57:42 PM PST 24
Peak memory 197156 kb
Host smart-2be183fd-d566-4e76-b3a2-d961b4e81654
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=407613083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.407613083
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1305321373
Short name T222
Test name
Test status
Simulation time 71931502 ps
CPU time 1.28 seconds
Started Jan 21 08:57:12 PM PST 24
Finished Jan 21 08:57:44 PM PST 24
Peak memory 191400 kb
Host smart-e8aa3204-721d-4c77-a2d9-db6df43b9172
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305321373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1305321373
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3305133198
Short name T223
Test name
Test status
Simulation time 52744973 ps
CPU time 1.12 seconds
Started Jan 21 08:57:13 PM PST 24
Finished Jan 21 08:57:45 PM PST 24
Peak memory 191296 kb
Host smart-8ee862c9-5fa7-4ca9-aefe-de8c20dea667
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3305133198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3305133198
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.16187619
Short name T207
Test name
Test status
Simulation time 145479176 ps
CPU time 1.19 seconds
Started Jan 21 08:57:13 PM PST 24
Finished Jan 21 08:57:45 PM PST 24
Peak memory 191328 kb
Host smart-9990a820-b628-4e1f-baa2-56025824d822
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.16187619
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1750993167
Short name T192
Test name
Test status
Simulation time 242913516 ps
CPU time 0.83 seconds
Started Jan 21 08:57:16 PM PST 24
Finished Jan 21 08:57:47 PM PST 24
Peak memory 191112 kb
Host smart-7ca4b430-7c97-4cb7-befe-0377a7a5c5aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1750993167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1750993167
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2972720537
Short name T215
Test name
Test status
Simulation time 42072657 ps
CPU time 0.96 seconds
Started Jan 21 08:57:11 PM PST 24
Finished Jan 21 08:57:42 PM PST 24
Peak memory 191340 kb
Host smart-673067f7-53b5-4401-9fa1-23ad444d28e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972720537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2972720537
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1490471947
Short name T191
Test name
Test status
Simulation time 133794742 ps
CPU time 1.11 seconds
Started Jan 21 08:56:06 PM PST 24
Finished Jan 21 08:56:39 PM PST 24
Peak memory 191324 kb
Host smart-847c84b8-d20b-46dc-8d31-d2ae8ad960c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490471947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1490471947
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2369577363
Short name T53
Test name
Test status
Simulation time 93954885 ps
CPU time 0.79 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191156 kb
Host smart-056e2744-79c7-4603-b737-99386df40431
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2369577363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2369577363
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3349557883
Short name T56
Test name
Test status
Simulation time 173143712 ps
CPU time 1.3 seconds
Started Jan 21 09:13:43 PM PST 24
Finished Jan 21 09:13:46 PM PST 24
Peak memory 191332 kb
Host smart-d554b054-22f9-453f-b6b0-0437a11efb50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349557883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3349557883
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.355597318
Short name T152
Test name
Test status
Simulation time 20915124 ps
CPU time 0.74 seconds
Started Jan 21 08:56:09 PM PST 24
Finished Jan 21 08:56:44 PM PST 24
Peak memory 191332 kb
Host smart-7dc15534-cc76-43ac-b605-d2cbebe052f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=355597318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.355597318
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1826171717
Short name T54
Test name
Test status
Simulation time 272770662 ps
CPU time 1.02 seconds
Started Jan 21 08:56:15 PM PST 24
Finished Jan 21 08:56:54 PM PST 24
Peak memory 191272 kb
Host smart-345a7017-8d17-49df-b522-ac5143ed165f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826171717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1826171717
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.582126850
Short name T163
Test name
Test status
Simulation time 36788837 ps
CPU time 1.19 seconds
Started Jan 21 08:56:17 PM PST 24
Finished Jan 21 08:56:57 PM PST 24
Peak memory 197716 kb
Host smart-aa28c1ad-1656-4f94-8063-639f838d1565
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=582126850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.582126850
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2067988608
Short name T167
Test name
Test status
Simulation time 58130997 ps
CPU time 1.03 seconds
Started Jan 21 08:56:14 PM PST 24
Finished Jan 21 08:56:53 PM PST 24
Peak memory 191128 kb
Host smart-923a0f12-bf97-4abb-91fe-6d19162bf9f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067988608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2067988608
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3460750004
Short name T209
Test name
Test status
Simulation time 40552615 ps
CPU time 1.19 seconds
Started Jan 21 08:56:16 PM PST 24
Finished Jan 21 08:56:56 PM PST 24
Peak memory 197620 kb
Host smart-b3d72e80-72a5-4924-ae44-d189f517a032
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3460750004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3460750004
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279104369
Short name T173
Test name
Test status
Simulation time 106569109 ps
CPU time 1.65 seconds
Started Jan 21 08:56:16 PM PST 24
Finished Jan 21 08:56:56 PM PST 24
Peak memory 191272 kb
Host smart-1c3afc96-6dde-4751-b6de-5239d99c8e6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279104369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1279104369
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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