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Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2588580 1 T51 134 T52 50 T53 34
auto[1] 2270461 1 T51 100 T52 52 T53 38


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3059683 1 T51 104 T52 51 T53 38
auto[1] 1799358 1 T51 130 T52 51 T53 34


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1682934 1 T51 57 T52 23 T53 23
auto[0] auto[1] 905646 1 T51 77 T52 27 T53 11
auto[1] auto[0] 1376749 1 T51 47 T52 28 T53 15
auto[1] auto[1] 893712 1 T51 53 T52 24 T53 23


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2589954 1 T51 114 T52 58 T53 36
auto[1] 2269087 1 T51 120 T52 44 T53 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3064475 1 T51 105 T52 45 T53 33
auto[1] 1794566 1 T51 129 T52 57 T53 39


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1688283 1 T51 52 T52 28 T53 20
auto[0] auto[1] 901671 1 T51 62 T52 30 T53 16
auto[1] auto[0] 1376192 1 T51 53 T52 17 T53 13
auto[1] auto[1] 892895 1 T51 67 T52 27 T53 23


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2588134 1 T51 126 T52 50 T53 28
auto[1] 2270907 1 T51 108 T52 52 T53 44


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3067569 1 T51 119 T52 54 T53 43
auto[1] 1791472 1 T51 115 T52 48 T53 29


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1686108 1 T51 65 T52 25 T53 18
auto[0] auto[1] 902026 1 T51 61 T52 25 T53 10
auto[1] auto[0] 1381461 1 T51 54 T52 29 T53 25
auto[1] auto[1] 889446 1 T51 54 T52 23 T53 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2591778 1 T51 116 T52 58 T53 28
auto[1] 2267263 1 T51 118 T52 44 T53 44


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3064977 1 T51 121 T52 59 T53 36
auto[1] 1794064 1 T51 113 T52 43 T53 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1689476 1 T51 62 T52 31 T53 16
auto[0] auto[1] 902302 1 T51 54 T52 27 T53 12
auto[1] auto[0] 1375501 1 T51 59 T52 28 T53 20
auto[1] auto[1] 891762 1 T51 59 T52 16 T53 24


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2588793 1 T51 120 T52 46 T53 30
auto[1] 2270248 1 T51 114 T52 56 T53 42


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3064713 1 T51 99 T52 49 T53 39
auto[1] 1794328 1 T51 135 T52 53 T53 33


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1686666 1 T51 47 T52 21 T53 18
auto[0] auto[1] 902127 1 T51 73 T52 25 T53 12
auto[1] auto[0] 1378047 1 T51 52 T52 28 T53 21
auto[1] auto[1] 892201 1 T51 62 T52 28 T53 21


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2591611 1 T51 114 T52 46 T53 34
auto[1] 2267430 1 T51 120 T52 56 T53 38


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3059956 1 T51 127 T52 58 T53 38
auto[1] 1799085 1 T51 107 T52 44 T53 34


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1684095 1 T51 69 T52 27 T53 19
auto[0] auto[1] 907516 1 T51 45 T52 19 T53 15
auto[1] auto[0] 1375861 1 T51 58 T52 31 T53 19
auto[1] auto[1] 891569 1 T51 62 T52 25 T53 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2591451 1 T51 110 T52 58 T53 38
auto[1] 2267590 1 T51 124 T52 44 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3063985 1 T51 99 T52 43 T53 40
auto[1] 1795056 1 T51 135 T52 59 T53 32


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1688695 1 T51 51 T52 22 T53 25
auto[0] auto[1] 902756 1 T51 59 T52 36 T53 13
auto[1] auto[0] 1375290 1 T51 48 T52 21 T53 15
auto[1] auto[1] 892300 1 T51 76 T52 23 T53 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2589036 1 T51 126 T52 50 T53 42
auto[1] 2270005 1 T51 108 T52 52 T53 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3063186 1 T51 123 T52 51 T53 41
auto[1] 1795855 1 T51 111 T52 51 T53 31


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1685934 1 T51 66 T52 23 T53 25
auto[0] auto[1] 903102 1 T51 60 T52 27 T53 17
auto[1] auto[0] 1377252 1 T51 57 T52 28 T53 16
auto[1] auto[1] 892753 1 T51 51 T52 24 T53 14


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2594656 1 T51 120 T52 46 T53 44
auto[1] 2264385 1 T51 114 T52 56 T53 28


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3076707 1 T51 120 T52 39 T53 41
auto[1] 1782334 1 T51 114 T52 63 T53 31


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1696836 1 T51 63 T52 17 T53 27
auto[0] auto[1] 897820 1 T51 57 T52 29 T53 17
auto[1] auto[0] 1379871 1 T51 57 T52 22 T53 14
auto[1] auto[1] 884514 1 T51 57 T52 34 T53 14


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2595795 1 T51 116 T52 48 T53 38
auto[1] 2263246 1 T51 118 T52 54 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3076300 1 T51 114 T52 57 T53 31
auto[1] 1782741 1 T51 120 T52 45 T53 41


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1696537 1 T51 56 T52 24 T53 17
auto[0] auto[1] 899258 1 T51 60 T52 24 T53 21
auto[1] auto[0] 1379763 1 T51 58 T52 33 T53 14
auto[1] auto[1] 883483 1 T51 60 T52 21 T53 20


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2593808 1 T51 116 T52 50 T53 38
auto[1] 2265233 1 T51 118 T52 52 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073552 1 T51 80 T52 56 T53 35
auto[1] 1785489 1 T51 154 T52 46 T53 37


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1696130 1 T51 40 T52 23 T53 17
auto[0] auto[1] 897678 1 T51 76 T52 27 T53 21
auto[1] auto[0] 1377422 1 T51 40 T52 33 T53 18
auto[1] auto[1] 887811 1 T51 78 T52 19 T53 16


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2593054 1 T51 138 T52 50 T53 32
auto[1] 2265987 1 T51 96 T52 52 T53 40


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3070911 1 T51 121 T52 59 T53 36
auto[1] 1788130 1 T51 113 T52 43 T53 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1692206 1 T51 71 T52 29 T53 19
auto[0] auto[1] 900848 1 T51 67 T52 21 T53 13
auto[1] auto[0] 1378705 1 T51 50 T52 30 T53 17
auto[1] auto[1] 887282 1 T51 46 T52 22 T53 23


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2588988 1 T51 116 T52 50 T53 32
auto[1] 2270053 1 T51 118 T52 52 T53 40


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3064646 1 T51 112 T52 51 T53 36
auto[1] 1794395 1 T51 122 T52 51 T53 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1686146 1 T51 56 T52 25 T53 14
auto[0] auto[1] 902842 1 T51 60 T52 25 T53 18
auto[1] auto[0] 1378500 1 T51 56 T52 26 T53 22
auto[1] auto[1] 891553 1 T51 62 T52 26 T53 18


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2593361 1 T51 118 T52 64 T53 38
auto[1] 2265680 1 T51 116 T52 38 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3072219 1 T51 126 T52 56 T53 42
auto[1] 1786822 1 T51 108 T52 46 T53 30


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1693111 1 T51 67 T52 35 T53 22
auto[0] auto[1] 900250 1 T51 51 T52 29 T53 16
auto[1] auto[0] 1379108 1 T51 59 T52 21 T53 20
auto[1] auto[1] 886572 1 T51 57 T52 17 T53 14


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2594226 1 T51 116 T52 58 T53 36
auto[1] 2264815 1 T51 118 T52 44 T53 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073950 1 T51 124 T52 57 T53 34
auto[1] 1785091 1 T51 110 T52 45 T53 38


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1694940 1 T51 60 T52 29 T53 18
auto[0] auto[1] 899286 1 T51 56 T52 29 T53 18
auto[1] auto[0] 1379010 1 T51 64 T52 28 T53 16
auto[1] auto[1] 885805 1 T51 54 T52 16 T53 20


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2589468 1 T51 126 T52 56 T53 22
auto[1] 2269573 1 T51 108 T52 46 T53 50


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3070209 1 T51 125 T52 51 T53 36
auto[1] 1788832 1 T51 109 T52 51 T53 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1689530 1 T51 69 T52 30 T53 14
auto[0] auto[1] 899938 1 T51 57 T52 26 T53 8
auto[1] auto[0] 1380679 1 T51 56 T52 21 T53 22
auto[1] auto[1] 888894 1 T51 52 T52 25 T53 28


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2587494 1 T51 120 T52 54 T53 38
auto[1] 2271547 1 T51 114 T52 48 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3072606 1 T51 103 T52 42 T53 39
auto[1] 1786435 1 T51 131 T52 60 T53 33


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1690672 1 T51 50 T52 23 T53 20
auto[0] auto[1] 896822 1 T51 70 T52 31 T53 18
auto[1] auto[0] 1381934 1 T51 53 T52 19 T53 19
auto[1] auto[1] 889613 1 T51 61 T52 29 T53 15


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2595475 1 T51 108 T52 46 T53 30
auto[1] 2263566 1 T51 126 T52 56 T53 42


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073756 1 T51 137 T52 56 T53 32
auto[1] 1785285 1 T51 97 T52 46 T53 40


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1696009 1 T51 66 T52 27 T53 15
auto[0] auto[1] 899466 1 T51 42 T52 19 T53 15
auto[1] auto[0] 1377747 1 T51 71 T52 29 T53 17
auto[1] auto[1] 885819 1 T51 55 T52 27 T53 25


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2588676 1 T51 108 T52 32 T53 36
auto[1] 2270365 1 T51 126 T52 70 T53 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073854 1 T51 106 T52 47 T53 36
auto[1] 1785187 1 T51 128 T52 55 T53 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1691198 1 T51 51 T52 17 T53 19
auto[0] auto[1] 897478 1 T51 57 T52 15 T53 17
auto[1] auto[0] 1382656 1 T51 55 T52 30 T53 17
auto[1] auto[1] 887709 1 T51 71 T52 40 T53 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2595883 1 T51 138 T52 52 T53 26
auto[1] 2263158 1 T51 96 T52 50 T53 46


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073200 1 T51 119 T52 61 T53 42
auto[1] 1785841 1 T51 115 T52 41 T53 30


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1694378 1 T51 67 T52 26 T53 15
auto[0] auto[1] 901505 1 T51 71 T52 26 T53 11
auto[1] auto[0] 1378822 1 T51 52 T52 35 T53 27
auto[1] auto[1] 884336 1 T51 44 T52 15 T53 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2591981 1 T51 108 T52 52 T53 28
auto[1] 2267060 1 T51 126 T52 50 T53 44


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073610 1 T51 126 T52 52 T53 41
auto[1] 1785431 1 T51 108 T52 50 T53 31


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1692806 1 T51 61 T52 26 T53 18
auto[0] auto[1] 899175 1 T51 47 T52 26 T53 10
auto[1] auto[0] 1380804 1 T51 65 T52 26 T53 23
auto[1] auto[1] 886256 1 T51 61 T52 24 T53 21


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2593874 1 T51 116 T52 50 T53 38
auto[1] 2265167 1 T51 118 T52 52 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073988 1 T51 120 T52 50 T53 32
auto[1] 1785053 1 T51 114 T52 52 T53 40


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1695415 1 T51 60 T52 21 T53 14
auto[0] auto[1] 898459 1 T51 56 T52 29 T53 24
auto[1] auto[0] 1378573 1 T51 60 T52 29 T53 18
auto[1] auto[1] 886594 1 T51 58 T52 23 T53 16


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2590358 1 T51 128 T52 50 T53 34
auto[1] 2268683 1 T51 106 T52 52 T53 38


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3070671 1 T51 108 T52 56 T53 36
auto[1] 1788370 1 T51 126 T52 46 T53 36


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1689261 1 T51 57 T52 27 T53 17
auto[0] auto[1] 901097 1 T51 71 T52 23 T53 17
auto[1] auto[0] 1381410 1 T51 51 T52 29 T53 19
auto[1] auto[1] 887273 1 T51 55 T52 23 T53 19


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2594488 1 T51 116 T52 52 T53 38
auto[1] 2264553 1 T51 118 T52 50 T53 34


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3063662 1 T51 111 T52 43 T53 35
auto[1] 1795379 1 T51 123 T52 59 T53 37


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1689148 1 T51 49 T52 22 T53 18
auto[0] auto[1] 905340 1 T51 67 T52 30 T53 20
auto[1] auto[0] 1374514 1 T51 62 T52 21 T53 17
auto[1] auto[1] 890039 1 T51 56 T52 29 T53 17


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2585180 1 T51 110 T52 56 T53 42
auto[1] 2273861 1 T51 124 T52 46 T53 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073474 1 T51 106 T52 47 T53 29
auto[1] 1785567 1 T51 128 T52 55 T53 43


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1689284 1 T51 51 T52 26 T53 16
auto[0] auto[1] 895896 1 T51 59 T52 30 T53 26
auto[1] auto[0] 1384190 1 T51 55 T52 21 T53 13
auto[1] auto[1] 889671 1 T51 69 T52 25 T53 17


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2589654 1 T51 108 T52 52 T53 30
auto[1] 2269387 1 T51 126 T52 50 T53 42


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3073414 1 T51 113 T52 47 T53 41
auto[1] 1785627 1 T51 121 T52 55 T53 31


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1692453 1 T51 55 T52 24 T53 19
auto[0] auto[1] 897201 1 T51 53 T52 28 T53 11
auto[1] auto[0] 1380961 1 T51 58 T52 23 T53 22
auto[1] auto[1] 888426 1 T51 68 T52 27 T53 20


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2594616 1 T51 128 T52 50 T53 42
auto[1] 2264425 1 T51 106 T52 52 T53 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3068273 1 T51 113 T52 61 T53 31
auto[1] 1790768 1 T51 121 T52 41 T53 41

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%