Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5073849	1			T25	27		T26	10		T27	10
all_pins[1]	5073849	1			T25	27		T26	10		T27	10
all_pins[2]	5073849	1			T25	27		T26	10		T27	10
all_pins[3]	5073849	1			T25	27		T26	10		T27	10
all_pins[4]	5073849	1			T25	27		T26	10		T27	10
all_pins[5]	5073849	1			T25	27		T26	10		T27	10
all_pins[6]	5073849	1			T25	27		T26	10		T27	10
all_pins[7]	5073849	1			T25	27		T26	10		T27	10
all_pins[8]	5073849	1			T25	27		T26	10		T27	10
all_pins[9]	5073849	1			T25	27		T26	10		T27	10
all_pins[10]	5073849	1			T25	27		T26	10		T27	10
all_pins[11]	5073849	1			T25	27		T26	10		T27	10
all_pins[12]	5073849	1			T25	27		T26	10		T27	10
all_pins[13]	5073849	1			T25	27		T26	10		T27	10
all_pins[14]	5073849	1			T25	27		T26	10		T27	10
all_pins[15]	5073849	1			T25	27		T26	10		T27	10
all_pins[16]	5073849	1			T25	27		T26	10		T27	10
all_pins[17]	5073849	1			T25	27		T26	10		T27	10
all_pins[18]	5073849	1			T25	27		T26	10		T27	10
all_pins[19]	5073849	1			T25	27		T26	10		T27	10
all_pins[20]	5073849	1			T25	27		T26	10		T27	10
all_pins[21]	5073849	1			T25	27		T26	10		T27	10
all_pins[22]	5073849	1			T25	27		T26	10		T27	10
all_pins[23]	5073849	1			T25	27		T26	10		T27	10
all_pins[24]	5073849	1			T25	27		T26	10		T27	10
all_pins[25]	5073849	1			T25	27		T26	10		T27	10
all_pins[26]	5073849	1			T25	27		T26	10		T27	10
all_pins[27]	5073849	1			T25	27		T26	10		T27	10
all_pins[28]	5073849	1			T25	27		T26	10		T27	10
all_pins[29]	5073849	1			T25	27		T26	10		T27	10
all_pins[30]	5073849	1			T25	27		T26	10		T27	10
all_pins[31]	5073849	1			T25	27		T26	10		T27	10

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	100576853	1			T25	619		T26	201		T27	252
values[0x1]	61786315	1			T25	245		T26	119		T27	68
transitions[0x0=>0x1]	36927164	1			T25	167		T26	59		T27	49
transitions[0x1=>0x0]	36927014	1			T25	167		T26	59		T27	49

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3144599	1			T25	21		T26	4		T27	9
all_pins[0]	values[0x1]	1929250	1			T25	6		T26	6		T27	1
all_pins[0]	transitions[0x0=>0x1]	1190746	1			T25	5		T26	6		T27	1
all_pins[0]	transitions[0x1=>0x0]	1191024	1			T25	8		T27	1		T28	2
all_pins[1]	values[0x0]	3144142	1			T25	23		T26	7		T27	5
all_pins[1]	values[0x1]	1929707	1			T25	4		T26	3		T27	5
all_pins[1]	transitions[0x0=>0x1]	1152149	1			T25	2		T27	4		T28	2
all_pins[1]	transitions[0x1=>0x0]	1151692	1			T25	4		T26	3		T29	9
all_pins[2]	values[0x0]	3147285	1			T25	18		T26	5		T27	6
all_pins[2]	values[0x1]	1926564	1			T25	9		T26	5		T27	4
all_pins[2]	transitions[0x0=>0x1]	1150955	1			T25	5		T26	4		T27	2
all_pins[2]	transitions[0x1=>0x0]	1154098	1			T26	2		T27	3		T29	1
all_pins[3]	values[0x0]	3141519	1			T25	17		T26	7		T27	10
all_pins[3]	values[0x1]	1932330	1			T25	10		T26	3		T28	6
all_pins[3]	transitions[0x0=>0x1]	1155735	1			T25	6		T26	1		T28	1
all_pins[3]	transitions[0x1=>0x0]	1149969	1			T25	5		T26	3		T27	4
all_pins[4]	values[0x0]	3143126	1			T25	11		T26	5		T27	9
all_pins[4]	values[0x1]	1930723	1			T25	16		T26	5		T27	1
all_pins[4]	transitions[0x0=>0x1]	1151992	1			T25	11		T26	4		T27	1
all_pins[4]	transitions[0x1=>0x0]	1153599	1			T25	5		T26	2		T28	5
all_pins[5]	values[0x0]	3138350	1			T25	14		T26	5		T27	7
all_pins[5]	values[0x1]	1935499	1			T25	13		T26	5		T27	3
all_pins[5]	transitions[0x0=>0x1]	1153607	1			T25	6		T26	1		T27	3
all_pins[5]	transitions[0x1=>0x0]	1148831	1			T25	9		T26	1		T27	1
all_pins[6]	values[0x0]	3139269	1			T25	16		T26	7		T27	5
all_pins[6]	values[0x1]	1934580	1			T25	11		T26	3		T27	5
all_pins[6]	transitions[0x0=>0x1]	1156378	1			T25	3		T26	1		T27	3
all_pins[6]	transitions[0x1=>0x0]	1157297	1			T25	5		T26	3		T27	1
all_pins[7]	values[0x0]	3145155	1			T25	19		T26	10		T27	5
all_pins[7]	values[0x1]	1928694	1			T25	8		T27	5		T28	2
all_pins[7]	transitions[0x0=>0x1]	1151399	1			T25	4		T27	3		T28	2
all_pins[7]	transitions[0x1=>0x0]	1157285	1			T25	7		T26	3		T27	3
all_pins[8]	values[0x0]	3148493	1			T25	27		T26	5		T27	8
all_pins[8]	values[0x1]	1925356	1			T26	5		T27	2		T28	3
all_pins[8]	transitions[0x0=>0x1]	1149506	1			T26	5		T27	2		T28	1
all_pins[8]	transitions[0x1=>0x0]	1152844	1			T25	8		T27	5		T29	4
all_pins[9]	values[0x0]	3138814	1			T25	25		T26	5		T27	10
all_pins[9]	values[0x1]	1935035	1			T25	2		T26	5		T28	5
all_pins[9]	transitions[0x0=>0x1]	1156786	1			T25	2		T26	2		T28	3
all_pins[9]	transitions[0x1=>0x0]	1147107	1			T26	2		T27	2		T28	1
all_pins[10]	values[0x0]	3144646	1			T25	23		T26	4		T27	9
all_pins[10]	values[0x1]	1929203	1			T25	4		T26	6		T27	1
all_pins[10]	transitions[0x0=>0x1]	1151297	1			T25	4		T26	2		T27	1
all_pins[10]	transitions[0x1=>0x0]	1157129	1			T25	2		T26	1		T28	5
all_pins[11]	values[0x0]	3143787	1			T25	17		T26	6		T27	3
all_pins[11]	values[0x1]	1930062	1			T25	10		T26	4		T27	7
all_pins[11]	transitions[0x0=>0x1]	1153423	1			T25	9		T26	1		T27	6
all_pins[11]	transitions[0x1=>0x0]	1152564	1			T25	3		T26	3		T29	3
all_pins[12]	values[0x0]	3132952	1			T25	19		T26	6		T27	10
all_pins[12]	values[0x1]	1940897	1			T25	8		T26	4		T28	1
all_pins[12]	transitions[0x0=>0x1]	1161516	1			T25	6		T26	2		T29	10
all_pins[12]	transitions[0x1=>0x0]	1150681	1			T25	8		T26	2		T27	7
all_pins[13]	values[0x0]	3140945	1			T25	20		T26	7		T27	6
all_pins[13]	values[0x1]	1932904	1			T25	7		T26	3		T27	4
all_pins[13]	transitions[0x0=>0x1]	1150594	1			T25	4		T26	1		T27	4
all_pins[13]	transitions[0x1=>0x0]	1158587	1			T25	5		T26	2		T28	1
all_pins[14]	values[0x0]	3143028	1			T25	18		T26	5		T27	3
all_pins[14]	values[0x1]	1930821	1			T25	9		T26	5		T27	7
all_pins[14]	transitions[0x0=>0x1]	1151987	1			T25	7		T26	3		T27	4
all_pins[14]	transitions[0x1=>0x0]	1154070	1			T25	5		T26	1		T27	1
all_pins[15]	values[0x0]	3142132	1			T25	17		T26	4		T27	7
all_pins[15]	values[0x1]	1931717	1			T25	10		T26	6		T27	3
all_pins[15]	transitions[0x0=>0x1]	1154470	1			T25	6		T26	2		T27	1
all_pins[15]	transitions[0x1=>0x0]	1153574	1			T25	5		T26	1		T27	5
all_pins[16]	values[0x0]	3141777	1			T25	21		T26	8		T27	8
all_pins[16]	values[0x1]	1932072	1			T25	6		T26	2		T27	2
all_pins[16]	transitions[0x0=>0x1]	1154229	1			T25	3		T26	1		T28	4
all_pins[16]	transitions[0x1=>0x0]	1153874	1			T25	7		T26	5		T27	1
all_pins[17]	values[0x0]	3140008	1			T25	26		T26	6		T27	10
all_pins[17]	values[0x1]	1933841	1			T25	1		T26	4		T28	2
all_pins[17]	transitions[0x0=>0x1]	1154696	1			T26	3		T29	7		T30	1
all_pins[17]	transitions[0x1=>0x0]	1152927	1			T25	5		T26	1		T27	2
all_pins[18]	values[0x0]	3146445	1			T25	17		T26	8		T27	7
all_pins[18]	values[0x1]	1927404	1			T25	10		T26	2		T27	3
all_pins[18]	transitions[0x0=>0x1]	1147897	1			T25	9		T27	3		T28	2
all_pins[18]	transitions[0x1=>0x0]	1154334	1			T26	2		T29	6		T30	1
all_pins[19]	values[0x0]	3147711	1			T25	22		T26	7		T27	9
all_pins[19]	values[0x1]	1926138	1			T25	5		T26	3		T27	1
all_pins[19]	transitions[0x0=>0x1]	1149920	1			T26	2		T29	2		T30	4
all_pins[19]	transitions[0x1=>0x0]	1151186	1			T25	5		T26	1		T27	2
all_pins[20]	values[0x0]	3137733	1			T25	10		T26	6		T27	10
all_pins[20]	values[0x1]	1936116	1			T25	17		T26	4		T28	5
all_pins[20]	transitions[0x0=>0x1]	1157561	1			T25	14		T26	2		T28	5
all_pins[20]	transitions[0x1=>0x0]	1147583	1			T25	2		T26	1		T27	1
all_pins[21]	values[0x0]	3146528	1			T25	22		T26	7		T27	9
all_pins[21]	values[0x1]	1927321	1			T25	5		T26	3		T27	1
all_pins[21]	transitions[0x0=>0x1]	1148811	1			T25	3		T26	1		T27	1
all_pins[21]	transitions[0x1=>0x0]	1157606	1			T25	15		T26	2		T28	4
all_pins[22]	values[0x0]	3144005	1			T25	20		T26	4		T27	9
all_pins[22]	values[0x1]	1929844	1			T25	7		T26	6		T27	1
all_pins[22]	transitions[0x0=>0x1]	1151499	1			T25	6		T26	4		T27	1
all_pins[22]	transitions[0x1=>0x0]	1148976	1			T25	4		T26	1		T27	1
all_pins[23]	values[0x0]	3143882	1			T25	18		T26	6		T27	10
all_pins[23]	values[0x1]	1929967	1			T25	9		T26	4		T28	4
all_pins[23]	transitions[0x0=>0x1]	1151562	1			T25	8		T28	4		T29	2
all_pins[23]	transitions[0x1=>0x0]	1151439	1			T25	6		T26	2		T27	1
all_pins[24]	values[0x0]	3144567	1			T25	18		T26	5		T27	6
all_pins[24]	values[0x1]	1929282	1			T25	9		T26	5		T27	4
all_pins[24]	transitions[0x0=>0x1]	1151593	1			T25	6		T26	3		T27	4
all_pins[24]	transitions[0x1=>0x0]	1152278	1			T25	6		T26	2		T28	2
all_pins[25]	values[0x0]	3138352	1			T25	14		T26	8		T27	8
all_pins[25]	values[0x1]	1935497	1			T25	13		T26	2		T27	2
all_pins[25]	transitions[0x0=>0x1]	1155344	1			T25	6		T26	1		T27	1
all_pins[25]	transitions[0x1=>0x0]	1149129	1			T25	2		T26	4		T27	3
all_pins[26]	values[0x0]	3144987	1			T25	23		T26	6		T27	9
all_pins[26]	values[0x1]	1928862	1			T25	4		T26	4		T27	1
all_pins[26]	transitions[0x0=>0x1]	1150355	1			T25	3		T26	2		T28	2
all_pins[26]	transitions[0x1=>0x0]	1156990	1			T25	12		T27	1		T29	5
all_pins[27]	values[0x0]	3151479	1			T25	19		T26	7		T27	10
all_pins[27]	values[0x1]	1922370	1			T25	8		T26	3		T28	1
all_pins[27]	transitions[0x0=>0x1]	1148461	1			T25	7		T28	1		T30	1
all_pins[27]	transitions[0x1=>0x0]	1154953	1			T25	3		T26	1		T27	1
all_pins[28]	values[0x0]	3141658	1			T25	20		T26	7		T27	10
all_pins[28]	values[0x1]	1932191	1			T25	7		T26	3		T28	5
all_pins[28]	transitions[0x0=>0x1]	1158648	1			T25	7		T26	2		T28	4
all_pins[28]	transitions[0x1=>0x0]	1148827	1			T25	8		T26	2		T29	3
all_pins[29]	values[0x0]	3140647	1			T25	21		T26	6		T27	7
all_pins[29]	values[0x1]	1933202	1			T25	6		T26	4		T27	3
all_pins[29]	transitions[0x0=>0x1]	1153684	1			T25	6		T26	3		T27	3
all_pins[29]	transitions[0x1=>0x0]	1152673	1			T25	7		T26	2		T28	3
all_pins[30]	values[0x0]	3144661	1			T25	25		T26	8		T27	9
all_pins[30]	values[0x1]	1929188	1			T25	2		T26	2		T27	1
all_pins[30]	transitions[0x0=>0x1]	1151035	1			T25	2		T28	3		T29	5
all_pins[30]	transitions[0x1=>0x0]	1155049	1			T25	6		T26	2		T27	2
all_pins[31]	values[0x0]	3144171	1			T25	18		T26	10		T27	9
all_pins[31]	values[0x1]	1929678	1			T25	9		T27	1		T28	2
all_pins[31]	transitions[0x0=>0x1]	1149329	1			T25	7		T27	1		T28	1
all_pins[31]	transitions[0x1=>0x0]	1148839	1			T26	2		T27	1		T28	2