Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17769182	1			T25	30		T26	12		T27	12
all_values[1]	17769182	1			T25	30		T26	12		T27	12
all_values[2]	17769182	1			T25	30		T26	12		T27	12
all_values[3]	17769182	1			T25	30		T26	12		T27	12
all_values[4]	17769182	1			T25	30		T26	12		T27	12
all_values[5]	17769182	1			T25	30		T26	12		T27	12
all_values[6]	17769182	1			T25	30		T26	12		T27	12
all_values[7]	17769182	1			T25	30		T26	12		T27	12
all_values[8]	17769182	1			T25	30		T26	12		T27	12
all_values[9]	17769182	1			T25	30		T26	12		T27	12
all_values[10]	17769182	1			T25	30		T26	12		T27	12
all_values[11]	17769182	1			T25	30		T26	12		T27	12
all_values[12]	17769182	1			T25	30		T26	12		T27	12
all_values[13]	17769182	1			T25	30		T26	12		T27	12
all_values[14]	17769182	1			T25	30		T26	12		T27	12
all_values[15]	17769182	1			T25	30		T26	12		T27	12
all_values[16]	17769182	1			T25	30		T26	12		T27	12
all_values[17]	17769182	1			T25	30		T26	12		T27	12
all_values[18]	17769182	1			T25	30		T26	12		T27	12
all_values[19]	17769182	1			T25	30		T26	12		T27	12
all_values[20]	17769182	1			T25	30		T26	12		T27	12
all_values[21]	17769182	1			T25	30		T26	12		T27	12
all_values[22]	17769182	1			T25	30		T26	12		T27	12
all_values[23]	17769182	1			T25	30		T26	12		T27	12
all_values[24]	17769182	1			T25	30		T26	12		T27	12
all_values[25]	17769182	1			T25	30		T26	12		T27	12
all_values[26]	17769182	1			T25	30		T26	12		T27	12
all_values[27]	17769182	1			T25	30		T26	12		T27	12
all_values[28]	17769182	1			T25	30		T26	12		T27	12
all_values[29]	17769182	1			T25	30		T26	12		T27	12
all_values[30]	17769182	1			T25	30		T26	12		T27	12
all_values[31]	17769182	1			T25	30		T26	12		T27	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321340217

1

T25

453

T26

276

T27

173

auto[1]

247273607

1

T25

507

T26

108

T27

211

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119495857

1

T25

513

T26

188

T27

249

auto[1]

449117967

1

T25

447

T26

196

T27

135

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

562340620

1

T25

802

T26

384

T27

334

auto[1]

6273204

1

T25

158

T27

50

T28

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3034204	1			T25	9		T26	2		T27	6
all_values[0]	auto[0]	auto[0]	auto[1]	6929460	1			T25	9		T26	4		T28	1
all_values[0]	auto[0]	auto[1]	auto[0]	708459	1			T25	3		T26	6		T27	4
all_values[0]	auto[0]	auto[1]	auto[1]	6900800	1			T25	3		T27	1		T29	5
all_values[0]	auto[1]	auto[0]	auto[1]	98195	1			T25	3		T28	1		T29	2
all_values[0]	auto[1]	auto[1]	auto[1]	98064	1			T25	3		T27	1		T29	4
all_values[1]	auto[0]	auto[0]	auto[0]	3022131	1			T25	7		T26	8		T27	1
all_values[1]	auto[0]	auto[0]	auto[1]	6933181	1			T25	5		T26	4		T29	5
all_values[1]	auto[0]	auto[1]	auto[0]	707045	1			T25	12		T27	5		T28	8
all_values[1]	auto[0]	auto[1]	auto[1]	6910793	1			T25	1		T27	5		T28	2
all_values[1]	auto[1]	auto[0]	auto[1]	98319	1			T25	2		T29	2		T32	1
all_values[1]	auto[1]	auto[1]	auto[1]	97713	1			T25	3		T27	1		T28	1
all_values[2]	auto[0]	auto[0]	auto[0]	3027864	1			T25	11		T26	2		T27	2
all_values[2]	auto[0]	auto[0]	auto[1]	6907031	1			T25	5		T26	4		T27	3
all_values[2]	auto[0]	auto[1]	auto[0]	708554	1			T25	4		T27	2		T28	4
all_values[2]	auto[0]	auto[1]	auto[1]	6929708	1			T25	5		T26	6		T27	2
all_values[2]	auto[1]	auto[0]	auto[1]	98311	1			T25	1		T27	1		T29	5
all_values[2]	auto[1]	auto[1]	auto[1]	97714	1			T25	4		T27	2		T28	3
all_values[3]	auto[0]	auto[0]	auto[0]	3022855	1			T25	8		T26	2		T27	1
all_values[3]	auto[0]	auto[0]	auto[1]	6872048	1			T25	5		T26	4		T29	7
all_values[3]	auto[0]	auto[1]	auto[0]	715763	1			T25	6		T27	11		T28	4
all_values[3]	auto[0]	auto[1]	auto[1]	6962856	1			T25	5		T26	6		T28	5
all_values[3]	auto[1]	auto[0]	auto[1]	97743	1			T25	1		T29	3		T32	1
all_values[3]	auto[1]	auto[1]	auto[1]	97917	1			T25	5		T28	2		T29	3
all_values[4]	auto[0]	auto[0]	auto[0]	3023345	1			T25	3		T26	4		T27	5
all_values[4]	auto[0]	auto[0]	auto[1]	6906899	1			T25	5		T26	2		T27	3
all_values[4]	auto[0]	auto[1]	auto[0]	707274	1			T25	1		T28	2		T29	2
all_values[4]	auto[0]	auto[1]	auto[1]	6935448	1			T25	14		T26	6		T27	1
all_values[4]	auto[1]	auto[0]	auto[1]	98082	1			T25	4		T27	3		T28	1
all_values[4]	auto[1]	auto[1]	auto[1]	98134	1			T25	3		T29	3		T32	1
all_values[5]	auto[0]	auto[0]	auto[0]	3022916	1			T25	8		T26	2		T27	2
all_values[5]	auto[0]	auto[0]	auto[1]	6927639	1			T25	1		T26	4		T27	5
all_values[5]	auto[0]	auto[1]	auto[0]	703195	1			T25	6		T26	3		T27	2
all_values[5]	auto[0]	auto[1]	auto[1]	6919442	1			T25	10		T26	3		T27	1
all_values[5]	auto[1]	auto[0]	auto[1]	97957	1			T25	1		T29	2		T32	2
all_values[5]	auto[1]	auto[1]	auto[1]	98033	1			T25	4		T27	2		T28	1
all_values[6]	auto[0]	auto[0]	auto[0]	3022714	1			T25	5		T26	3		T27	1
all_values[6]	auto[0]	auto[0]	auto[1]	6905126	1			T25	3		T26	9		T27	1
all_values[6]	auto[0]	auto[1]	auto[0]	708586	1			T25	7		T27	4		T28	11
all_values[6]	auto[0]	auto[1]	auto[1]	6936629	1			T25	6		T27	3		T29	3
all_values[6]	auto[1]	auto[0]	auto[1]	98277	1			T25	3		T29	3		T30	2
all_values[6]	auto[1]	auto[1]	auto[1]	97850	1			T25	6		T27	3		T29	2
all_values[7]	auto[0]	auto[0]	auto[0]	3025283	1			T25	5		T26	12		T27	5
all_values[7]	auto[0]	auto[0]	auto[1]	6911758	1			T25	1		T27	1		T28	2
all_values[7]	auto[0]	auto[1]	auto[0]	707072	1			T25	15		T27	1		T28	1
all_values[7]	auto[0]	auto[1]	auto[1]	6928836	1			T25	5		T27	4		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	98760	1			T28	2		T29	5		T30	1
all_values[7]	auto[1]	auto[1]	auto[1]	97473	1			T25	4		T27	1		T28	1
all_values[8]	auto[0]	auto[0]	auto[0]	3025995	1			T25	9		T26	2		T27	4
all_values[8]	auto[0]	auto[0]	auto[1]	6913956	1			T26	4		T27	1		T28	4
all_values[8]	auto[0]	auto[1]	auto[0]	707778	1			T25	21		T27	2		T29	5
all_values[8]	auto[0]	auto[1]	auto[1]	6925619	1			T26	6		T27	2		T28	2
all_values[8]	auto[1]	auto[0]	auto[1]	98128	1			T27	2		T28	1		T29	5
all_values[8]	auto[1]	auto[1]	auto[1]	97706	1			T27	1		T28	1		T29	1
all_values[9]	auto[0]	auto[0]	auto[0]	3018688	1			T25	14		T26	2		T27	12
all_values[9]	auto[0]	auto[0]	auto[1]	6895191	1			T25	8		T26	4		T28	2
all_values[9]	auto[0]	auto[1]	auto[0]	706733	1			T25	1		T28	3		T29	6
all_values[9]	auto[0]	auto[1]	auto[1]	6952942	1			T25	1		T26	6		T28	3
all_values[9]	auto[1]	auto[0]	auto[1]	97716	1			T25	5		T29	1		T30	1
all_values[9]	auto[1]	auto[1]	auto[1]	97912	1			T25	1		T28	2		T29	4
all_values[10]	auto[0]	auto[0]	auto[0]	3027115	1			T25	8		T26	2		T27	4
all_values[10]	auto[0]	auto[0]	auto[1]	6861983	1			T25	5		T26	4		T27	4
all_values[10]	auto[0]	auto[1]	auto[0]	715476	1			T25	11		T26	1		T28	3
all_values[10]	auto[0]	auto[1]	auto[1]	6968500	1			T25	3		T26	5		T27	1
all_values[10]	auto[1]	auto[0]	auto[1]	98063	1			T25	2		T27	3		T29	4
all_values[10]	auto[1]	auto[1]	auto[1]	98045	1			T25	1		T29	1		T32	2
all_values[11]	auto[0]	auto[0]	auto[0]	3021480	1			T25	3		T26	2		T27	1
all_values[11]	auto[0]	auto[0]	auto[1]	6929805	1			T25	6		T26	4		T29	10
all_values[11]	auto[0]	auto[1]	auto[0]	713247	1			T25	7		T26	6		T27	3
all_values[11]	auto[0]	auto[1]	auto[1]	6908971	1			T25	7		T27	5		T28	4
all_values[11]	auto[1]	auto[0]	auto[1]	97800	1			T25	3		T29	4		T30	1
all_values[11]	auto[1]	auto[1]	auto[1]	97879	1			T25	4		T27	3		T28	2
all_values[12]	auto[0]	auto[0]	auto[0]	3027136	1			T25	5		T26	8		T27	6
all_values[12]	auto[0]	auto[0]	auto[1]	6881606	1			T25	6		T26	4		T28	1
all_values[12]	auto[0]	auto[1]	auto[0]	719376	1			T25	5		T27	6		T28	5
all_values[12]	auto[0]	auto[1]	auto[1]	6944714	1			T25	7		T28	1		T29	12
all_values[12]	auto[1]	auto[0]	auto[1]	97971	1			T25	5		T28	2		T29	1
all_values[12]	auto[1]	auto[1]	auto[1]	98379	1			T25	2		T29	2		T32	1
all_values[13]	auto[0]	auto[0]	auto[0]	3024528	1			T25	10		T26	8		T27	1
all_values[13]	auto[0]	auto[0]	auto[1]	6898946	1			T25	4		T26	4		T28	2
all_values[13]	auto[0]	auto[1]	auto[0]	713044	1			T25	7		T27	6		T28	7
all_values[13]	auto[0]	auto[1]	auto[1]	6936690	1			T25	5		T27	3		T29	5
all_values[13]	auto[1]	auto[0]	auto[1]	97823	1			T25	2		T29	1		T32	2
all_values[13]	auto[1]	auto[1]	auto[1]	98151	1			T25	2		T27	2		T28	1
all_values[14]	auto[0]	auto[0]	auto[0]	3022433	1			T25	11		T26	4		T27	1
all_values[14]	auto[0]	auto[0]	auto[1]	6943582	1			T25	5		T26	2		T27	1
all_values[14]	auto[0]	auto[1]	auto[0]	711657	1			T25	4		T26	6		T27	2
all_values[14]	auto[0]	auto[1]	auto[1]	6895352	1			T25	7		T27	5		T28	5
all_values[14]	auto[1]	auto[0]	auto[1]	98263	1			T25	1		T29	4		T30	1
all_values[14]	auto[1]	auto[1]	auto[1]	97895	1			T25	2		T27	3		T28	1
all_values[15]	auto[0]	auto[0]	auto[0]	3015176	1			T25	6		T26	3		T27	5
all_values[15]	auto[0]	auto[0]	auto[1]	6928525	1			T25	4		T26	3		T27	1
all_values[15]	auto[0]	auto[1]	auto[0]	700792	1			T25	9		T26	6		T27	3
all_values[15]	auto[0]	auto[1]	auto[1]	6928551	1			T25	7		T27	1		T28	1
all_values[15]	auto[1]	auto[0]	auto[1]	98233	1			T25	1		T28	1		T29	3
all_values[15]	auto[1]	auto[1]	auto[1]	97905	1			T25	3		T27	2		T29	3
all_values[16]	auto[0]	auto[0]	auto[0]	3022041	1			T25	7		T26	2		T27	2
all_values[16]	auto[0]	auto[0]	auto[1]	6930998	1			T25	10		T26	4		T27	4
all_values[16]	auto[0]	auto[1]	auto[0]	706185	1			T25	3		T27	4		T28	3
all_values[16]	auto[0]	auto[1]	auto[1]	6913182	1			T25	3		T26	6		T27	1
all_values[16]	auto[1]	auto[0]	auto[1]	98378	1			T25	4		T28	1		T30	1
all_values[16]	auto[1]	auto[1]	auto[1]	98398	1			T25	3		T27	1		T28	1
all_values[17]	auto[0]	auto[0]	auto[0]	3032609	1			T25	17		T26	2		T27	5
all_values[17]	auto[0]	auto[0]	auto[1]	6884606	1			T25	1		T26	4		T27	1
all_values[17]	auto[0]	auto[1]	auto[0]	706080	1			T25	8		T26	6		T27	5
all_values[17]	auto[0]	auto[1]	auto[1]	6950175	1			T28	2		T29	6		T30	1
all_values[17]	auto[1]	auto[0]	auto[1]	98156	1			T25	3		T27	1		T28	1
all_values[17]	auto[1]	auto[1]	auto[1]	97556	1			T25	1		T28	1		T29	3
all_values[18]	auto[0]	auto[0]	auto[0]	3029694	1			T25	9		T26	10		T27	1
all_values[18]	auto[0]	auto[0]	auto[1]	6920094	1			T26	2		T28	3		T29	10
all_values[18]	auto[0]	auto[1]	auto[0]	709175	1			T25	9		T27	7		T28	3
all_values[18]	auto[0]	auto[1]	auto[1]	6914467	1			T25	5		T27	2		T28	3
all_values[18]	auto[1]	auto[0]	auto[1]	98716	1			T25	2		T29	3		T30	1
all_values[18]	auto[1]	auto[1]	auto[1]	97036	1			T25	5		T27	2		T28	2
all_values[19]	auto[0]	auto[0]	auto[0]	3016659	1			T25	10		T26	6		T27	2
all_values[19]	auto[0]	auto[0]	auto[1]	6965413	1			T25	5		T26	6		T29	7
all_values[19]	auto[0]	auto[1]	auto[0]	711759	1			T25	7		T27	9		T28	6
all_values[19]	auto[0]	auto[1]	auto[1]	6879266	1			T25	2		T29	4		T30	5
all_values[19]	auto[1]	auto[0]	auto[1]	98078	1			T25	3		T29	3		T30	2
all_values[19]	auto[1]	auto[1]	auto[1]	98007	1			T25	3		T27	1		T29	1
all_values[20]	auto[0]	auto[0]	auto[0]	3019147	1			T25	2		T26	8		T27	5
all_values[20]	auto[0]	auto[0]	auto[1]	6894331	1			T25	3		T26	4		T27	1
all_values[20]	auto[0]	auto[1]	auto[0]	721808	1			T25	6		T27	5		T28	3
all_values[20]	auto[0]	auto[1]	auto[1]	6938038	1			T25	13		T28	3		T34	1
all_values[20]	auto[1]	auto[0]	auto[1]	98338	1			T25	2		T27	1		T32	1
all_values[20]	auto[1]	auto[1]	auto[1]	97520	1			T25	4		T28	2		T29	2
all_values[21]	auto[0]	auto[0]	auto[0]	3023743	1			T25	6		T26	2		T27	2
all_values[21]	auto[0]	auto[0]	auto[1]	6948807	1			T25	4		T26	10		T28	2
all_values[21]	auto[0]	auto[1]	auto[0]	717034	1			T25	13		T27	8		T28	4
all_values[21]	auto[0]	auto[1]	auto[1]	6883483	1			T25	4		T27	1		T29	2
all_values[21]	auto[1]	auto[0]	auto[1]	98534	1			T25	2		T28	1		T29	4
all_values[21]	auto[1]	auto[1]	auto[1]	97581	1			T25	1		T27	1		T28	1
all_values[22]	auto[0]	auto[0]	auto[0]	3025014	1			T25	4		T26	2		T27	3
all_values[22]	auto[0]	auto[0]	auto[1]	6915578	1			T25	7		T26	4		T27	5
all_values[22]	auto[0]	auto[1]	auto[0]	711487	1			T25	8		T28	3		T29	8
all_values[22]	auto[0]	auto[1]	auto[1]	6921161	1			T25	4		T26	6		T27	1
all_values[22]	auto[1]	auto[0]	auto[1]	98330	1			T25	4		T27	3		T29	4
all_values[22]	auto[1]	auto[1]	auto[1]	97612	1			T25	3		T29	1		T30	1
all_values[23]	auto[0]	auto[0]	auto[0]	3028126	1			T25	6		T26	2		T27	7
all_values[23]	auto[0]	auto[0]	auto[1]	6942096	1			T25	2		T26	4		T29	5
all_values[23]	auto[0]	auto[1]	auto[0]	711186	1			T25	12		T26	6		T27	5
all_values[23]	auto[0]	auto[1]	auto[1]	6891398	1			T25	5		T28	3		T29	1
all_values[23]	auto[1]	auto[0]	auto[1]	98151	1			T25	1		T29	3		T30	3
all_values[23]	auto[1]	auto[1]	auto[1]	98225	1			T25	4		T28	2		T29	1
all_values[24]	auto[0]	auto[0]	auto[0]	3022009	1			T25	11		T26	3		T27	1
all_values[24]	auto[0]	auto[0]	auto[1]	6954088	1			T26	3		T27	1		T29	9
all_values[24]	auto[0]	auto[1]	auto[0]	704309	1			T25	9		T26	1		T27	5
all_values[24]	auto[0]	auto[1]	auto[1]	6892780	1			T25	5		T26	5		T27	3
all_values[24]	auto[1]	auto[0]	auto[1]	98289	1			T25	1		T29	5		T30	3
all_values[24]	auto[1]	auto[1]	auto[1]	97707	1			T25	4		T27	2		T28	2
all_values[25]	auto[0]	auto[0]	auto[0]	3026167	1			T25	6		T26	2		T27	5
all_values[25]	auto[0]	auto[0]	auto[1]	6889654	1			T25	3		T26	10		T27	1
all_values[25]	auto[0]	auto[1]	auto[0]	710097	1			T25	5		T27	4		T28	4
all_values[25]	auto[0]	auto[1]	auto[1]	6947007	1			T25	11		T27	1		T29	5
all_values[25]	auto[1]	auto[0]	auto[1]	97973	1			T25	3		T29	3		T30	2
all_values[25]	auto[1]	auto[1]	auto[1]	98284	1			T25	2		T27	1		T28	1
all_values[26]	auto[0]	auto[0]	auto[0]	3018217	1			T25	8		T26	8		T27	5
all_values[26]	auto[0]	auto[0]	auto[1]	6935868	1			T25	8		T26	4		T27	2
all_values[26]	auto[0]	auto[1]	auto[0]	707233	1			T25	4		T27	4		T28	5
all_values[26]	auto[0]	auto[1]	auto[1]	6911962	1			T25	5		T28	1		T29	4
all_values[26]	auto[1]	auto[0]	auto[1]	98256	1			T25	5		T29	1		T32	1
all_values[26]	auto[1]	auto[1]	auto[1]	97646	1			T27	1		T28	2		T29	3
all_values[27]	auto[0]	auto[0]	auto[0]	3034138	1			T25	7		T26	6		T27	11
all_values[27]	auto[0]	auto[0]	auto[1]	6922974	1			T25	1		T26	6		T28	4
all_values[27]	auto[0]	auto[1]	auto[0]	703232	1			T25	11		T28	1		T29	9
all_values[27]	auto[0]	auto[1]	auto[1]	6912965	1			T25	6		T28	2		T29	2
all_values[27]	auto[1]	auto[0]	auto[1]	98271	1			T25	3		T27	1		T28	2
all_values[27]	auto[1]	auto[1]	auto[1]	97602	1			T25	2		T29	1		T32	1
all_values[28]	auto[0]	auto[0]	auto[0]	3029134	1			T25	6		T26	8		T27	2
all_values[28]	auto[0]	auto[0]	auto[1]	6929670	1			T25	3		T26	4		T29	2
all_values[28]	auto[0]	auto[1]	auto[0]	706156	1			T25	13		T27	10		T28	5
all_values[28]	auto[0]	auto[1]	auto[1]	6908213	1			T25	3		T28	5		T29	8
all_values[28]	auto[1]	auto[0]	auto[1]	98004	1			T25	1		T29	3		T30	2
all_values[28]	auto[1]	auto[1]	auto[1]	98005	1			T25	4		T28	1		T29	1
all_values[29]	auto[0]	auto[0]	auto[0]	3028480	1			T25	16		T26	2		T27	1
all_values[29]	auto[0]	auto[0]	auto[1]	6921362	1			T25	1		T26	4		T27	1
all_values[29]	auto[0]	auto[1]	auto[0]	708726	1			T25	6		T27	6		T28	5
all_values[29]	auto[0]	auto[1]	auto[1]	6915072	1			T25	5		T26	6		T27	2
all_values[29]	auto[1]	auto[0]	auto[1]	98096	1			T25	1		T29	3		T30	2
all_values[29]	auto[1]	auto[1]	auto[1]	97446	1			T25	1		T27	2		T28	1
all_values[30]	auto[0]	auto[0]	auto[0]	3021374	1			T25	13		T26	6		T27	3
all_values[30]	auto[0]	auto[0]	auto[1]	6979919	1			T25	2		T27	2		T28	4
all_values[30]	auto[0]	auto[1]	auto[0]	707613	1			T25	13		T27	4		T29	8
all_values[30]	auto[0]	auto[1]	auto[1]	6864304	1			T26	6		T27	1		T28	3
all_values[30]	auto[1]	auto[0]	auto[1]	98214	1			T27	2		T28	1		T30	2
all_values[30]	auto[1]	auto[1]	auto[1]	97758	1			T25	2		T29	2		T32	3
all_values[31]	auto[0]	auto[0]	auto[0]	3023453	1			T25	8		T26	12		T27	6
all_values[31]	auto[0]	auto[0]	auto[1]	6932477	1			T25	4		T29	5		T31	1
all_values[31]	auto[0]	auto[1]	auto[0]	715858	1			T25	9		T27	4		T28	3
all_values[31]	auto[0]	auto[1]	auto[1]	6900768	1			T25	6		T27	1		T28	2
all_values[31]	auto[1]	auto[0]	auto[1]	98253	1			T29	3		T30	1		T83	1
all_values[31]	auto[1]	auto[1]	auto[1]	98373	1			T25	3		T27	1		T28	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal