Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[1]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[2]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[3]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[4]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[5]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[6]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[7]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[8]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[9]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[10]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[11]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[12]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[13]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[14]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[15]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[16]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[17]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[18]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[19]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[20]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[21]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[22]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[23]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[24]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[25]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[26]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[27]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[28]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[29]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[30]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[31]	17544303	1			T25	1		T26	12		T27	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343815505

1

T25

32

T26

384

T27

32

auto[1]

217602191

1

T51

6784

T52

4274

T53

2372

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

450447762

1

T25

32

T26

384

T27

32

auto[1]

110969934

1

T51

7564

T52

3188

T53

2236

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417123038

1

T25

32

T26

384

T27

32

auto[1]

144294658

1

T51

7333

T52

3257

T53

2342

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6629908	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4650837	1			T51	102		T52	83		T53	38
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1748554	1			T51	154		T52	53		T53	22
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2355354	1			T51	94		T52	56		T53	30
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	426020	1			T61	113		T62	186		T63	106
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1733630	1			T51	106		T52	48		T53	46
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6648882	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4642379	1			T51	90		T52	84		T53	35
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1740748	1			T51	124		T52	59		T53	31
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2354307	1			T51	106		T52	34		T53	26
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	425420	1			T61	126		T62	176		T63	98
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1732567	1			T51	133		T52	54		T53	46
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6635526	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4651554	1			T51	89		T52	93		T53	39
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1742803	1			T51	120		T52	49		T53	36
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2359520	1			T51	112		T52	52		T53	43
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	424902	1			T61	108		T62	126		T63	100
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1729998	1			T51	124		T52	52		T53	36
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6645072	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4648288	1			T51	88		T52	89		T53	41
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1747749	1			T51	134		T52	60		T53	39
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2351415	1			T51	124		T52	42		T53	34
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	424652	1			T61	108		T62	154		T63	133
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1727127	1			T51	111		T52	57		T53	34
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6647700	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4650509	1			T51	100		T52	93		T53	34
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1743056	1			T51	130		T52	43		T53	51
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2355018	1			T51	100		T52	66		T53	30
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	424874	1			T61	99		T62	172		T63	108
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1723146	1			T51	111		T52	38		T53	30
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6639539	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4652375	1			T51	100		T52	79		T53	43
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1743917	1			T51	108		T52	43		T53	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2358117	1			T51	98		T52	58		T53	58
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	425612	1			T61	113		T62	190		T63	118
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1724743	1			T51	113		T52	46		T53	37
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6647696	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4640037	1			T51	96		T52	85		T53	44
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1749431	1			T51	88		T52	52		T53	44
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2348133	1			T51	124		T52	47		T53	31
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	422924	1			T61	118		T62	176		T63	118
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1736082	1			T51	112		T52	48		T53	24
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6639828	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4653946	1			T51	94		T52	86		T53	34
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1743962	1			T51	116		T52	46		T53	40
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2350606	1			T51	120		T52	66		T53	28
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	423772	1			T61	122		T62	178		T63	111
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1732189	1			T51	104		T52	34		T53	36
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6651210	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4640500	1			T51	92		T52	88		T53	39
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1749758	1			T51	104		T52	48		T53	52
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2348437	1			T51	131		T52	59		T53	22
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	423959	1			T61	114		T62	194		T63	72
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1730439	1			T51	96		T52	56		T53	29
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6636329	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4647098	1			T51	88		T52	80		T53	34
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1744491	1			T51	130		T52	57		T53	33
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2356321	1			T51	105		T52	48		T53	32
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	424973	1			T61	122		T62	174		T63	113
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1735091	1			T51	134		T52	64		T53	36
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6638516	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4648326	1			T51	102		T52	88		T53	36
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1741062	1			T51	122		T52	50		T53	20
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2363765	1			T51	108		T52	58		T53	50
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	426502	1			T61	102		T62	144		T63	90
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1726132	1			T51	107		T52	46		T53	37
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6639767	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4653925	1			T51	81		T52	75		T53	39
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1741852	1			T51	107		T52	54		T53	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2353809	1			T51	118		T52	56		T53	39
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	424626	1			T61	119		T62	157		T63	100
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1730324	1			T51	118		T52	31		T53	48
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6649673	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4638598	1			T51	87		T52	83		T53	33
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1741551	1			T51	146		T52	49		T53	24
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2358739	1			T51	104		T52	56		T53	42
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	424512	1			T61	172		T62	218		T63	115
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1731230	1			T51	123		T52	56		T53	41
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6640914	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4642890	1			T51	101		T52	80		T53	42
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1752135	1			T51	89		T52	38		T53	30
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2354522	1			T51	116		T52	61		T53	37
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	424281	1			T61	124		T62	183		T63	114
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1729561	1			T51	124		T52	50		T53	38
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6643715	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4648226	1			T51	83		T52	82		T53	31
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1743003	1			T51	118		T52	71		T53	26
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2352522	1			T51	96		T52	42		T53	30
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	425325	1			T61	114		T62	200		T63	93
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1731512	1			T51	151		T52	46		T53	38
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6637399	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4649136	1			T51	80		T52	83		T53	32
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1743490	1			T51	119		T52	53		T53	33
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2356650	1			T51	114		T52	56		T53	32
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	425190	1			T61	116		T62	177		T63	118
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1732438	1			T51	102		T52	48		T53	28
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6653859	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4652474	1			T51	104		T52	82		T53	36
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1735336	1			T51	114		T52	57		T53	34
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2360940	1			T51	113		T52	44		T53	28
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	423065	1			T61	110		T62	154		T63	95
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1718629	1			T51	114		T52	68		T53	27
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6649124	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4656584	1			T51	91		T52	86		T53	37
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1738246	1			T51	120		T52	48		T53	41
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2360551	1			T51	116		T52	66		T53	28
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	423596	1			T61	110		T62	176		T63	172
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1716202	1			T51	120		T52	41		T53	40
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6651343	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4652804	1			T51	99		T52	90		T53	40
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1735219	1			T51	152		T52	54		T53	41
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2356705	1			T51	79		T52	66		T53	36
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	423614	1			T61	96		T62	172		T63	104
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1724618	1			T51	156		T52	38		T53	32
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6657882	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4638676	1			T51	97		T52	87		T53	41
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1741451	1			T51	133		T52	42		T53	26
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2356183	1			T51	100		T52	60		T53	33
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	426621	1			T61	122		T62	180		T63	111
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1723490	1			T51	92		T52	43		T53	46
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6648592	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4649402	1			T51	94		T52	79		T53	39
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1740196	1			T51	102		T52	58		T53	32
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2362155	1			T51	118		T52	42		T53	39
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	421597	1			T61	134		T62	162		T63	134
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1722361	1			T51	114		T52	34		T53	28
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6654771	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4647809	1			T51	107		T52	93		T53	28
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1738035	1			T51	112		T52	57		T53	36
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2359444	1			T51	127		T52	56		T53	32
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	423420	1			T61	135		T62	164		T63	106
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1720824	1			T51	108		T52	32		T53	40
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6643037	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4648412	1			T51	88		T52	86		T53	38
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1739433	1			T51	113		T52	52		T53	16
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2362262	1			T51	112		T52	42		T53	43
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	424452	1			T61	108		T62	196		T63	84
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1726707	1			T51	104		T52	49		T53	56
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6634580	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4657892	1			T51	103		T52	80		T53	39
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1733257	1			T51	140		T52	62		T53	36
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2364586	1			T51	106		T52	38		T53	38
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	425654	1			T61	116		T62	167		T63	114
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1728334	1			T51	121		T52	58		T53	29
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6642694	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4662187	1			T51	94		T52	81		T53	34
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1738192	1			T51	83		T52	38		T53	30
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2355388	1			T51	142		T52	57		T53	33
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	424918	1			T61	114		T62	198		T63	126
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1720924	1			T51	110		T52	54		T53	50
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6641151	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4653673	1			T51	97		T52	93		T53	36
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1735062	1			T51	114		T52	30		T53	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2363538	1			T51	110		T52	60		T53	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	426718	1			T61	111		T62	211		T63	103
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1724161	1			T51	142		T52	79		T53	38
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6662776	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4638295	1			T51	101		T52	90		T53	32
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1742259	1			T51	141		T52	51		T53	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2356248	1			T51	104		T52	70		T53	53
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	426532	1			T61	122		T62	172		T63	116
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1718193	1			T51	88		T52	30		T53	38
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6655190	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4642535	1			T51	101		T52	101		T53	32
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1738137	1			T51	94		T52	52		T53	20
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2360991	1			T51	129		T52	52		T53	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	425669	1			T61	125		T62	188		T63	109
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1721781	1			T51	122		T52	48		T53	41
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6657312	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4644838	1			T51	92		T52	87		T53	39
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1736985	1			T51	112		T52	58		T53	48
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2359065	1			T51	120		T52	58		T53	36
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	423605	1			T61	144		T62	158		T63	103
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1722498	1			T51	116		T52	46		T53	32
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6648241	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4641989	1			T51	87		T52	91		T53	40
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1741882	1			T51	142		T52	46		T53	34
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2361754	1			T51	102		T52	58		T53	37
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	426830	1			T61	121		T62	196		T63	110
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1723607	1			T51	110		T52	46		T53	38
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6641976	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4648085	1			T51	101		T52	72		T53	39
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1731553	1			T51	118		T52	59		T53	51
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2369074	1			T51	110		T52	42		T53	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	425218	1			T61	96		T62	162		T63	98
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1728397	1			T51	138		T52	50		T53	34
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6634815	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4662884	1			T51	96		T52	82		T53	36
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1734053	1			T51	106		T52	56		T53	22
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2363511	1			T51	116		T52	46		T53	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	422899	1			T61	139		T62	134		T63	90
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1726141	1			T51	135		T52	53		T53	39

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal