Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[1]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[2]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[3]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[4]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[5]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[6]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[7]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[8]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[9]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[10]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[11]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[12]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[13]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[14]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[15]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[16]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[17]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[18]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[19]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[20]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[21]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[22]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[23]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[24]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[25]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[26]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[27]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[28]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[29]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[30]	17544303	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[31]	17544303	1			T25	1		T26	12		T27	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343815505

1

T25

32

T26

384

T27

32

auto[1]

217602191

1

T51

6784

T52

4274

T53

2372

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343806741

1

T25

32

T26

291

T27

32

auto[1]

217610955

1

T26

93

T31

18

T33

17

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10424729	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	308829	1			T51	34		T52	15		T53	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	309087	1			T26	4		T31	2		T34	5
bins_for_gpio_bits[0]	auto[1]	auto[1]	6501658	1			T51	174		T52	116		T53	75
bins_for_gpio_bits[1]	auto[0]	auto[0]	10434496	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	309197	1			T51	36		T52	13		T53	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	309441	1			T34	4		T2	1		T16	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	6491169	1			T51	187		T52	125		T53	73
bins_for_gpio_bits[2]	auto[0]	auto[0]	10428214	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	309373	1			T51	31		T52	13		T53	9
bins_for_gpio_bits[2]	auto[1]	auto[0]	309635	1			T26	2		T31	1		T33	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	6497081	1			T51	182		T52	132		T53	66
bins_for_gpio_bits[3]	auto[0]	auto[0]	10435633	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	308300	1			T51	31		T52	13		T53	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	308603	1			T26	4		T33	1		T34	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	6491767	1			T51	168		T52	133		T53	65
bins_for_gpio_bits[4]	auto[0]	auto[0]	10437658	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	307849	1			T51	31		T52	11		T53	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	308116	1			T26	4		T33	1		T34	7
bins_for_gpio_bits[4]	auto[1]	auto[1]	6490680	1			T51	180		T52	120		T53	55
bins_for_gpio_bits[5]	auto[0]	auto[0]	10433311	1			T25	1		T26	9		T27	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	307992	1			T51	30		T52	12		T53	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	308262	1			T26	3		T34	9		T14	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	6494738	1			T51	183		T52	113		T53	72
bins_for_gpio_bits[6]	auto[0]	auto[0]	10436117	1			T25	1		T26	7		T27	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	308909	1			T51	23		T52	12		T53	7
bins_for_gpio_bits[6]	auto[1]	auto[0]	309143	1			T26	5		T33	1		T34	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	6490134	1			T51	185		T52	121		T53	61
bins_for_gpio_bits[7]	auto[0]	auto[0]	10425328	1			T25	1		T26	6		T27	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	308808	1			T51	24		T52	12		T53	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	309068	1			T26	6		T34	3		T35	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	6501099	1			T51	174		T52	108		T53	61
bins_for_gpio_bits[8]	auto[0]	auto[0]	10440104	1			T25	1		T26	6		T27	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	309030	1			T51	27		T52	17		T53	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	309301	1			T26	6		T31	1		T33	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	6485868	1			T51	161		T52	127		T53	60
bins_for_gpio_bits[9]	auto[0]	auto[0]	10427357	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	309494	1			T51	33		T52	15		T53	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	309784	1			T31	1		T33	1		T34	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	6497668	1			T51	189		T52	129		T53	60
bins_for_gpio_bits[10]	auto[0]	auto[0]	10434914	1			T25	1		T26	9		T27	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	308154	1			T51	30		T52	13		T53	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	308429	1			T26	3		T31	1		T33	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	6492806	1			T51	179		T52	121		T53	63
bins_for_gpio_bits[11]	auto[0]	auto[0]	10426772	1			T25	1		T26	9		T27	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	308346	1			T51	32		T52	11		T53	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	308656	1			T26	3		T33	1		T34	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	6500529	1			T51	167		T52	95		T53	77
bins_for_gpio_bits[12]	auto[0]	auto[0]	10440590	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	309118	1			T51	32		T52	14		T53	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	309373	1			T26	2		T34	8		T35	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	6485222	1			T51	178		T52	125		T53	63
bins_for_gpio_bits[13]	auto[0]	auto[0]	10438182	1			T25	1		T26	11		T27	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	309172	1			T51	27		T52	13		T53	8
bins_for_gpio_bits[13]	auto[1]	auto[0]	309389	1			T26	1		T31	1		T33	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	6487560	1			T51	198		T52	117		T53	72
bins_for_gpio_bits[14]	auto[0]	auto[0]	10429950	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	309037	1			T51	27		T52	14		T53	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	309290	1			T26	4		T34	6		T14	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	6496026	1			T51	207		T52	114		T53	62
bins_for_gpio_bits[15]	auto[0]	auto[0]	10428184	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	309071	1			T51	20		T52	14		T53	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	309355	1			T26	2		T33	1		T34	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	6497693	1			T51	162		T52	117		T53	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	10441577	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	308302	1			T51	30		T52	14		T53	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	308558	1			T26	4		T31	1		T34	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	6485866	1			T51	188		T52	136		T53	55
bins_for_gpio_bits[17]	auto[0]	auto[0]	10439044	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	308569	1			T51	32		T52	7		T53	7
bins_for_gpio_bits[17]	auto[1]	auto[0]	308877	1			T26	2		T31	2		T34	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	6487813	1			T51	179		T52	120		T53	70
bins_for_gpio_bits[18]	auto[0]	auto[0]	10434280	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	308697	1			T51	30		T52	14		T53	9
bins_for_gpio_bits[18]	auto[1]	auto[0]	308987	1			T26	2		T34	1		T35	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	6492339	1			T51	225		T52	114		T53	63
bins_for_gpio_bits[19]	auto[0]	auto[0]	10446573	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	308689	1			T51	32		T52	12		T53	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	308943	1			T31	1		T33	1		T34	5
bins_for_gpio_bits[19]	auto[1]	auto[1]	6480098	1			T51	157		T52	118		T53	77
bins_for_gpio_bits[20]	auto[0]	auto[0]	10440888	1			T25	1		T26	7		T27	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	309730	1			T51	28		T52	10		T53	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	310055	1			T26	5		T31	1		T33	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	6483630	1			T51	180		T52	103		T53	58
bins_for_gpio_bits[21]	auto[0]	auto[0]	10443242	1			T25	1		T26	5		T27	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	308709	1			T51	29		T52	10		T53	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	309008	1			T26	7		T33	1		T34	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	6483344	1			T51	186		T52	115		T53	55
bins_for_gpio_bits[22]	auto[0]	auto[0]	10434778	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	309690	1			T51	29		T52	13		T53	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	309954	1			T31	2		T34	2		T35	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	6489881	1			T51	163		T52	122		T53	83
bins_for_gpio_bits[23]	auto[0]	auto[0]	10423002	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	309131	1			T51	29		T52	13		T53	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	309421	1			T26	2		T34	6		T16	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	6502749	1			T51	195		T52	125		T53	60
bins_for_gpio_bits[24]	auto[0]	auto[0]	10428005	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	307991	1			T51	29		T52	9		T53	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	308269	1			T26	4		T33	1		T34	4
bins_for_gpio_bits[24]	auto[1]	auto[1]	6500038	1			T51	175		T52	126		T53	74
bins_for_gpio_bits[25]	auto[0]	auto[0]	10430792	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	308695	1			T51	30		T52	17		T53	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	308959	1			T31	1		T34	6		T14	5
bins_for_gpio_bits[25]	auto[1]	auto[1]	6495857	1			T51	209		T52	155		T53	65
bins_for_gpio_bits[26]	auto[0]	auto[0]	10452471	1			T25	1		T26	9		T27	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	308538	1			T51	28		T52	10		T53	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	308812	1			T26	3		T33	1		T34	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	6474482	1			T51	161		T52	110		T53	58
bins_for_gpio_bits[27]	auto[0]	auto[0]	10445253	1			T25	1		T26	10		T27	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	308805	1			T51	34		T52	13		T53	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	309065	1			T26	2		T31	1		T34	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	6481180	1			T51	189		T52	136		T53	66
bins_for_gpio_bits[28]	auto[0]	auto[0]	10444394	1			T25	1		T26	9		T27	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	308708	1			T51	29		T52	10		T53	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	308968	1			T26	3		T34	3		T14	3
bins_for_gpio_bits[28]	auto[1]	auto[1]	6482233	1			T51	179		T52	123		T53	63
bins_for_gpio_bits[29]	auto[0]	auto[0]	10442464	1			T25	1		T26	6		T27	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	309129	1			T51	31		T52	13		T53	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	309413	1			T26	6		T33	1		T34	7
bins_for_gpio_bits[29]	auto[1]	auto[1]	6483297	1			T51	166		T52	124		T53	69
bins_for_gpio_bits[30]	auto[0]	auto[0]	10432535	1			T25	1		T26	8		T27	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	309767	1			T51	37		T52	12		T53	10
bins_for_gpio_bits[30]	auto[1]	auto[0]	310068	1			T26	4		T31	1		T33	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	6491933	1			T51	202		T52	110		T53	63
bins_for_gpio_bits[31]	auto[0]	auto[0]	10422955	1			T25	1		T26	12		T27	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	309120	1			T51	25		T52	13		T53	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	309424	1			T31	1		T34	7		T16	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	6502804	1			T51	206		T52	122		T53	67