Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10061859 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7707323 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16765624 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1003558 |
1 |
|
|
T43 |
1670 |
|
T120 |
6 |
|
T121 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10052092 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7717090 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T34 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3367765 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T34 |
4 |
| auto[1] |
auto[0] |
auto[1] |
504955 |
1 |
|
|
T43 |
939 |
|
T120 |
3 |
|
T121 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3345767 |
1 |
|
|
T34 |
2 |
|
T35 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
498603 |
1 |
|
|
T43 |
731 |
|
T120 |
3 |
|
T121 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053631 |
1 |
|
|
T25 |
14 |
|
T26 |
12 |
|
T27 |
1 |
| auto[1] |
7715551 |
1 |
|
|
T25 |
16 |
|
T27 |
11 |
|
T28 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16766193 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1002989 |
1 |
|
|
T16 |
1 |
|
T88 |
2 |
|
T10 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10067583 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7701599 |
1 |
|
|
T31 |
2 |
|
T34 |
5 |
|
T35 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3355410 |
1 |
|
|
T31 |
2 |
|
T34 |
3 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
501716 |
1 |
|
|
T16 |
1 |
|
T88 |
2 |
|
T43 |
962 |
| auto[1] |
auto[1] |
auto[0] |
3343200 |
1 |
|
|
T34 |
2 |
|
T14 |
10 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[1] |
501273 |
1 |
|
|
T10 |
2 |
|
T43 |
946 |
|
T120 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9987161 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
7782021 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764087 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1005095 |
1 |
|
|
T26 |
1 |
|
T14 |
1 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10061235 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7707947 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3327386 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
498541 |
1 |
|
|
T26 |
1 |
|
T14 |
1 |
|
T88 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3375466 |
1 |
|
|
T34 |
1 |
|
T14 |
9 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506554 |
1 |
|
|
T16 |
1 |
|
T43 |
856 |
|
T120 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10049085 |
1 |
|
|
T25 |
12 |
|
T26 |
6 |
|
T27 |
1 |
| auto[1] |
7720097 |
1 |
|
|
T25 |
18 |
|
T26 |
6 |
|
T27 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16769397 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
999785 |
1 |
|
|
T26 |
1 |
|
T14 |
1 |
|
T10 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10086230 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7682952 |
1 |
|
|
T26 |
4 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3348648 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
501886 |
1 |
|
|
T26 |
1 |
|
T43 |
853 |
|
T120 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3334519 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T35 |
1 |
| auto[1] |
auto[1] |
auto[1] |
497899 |
1 |
|
|
T14 |
1 |
|
T10 |
1 |
|
T43 |
968 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10006713 |
1 |
|
|
T25 |
16 |
|
T26 |
12 |
|
T27 |
6 |
| auto[1] |
7762469 |
1 |
|
|
T25 |
14 |
|
T27 |
6 |
|
T28 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16766766 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1002416 |
1 |
|
|
T26 |
1 |
|
T88 |
1 |
|
T10 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10074297 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7694885 |
1 |
|
|
T26 |
4 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3344693 |
1 |
|
|
T26 |
3 |
|
T31 |
2 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
500856 |
1 |
|
|
T26 |
1 |
|
T10 |
2 |
|
T43 |
983 |
| auto[1] |
auto[1] |
auto[0] |
3347776 |
1 |
|
|
T34 |
2 |
|
T14 |
3 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[1] |
501560 |
1 |
|
|
T88 |
1 |
|
T43 |
803 |
|
T120 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021297 |
1 |
|
|
T25 |
16 |
|
T26 |
12 |
|
T27 |
1 |
| auto[1] |
7747885 |
1 |
|
|
T25 |
14 |
|
T27 |
11 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16763955 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1005227 |
1 |
|
|
T14 |
1 |
|
T3 |
1 |
|
T43 |
1697 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050976 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7718206 |
1 |
|
|
T31 |
3 |
|
T33 |
1 |
|
T34 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3354577 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T14 |
2 |
| auto[1] |
auto[0] |
auto[1] |
502265 |
1 |
|
|
T14 |
1 |
|
T43 |
849 |
|
T121 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3358402 |
1 |
|
|
T31 |
2 |
|
T33 |
1 |
|
T34 |
3 |
| auto[1] |
auto[1] |
auto[1] |
502962 |
1 |
|
|
T3 |
1 |
|
T43 |
848 |
|
T120 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10064278 |
1 |
|
|
T25 |
17 |
|
T26 |
6 |
|
T27 |
2 |
| auto[1] |
7704904 |
1 |
|
|
T25 |
13 |
|
T26 |
6 |
|
T27 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16763531 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1005651 |
1 |
|
|
T3 |
1 |
|
T43 |
1864 |
|
T120 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10056338 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7712844 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3364019 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T35 |
2 |
| auto[1] |
auto[0] |
auto[1] |
504976 |
1 |
|
|
T3 |
1 |
|
T43 |
857 |
|
T44 |
32 |
| auto[1] |
auto[1] |
auto[0] |
3343174 |
1 |
|
|
T33 |
1 |
|
T34 |
3 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
500675 |
1 |
|
|
T43 |
1007 |
|
T120 |
5 |
|
T44 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10041934 |
1 |
|
|
T25 |
11 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7727248 |
1 |
|
|
T25 |
19 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16760349 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1008833 |
1 |
|
|
T14 |
1 |
|
T88 |
1 |
|
T119 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10031576 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7737606 |
1 |
|
|
T31 |
2 |
|
T33 |
1 |
|
T34 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3358579 |
1 |
|
|
T31 |
2 |
|
T33 |
1 |
|
T34 |
3 |
| auto[1] |
auto[0] |
auto[1] |
503536 |
1 |
|
|
T14 |
1 |
|
T119 |
1 |
|
T43 |
943 |
| auto[1] |
auto[1] |
auto[0] |
3370194 |
1 |
|
|
T34 |
1 |
|
T13 |
1 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
505297 |
1 |
|
|
T88 |
1 |
|
T43 |
882 |
|
T120 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10051417 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7717765 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16766739 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1002443 |
1 |
|
|
T14 |
1 |
|
T88 |
2 |
|
T43 |
1896 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10066802 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7702380 |
1 |
|
|
T31 |
2 |
|
T34 |
5 |
|
T14 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3354276 |
1 |
|
|
T31 |
2 |
|
T34 |
3 |
|
T14 |
10 |
| auto[1] |
auto[0] |
auto[1] |
502866 |
1 |
|
|
T14 |
1 |
|
T88 |
2 |
|
T43 |
947 |
| auto[1] |
auto[1] |
auto[0] |
3345661 |
1 |
|
|
T34 |
2 |
|
T19 |
1 |
|
T7 |
3 |
| auto[1] |
auto[1] |
auto[1] |
499577 |
1 |
|
|
T43 |
949 |
|
T120 |
3 |
|
T121 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10015371 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
7 |
| auto[1] |
7753811 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16759663 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1009519 |
1 |
|
|
T10 |
2 |
|
T43 |
1878 |
|
T120 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10036225 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7732957 |
1 |
|
|
T31 |
2 |
|
T33 |
2 |
|
T34 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3348173 |
1 |
|
|
T31 |
2 |
|
T33 |
2 |
|
T34 |
1 |
| auto[1] |
auto[0] |
auto[1] |
501981 |
1 |
|
|
T43 |
899 |
|
T120 |
7 |
|
T44 |
32 |
| auto[1] |
auto[1] |
auto[0] |
3375265 |
1 |
|
|
T34 |
3 |
|
T14 |
2 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[1] |
507538 |
1 |
|
|
T10 |
2 |
|
T43 |
979 |
|
T120 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048504 |
1 |
|
|
T25 |
11 |
|
T26 |
12 |
|
T27 |
1 |
| auto[1] |
7720678 |
1 |
|
|
T25 |
19 |
|
T27 |
11 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764248 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1004934 |
1 |
|
|
T14 |
1 |
|
T88 |
2 |
|
T43 |
1817 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048265 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7720917 |
1 |
|
|
T31 |
2 |
|
T33 |
1 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3360190 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
501272 |
1 |
|
|
T43 |
860 |
|
T120 |
1 |
|
T121 |
8 |
| auto[1] |
auto[1] |
auto[0] |
3355793 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
6 |
| auto[1] |
auto[1] |
auto[1] |
503662 |
1 |
|
|
T14 |
1 |
|
T88 |
2 |
|
T43 |
957 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10080150 |
1 |
|
|
T25 |
18 |
|
T26 |
12 |
|
T27 |
2 |
| auto[1] |
7689032 |
1 |
|
|
T25 |
12 |
|
T27 |
10 |
|
T28 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16755358 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1013824 |
1 |
|
|
T16 |
1 |
|
T43 |
1891 |
|
T120 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9995206 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7773976 |
1 |
|
|
T31 |
2 |
|
T33 |
2 |
|
T34 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3402887 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
4 |
| auto[1] |
auto[0] |
auto[1] |
511283 |
1 |
|
|
T16 |
1 |
|
T43 |
955 |
|
T120 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3357265 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[1] |
502541 |
1 |
|
|
T43 |
936 |
|
T120 |
2 |
|
T121 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10033206 |
1 |
|
|
T25 |
17 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7735976 |
1 |
|
|
T25 |
13 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16765205 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1003977 |
1 |
|
|
T14 |
1 |
|
T88 |
1 |
|
T43 |
1860 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10055430 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7713752 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3358313 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
2 |
| auto[1] |
auto[0] |
auto[1] |
502368 |
1 |
|
|
T14 |
1 |
|
T88 |
1 |
|
T43 |
923 |
| auto[1] |
auto[1] |
auto[0] |
3351462 |
1 |
|
|
T34 |
1 |
|
T13 |
1 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
501609 |
1 |
|
|
T43 |
937 |
|
T120 |
6 |
|
T121 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011816 |
1 |
|
|
T25 |
7 |
|
T26 |
12 |
|
T27 |
7 |
| auto[1] |
7757366 |
1 |
|
|
T25 |
23 |
|
T27 |
5 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764824 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1004358 |
1 |
|
|
T26 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10058368 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7710814 |
1 |
|
|
T26 |
4 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3352683 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T34 |
5 |
| auto[1] |
auto[0] |
auto[1] |
502007 |
1 |
|
|
T26 |
1 |
|
T7 |
1 |
|
T10 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3353773 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[1] |
502351 |
1 |
|
|
T3 |
1 |
|
T43 |
981 |
|
T120 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10071084 |
1 |
|
|
T25 |
12 |
|
T26 |
12 |
|
T27 |
2 |
| auto[1] |
7698098 |
1 |
|
|
T25 |
18 |
|
T27 |
10 |
|
T28 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761493 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1007689 |
1 |
|
|
T14 |
4 |
|
T16 |
1 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10039608 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7729574 |
1 |
|
|
T31 |
3 |
|
T34 |
6 |
|
T35 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3383324 |
1 |
|
|
T31 |
2 |
|
T34 |
3 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
506607 |
1 |
|
|
T16 |
1 |
|
T43 |
875 |
|
T121 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3338561 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T14 |
5 |
| auto[1] |
auto[1] |
auto[1] |
501082 |
1 |
|
|
T14 |
4 |
|
T3 |
1 |
|
T43 |
980 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038922 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
7730260 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16760762 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1008420 |
1 |
|
|
T14 |
1 |
|
T16 |
1 |
|
T88 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10032005 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7737177 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3366588 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
503629 |
1 |
|
|
T14 |
1 |
|
T88 |
1 |
|
T43 |
908 |
| auto[1] |
auto[1] |
auto[0] |
3362169 |
1 |
|
|
T34 |
2 |
|
T14 |
9 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[1] |
504791 |
1 |
|
|
T16 |
1 |
|
T43 |
955 |
|
T120 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10068373 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
7 |
| auto[1] |
7700809 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762447 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
1006735 |
1 |
|
|
T26 |
2 |
|
T88 |
4 |
|
T43 |
1873 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10040361 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7728821 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T34 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3372659 |
1 |
|
|
T26 |
2 |
|
T33 |
1 |
|
T34 |
4 |
| auto[1] |
auto[0] |
auto[1] |
505895 |
1 |
|
|
T26 |
2 |
|
T88 |
2 |
|
T43 |
1008 |
| auto[1] |
auto[1] |
auto[0] |
3349427 |
1 |
|
|
T34 |
2 |
|
T13 |
1 |
|
T14 |
2 |
| auto[1] |
auto[1] |
auto[1] |
500840 |
1 |
|
|
T88 |
2 |
|
T43 |
865 |
|
T120 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10074386 |
1 |
|
|
T25 |
12 |
|
T26 |
6 |
|
T27 |
2 |
| auto[1] |
7694796 |
1 |
|
|
T25 |
18 |
|
T26 |
6 |
|
T27 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762920 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1006262 |
1 |
|
|
T14 |
3 |
|
T88 |
1 |
|
T43 |
1751 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038917 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7730265 |
1 |
|
|
T31 |
1 |
|
T33 |
2 |
|
T34 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3384382 |
1 |
|
|
T33 |
1 |
|
T34 |
4 |
|
T14 |
4 |
| auto[1] |
auto[0] |
auto[1] |
507194 |
1 |
|
|
T43 |
877 |
|
T120 |
6 |
|
T121 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3339621 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[1] |
499068 |
1 |
|
|
T14 |
3 |
|
T88 |
1 |
|
T43 |
874 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10013794 |
1 |
|
|
T25 |
12 |
|
T26 |
12 |
|
T27 |
6 |
| auto[1] |
7755388 |
1 |
|
|
T25 |
18 |
|
T27 |
6 |
|
T28 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16768396 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1000786 |
1 |
|
|
T14 |
3 |
|
T88 |
1 |
|
T43 |
1811 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10075138 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7694044 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3343335 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
500200 |
1 |
|
|
T14 |
3 |
|
T88 |
1 |
|
T43 |
829 |
| auto[1] |
auto[1] |
auto[0] |
3349923 |
1 |
|
|
T34 |
2 |
|
T14 |
3 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
500586 |
1 |
|
|
T43 |
982 |
|
T120 |
2 |
|
T121 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10052341 |
1 |
|
|
T25 |
21 |
|
T26 |
12 |
|
T27 |
7 |
| auto[1] |
7716841 |
1 |
|
|
T25 |
9 |
|
T27 |
5 |
|
T28 |
8 |