Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764004 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1005178 |
1 |
|
|
T26 |
1 |
|
T14 |
3 |
|
T119 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10055133 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7714049 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T34 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3363151 |
1 |
|
|
T26 |
3 |
|
T34 |
2 |
|
T14 |
2 |
| auto[1] |
auto[0] |
auto[1] |
502562 |
1 |
|
|
T26 |
1 |
|
T119 |
1 |
|
T43 |
965 |
| auto[1] |
auto[1] |
auto[0] |
3345720 |
1 |
|
|
T33 |
1 |
|
T34 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
502616 |
1 |
|
|
T14 |
3 |
|
T43 |
814 |
|
T120 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |