Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038922 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
7730260 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14673746 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
3095436 |
1 |
|
|
T31 |
2 |
|
T14 |
3 |
|
T17 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10039862 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7729320 |
1 |
|
|
T26 |
4 |
|
T31 |
3 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2314587 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T34 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1545741 |
1 |
|
|
T31 |
2 |
|
T14 |
2 |
|
T88 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2319297 |
1 |
|
|
T33 |
1 |
|
T35 |
1 |
|
T14 |
9 |
| auto[1] |
auto[1] |
auto[1] |
1549695 |
1 |
|
|
T14 |
1 |
|
T17 |
5 |
|
T46 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |