Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10054183 |
1 |
|
|
T25 |
12 |
|
T26 |
12 |
|
T27 |
6 |
| auto[1] |
7714999 |
1 |
|
|
T25 |
18 |
|
T27 |
6 |
|
T28 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757285 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1011897 |
1 |
|
|
T16 |
1 |
|
T88 |
1 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10015298 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7753884 |
1 |
|
|
T26 |
4 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3359208 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
503530 |
1 |
|
|
T88 |
1 |
|
T7 |
1 |
|
T43 |
930 |
| auto[1] |
auto[1] |
auto[0] |
3382779 |
1 |
|
|
T31 |
1 |
|
T34 |
6 |
|
T14 |
1 |
| auto[1] |
auto[1] |
auto[1] |
508367 |
1 |
|
|
T16 |
1 |
|
T43 |
808 |
|
T120 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |