Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011595 |
1 |
|
|
T25 |
27 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7757587 |
1 |
|
|
T25 |
3 |
|
T26 |
6 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13158602 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
4610580 |
1 |
|
|
T26 |
10 |
|
T33 |
1 |
|
T34 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10061513 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7707669 |
1 |
|
|
T26 |
10 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1551228 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T6 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2299229 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1545861 |
1 |
|
|
T34 |
1 |
|
T16 |
2 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2311351 |
1 |
|
|
T26 |
6 |
|
T34 |
3 |
|
T14 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10061859 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7707323 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761291 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1007891 |
1 |
|
|
T34 |
1 |
|
T88 |
4 |
|
T5 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038332 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7730850 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3368617 |
1 |
|
|
T33 |
1 |
|
T34 |
4 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
505840 |
1 |
|
|
T34 |
1 |
|
T88 |
1 |
|
T5 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3354342 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[1] |
502051 |
1 |
|
|
T88 |
3 |
|
T46 |
1 |
|
T43 |
864 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053631 |
1 |
|
|
T25 |
14 |
|
T26 |
12 |
|
T27 |
1 |
| auto[1] |
7715551 |
1 |
|
|
T25 |
16 |
|
T27 |
11 |
|
T28 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762461 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1006721 |
1 |
|
|
T34 |
1 |
|
T16 |
1 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10044523 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7724659 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3377876 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T34 |
3 |
| auto[1] |
auto[0] |
auto[1] |
505365 |
1 |
|
|
T88 |
3 |
|
T5 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3340062 |
1 |
|
|
T33 |
1 |
|
T34 |
3 |
|
T14 |
1 |
| auto[1] |
auto[1] |
auto[1] |
501356 |
1 |
|
|
T34 |
1 |
|
T16 |
1 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9987161 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
7782021 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16767925 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1001257 |
1 |
|
|
T26 |
1 |
|
T33 |
1 |
|
T24 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10065790 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7703392 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3324905 |
1 |
|
|
T26 |
3 |
|
T34 |
4 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
496856 |
1 |
|
|
T26 |
1 |
|
T24 |
1 |
|
T88 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3377230 |
1 |
|
|
T34 |
3 |
|
T14 |
1 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[1] |
504401 |
1 |
|
|
T33 |
1 |
|
T10 |
2 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10049085 |
1 |
|
|
T25 |
12 |
|
T26 |
6 |
|
T27 |
1 |
| auto[1] |
7720097 |
1 |
|
|
T25 |
18 |
|
T26 |
6 |
|
T27 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761953 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1007229 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T24 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10035874 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7733308 |
1 |
|
|
T26 |
6 |
|
T31 |
1 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3383250 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T14 |
3 |
| auto[1] |
auto[0] |
auto[1] |
507812 |
1 |
|
|
T19 |
1 |
|
T119 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3342829 |
1 |
|
|
T26 |
6 |
|
T34 |
4 |
|
T35 |
1 |
| auto[1] |
auto[1] |
auto[1] |
499417 |
1 |
|
|
T14 |
1 |
|
T24 |
1 |
|
T87 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10006713 |
1 |
|
|
T25 |
16 |
|
T26 |
12 |
|
T27 |
6 |
| auto[1] |
7762469 |
1 |
|
|
T25 |
14 |
|
T27 |
6 |
|
T28 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762730 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1006452 |
1 |
|
|
T34 |
2 |
|
T35 |
1 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10051821 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7717361 |
1 |
|
|
T26 |
6 |
|
T31 |
1 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3333427 |
1 |
|
|
T26 |
6 |
|
T31 |
1 |
|
T34 |
3 |
| auto[1] |
auto[0] |
auto[1] |
499939 |
1 |
|
|
T34 |
1 |
|
T17 |
2 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3377482 |
1 |
|
|
T34 |
2 |
|
T14 |
10 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506513 |
1 |
|
|
T34 |
1 |
|
T35 |
1 |
|
T43 |
888 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10021297 |
1 |
|
|
T25 |
16 |
|
T26 |
12 |
|
T27 |
1 |
| auto[1] |
7747885 |
1 |
|
|
T25 |
14 |
|
T27 |
11 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761926 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1007256 |
1 |
|
|
T26 |
1 |
|
T31 |
1 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10040629 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7728553 |
1 |
|
|
T26 |
10 |
|
T31 |
2 |
|
T34 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3346858 |
1 |
|
|
T26 |
9 |
|
T34 |
4 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
500703 |
1 |
|
|
T26 |
1 |
|
T31 |
1 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3374439 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506553 |
1 |
|
|
T34 |
1 |
|
T6 |
1 |
|
T46 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10064278 |
1 |
|
|
T25 |
17 |
|
T26 |
6 |
|
T27 |
2 |
| auto[1] |
7704904 |
1 |
|
|
T25 |
13 |
|
T26 |
6 |
|
T27 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762453 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1006729 |
1 |
|
|
T34 |
3 |
|
T14 |
1 |
|
T24 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10046564 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7722618 |
1 |
|
|
T31 |
1 |
|
T34 |
8 |
|
T35 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3375957 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
507011 |
1 |
|
|
T34 |
1 |
|
T24 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3339932 |
1 |
|
|
T34 |
2 |
|
T2 |
1 |
|
T14 |
1 |
| auto[1] |
auto[1] |
auto[1] |
499718 |
1 |
|
|
T34 |
2 |
|
T14 |
1 |
|
T7 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10041934 |
1 |
|
|
T25 |
11 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7727248 |
1 |
|
|
T25 |
19 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16754212 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1014970 |
1 |
|
|
T34 |
4 |
|
T35 |
1 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9995658 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7773524 |
1 |
|
|
T31 |
2 |
|
T34 |
5 |
|
T35 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3368885 |
1 |
|
|
T31 |
2 |
|
T34 |
1 |
|
T14 |
9 |
| auto[1] |
auto[0] |
auto[1] |
505429 |
1 |
|
|
T34 |
3 |
|
T35 |
1 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3389669 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
509541 |
1 |
|
|
T34 |
1 |
|
T119 |
1 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10051417 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7717765 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16759545 |
1 |
|
|
T25 |
30 |
|
T26 |
9 |
|
T27 |
12 |
| auto[1] |
1009637 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T34 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10029666 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7739516 |
1 |
|
|
T26 |
10 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3355312 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T34 |
2 |
| auto[1] |
auto[0] |
auto[1] |
503328 |
1 |
|
|
T26 |
1 |
|
T31 |
1 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3374567 |
1 |
|
|
T26 |
4 |
|
T33 |
1 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506309 |
1 |
|
|
T26 |
2 |
|
T34 |
1 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10015371 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
7 |
| auto[1] |
7753811 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16765110 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1004072 |
1 |
|
|
T31 |
2 |
|
T35 |
1 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10057760 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7711422 |
1 |
|
|
T26 |
6 |
|
T31 |
3 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3344156 |
1 |
|
|
T33 |
1 |
|
T34 |
4 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
501112 |
1 |
|
|
T31 |
2 |
|
T35 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3363194 |
1 |
|
|
T26 |
6 |
|
T31 |
1 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[1] |
502960 |
1 |
|
|
T19 |
1 |
|
T4 |
1 |
|
T88 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048504 |
1 |
|
|
T25 |
11 |
|
T26 |
12 |
|
T27 |
1 |
| auto[1] |
7720678 |
1 |
|
|
T25 |
19 |
|
T27 |
11 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16766820 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1002362 |
1 |
|
|
T34 |
1 |
|
T14 |
2 |
|
T4 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10076308 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7692874 |
1 |
|
|
T31 |
3 |
|
T33 |
1 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3341834 |
1 |
|
|
T31 |
2 |
|
T34 |
4 |
|
T19 |
1 |
| auto[1] |
auto[0] |
auto[1] |
499663 |
1 |
|
|
T34 |
1 |
|
T4 |
1 |
|
T88 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3348678 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[1] |
502699 |
1 |
|
|
T14 |
2 |
|
T46 |
2 |
|
T43 |
830 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10080150 |
1 |
|
|
T25 |
18 |
|
T26 |
12 |
|
T27 |
2 |
| auto[1] |
7689032 |
1 |
|
|
T25 |
12 |
|
T27 |
10 |
|
T28 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761391 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1007791 |
1 |
|
|
T33 |
1 |
|
T34 |
2 |
|
T24 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10045388 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7723794 |
1 |
|
|
T31 |
2 |
|
T33 |
1 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3381764 |
1 |
|
|
T31 |
2 |
|
T34 |
1 |
|
T16 |
2 |
| auto[1] |
auto[0] |
auto[1] |
508528 |
1 |
|
|
T34 |
2 |
|
T6 |
2 |
|
T46 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3334239 |
1 |
|
|
T34 |
4 |
|
T2 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
499263 |
1 |
|
|
T33 |
1 |
|
T24 |
1 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10033206 |
1 |
|
|
T25 |
17 |
|
T26 |
6 |
|
T27 |
6 |
| auto[1] |
7735976 |
1 |
|
|
T25 |
13 |
|
T26 |
6 |
|
T27 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762359 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1006823 |
1 |
|
|
T16 |
1 |
|
T24 |
2 |
|
T88 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10060043 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7709139 |
1 |
|
|
T33 |
1 |
|
T34 |
7 |
|
T14 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3339496 |
1 |
|
|
T33 |
1 |
|
T34 |
5 |
|
T14 |
2 |
| auto[1] |
auto[0] |
auto[1] |
500583 |
1 |
|
|
T16 |
1 |
|
T24 |
2 |
|
T5 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3362820 |
1 |
|
|
T34 |
2 |
|
T16 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506240 |
1 |
|
|
T88 |
3 |
|
T43 |
948 |
|
T120 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10011816 |
1 |
|
|
T25 |
7 |
|
T26 |
12 |
|
T27 |
7 |
| auto[1] |
7757366 |
1 |
|
|
T25 |
23 |
|
T27 |
5 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16765539 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1003643 |
1 |
|
|
T16 |
1 |
|
T24 |
1 |
|
T6 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10063055 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7706127 |
1 |
|
|
T31 |
2 |
|
T34 |
4 |
|
T35 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3340255 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
498853 |
1 |
|
|
T16 |
1 |
|
T24 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3362229 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[1] |
504790 |
1 |
|
|
T46 |
1 |
|
T43 |
969 |
|
T120 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |