Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10071084 |
1 |
|
|
T25 |
12 |
|
T26 |
12 |
|
T27 |
2 |
| auto[1] |
7698098 |
1 |
|
|
T25 |
18 |
|
T27 |
10 |
|
T28 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16762460 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
1006722 |
1 |
|
|
T26 |
2 |
|
T34 |
4 |
|
T24 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10055009 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7714173 |
1 |
|
|
T26 |
10 |
|
T31 |
3 |
|
T34 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3364223 |
1 |
|
|
T26 |
8 |
|
T31 |
2 |
|
T34 |
1 |
| auto[1] |
auto[0] |
auto[1] |
503842 |
1 |
|
|
T26 |
2 |
|
T34 |
3 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3343228 |
1 |
|
|
T31 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
502880 |
1 |
|
|
T34 |
1 |
|
T24 |
1 |
|
T46 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10038922 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
7730260 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16769599 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
999583 |
1 |
|
|
T31 |
2 |
|
T14 |
1 |
|
T24 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10102241 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7666941 |
1 |
|
|
T26 |
4 |
|
T31 |
2 |
|
T34 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3337799 |
1 |
|
|
T26 |
4 |
|
T34 |
3 |
|
T14 |
1 |
| auto[1] |
auto[0] |
auto[1] |
498714 |
1 |
|
|
T31 |
2 |
|
T14 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3329559 |
1 |
|
|
T34 |
3 |
|
T16 |
2 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
500869 |
1 |
|
|
T46 |
2 |
|
T43 |
869 |
|
T120 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10068373 |
1 |
|
|
T25 |
9 |
|
T26 |
6 |
|
T27 |
7 |
| auto[1] |
7700809 |
1 |
|
|
T25 |
21 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16767462 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1001720 |
1 |
|
|
T34 |
2 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10075529 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7693653 |
1 |
|
|
T26 |
6 |
|
T31 |
3 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3368411 |
1 |
|
|
T31 |
1 |
|
T34 |
2 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
505211 |
1 |
|
|
T34 |
2 |
|
T3 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3323522 |
1 |
|
|
T26 |
6 |
|
T31 |
2 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
496509 |
1 |
|
|
T19 |
1 |
|
T46 |
1 |
|
T42 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10074386 |
1 |
|
|
T25 |
12 |
|
T26 |
6 |
|
T27 |
2 |
| auto[1] |
7694796 |
1 |
|
|
T25 |
18 |
|
T26 |
6 |
|
T27 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16770366 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
998816 |
1 |
|
|
T26 |
2 |
|
T34 |
2 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10083361 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7685821 |
1 |
|
|
T26 |
6 |
|
T31 |
1 |
|
T34 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3362984 |
1 |
|
|
T31 |
1 |
|
T34 |
2 |
|
T35 |
1 |
| auto[1] |
auto[0] |
auto[1] |
503527 |
1 |
|
|
T34 |
2 |
|
T3 |
1 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3324021 |
1 |
|
|
T26 |
4 |
|
T34 |
6 |
|
T14 |
8 |
| auto[1] |
auto[1] |
auto[1] |
495289 |
1 |
|
|
T26 |
2 |
|
T2 |
1 |
|
T14 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10013794 |
1 |
|
|
T25 |
12 |
|
T26 |
12 |
|
T27 |
6 |
| auto[1] |
7755388 |
1 |
|
|
T25 |
18 |
|
T27 |
6 |
|
T28 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757702 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1011480 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T14 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10016920 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7752262 |
1 |
|
|
T26 |
4 |
|
T31 |
3 |
|
T34 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3364640 |
1 |
|
|
T26 |
4 |
|
T31 |
2 |
|
T34 |
7 |
| auto[1] |
auto[0] |
auto[1] |
505193 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T14 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3376142 |
1 |
|
|
T34 |
1 |
|
T14 |
2 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506287 |
1 |
|
|
T16 |
1 |
|
T90 |
1 |
|
T46 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10052341 |
1 |
|
|
T25 |
21 |
|
T26 |
12 |
|
T27 |
7 |
| auto[1] |
7716841 |
1 |
|
|
T25 |
9 |
|
T27 |
5 |
|
T28 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16763988 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
1005194 |
1 |
|
|
T26 |
2 |
|
T34 |
1 |
|
T14 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10052472 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7716710 |
1 |
|
|
T26 |
10 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3341686 |
1 |
|
|
T26 |
8 |
|
T31 |
1 |
|
T34 |
2 |
| auto[1] |
auto[0] |
auto[1] |
499016 |
1 |
|
|
T26 |
2 |
|
T34 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3369830 |
1 |
|
|
T33 |
1 |
|
T34 |
3 |
|
T35 |
1 |
| auto[1] |
auto[1] |
auto[1] |
506178 |
1 |
|
|
T14 |
2 |
|
T119 |
1 |
|
T46 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10055383 |
1 |
|
|
T25 |
11 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7713799 |
1 |
|
|
T25 |
19 |
|
T28 |
3 |
|
T29 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16758085 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
1011097 |
1 |
|
|
T26 |
2 |
|
T31 |
1 |
|
T34 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10015252 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7753930 |
1 |
|
|
T26 |
6 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3367266 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[0] |
auto[1] |
503749 |
1 |
|
|
T26 |
2 |
|
T31 |
1 |
|
T34 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3375567 |
1 |
|
|
T34 |
2 |
|
T13 |
1 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[1] |
507348 |
1 |
|
|
T34 |
2 |
|
T90 |
1 |
|
T43 |
733 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10056808 |
1 |
|
|
T25 |
10 |
|
T26 |
12 |
|
T27 |
2 |
| auto[1] |
7712374 |
1 |
|
|
T25 |
20 |
|
T27 |
10 |
|
T28 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764003 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
1005179 |
1 |
|
|
T26 |
2 |
|
T34 |
2 |
|
T87 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053657 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7715525 |
1 |
|
|
T26 |
10 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3356583 |
1 |
|
|
T26 |
8 |
|
T31 |
1 |
|
T34 |
3 |
| auto[1] |
auto[0] |
auto[1] |
503853 |
1 |
|
|
T26 |
2 |
|
T34 |
2 |
|
T122 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3353763 |
1 |
|
|
T31 |
1 |
|
T33 |
1 |
|
T34 |
4 |
| auto[1] |
auto[1] |
auto[1] |
501326 |
1 |
|
|
T87 |
1 |
|
T10 |
4 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10047938 |
1 |
|
|
T25 |
18 |
|
T26 |
6 |
|
T27 |
2 |
| auto[1] |
7721244 |
1 |
|
|
T25 |
12 |
|
T26 |
6 |
|
T27 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16766385 |
1 |
|
|
T25 |
30 |
|
T26 |
9 |
|
T27 |
12 |
| auto[1] |
1002797 |
1 |
|
|
T26 |
3 |
|
T33 |
1 |
|
T34 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10072741 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7696441 |
1 |
|
|
T26 |
10 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3342811 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T34 |
1 |
| auto[1] |
auto[0] |
auto[1] |
499796 |
1 |
|
|
T26 |
1 |
|
T33 |
1 |
|
T88 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3350833 |
1 |
|
|
T26 |
4 |
|
T31 |
1 |
|
T34 |
3 |
| auto[1] |
auto[1] |
auto[1] |
503001 |
1 |
|
|
T26 |
2 |
|
T34 |
2 |
|
T14 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9992646 |
1 |
|
|
T25 |
14 |
|
T26 |
6 |
|
T27 |
1 |
| auto[1] |
7776536 |
1 |
|
|
T25 |
16 |
|
T26 |
6 |
|
T27 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764045 |
1 |
|
|
T25 |
30 |
|
T26 |
9 |
|
T27 |
12 |
| auto[1] |
1005137 |
1 |
|
|
T26 |
3 |
|
T34 |
1 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053032 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7716150 |
1 |
|
|
T26 |
6 |
|
T31 |
1 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3331798 |
1 |
|
|
T34 |
3 |
|
T24 |
1 |
|
T90 |
1 |
| auto[1] |
auto[0] |
auto[1] |
497462 |
1 |
|
|
T34 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3379215 |
1 |
|
|
T26 |
3 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
507675 |
1 |
|
|
T26 |
3 |
|
T14 |
2 |
|
T24 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10099507 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
7 |
| auto[1] |
7669675 |
1 |
|
|
T25 |
15 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761957 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1007225 |
1 |
|
|
T26 |
1 |
|
T31 |
1 |
|
T34 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10042333 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7726849 |
1 |
|
|
T26 |
6 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3406266 |
1 |
|
|
T34 |
4 |
|
T2 |
1 |
|
T14 |
3 |
| auto[1] |
auto[0] |
auto[1] |
511632 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3313358 |
1 |
|
|
T26 |
5 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
495593 |
1 |
|
|
T26 |
1 |
|
T34 |
1 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10054183 |
1 |
|
|
T25 |
12 |
|
T26 |
12 |
|
T27 |
6 |
| auto[1] |
7714999 |
1 |
|
|
T25 |
18 |
|
T27 |
6 |
|
T28 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16764773 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1004409 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T24 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10058654 |
1 |
|
|
T25 |
30 |
|
T26 |
2 |
|
T27 |
12 |
| auto[1] |
7710528 |
1 |
|
|
T26 |
10 |
|
T31 |
3 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3370448 |
1 |
|
|
T26 |
10 |
|
T34 |
4 |
|
T17 |
7 |
| auto[1] |
auto[0] |
auto[1] |
505633 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3335671 |
1 |
|
|
T31 |
2 |
|
T33 |
1 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[1] |
498776 |
1 |
|
|
T34 |
2 |
|
T24 |
1 |
|
T88 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10028326 |
1 |
|
|
T25 |
12 |
|
T26 |
6 |
|
T27 |
11 |
| auto[1] |
7740856 |
1 |
|
|
T25 |
18 |
|
T26 |
6 |
|
T27 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16763429 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
1005753 |
1 |
|
|
T34 |
3 |
|
T14 |
2 |
|
T24 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048369 |
1 |
|
|
T25 |
30 |
|
T26 |
12 |
|
T27 |
12 |
| auto[1] |
7720813 |
1 |
|
|
T31 |
2 |
|
T34 |
7 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3347723 |
1 |
|
|
T31 |
1 |
|
T34 |
1 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
500604 |
1 |
|
|
T34 |
1 |
|
T88 |
3 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3367337 |
1 |
|
|
T31 |
1 |
|
T34 |
3 |
|
T14 |
7 |
| auto[1] |
auto[1] |
auto[1] |
505149 |
1 |
|
|
T34 |
2 |
|
T14 |
2 |
|
T24 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10048512 |
1 |
|
|
T25 |
10 |
|
T26 |
6 |
|
T27 |
7 |
| auto[1] |
7720670 |
1 |
|
|
T25 |
20 |
|
T26 |
6 |
|
T27 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757903 |
1 |
|
|
T25 |
30 |
|
T26 |
11 |
|
T27 |
12 |
| auto[1] |
1011279 |
1 |
|
|
T26 |
1 |
|
T34 |
5 |
|
T14 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10017280 |
1 |
|
|
T25 |
30 |
|
T26 |
6 |
|
T27 |
12 |
| auto[1] |
7751902 |
1 |
|
|
T26 |
6 |
|
T31 |
2 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3363159 |
1 |
|
|
T31 |
1 |
|
T14 |
3 |
|
T16 |
2 |
| auto[1] |
auto[0] |
auto[1] |
503962 |
1 |
|
|
T34 |
3 |
|
T5 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3377464 |
1 |
|
|
T26 |
5 |
|
T31 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
507317 |
1 |
|
|
T26 |
1 |
|
T34 |
2 |
|
T14 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10026117 |
1 |
|
|
T25 |
11 |
|
T26 |
12 |
|
T27 |
2 |
| auto[1] |
7743065 |
1 |
|
|
T25 |
19 |
|
T27 |
10 |
|
T28 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16761888 |
1 |
|
|
T25 |
30 |
|
T26 |
10 |
|
T27 |
12 |
| auto[1] |
1007294 |
1 |
|
|
T26 |
2 |
|
T33 |
1 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10053069 |
1 |
|
|
T25 |
30 |
|
T26 |
8 |
|
T27 |
12 |
| auto[1] |
7716113 |
1 |
|
|
T26 |
4 |
|
T31 |
3 |
|
T33 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3355788 |
1 |
|
|
T26 |
2 |
|
T31 |
3 |
|
T34 |
1 |
| auto[1] |
auto[0] |
auto[1] |
502907 |
1 |
|
|
T26 |
2 |
|
T33 |
1 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3353031 |
1 |
|
|
T34 |
4 |
|
T35 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
504387 |
1 |
|
|
T34 |
1 |
|
T19 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |