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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 100.00


Total test records in report: 961
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T776 /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3250511887 Jan 24 01:27:14 PM PST 24 Jan 24 01:27:49 PM PST 24 236135647 ps
T777 /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.926705440 Jan 24 01:25:52 PM PST 24 Jan 24 01:26:41 PM PST 24 58817825 ps
T778 /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3179449908 Jan 24 01:24:54 PM PST 24 Jan 24 01:25:27 PM PST 24 24362273 ps
T779 /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.145533375 Jan 24 02:33:47 PM PST 24 Jan 24 02:34:02 PM PST 24 62815870 ps
T780 /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2686743914 Jan 24 01:25:05 PM PST 24 Jan 24 01:25:40 PM PST 24 72308253 ps
T781 /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.974939217 Jan 24 01:26:36 PM PST 24 Jan 24 01:27:29 PM PST 24 216765310 ps
T782 /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2861094747 Jan 24 01:27:40 PM PST 24 Jan 24 01:28:09 PM PST 24 80704793 ps
T783 /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3016350794 Jan 24 01:25:35 PM PST 24 Jan 24 01:26:26 PM PST 24 20979914 ps
T784 /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.353228470 Jan 24 01:27:54 PM PST 24 Jan 24 01:42:09 PM PST 24 472157428330 ps
T785 /workspace/coverage/default/40.gpio_stress_all.3493228497 Jan 24 01:27:25 PM PST 24 Jan 24 01:29:26 PM PST 24 7227186679 ps
T786 /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3325211764 Jan 24 01:24:09 PM PST 24 Jan 24 01:24:46 PM PST 24 77059080 ps
T787 /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1331381022 Jan 24 01:22:26 PM PST 24 Jan 24 01:23:24 PM PST 24 187569845 ps
T788 /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3335088718 Jan 24 01:25:48 PM PST 24 Jan 24 01:26:36 PM PST 24 162325746 ps
T789 /workspace/coverage/default/31.gpio_stress_all.2907718301 Jan 24 01:25:51 PM PST 24 Jan 24 01:29:40 PM PST 24 51120823059 ps
T790 /workspace/coverage/default/4.gpio_rand_intr_trigger.4212244095 Jan 24 01:21:48 PM PST 24 Jan 24 01:22:47 PM PST 24 119616333 ps
T791 /workspace/coverage/default/27.gpio_rand_intr_trigger.1626929050 Jan 24 01:28:50 PM PST 24 Jan 24 01:29:12 PM PST 24 453526582 ps
T792 /workspace/coverage/default/45.gpio_random_dout_din.2362788541 Jan 24 01:28:06 PM PST 24 Jan 24 01:28:35 PM PST 24 51048521 ps
T793 /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1989231892 Jan 24 01:52:00 PM PST 24 Jan 24 01:52:09 PM PST 24 335367203 ps
T794 /workspace/coverage/default/44.gpio_alert_test.2433541844 Jan 24 01:28:05 PM PST 24 Jan 24 01:28:34 PM PST 24 19628251 ps
T795 /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2168720996 Jan 24 01:32:36 PM PST 24 Jan 24 01:33:13 PM PST 24 43760716 ps
T796 /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.957290388 Jan 24 01:25:05 PM PST 24 Jan 24 01:31:44 PM PST 24 21503959046 ps
T797 /workspace/coverage/default/12.gpio_intr_rand_pgm.1767267785 Jan 24 01:23:09 PM PST 24 Jan 24 01:24:00 PM PST 24 153090984 ps
T798 /workspace/coverage/default/41.gpio_alert_test.3128229917 Jan 24 01:27:31 PM PST 24 Jan 24 01:28:03 PM PST 24 37195301 ps
T799 /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4045966548 Jan 24 01:22:14 PM PST 24 Jan 24 01:23:12 PM PST 24 66039633 ps
T800 /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1995560775 Jan 24 01:22:42 PM PST 24 Jan 24 01:29:28 PM PST 24 22245217625 ps
T801 /workspace/coverage/default/6.gpio_intr_rand_pgm.2632458947 Jan 24 01:22:14 PM PST 24 Jan 24 01:23:13 PM PST 24 70919815 ps
T802 /workspace/coverage/default/19.gpio_stress_all.2565594303 Jan 24 01:24:17 PM PST 24 Jan 24 01:26:41 PM PST 24 28635931866 ps
T803 /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2007201521 Jan 24 01:25:55 PM PST 24 Jan 24 01:35:47 PM PST 24 120394074496 ps
T804 /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2919673273 Jan 24 01:23:14 PM PST 24 Jan 24 01:24:08 PM PST 24 277094722 ps
T805 /workspace/coverage/default/32.gpio_smoke.2281961592 Jan 24 01:26:00 PM PST 24 Jan 24 01:26:52 PM PST 24 131336777 ps
T806 /workspace/coverage/default/33.gpio_full_random.1096440669 Jan 24 01:26:10 PM PST 24 Jan 24 01:27:08 PM PST 24 27240016 ps
T807 /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1417575448 Jan 24 01:26:18 PM PST 24 Jan 24 01:27:22 PM PST 24 1457937791 ps
T808 /workspace/coverage/default/6.gpio_filter_stress.3009185247 Jan 24 01:42:47 PM PST 24 Jan 24 01:43:44 PM PST 24 340179620 ps
T809 /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3276646583 Jan 24 01:28:40 PM PST 24 Jan 24 01:29:06 PM PST 24 286375598 ps
T810 /workspace/coverage/default/38.gpio_full_random.2067217121 Jan 24 01:27:01 PM PST 24 Jan 24 01:27:40 PM PST 24 45607484 ps
T811 /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2512523260 Jan 24 01:22:46 PM PST 24 Jan 24 01:38:20 PM PST 24 254163762448 ps
T812 /workspace/coverage/default/19.gpio_filter_stress.871905600 Jan 24 01:24:25 PM PST 24 Jan 24 01:25:09 PM PST 24 385696213 ps
T813 /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1431544797 Jan 24 01:27:23 PM PST 24 Jan 24 01:34:46 PM PST 24 31776442920 ps
T814 /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4100847525 Jan 24 02:40:03 PM PST 24 Jan 24 02:40:21 PM PST 24 67557677 ps
T815 /workspace/coverage/default/45.gpio_alert_test.2579328806 Jan 24 01:28:23 PM PST 24 Jan 24 01:28:46 PM PST 24 40628002 ps
T816 /workspace/coverage/default/45.gpio_full_random.1422743218 Jan 24 01:28:27 PM PST 24 Jan 24 01:28:51 PM PST 24 225124961 ps
T817 /workspace/coverage/default/22.gpio_full_random.2738223695 Jan 24 01:25:05 PM PST 24 Jan 24 01:25:40 PM PST 24 100214930 ps
T818 /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1270075641 Jan 24 01:26:54 PM PST 24 Jan 24 01:27:37 PM PST 24 23291880 ps
T819 /workspace/coverage/default/20.gpio_filter_stress.1134406576 Jan 24 01:24:34 PM PST 24 Jan 24 01:25:31 PM PST 24 6673041951 ps
T820 /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3470639561 Jan 24 01:25:02 PM PST 24 Jan 24 01:25:37 PM PST 24 90739863 ps
T821 /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.777492208 Jan 24 02:24:50 PM PST 24 Jan 24 02:24:56 PM PST 24 38574519 ps
T822 /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3213296990 Jan 24 01:25:08 PM PST 24 Jan 24 01:46:04 PM PST 24 82483228609 ps
T823 /workspace/coverage/default/0.gpio_alert_test.1792577863 Jan 24 01:21:08 PM PST 24 Jan 24 01:22:15 PM PST 24 32666807 ps
T824 /workspace/coverage/default/18.gpio_rand_intr_trigger.1875495177 Jan 24 01:24:18 PM PST 24 Jan 24 01:24:53 PM PST 24 90427144 ps
T825 /workspace/coverage/default/37.gpio_smoke.1883150794 Jan 24 01:26:43 PM PST 24 Jan 24 01:27:31 PM PST 24 221245760 ps
T826 /workspace/coverage/default/19.gpio_random_dout_din.535964403 Jan 24 01:24:17 PM PST 24 Jan 24 01:24:52 PM PST 24 154445071 ps
T827 /workspace/coverage/default/30.gpio_alert_test.3582262720 Jan 24 01:25:52 PM PST 24 Jan 24 01:26:41 PM PST 24 15711947 ps
T828 /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3258267235 Jan 24 01:25:43 PM PST 24 Jan 24 01:26:31 PM PST 24 77606676 ps
T829 /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2502619052 Jan 24 01:25:06 PM PST 24 Jan 24 01:25:44 PM PST 24 27699430 ps
T830 /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.562644026 Jan 24 01:27:11 PM PST 24 Jan 24 01:27:47 PM PST 24 27823794 ps
T831 /workspace/coverage/default/49.gpio_smoke.3960023184 Jan 24 01:28:41 PM PST 24 Jan 24 01:29:06 PM PST 24 66223621 ps
T832 /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2179164431 Jan 24 01:24:46 PM PST 24 Jan 24 01:25:19 PM PST 24 29293324 ps
T833 /workspace/coverage/default/14.gpio_random_dout_din.3210024536 Jan 24 01:23:26 PM PST 24 Jan 24 01:24:14 PM PST 24 72706608 ps
T834 /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3992125956 Jan 24 01:25:41 PM PST 24 Jan 24 01:26:30 PM PST 24 175290152 ps
T835 /workspace/coverage/default/0.gpio_intr_rand_pgm.1797429377 Jan 24 01:21:06 PM PST 24 Jan 24 01:22:14 PM PST 24 76897935 ps
T836 /workspace/coverage/default/7.gpio_smoke.4199038460 Jan 24 01:22:13 PM PST 24 Jan 24 01:23:12 PM PST 24 73072013 ps
T837 /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1021181341 Jan 24 02:40:42 PM PST 24 Jan 24 02:40:53 PM PST 24 63391776 ps
T838 /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2210459278 Jan 24 01:25:50 PM PST 24 Jan 24 01:26:39 PM PST 24 164804895 ps
T839 /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1271797844 Jan 24 01:26:39 PM PST 24 Jan 24 01:27:29 PM PST 24 120276033 ps
T840 /workspace/coverage/default/48.gpio_alert_test.1964512633 Jan 24 01:28:40 PM PST 24 Jan 24 01:29:03 PM PST 24 39128767 ps
T841 /workspace/coverage/default/8.gpio_alert_test.4008061048 Jan 24 01:22:36 PM PST 24 Jan 24 01:23:32 PM PST 24 15288367 ps
T842 /workspace/coverage/default/6.gpio_random_dout_din.3265181242 Jan 24 01:22:13 PM PST 24 Jan 24 01:23:12 PM PST 24 51432515 ps
T843 /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1264035736 Jan 24 01:23:25 PM PST 24 Jan 24 01:24:13 PM PST 24 116064738 ps
T844 /workspace/coverage/default/33.gpio_filter_stress.132272280 Jan 24 01:33:08 PM PST 24 Jan 24 01:33:46 PM PST 24 1068950059 ps
T845 /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.828911232 Jan 24 01:28:26 PM PST 24 Jan 24 01:28:49 PM PST 24 131178191 ps
T846 /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3546488362 Jan 24 01:24:18 PM PST 24 Jan 24 01:24:53 PM PST 24 228448709 ps
T847 /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.4006318640 Jan 24 01:26:20 PM PST 24 Jan 24 01:32:36 PM PST 24 47330645374 ps
T848 /workspace/coverage/default/6.gpio_rand_intr_trigger.2052045249 Jan 24 01:22:21 PM PST 24 Jan 24 01:23:18 PM PST 24 186425066 ps
T849 /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3717371304 Jan 24 01:25:20 PM PST 24 Jan 24 01:26:08 PM PST 24 83470774 ps
T850 /workspace/coverage/default/27.gpio_filter_stress.2439904557 Jan 24 01:25:19 PM PST 24 Jan 24 01:26:25 PM PST 24 824669111 ps
T851 /workspace/coverage/default/7.gpio_rand_intr_trigger.411294680 Jan 24 01:22:17 PM PST 24 Jan 24 01:23:16 PM PST 24 287196259 ps
T852 /workspace/coverage/default/40.gpio_full_random.4219188988 Jan 24 01:27:23 PM PST 24 Jan 24 01:27:56 PM PST 24 70902915 ps
T853 /workspace/coverage/default/43.gpio_full_random.2687947628 Jan 24 01:27:55 PM PST 24 Jan 24 01:28:25 PM PST 24 95785450 ps
T854 /workspace/coverage/default/27.gpio_random_dout_din.3332465450 Jan 24 01:25:15 PM PST 24 Jan 24 01:26:00 PM PST 24 270366462 ps
T855 /workspace/coverage/default/34.gpio_stress_all.4098896059 Jan 24 01:26:18 PM PST 24 Jan 24 01:27:41 PM PST 24 8200324868 ps
T856 /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4147683417 Jan 24 01:25:11 PM PST 24 Jan 24 01:25:53 PM PST 24 23756251 ps
T857 /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.420741610 Jan 24 01:24:01 PM PST 24 Jan 24 01:24:41 PM PST 24 69222635 ps
T858 /workspace/coverage/default/38.gpio_stress_all.4082317510 Jan 24 01:26:51 PM PST 24 Jan 24 01:30:08 PM PST 24 56553718573 ps
T859 /workspace/coverage/default/39.gpio_stress_all.2328522758 Jan 24 01:27:13 PM PST 24 Jan 24 01:30:32 PM PST 24 10755050201 ps
T860 /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1408184508 Jan 24 01:21:40 PM PST 24 Jan 24 01:22:42 PM PST 24 45302424 ps
T861 /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4248761021 Jan 24 01:26:19 PM PST 24 Jan 24 01:27:20 PM PST 24 191357831 ps
T862 /workspace/coverage/default/3.gpio_stress_all.3827848930 Jan 24 01:22:00 PM PST 24 Jan 24 01:25:52 PM PST 24 27196536795 ps
T863 /workspace/coverage/default/11.gpio_alert_test.2660473635 Jan 24 01:23:02 PM PST 24 Jan 24 01:23:54 PM PST 24 18941507 ps
T864 /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1779418456 Jan 24 01:26:10 PM PST 24 Jan 24 01:27:09 PM PST 24 125822779 ps
T865 /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4293684560 Jan 24 01:28:02 PM PST 24 Jan 24 01:28:30 PM PST 24 64062141 ps
T866 /workspace/coverage/default/20.gpio_stress_all.76188900 Jan 24 01:24:34 PM PST 24 Jan 24 01:25:34 PM PST 24 7941420330 ps
T867 /workspace/coverage/default/22.gpio_stress_all.646176197 Jan 24 01:24:46 PM PST 24 Jan 24 01:26:32 PM PST 24 23130815605 ps
T868 /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2436064472 Jan 24 01:25:39 PM PST 24 Jan 24 01:48:09 PM PST 24 1553717233529 ps
T869 /workspace/coverage/default/2.gpio_filter_stress.3108006177 Jan 24 01:21:31 PM PST 24 Jan 24 01:22:53 PM PST 24 712842575 ps
T870 /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.207647014 Jan 24 01:28:24 PM PST 24 Jan 24 01:28:49 PM PST 24 427543413 ps
T871 /workspace/coverage/default/14.gpio_intr_rand_pgm.2668976750 Jan 24 01:23:22 PM PST 24 Jan 24 01:24:12 PM PST 24 87903094 ps
T872 /workspace/coverage/default/23.gpio_full_random.839491039 Jan 24 01:24:52 PM PST 24 Jan 24 01:25:25 PM PST 24 33744664 ps
T873 /workspace/coverage/default/11.gpio_filter_stress.3994218602 Jan 24 01:23:02 PM PST 24 Jan 24 01:24:14 PM PST 24 412186791 ps
T874 /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.381174137 Jan 24 01:24:36 PM PST 24 Jan 24 01:25:07 PM PST 24 95070639 ps
T875 /workspace/coverage/default/10.gpio_full_random.2843955304 Jan 24 01:22:48 PM PST 24 Jan 24 01:23:45 PM PST 24 43435611 ps
T876 /workspace/coverage/default/28.gpio_full_random.2735586477 Jan 24 01:25:38 PM PST 24 Jan 24 01:26:28 PM PST 24 57390202 ps
T877 /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.4218242471 Jan 24 01:28:43 PM PST 24 Jan 24 01:29:07 PM PST 24 185613466 ps
T878 /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1420144036 Jan 24 01:22:04 PM PST 24 Jan 24 01:23:05 PM PST 24 108275975 ps
T879 /workspace/coverage/default/33.gpio_alert_test.68364036 Jan 24 01:26:09 PM PST 24 Jan 24 01:27:08 PM PST 24 48341011 ps
T880 /workspace/coverage/default/22.gpio_smoke.828480367 Jan 24 01:24:43 PM PST 24 Jan 24 01:25:16 PM PST 24 72345676 ps
T881 /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1207982216 Jan 24 01:26:33 PM PST 24 Jan 24 01:27:27 PM PST 24 50644113 ps
T882 /workspace/coverage/default/42.gpio_alert_test.189176986 Jan 24 01:27:42 PM PST 24 Jan 24 01:28:10 PM PST 24 14546940 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2125384968 Jan 24 10:47:42 PM PST 24 Jan 24 10:47:44 PM PST 24 88106130 ps
T883 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3254681262 Jan 24 10:48:30 PM PST 24 Jan 24 10:48:32 PM PST 24 87138889 ps
T884 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3742095740 Jan 24 10:47:47 PM PST 24 Jan 24 10:47:49 PM PST 24 78757884 ps
T116 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2135069563 Jan 24 10:49:32 PM PST 24 Jan 24 10:49:39 PM PST 24 175092277 ps
T885 /workspace/coverage/cover_reg_top/14.gpio_intr_test.980739738 Jan 24 10:49:53 PM PST 24 Jan 24 10:49:55 PM PST 24 11742695 ps
T117 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.4220144833 Jan 24 10:48:20 PM PST 24 Jan 24 10:48:21 PM PST 24 14957439 ps
T886 /workspace/coverage/cover_reg_top/36.gpio_intr_test.365205719 Jan 24 10:50:54 PM PST 24 Jan 24 10:50:57 PM PST 24 26293701 ps
T887 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3525138025 Jan 24 10:48:33 PM PST 24 Jan 24 10:48:37 PM PST 24 82076120 ps
T47 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.815157057 Jan 24 10:49:11 PM PST 24 Jan 24 10:49:13 PM PST 24 123005259 ps
T888 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3878113813 Jan 24 10:48:56 PM PST 24 Jan 24 10:48:57 PM PST 24 27719159 ps
T889 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3685805849 Jan 24 10:51:12 PM PST 24 Jan 24 10:51:13 PM PST 24 60105658 ps
T118 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2212906099 Jan 24 10:49:24 PM PST 24 Jan 24 10:49:32 PM PST 24 53637606 ps
T890 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2854085907 Jan 24 10:50:38 PM PST 24 Jan 24 10:50:40 PM PST 24 16783093 ps
T891 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3353185881 Jan 25 02:10:34 AM PST 24 Jan 25 02:10:38 AM PST 24 10810217 ps
T892 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2150390273 Jan 24 11:04:34 PM PST 24 Jan 24 11:04:37 PM PST 24 149795929 ps
T48 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3274653228 Jan 24 10:49:19 PM PST 24 Jan 24 10:49:27 PM PST 24 160014247 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.756245779 Jan 24 10:47:48 PM PST 24 Jan 24 10:47:50 PM PST 24 39941225 ps
T100 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3255739966 Jan 24 10:49:59 PM PST 24 Jan 24 10:50:02 PM PST 24 120810428 ps
T101 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3140195263 Jan 24 10:50:29 PM PST 24 Jan 24 10:50:31 PM PST 24 19990633 ps
T102 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3452205407 Jan 25 01:33:32 AM PST 24 Jan 25 01:33:34 AM PST 24 30382926 ps
T103 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3720314740 Jan 25 12:05:20 AM PST 24 Jan 25 12:05:23 AM PST 24 35308074 ps
T104 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2768010801 Jan 24 10:49:19 PM PST 24 Jan 24 10:49:28 PM PST 24 576433442 ps
T94 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2865119623 Jan 24 10:48:32 PM PST 24 Jan 24 10:48:33 PM PST 24 12740005 ps
T105 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2233195521 Jan 24 10:47:45 PM PST 24 Jan 24 10:47:46 PM PST 24 14595064 ps
T893 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4099488648 Jan 24 10:49:18 PM PST 24 Jan 24 10:49:27 PM PST 24 85379830 ps
T894 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.260571816 Jan 24 10:48:56 PM PST 24 Jan 24 10:49:00 PM PST 24 255682234 ps
T895 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.37642971 Jan 24 10:47:45 PM PST 24 Jan 24 10:47:47 PM PST 24 106949677 ps
T896 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1641942496 Jan 24 10:50:40 PM PST 24 Jan 24 10:50:44 PM PST 24 34422662 ps
T40 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2104820010 Jan 24 10:49:19 PM PST 24 Jan 24 10:49:27 PM PST 24 424700314 ps
T897 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2859236332 Jan 24 10:49:53 PM PST 24 Jan 24 10:49:56 PM PST 24 465779786 ps
T898 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2606837657 Jan 24 10:50:25 PM PST 24 Jan 24 10:50:27 PM PST 24 22125732 ps
T899 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3072554859 Jan 24 10:49:08 PM PST 24 Jan 24 10:49:11 PM PST 24 116315904 ps
T900 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.532764691 Jan 24 10:49:32 PM PST 24 Jan 24 10:49:38 PM PST 24 33594353 ps
T901 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3388695889 Jan 24 10:50:28 PM PST 24 Jan 24 10:50:30 PM PST 24 47000204 ps
T902 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3706596162 Jan 24 10:50:36 PM PST 24 Jan 24 10:50:38 PM PST 24 12408749 ps
T903 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1728787178 Jan 24 11:55:18 PM PST 24 Jan 24 11:55:22 PM PST 24 164839577 ps
T904 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2150748001 Jan 24 10:48:49 PM PST 24 Jan 24 10:48:52 PM PST 24 176825000 ps
T41 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.286022426 Jan 24 10:47:46 PM PST 24 Jan 24 10:47:48 PM PST 24 42482650 ps
T95 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3691001905 Jan 24 10:50:38 PM PST 24 Jan 24 10:50:40 PM PST 24 35920301 ps
T106 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1726432749 Jan 24 10:50:39 PM PST 24 Jan 24 10:50:41 PM PST 24 19421099 ps
T905 /workspace/coverage/cover_reg_top/30.gpio_intr_test.424166374 Jan 24 10:50:50 PM PST 24 Jan 24 10:50:52 PM PST 24 38774728 ps
T906 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1701035862 Jan 24 10:49:46 PM PST 24 Jan 24 10:49:49 PM PST 24 616047245 ps
T907 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3095892625 Jan 25 12:43:30 AM PST 24 Jan 25 12:43:32 AM PST 24 1690177743 ps
T908 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2820971268 Jan 24 10:50:26 PM PST 24 Jan 24 10:50:30 PM PST 24 180905102 ps
T909 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.641447262 Jan 24 10:48:50 PM PST 24 Jan 24 10:48:52 PM PST 24 31497271 ps
T910 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2075999687 Jan 24 10:47:48 PM PST 24 Jan 24 10:47:50 PM PST 24 19456441 ps
T50 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1684847270 Jan 24 10:47:47 PM PST 24 Jan 24 10:47:49 PM PST 24 562022061 ps
T911 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2250818999 Jan 24 10:48:23 PM PST 24 Jan 24 10:48:26 PM PST 24 100972982 ps
T912 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1590801640 Jan 24 10:50:39 PM PST 24 Jan 24 10:50:42 PM PST 24 49582283 ps
T913 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3409674116 Jan 24 10:49:32 PM PST 24 Jan 24 10:49:40 PM PST 24 25222539 ps
T49 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.360714069 Jan 24 10:48:20 PM PST 24 Jan 24 10:48:21 PM PST 24 138088596 ps
T914 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.76599860 Jan 24 10:49:36 PM PST 24 Jan 24 10:49:40 PM PST 24 52825819 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3019258691 Jan 24 10:47:46 PM PST 24 Jan 24 10:47:47 PM PST 24 12237598 ps
T915 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2656622525 Jan 24 10:48:09 PM PST 24 Jan 24 10:48:13 PM PST 24 939630491 ps
T916 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2745733274 Jan 24 10:50:00 PM PST 24 Jan 24 10:50:02 PM PST 24 330838740 ps
T917 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1841232698 Jan 24 10:49:31 PM PST 24 Jan 24 10:49:38 PM PST 24 46832205 ps
T918 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3711273499 Jan 24 10:48:47 PM PST 24 Jan 24 10:48:49 PM PST 24 40678932 ps
T97 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1885926905 Jan 24 10:48:31 PM PST 24 Jan 24 10:48:32 PM PST 24 12210472 ps
T919 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.133310108 Jan 24 10:48:19 PM PST 24 Jan 24 10:48:21 PM PST 24 29323512 ps
T920 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1000488684 Jan 24 10:50:26 PM PST 24 Jan 24 10:50:28 PM PST 24 26687206 ps
T921 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.292104445 Jan 25 01:07:47 AM PST 24 Jan 25 01:07:49 AM PST 24 12296339 ps
T922 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3901087888 Jan 24 10:50:32 PM PST 24 Jan 24 10:50:33 PM PST 24 172857259 ps
T923 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.778297288 Jan 24 10:48:46 PM PST 24 Jan 24 10:48:48 PM PST 24 70202435 ps
T924 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2553828390 Jan 24 10:50:55 PM PST 24 Jan 24 10:50:58 PM PST 24 89184387 ps
T925 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2773204737 Jan 24 10:49:18 PM PST 24 Jan 24 10:49:27 PM PST 24 31680180 ps
T926 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1298887167 Jan 24 10:50:51 PM PST 24 Jan 24 10:50:53 PM PST 24 17372061 ps
T927 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1635452895 Jan 24 10:50:24 PM PST 24 Jan 24 10:50:26 PM PST 24 17520633 ps
T928 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3949647379 Jan 24 10:48:21 PM PST 24 Jan 24 10:48:23 PM PST 24 11261605 ps
T929 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2552136451 Jan 24 10:47:47 PM PST 24 Jan 24 10:47:50 PM PST 24 202624182 ps
T930 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2608417132 Jan 24 10:48:59 PM PST 24 Jan 24 10:49:02 PM PST 24 78774183 ps
T99 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2355858431 Jan 24 10:47:45 PM PST 24 Jan 24 10:47:48 PM PST 24 815958750 ps
T931 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3969219038 Jan 25 02:21:56 AM PST 24 Jan 25 02:22:03 AM PST 24 97867879 ps
T932 /workspace/coverage/cover_reg_top/3.gpio_intr_test.498279934 Jan 24 10:48:21 PM PST 24 Jan 24 10:48:23 PM PST 24 91571285 ps
T933 /workspace/coverage/cover_reg_top/18.gpio_intr_test.641487590 Jan 24 10:50:24 PM PST 24 Jan 24 10:50:26 PM PST 24 35695153 ps
T98 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2495651092 Jan 24 10:48:45 PM PST 24 Jan 24 10:48:46 PM PST 24 176053720 ps
T934 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1863254731 Jan 24 10:49:11 PM PST 24 Jan 24 10:49:13 PM PST 24 289714488 ps
T935 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3377974315 Jan 24 10:50:29 PM PST 24 Jan 24 10:50:33 PM PST 24 112873569 ps
T936 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2020302795 Jan 24 10:48:21 PM PST 24 Jan 24 10:48:24 PM PST 24 1038785411 ps
T937 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.239372704 Jan 24 10:48:49 PM PST 24 Jan 24 10:48:51 PM PST 24 170272835 ps
T938 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1199771596 Jan 24 10:50:54 PM PST 24 Jan 24 10:50:56 PM PST 24 49207192 ps
T939 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.277839487 Jan 24 10:49:50 PM PST 24 Jan 24 10:49:51 PM PST 24 40883141 ps
T940 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1125939372 Jan 24 10:48:49 PM PST 24 Jan 24 10:48:51 PM PST 24 18371745 ps
T941 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1802213677 Jan 24 10:48:06 PM PST 24 Jan 24 10:48:07 PM PST 24 32179500 ps
T942 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1313839710 Jan 24 10:50:02 PM PST 24 Jan 24 10:50:04 PM PST 24 46466581 ps
T943 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3619926138 Jan 24 10:50:55 PM PST 24 Jan 24 10:50:58 PM PST 24 47184629 ps
T944 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1830265811 Jan 24 10:49:32 PM PST 24 Jan 24 10:49:38 PM PST 24 37295949 ps
T945 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.26031885 Jan 24 10:48:08 PM PST 24 Jan 24 10:48:10 PM PST 24 95714066 ps
T946 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2885624953 Jan 24 10:50:38 PM PST 24 Jan 24 10:50:41 PM PST 24 46606889 ps
T947 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.531293478 Jan 24 10:49:33 PM PST 24 Jan 24 10:49:40 PM PST 24 115678932 ps
T948 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3450002422 Jan 24 10:56:34 PM PST 24 Jan 24 10:56:38 PM PST 24 116422868 ps
T949 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1093251953 Jan 24 10:48:47 PM PST 24 Jan 24 10:48:48 PM PST 24 44115236 ps
T950 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3402901997 Jan 24 10:50:37 PM PST 24 Jan 24 10:50:42 PM PST 24 50008790 ps
T107 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.783143638 Jan 24 10:48:26 PM PST 24 Jan 24 10:48:27 PM PST 24 23345757 ps
T951 /workspace/coverage/cover_reg_top/8.gpio_intr_test.624420883 Jan 24 10:49:08 PM PST 24 Jan 24 10:49:09 PM PST 24 14644970 ps
T952 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.559974296 Jan 24 10:50:38 PM PST 24 Jan 24 10:50:41 PM PST 24 841786925 ps
T953 /workspace/coverage/cover_reg_top/10.gpio_intr_test.263875809 Jan 24 10:49:18 PM PST 24 Jan 24 10:49:26 PM PST 24 42244562 ps
T954 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1699377551 Jan 24 10:48:32 PM PST 24 Jan 24 10:48:34 PM PST 24 293384069 ps
T955 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4005970425 Jan 24 10:48:22 PM PST 24 Jan 24 10:48:24 PM PST 24 41669755 ps
T956 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3581794266 Jan 24 11:09:03 PM PST 24 Jan 24 11:09:05 PM PST 24 71594859 ps
T957 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.581463299 Jan 25 03:51:17 AM PST 24 Jan 25 03:51:19 AM PST 24 59904011 ps
T958 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2646107126 Jan 25 12:06:37 AM PST 24 Jan 25 12:06:39 AM PST 24 32483220 ps
T959 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.516095122 Jan 24 10:49:47 PM PST 24 Jan 24 10:49:49 PM PST 24 47313519 ps
T960 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3567433162 Jan 25 02:08:51 AM PST 24 Jan 25 02:08:53 AM PST 24 18008346 ps
T961 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3935225280 Jan 24 10:49:51 PM PST 24 Jan 24 10:49:53 PM PST 24 57909597 ps

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.98340555
Short name T34
Test name
Test status
Simulation time 131253298 ps
CPU time 1.16 seconds
Started Jan 24 11:18:46 PM PST 24
Finished Jan 24 11:18:50 PM PST 24
Peak memory 198332 kb
Host smart-df2a3c54-a087-4311-b4f5-0a24725d09a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98340555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.gpio_tl_intg_err.98340555
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2415488801
Short name T51
Test name
Test status
Simulation time 318387829 ps
CPU time 1.28 seconds
Started Jan 24 10:56:39 PM PST 24
Finished Jan 24 10:56:45 PM PST 24
Peak memory 197732 kb
Host smart-9d20b5da-36ce-4047-baea-c9eb6f9de9e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2415488801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2415488801
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.937352520
Short name T54
Test name
Test status
Simulation time 268876057 ps
CPU time 2.77 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:24:54 PM PST 24
Peak memory 198188 kb
Host smart-9a9203b6-44f7-45b0-95a0-495d5baab33c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937352520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.937352520
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2251917886
Short name T43
Test name
Test status
Simulation time 34104246729 ps
CPU time 62.46 seconds
Started Jan 24 01:27:33 PM PST 24
Finished Jan 24 01:29:06 PM PST 24
Peak memory 198336 kb
Host smart-e5a57613-b1b2-4276-8e6f-eef6a9bbc5d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251917886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2251917886
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.841322876
Short name T1
Test name
Test status
Simulation time 46056394 ps
CPU time 1.16 seconds
Started Jan 24 11:15:19 PM PST 24
Finished Jan 24 11:15:22 PM PST 24
Peak memory 198284 kb
Host smart-3aaeb79e-2b94-48fb-bf2c-299703c51d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841322876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.841322876
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2742396020
Short name T29
Test name
Test status
Simulation time 131432663 ps
CPU time 0.69 seconds
Started Jan 24 11:30:32 PM PST 24
Finished Jan 24 11:30:34 PM PST 24
Peak memory 193944 kb
Host smart-a55d4829-4b89-40e6-985c-2bd65df6d20c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742396020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2742396020
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3020676832
Short name T3
Test name
Test status
Simulation time 16580837 ps
CPU time 0.64 seconds
Started Jan 24 10:49:24 PM PST 24
Finished Jan 24 10:49:32 PM PST 24
Peak memory 195496 kb
Host smart-bb3b6965-997d-4c08-953e-2a7324b0947b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020676832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3020676832
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.960653606
Short name T80
Test name
Test status
Simulation time 106393792760 ps
CPU time 778.77 seconds
Started Jan 24 01:21:10 PM PST 24
Finished Jan 24 01:35:16 PM PST 24
Peak memory 198344 kb
Host smart-fb1aac51-4363-4ee8-a3b2-b3baf2d694d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=960653606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.960653606
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2428537710
Short name T36
Test name
Test status
Simulation time 112891031 ps
CPU time 0.95 seconds
Started Jan 24 01:21:10 PM PST 24
Finished Jan 24 01:22:18 PM PST 24
Peak memory 214720 kb
Host smart-a8fae6fb-42f8-4cc5-abc6-21639331bc6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428537710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2428537710
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4213655694
Short name T42
Test name
Test status
Simulation time 327093855 ps
CPU time 1.47 seconds
Started Jan 25 01:22:24 AM PST 24
Finished Jan 25 01:22:26 AM PST 24
Peak memory 198324 kb
Host smart-a423d82d-d244-4aaa-aa45-186dd8907300
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213655694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4213655694
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.791169067
Short name T26
Test name
Test status
Simulation time 26222294 ps
CPU time 0.76 seconds
Started Jan 24 10:47:43 PM PST 24
Finished Jan 24 10:47:45 PM PST 24
Peak memory 196360 kb
Host smart-f88928ae-62ab-468a-8885-ce2a58bd6010
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791169067 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.791169067
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.756245779
Short name T93
Test name
Test status
Simulation time 39941225 ps
CPU time 0.63 seconds
Started Jan 24 10:47:48 PM PST 24
Finished Jan 24 10:47:50 PM PST 24
Peak memory 195300 kb
Host smart-0024e29c-f4cf-443f-ab7a-7359d3488387
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756245779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.756245779
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.315276056
Short name T61
Test name
Test status
Simulation time 63757197 ps
CPU time 1.24 seconds
Started Jan 25 02:02:24 AM PST 24
Finished Jan 25 02:02:46 AM PST 24
Peak memory 191376 kb
Host smart-8220c387-56e5-4864-a6f6-b843c958b62f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=315276056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.315276056
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4193393855
Short name T85
Test name
Test status
Simulation time 13631498 ps
CPU time 0.63 seconds
Started Jan 24 10:50:12 PM PST 24
Finished Jan 24 10:50:14 PM PST 24
Peak memory 195040 kb
Host smart-519725a1-8b34-4c1f-8007-692ede9c0095
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193393855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4193393855
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/default/19.gpio_alert_test.105287291
Short name T58
Test name
Test status
Simulation time 18275454 ps
CPU time 0.58 seconds
Started Jan 24 01:24:23 PM PST 24
Finished Jan 24 01:24:55 PM PST 24
Peak memory 194900 kb
Host smart-582932f0-4b57-4f57-bb2a-fc770a547112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105287291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.105287291
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2089560773
Short name T15
Test name
Test status
Simulation time 496307258 ps
CPU time 3.39 seconds
Started Jan 24 10:47:45 PM PST 24
Finished Jan 24 10:47:49 PM PST 24
Peak memory 198256 kb
Host smart-39c666f3-a393-4d74-8f85-410e75379cbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089560773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2089560773
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3416875461
Short name T108
Test name
Test status
Simulation time 15945932 ps
CPU time 0.6 seconds
Started Jan 24 10:50:54 PM PST 24
Finished Jan 24 10:50:56 PM PST 24
Peak memory 193912 kb
Host smart-8edebd91-5765-4243-b589-6adb20f7fd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416875461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3416875461
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1684847270
Short name T50
Test name
Test status
Simulation time 562022061 ps
CPU time 1.56 seconds
Started Jan 24 10:47:47 PM PST 24
Finished Jan 24 10:47:49 PM PST 24
Peak memory 198324 kb
Host smart-7043dae0-d4af-4dba-ba34-9d192957edfa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684847270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1684847270
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4166992441
Short name T14
Test name
Test status
Simulation time 56817453 ps
CPU time 0.83 seconds
Started Jan 24 11:19:40 PM PST 24
Finished Jan 24 11:19:41 PM PST 24
Peak memory 197280 kb
Host smart-f05cfb64-c5b2-4f6a-a584-22c2e1e24920
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166992441 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.4166992441
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1964684700
Short name T84
Test name
Test status
Simulation time 266990602 ps
CPU time 0.67 seconds
Started Jan 24 10:47:45 PM PST 24
Finished Jan 24 10:47:47 PM PST 24
Peak memory 194860 kb
Host smart-99a6e777-2179-431c-9291-e2ba7f45527e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964684700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1964684700
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2075999687
Short name T910
Test name
Test status
Simulation time 19456441 ps
CPU time 0.66 seconds
Started Jan 24 10:47:48 PM PST 24
Finished Jan 24 10:47:50 PM PST 24
Peak memory 195184 kb
Host smart-ae8a1b8a-6b90-4721-9cc4-546f041e87cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075999687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2075999687
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3271062246
Short name T87
Test name
Test status
Simulation time 73282106 ps
CPU time 0.84 seconds
Started Jan 24 10:47:47 PM PST 24
Finished Jan 24 10:47:48 PM PST 24
Peak memory 198152 kb
Host smart-891424b5-b6d1-4134-aa9b-04888e033979
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271062246 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3271062246
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.863707536
Short name T127
Test name
Test status
Simulation time 58203017 ps
CPU time 0.56 seconds
Started Jan 24 10:47:42 PM PST 24
Finished Jan 24 10:47:44 PM PST 24
Peak memory 194564 kb
Host smart-1252bd7e-0985-45ef-9a87-5ba9453dc07c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863707536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.863707536
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.37642971
Short name T895
Test name
Test status
Simulation time 106949677 ps
CPU time 0.75 seconds
Started Jan 24 10:47:45 PM PST 24
Finished Jan 24 10:47:47 PM PST 24
Peak memory 196824 kb
Host smart-c1f16ad1-65b6-419b-90b2-b4f52e7e29f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642971 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.gpio_same_csr_outstanding.37642971
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2552136451
Short name T929
Test name
Test status
Simulation time 202624182 ps
CPU time 2.23 seconds
Started Jan 24 10:47:47 PM PST 24
Finished Jan 24 10:47:50 PM PST 24
Peak memory 198296 kb
Host smart-fe86d954-48b8-4a5c-b123-3f872c163c79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552136451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2552136451
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.604654481
Short name T18
Test name
Test status
Simulation time 21114559 ps
CPU time 0.69 seconds
Started Jan 24 10:47:46 PM PST 24
Finished Jan 24 10:47:48 PM PST 24
Peak memory 194620 kb
Host smart-33a4c451-fbfe-48b3-8e6a-d0d8e911cf4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604654481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.604654481
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2355858431
Short name T99
Test name
Test status
Simulation time 815958750 ps
CPU time 2.68 seconds
Started Jan 24 10:47:45 PM PST 24
Finished Jan 24 10:47:48 PM PST 24
Peak memory 196704 kb
Host smart-e27acc1a-1d44-40f4-8333-dc200d36c8aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355858431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2355858431
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2125384968
Short name T92
Test name
Test status
Simulation time 88106130 ps
CPU time 0.67 seconds
Started Jan 24 10:47:42 PM PST 24
Finished Jan 24 10:47:44 PM PST 24
Peak memory 195036 kb
Host smart-67881863-4baa-4756-92ff-4df1dfa6486c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125384968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2125384968
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3450002422
Short name T948
Test name
Test status
Simulation time 116422868 ps
CPU time 1.52 seconds
Started Jan 24 10:56:34 PM PST 24
Finished Jan 24 10:56:38 PM PST 24
Peak memory 198300 kb
Host smart-248c14b8-2664-428f-9635-03f79136db6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450002422 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3450002422
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3019258691
Short name T96
Test name
Test status
Simulation time 12237598 ps
CPU time 0.64 seconds
Started Jan 24 10:47:46 PM PST 24
Finished Jan 24 10:47:47 PM PST 24
Peak memory 194760 kb
Host smart-cd19b144-869f-40de-acf2-925643e008a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019258691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3019258691
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3742095740
Short name T884
Test name
Test status
Simulation time 78757884 ps
CPU time 0.58 seconds
Started Jan 24 10:47:47 PM PST 24
Finished Jan 24 10:47:49 PM PST 24
Peak memory 193904 kb
Host smart-ffaa7800-7ea1-4527-871a-67757ef5d609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742095740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3742095740
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.518283569
Short name T7
Test name
Test status
Simulation time 18321000 ps
CPU time 0.7 seconds
Started Jan 25 12:36:01 AM PST 24
Finished Jan 25 12:36:04 AM PST 24
Peak memory 195052 kb
Host smart-d1582d32-d7da-4acb-b38a-f5f89289e37c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518283569 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.518283569
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.286022426
Short name T41
Test name
Test status
Simulation time 42482650 ps
CPU time 0.86 seconds
Started Jan 24 10:47:46 PM PST 24
Finished Jan 24 10:47:48 PM PST 24
Peak memory 197492 kb
Host smart-d891f806-6405-4ba3-8e23-623fde7ba1da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286022426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.286022426
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3795533555
Short name T90
Test name
Test status
Simulation time 14209640 ps
CPU time 0.63 seconds
Started Jan 24 10:49:17 PM PST 24
Finished Jan 24 10:49:23 PM PST 24
Peak memory 196856 kb
Host smart-b29ef401-a32d-4cdb-8be5-f20ac345845c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795533555 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3795533555
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.392586418
Short name T13
Test name
Test status
Simulation time 94570060 ps
CPU time 0.57 seconds
Started Jan 24 10:49:18 PM PST 24
Finished Jan 24 10:49:26 PM PST 24
Peak memory 194912 kb
Host smart-57ba2bae-f169-4e95-b093-099d98009596
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392586418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.392586418
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.263875809
Short name T953
Test name
Test status
Simulation time 42244562 ps
CPU time 0.62 seconds
Started Jan 24 10:49:18 PM PST 24
Finished Jan 24 10:49:26 PM PST 24
Peak memory 194536 kb
Host smart-cb248279-cf08-4a14-93da-4d91729dd53f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263875809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.263875809
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4099488648
Short name T893
Test name
Test status
Simulation time 85379830 ps
CPU time 0.92 seconds
Started Jan 24 10:49:18 PM PST 24
Finished Jan 24 10:49:27 PM PST 24
Peak memory 196484 kb
Host smart-735f9c4b-0f8c-41d1-821e-9f850cf3ce8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099488648 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4099488648
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2304479786
Short name T8
Test name
Test status
Simulation time 650843409 ps
CPU time 2.92 seconds
Started Jan 24 10:49:17 PM PST 24
Finished Jan 24 10:49:27 PM PST 24
Peak memory 198280 kb
Host smart-148029fe-7420-463d-b9c8-284d35366f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304479786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2304479786
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3274653228
Short name T48
Test name
Test status
Simulation time 160014247 ps
CPU time 0.84 seconds
Started Jan 24 10:49:19 PM PST 24
Finished Jan 24 10:49:27 PM PST 24
Peak memory 198128 kb
Host smart-50e93e50-7a19-4a68-b5bc-d2b3c6da06f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274653228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3274653228
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1546247925
Short name T129
Test name
Test status
Simulation time 13972975 ps
CPU time 0.73 seconds
Started Jan 24 10:49:30 PM PST 24
Finished Jan 24 10:49:37 PM PST 24
Peak memory 197452 kb
Host smart-73458e42-bf11-409c-be82-135f3782ed3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546247925 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1546247925
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1830265811
Short name T944
Test name
Test status
Simulation time 37295949 ps
CPU time 0.58 seconds
Started Jan 24 10:49:32 PM PST 24
Finished Jan 24 10:49:38 PM PST 24
Peak memory 193560 kb
Host smart-e6d50956-abf8-4899-9cd7-f75d475774b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830265811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1830265811
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.562387201
Short name T110
Test name
Test status
Simulation time 30262337 ps
CPU time 0.63 seconds
Started Jan 24 10:49:33 PM PST 24
Finished Jan 24 10:49:40 PM PST 24
Peak memory 194696 kb
Host smart-816ad701-810f-4911-ba7f-53f412e23e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562387201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.562387201
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2135069563
Short name T116
Test name
Test status
Simulation time 175092277 ps
CPU time 0.62 seconds
Started Jan 24 10:49:32 PM PST 24
Finished Jan 24 10:49:39 PM PST 24
Peak memory 194744 kb
Host smart-da55a9d7-c10a-4bc5-aff5-052e7794f446
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135069563 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2135069563
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.76599860
Short name T914
Test name
Test status
Simulation time 52825819 ps
CPU time 1.13 seconds
Started Jan 24 10:49:36 PM PST 24
Finished Jan 24 10:49:40 PM PST 24
Peak memory 198116 kb
Host smart-f4c04293-559a-41c1-8e31-580018c0d203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76599860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.76599860
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1841232698
Short name T917
Test name
Test status
Simulation time 46832205 ps
CPU time 0.86 seconds
Started Jan 24 10:49:31 PM PST 24
Finished Jan 24 10:49:38 PM PST 24
Peak memory 197516 kb
Host smart-c3fa5f10-6a5f-4fa5-8ce0-fb1091e18382
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841232698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1841232698
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3409674116
Short name T913
Test name
Test status
Simulation time 25222539 ps
CPU time 0.82 seconds
Started Jan 24 10:49:32 PM PST 24
Finished Jan 24 10:49:40 PM PST 24
Peak memory 198176 kb
Host smart-38cb1f9a-52f2-4eee-886d-232e0c963fa6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409674116 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3409674116
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.532764691
Short name T900
Test name
Test status
Simulation time 33594353 ps
CPU time 0.57 seconds
Started Jan 24 10:49:32 PM PST 24
Finished Jan 24 10:49:38 PM PST 24
Peak memory 194888 kb
Host smart-719dc416-a060-45f3-a00c-cc213a336e25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532764691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.532764691
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1689345272
Short name T111
Test name
Test status
Simulation time 12818851 ps
CPU time 0.61 seconds
Started Jan 24 10:49:56 PM PST 24
Finished Jan 24 10:49:57 PM PST 24
Peak memory 193880 kb
Host smart-127686fc-4b4a-4fd1-9c99-8f48e3e9fd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689345272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1689345272
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3679394149
Short name T10
Test name
Test status
Simulation time 54128559 ps
CPU time 0.75 seconds
Started Jan 24 10:49:30 PM PST 24
Finished Jan 24 10:49:37 PM PST 24
Peak memory 195120 kb
Host smart-38c45584-4700-408e-afe1-aa9686d6b8b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679394149 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3679394149
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1701035862
Short name T906
Test name
Test status
Simulation time 616047245 ps
CPU time 2.17 seconds
Started Jan 24 10:49:46 PM PST 24
Finished Jan 24 10:49:49 PM PST 24
Peak memory 198256 kb
Host smart-6065f43d-bad9-4f8f-87ad-75d6491ccd5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701035862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1701035862
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.531293478
Short name T947
Test name
Test status
Simulation time 115678932 ps
CPU time 1.44 seconds
Started Jan 24 10:49:33 PM PST 24
Finished Jan 24 10:49:40 PM PST 24
Peak memory 198336 kb
Host smart-fc1e7ef3-63f7-4f12-9a58-2535c6da54cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531293478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.531293478
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.113730735
Short name T31
Test name
Test status
Simulation time 49492674 ps
CPU time 0.91 seconds
Started Jan 24 10:49:47 PM PST 24
Finished Jan 24 10:49:49 PM PST 24
Peak memory 198160 kb
Host smart-11f1a9b0-ae72-4a06-a793-e03e81bed228
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113730735 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.113730735
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.592435668
Short name T20
Test name
Test status
Simulation time 14072063 ps
CPU time 0.6 seconds
Started Jan 24 10:49:56 PM PST 24
Finished Jan 24 10:49:57 PM PST 24
Peak memory 194212 kb
Host smart-dc4419fb-b08a-41cf-9c7b-2621d5927616
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592435668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.592435668
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3452205407
Short name T102
Test name
Test status
Simulation time 30382926 ps
CPU time 0.65 seconds
Started Jan 25 01:33:32 AM PST 24
Finished Jan 25 01:33:34 AM PST 24
Peak memory 193940 kb
Host smart-d42fadbc-ff08-4957-a355-8ac5bb7b8f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452205407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3452205407
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2357760431
Short name T82
Test name
Test status
Simulation time 725911943 ps
CPU time 3.16 seconds
Started Jan 24 10:49:56 PM PST 24
Finished Jan 24 10:50:00 PM PST 24
Peak memory 198280 kb
Host smart-0f1f23f4-093a-4bd5-b441-b298131a2551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357760431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2357760431
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1047532963
Short name T6
Test name
Test status
Simulation time 925640757 ps
CPU time 1.39 seconds
Started Jan 24 10:49:56 PM PST 24
Finished Jan 24 10:49:58 PM PST 24
Peak memory 198292 kb
Host smart-5e9ded38-8adc-4195-b7bc-48b76cf608c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047532963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1047532963
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.115515985
Short name T33
Test name
Test status
Simulation time 99975880 ps
CPU time 0.91 seconds
Started Jan 24 10:49:53 PM PST 24
Finished Jan 24 10:49:55 PM PST 24
Peak memory 198200 kb
Host smart-8e20c564-da86-47b2-95af-298e1e5395af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115515985 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.115515985
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.277839487
Short name T939
Test name
Test status
Simulation time 40883141 ps
CPU time 0.63 seconds
Started Jan 24 10:49:50 PM PST 24
Finished Jan 24 10:49:51 PM PST 24
Peak memory 195884 kb
Host smart-89b42591-caac-4aff-943b-dd8f1851873b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277839487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.277839487
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.980739738
Short name T885
Test name
Test status
Simulation time 11742695 ps
CPU time 0.6 seconds
Started Jan 24 10:49:53 PM PST 24
Finished Jan 24 10:49:55 PM PST 24
Peak memory 194244 kb
Host smart-f3f5c4fd-fbf4-4fe4-85a8-b5b607c48c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980739738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.980739738
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3935225280
Short name T961
Test name
Test status
Simulation time 57909597 ps
CPU time 0.85 seconds
Started Jan 24 10:49:51 PM PST 24
Finished Jan 24 10:49:53 PM PST 24
Peak memory 196412 kb
Host smart-4cd2518f-38f2-4c83-9009-a3b00688ba71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935225280 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3935225280
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1042508401
Short name T9
Test name
Test status
Simulation time 111942820 ps
CPU time 2.32 seconds
Started Jan 25 02:25:26 AM PST 24
Finished Jan 25 02:25:34 AM PST 24
Peak memory 198348 kb
Host smart-108365ba-34fa-4486-8aa2-536683499651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042508401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1042508401
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2150390273
Short name T892
Test name
Test status
Simulation time 149795929 ps
CPU time 0.99 seconds
Started Jan 24 11:04:34 PM PST 24
Finished Jan 24 11:04:37 PM PST 24
Peak memory 198184 kb
Host smart-b17c7506-7a07-4f29-a9a7-1e1ec6b7fed2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150390273 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2150390273
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.744418063
Short name T2
Test name
Test status
Simulation time 21533468 ps
CPU time 0.57 seconds
Started Jan 24 11:39:43 PM PST 24
Finished Jan 24 11:39:44 PM PST 24
Peak memory 193584 kb
Host smart-b4ff1607-24d4-4e4b-ae2f-ff2d789439e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744418063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.744418063
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1600380058
Short name T30
Test name
Test status
Simulation time 12088620 ps
CPU time 0.6 seconds
Started Jan 24 10:49:50 PM PST 24
Finished Jan 24 10:49:52 PM PST 24
Peak memory 193912 kb
Host smart-6630369c-cbae-48cf-99cd-b1dcac51f061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600380058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1600380058
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.516095122
Short name T959
Test name
Test status
Simulation time 47313519 ps
CPU time 0.6 seconds
Started Jan 24 10:49:47 PM PST 24
Finished Jan 24 10:49:49 PM PST 24
Peak memory 194328 kb
Host smart-11ea3ada-e880-47ef-8fc0-972fef721848
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516095122 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.516095122
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2859236332
Short name T897
Test name
Test status
Simulation time 465779786 ps
CPU time 2.12 seconds
Started Jan 24 10:49:53 PM PST 24
Finished Jan 24 10:49:56 PM PST 24
Peak memory 197912 kb
Host smart-10f2c306-c9af-4c96-b4e8-3ec6b1118d42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859236332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2859236332
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3095892625
Short name T907
Test name
Test status
Simulation time 1690177743 ps
CPU time 1.38 seconds
Started Jan 25 12:43:30 AM PST 24
Finished Jan 25 12:43:32 AM PST 24
Peak memory 198340 kb
Host smart-5dbc3d28-4036-4fa2-a882-6903230314e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095892625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3095892625
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3255739966
Short name T100
Test name
Test status
Simulation time 120810428 ps
CPU time 0.98 seconds
Started Jan 24 10:49:59 PM PST 24
Finished Jan 24 10:50:02 PM PST 24
Peak memory 198184 kb
Host smart-88a158db-7f30-4ba5-bbba-05598677647f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255739966 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3255739966
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.292104445
Short name T921
Test name
Test status
Simulation time 12296339 ps
CPU time 0.65 seconds
Started Jan 25 01:07:47 AM PST 24
Finished Jan 25 01:07:49 AM PST 24
Peak memory 195220 kb
Host smart-e9dca973-9d88-4497-ae9b-d43efa712a06
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292104445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.292104445
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1313839710
Short name T942
Test name
Test status
Simulation time 46466581 ps
CPU time 0.63 seconds
Started Jan 24 10:50:02 PM PST 24
Finished Jan 24 10:50:04 PM PST 24
Peak memory 194652 kb
Host smart-b59caafd-482d-4046-a580-8ac6add228ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313839710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1313839710
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1983242431
Short name T17
Test name
Test status
Simulation time 16640132 ps
CPU time 0.69 seconds
Started Jan 24 10:50:00 PM PST 24
Finished Jan 24 10:50:03 PM PST 24
Peak memory 195276 kb
Host smart-ecbb37b8-3286-4171-aa85-e23872ddd98e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983242431 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1983242431
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1728787178
Short name T903
Test name
Test status
Simulation time 164839577 ps
CPU time 2.89 seconds
Started Jan 24 11:55:18 PM PST 24
Finished Jan 24 11:55:22 PM PST 24
Peak memory 198332 kb
Host smart-b5868fbb-55c2-49fa-ade3-bdfcf7bb182c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728787178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1728787178
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2745733274
Short name T916
Test name
Test status
Simulation time 330838740 ps
CPU time 1.12 seconds
Started Jan 24 10:50:00 PM PST 24
Finished Jan 24 10:50:02 PM PST 24
Peak memory 198360 kb
Host smart-8650c84b-37e3-417c-b226-fe5fd4e76812
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745733274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2745733274
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2606837657
Short name T898
Test name
Test status
Simulation time 22125732 ps
CPU time 0.81 seconds
Started Jan 24 10:50:25 PM PST 24
Finished Jan 24 10:50:27 PM PST 24
Peak memory 198132 kb
Host smart-f64c06a4-f7d9-46a0-8cfe-deee3f2695fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606837657 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2606837657
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1000488684
Short name T920
Test name
Test status
Simulation time 26687206 ps
CPU time 0.65 seconds
Started Jan 24 10:50:26 PM PST 24
Finished Jan 24 10:50:28 PM PST 24
Peak memory 193768 kb
Host smart-8371cba6-c7d3-46de-b233-df7f07a4bdfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000488684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1000488684
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3140195263
Short name T101
Test name
Test status
Simulation time 19990633 ps
CPU time 0.65 seconds
Started Jan 24 10:50:29 PM PST 24
Finished Jan 24 10:50:31 PM PST 24
Peak memory 195068 kb
Host smart-36cc9073-7f6d-479f-954c-f564c229b238
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140195263 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3140195263
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3377974315
Short name T935
Test name
Test status
Simulation time 112873569 ps
CPU time 2.09 seconds
Started Jan 24 10:50:29 PM PST 24
Finished Jan 24 10:50:33 PM PST 24
Peak memory 198244 kb
Host smart-5319b200-0c9b-4a79-a4be-098ffe98e0c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377974315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3377974315
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3901087888
Short name T922
Test name
Test status
Simulation time 172857259 ps
CPU time 0.86 seconds
Started Jan 24 10:50:32 PM PST 24
Finished Jan 24 10:50:33 PM PST 24
Peak memory 197484 kb
Host smart-15ca6678-88be-4478-adb0-7d7ab4fb5beb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901087888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3901087888
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2267919488
Short name T126
Test name
Test status
Simulation time 78230947 ps
CPU time 1.13 seconds
Started Jan 24 10:50:24 PM PST 24
Finished Jan 24 10:50:27 PM PST 24
Peak memory 198152 kb
Host smart-3db91d16-75ab-4d45-90f8-5e796056392a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267919488 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2267919488
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3388695889
Short name T901
Test name
Test status
Simulation time 47000204 ps
CPU time 0.62 seconds
Started Jan 24 10:50:28 PM PST 24
Finished Jan 24 10:50:30 PM PST 24
Peak memory 195692 kb
Host smart-fd3330c6-b23f-4ba7-b85f-e8b8b13e961b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388695889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3388695889
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.641487590
Short name T933
Test name
Test status
Simulation time 35695153 ps
CPU time 0.62 seconds
Started Jan 24 10:50:24 PM PST 24
Finished Jan 24 10:50:26 PM PST 24
Peak memory 193976 kb
Host smart-4c1e91da-3faf-4d6e-9ed0-12fff0b4c86e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641487590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.641487590
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1635452895
Short name T927
Test name
Test status
Simulation time 17520633 ps
CPU time 0.74 seconds
Started Jan 24 10:50:24 PM PST 24
Finished Jan 24 10:50:26 PM PST 24
Peak memory 196232 kb
Host smart-b639e0ee-0986-4fbd-b40a-da3e742518f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635452895 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1635452895
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2820971268
Short name T908
Test name
Test status
Simulation time 180905102 ps
CPU time 2.33 seconds
Started Jan 24 10:50:26 PM PST 24
Finished Jan 24 10:50:30 PM PST 24
Peak memory 198064 kb
Host smart-e510100a-6354-4680-ab40-6bd5e20fe1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820971268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2820971268
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.408064414
Short name T5
Test name
Test status
Simulation time 678290445 ps
CPU time 0.82 seconds
Started Jan 24 10:50:25 PM PST 24
Finished Jan 24 10:50:27 PM PST 24
Peak memory 197144 kb
Host smart-42f27aff-cfce-4858-810e-0b69c130f094
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408064414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.408064414
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1643481890
Short name T35
Test name
Test status
Simulation time 98861809 ps
CPU time 0.92 seconds
Started Jan 24 10:50:39 PM PST 24
Finished Jan 24 10:50:42 PM PST 24
Peak memory 198184 kb
Host smart-c75d1dab-cdc3-4e07-ab3a-34be5428032c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643481890 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1643481890
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3691001905
Short name T95
Test name
Test status
Simulation time 35920301 ps
CPU time 0.58 seconds
Started Jan 24 10:50:38 PM PST 24
Finished Jan 24 10:50:40 PM PST 24
Peak memory 193520 kb
Host smart-05511c69-4188-4289-b07c-b91117c536f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691001905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3691001905
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1326875255
Short name T12
Test name
Test status
Simulation time 55216383 ps
CPU time 0.58 seconds
Started Jan 24 10:50:39 PM PST 24
Finished Jan 24 10:50:43 PM PST 24
Peak memory 193936 kb
Host smart-431a3839-0a57-4419-9927-09c55d861c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326875255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1326875255
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1641942496
Short name T896
Test name
Test status
Simulation time 34422662 ps
CPU time 0.84 seconds
Started Jan 24 10:50:40 PM PST 24
Finished Jan 24 10:50:44 PM PST 24
Peak memory 196264 kb
Host smart-fded7b72-bd1c-4a4b-b34a-63d3893b93c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641942496 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1641942496
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3402901997
Short name T950
Test name
Test status
Simulation time 50008790 ps
CPU time 2.57 seconds
Started Jan 24 10:50:37 PM PST 24
Finished Jan 24 10:50:42 PM PST 24
Peak memory 198296 kb
Host smart-040b3677-2190-4e67-938a-f67231809578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402901997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3402901997
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.559974296
Short name T952
Test name
Test status
Simulation time 841786925 ps
CPU time 1.08 seconds
Started Jan 24 10:50:38 PM PST 24
Finished Jan 24 10:50:41 PM PST 24
Peak memory 197152 kb
Host smart-b4e3ef05-ab45-4c16-b4c2-ffe9021c7e64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559974296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.559974296
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1802213677
Short name T941
Test name
Test status
Simulation time 32179500 ps
CPU time 0.7 seconds
Started Jan 24 10:48:06 PM PST 24
Finished Jan 24 10:48:07 PM PST 24
Peak memory 195008 kb
Host smart-d913f1eb-26bb-4e2c-8b28-285fa437cb58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802213677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1802213677
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2020302795
Short name T936
Test name
Test status
Simulation time 1038785411 ps
CPU time 2.47 seconds
Started Jan 24 10:48:21 PM PST 24
Finished Jan 24 10:48:24 PM PST 24
Peak memory 198276 kb
Host smart-a18bca31-32ed-41e2-b700-e916618418f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020302795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2020302795
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.783143638
Short name T107
Test name
Test status
Simulation time 23345757 ps
CPU time 0.72 seconds
Started Jan 24 10:48:26 PM PST 24
Finished Jan 24 10:48:27 PM PST 24
Peak memory 195684 kb
Host smart-6a009844-2f40-461a-8c5a-8d235b3a672b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783143638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.783143638
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.26031885
Short name T945
Test name
Test status
Simulation time 95714066 ps
CPU time 1.08 seconds
Started Jan 24 10:48:08 PM PST 24
Finished Jan 24 10:48:10 PM PST 24
Peak memory 198140 kb
Host smart-f1ebc653-8f5e-4e20-be52-1712eeacc150
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26031885 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.26031885
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2233195521
Short name T105
Test name
Test status
Simulation time 14595064 ps
CPU time 0.61 seconds
Started Jan 24 10:47:45 PM PST 24
Finished Jan 24 10:47:46 PM PST 24
Peak memory 193756 kb
Host smart-03b0158e-138c-4bd5-9dfc-212fec70e577
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233195521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2233195521
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3949647379
Short name T928
Test name
Test status
Simulation time 11261605 ps
CPU time 0.59 seconds
Started Jan 24 10:48:21 PM PST 24
Finished Jan 24 10:48:23 PM PST 24
Peak memory 193940 kb
Host smart-9ee18b8d-27dd-489a-a140-91b750354eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949647379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3949647379
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2656622525
Short name T915
Test name
Test status
Simulation time 939630491 ps
CPU time 2.25 seconds
Started Jan 24 10:48:09 PM PST 24
Finished Jan 24 10:48:13 PM PST 24
Peak memory 198276 kb
Host smart-fbd2369c-57bf-41c0-acbc-bea24c97d209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656622525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2656622525
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2470642814
Short name T46
Test name
Test status
Simulation time 96828150 ps
CPU time 1.17 seconds
Started Jan 24 10:48:06 PM PST 24
Finished Jan 24 10:48:08 PM PST 24
Peak memory 198284 kb
Host smart-c2573352-26fa-4bb3-b0a4-fdaf0fcf4dea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470642814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2470642814
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.638341228
Short name T21
Test name
Test status
Simulation time 14544392 ps
CPU time 0.63 seconds
Started Jan 24 11:05:31 PM PST 24
Finished Jan 24 11:05:32 PM PST 24
Peak memory 193936 kb
Host smart-e3b157d1-fdfd-4d32-9d1f-7a74ec41a25f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638341228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.638341228
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2885624953
Short name T946
Test name
Test status
Simulation time 46606889 ps
CPU time 0.6 seconds
Started Jan 24 10:50:38 PM PST 24
Finished Jan 24 10:50:41 PM PST 24
Peak memory 193936 kb
Host smart-c6b922f9-b0d5-4669-b499-dd956c8876f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885624953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2885624953
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1726432749
Short name T106
Test name
Test status
Simulation time 19421099 ps
CPU time 0.61 seconds
Started Jan 24 10:50:39 PM PST 24
Finished Jan 24 10:50:41 PM PST 24
Peak memory 194660 kb
Host smart-41bf68e4-f1de-42a8-bd65-67f464d1b7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726432749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1726432749
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.4223568642
Short name T128
Test name
Test status
Simulation time 33090180 ps
CPU time 0.6 seconds
Started Jan 24 10:50:38 PM PST 24
Finished Jan 24 10:50:41 PM PST 24
Peak memory 193928 kb
Host smart-21b581d6-d152-4a2e-90b8-6e1689bd92ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223568642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.4223568642
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1590801640
Short name T912
Test name
Test status
Simulation time 49582283 ps
CPU time 0.58 seconds
Started Jan 24 10:50:39 PM PST 24
Finished Jan 24 10:50:42 PM PST 24
Peak memory 193976 kb
Host smart-256e4e1e-d1e1-4fb9-82eb-9b8c389ec9a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590801640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1590801640
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1204457636
Short name T109
Test name
Test status
Simulation time 22109688 ps
CPU time 0.58 seconds
Started Jan 24 10:50:40 PM PST 24
Finished Jan 24 10:50:43 PM PST 24
Peak memory 194540 kb
Host smart-d66be36e-aeb3-4757-84a6-d42b33103f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204457636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1204457636
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3706596162
Short name T902
Test name
Test status
Simulation time 12408749 ps
CPU time 0.63 seconds
Started Jan 24 10:50:36 PM PST 24
Finished Jan 24 10:50:38 PM PST 24
Peak memory 193972 kb
Host smart-677298a1-61ee-41c0-97b4-2d55b6f732be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706596162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3706596162
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2854085907
Short name T890
Test name
Test status
Simulation time 16783093 ps
CPU time 0.62 seconds
Started Jan 24 10:50:38 PM PST 24
Finished Jan 24 10:50:40 PM PST 24
Peak memory 193996 kb
Host smart-7657961c-f2c6-499d-9a6a-212d42358882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854085907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2854085907
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.142630369
Short name T22
Test name
Test status
Simulation time 14249710 ps
CPU time 0.62 seconds
Started Jan 24 10:50:54 PM PST 24
Finished Jan 24 10:50:57 PM PST 24
Peak memory 193940 kb
Host smart-1d6ac82d-e5c3-4d4e-876a-956b6801cfdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142630369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.142630369
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1298887167
Short name T926
Test name
Test status
Simulation time 17372061 ps
CPU time 0.63 seconds
Started Jan 24 10:50:51 PM PST 24
Finished Jan 24 10:50:53 PM PST 24
Peak memory 193968 kb
Host smart-b3e1bd96-d709-4830-be22-c72d3f9e9f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298887167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1298887167
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.550238646
Short name T119
Test name
Test status
Simulation time 93679817 ps
CPU time 0.78 seconds
Started Jan 24 10:48:23 PM PST 24
Finished Jan 24 10:48:25 PM PST 24
Peak memory 196828 kb
Host smart-2454ff00-8df0-4e6c-8830-c2a85a92d78f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550238646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.550238646
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3525138025
Short name T887
Test name
Test status
Simulation time 82076120 ps
CPU time 2.99 seconds
Started Jan 24 10:48:33 PM PST 24
Finished Jan 24 10:48:37 PM PST 24
Peak memory 197472 kb
Host smart-75666d02-e59c-4a80-95e8-386fac9ab6ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525138025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3525138025
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.133310108
Short name T919
Test name
Test status
Simulation time 29323512 ps
CPU time 0.63 seconds
Started Jan 24 10:48:19 PM PST 24
Finished Jan 24 10:48:21 PM PST 24
Peak memory 195020 kb
Host smart-74b00dfc-f7bf-4bcb-9e84-624dcc9ef0be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133310108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.133310108
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2730400983
Short name T4
Test name
Test status
Simulation time 32078938 ps
CPU time 0.76 seconds
Started Jan 24 10:48:22 PM PST 24
Finished Jan 24 10:48:23 PM PST 24
Peak memory 197852 kb
Host smart-aabd0870-0c86-4953-a11f-38bbfecfc051
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730400983 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2730400983
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4005970425
Short name T955
Test name
Test status
Simulation time 41669755 ps
CPU time 0.58 seconds
Started Jan 24 10:48:22 PM PST 24
Finished Jan 24 10:48:24 PM PST 24
Peak memory 194804 kb
Host smart-aec00f1a-1c88-43bf-ba4c-236df4e4e9f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005970425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4005970425
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.498279934
Short name T932
Test name
Test status
Simulation time 91571285 ps
CPU time 0.59 seconds
Started Jan 24 10:48:21 PM PST 24
Finished Jan 24 10:48:23 PM PST 24
Peak memory 194000 kb
Host smart-bb4f4bb8-efe4-4ec6-8745-4c25ca04278e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498279934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.498279934
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.4220144833
Short name T117
Test name
Test status
Simulation time 14957439 ps
CPU time 0.67 seconds
Started Jan 24 10:48:20 PM PST 24
Finished Jan 24 10:48:21 PM PST 24
Peak memory 195636 kb
Host smart-a4da1b1a-db0d-46ff-b390-8205aacc11f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220144833 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.4220144833
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2250818999
Short name T911
Test name
Test status
Simulation time 100972982 ps
CPU time 2.12 seconds
Started Jan 24 10:48:23 PM PST 24
Finished Jan 24 10:48:26 PM PST 24
Peak memory 198248 kb
Host smart-de07e4fe-d613-4010-b082-908f76b837f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250818999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2250818999
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.360714069
Short name T49
Test name
Test status
Simulation time 138088596 ps
CPU time 1.13 seconds
Started Jan 24 10:48:20 PM PST 24
Finished Jan 24 10:48:21 PM PST 24
Peak memory 198268 kb
Host smart-a4cd6fcb-b9de-4b84-94df-b2b0be3b1276
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360714069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.360714069
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.424166374
Short name T905
Test name
Test status
Simulation time 38774728 ps
CPU time 0.61 seconds
Started Jan 24 10:50:50 PM PST 24
Finished Jan 24 10:50:52 PM PST 24
Peak memory 194716 kb
Host smart-e9c7c6df-cded-4cbe-a937-99ff93b07e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424166374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.424166374
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.806203711
Short name T25
Test name
Test status
Simulation time 15028768 ps
CPU time 0.61 seconds
Started Jan 24 10:50:55 PM PST 24
Finished Jan 24 10:50:58 PM PST 24
Peak memory 193952 kb
Host smart-c4549cde-c3fa-4d7a-9522-cca2eceda5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806203711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.806203711
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2553828390
Short name T924
Test name
Test status
Simulation time 89184387 ps
CPU time 0.6 seconds
Started Jan 24 10:50:55 PM PST 24
Finished Jan 24 10:50:58 PM PST 24
Peak memory 193696 kb
Host smart-78c71fdc-6d8b-4778-a2ee-1e85e102feaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553828390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2553828390
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1199771596
Short name T938
Test name
Test status
Simulation time 49207192 ps
CPU time 0.59 seconds
Started Jan 24 10:50:54 PM PST 24
Finished Jan 24 10:50:56 PM PST 24
Peak memory 193956 kb
Host smart-8ad177bb-83b4-4cff-a7dc-733ad37013e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199771596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1199771596
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3329623070
Short name T133
Test name
Test status
Simulation time 28281787 ps
CPU time 0.63 seconds
Started Jan 24 10:51:02 PM PST 24
Finished Jan 24 10:51:04 PM PST 24
Peak memory 194576 kb
Host smart-6449669e-b3e5-4a23-b123-c821e2624921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329623070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3329623070
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3353185881
Short name T891
Test name
Test status
Simulation time 10810217 ps
CPU time 0.61 seconds
Started Jan 25 02:10:34 AM PST 24
Finished Jan 25 02:10:38 AM PST 24
Peak memory 193944 kb
Host smart-223f6e00-1a03-4de7-bbcd-d7ae15bbb845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353185881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3353185881
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.365205719
Short name T886
Test name
Test status
Simulation time 26293701 ps
CPU time 0.64 seconds
Started Jan 24 10:50:54 PM PST 24
Finished Jan 24 10:50:57 PM PST 24
Peak memory 194632 kb
Host smart-06f666f6-6ca2-4d81-8f17-f37355b86b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365205719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.365205719
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.314487794
Short name T130
Test name
Test status
Simulation time 85735796 ps
CPU time 0.64 seconds
Started Jan 24 10:50:54 PM PST 24
Finished Jan 24 10:50:57 PM PST 24
Peak memory 194640 kb
Host smart-4d75635d-d819-4c32-9e0e-dd91f6b02c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314487794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.314487794
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2897022859
Short name T19
Test name
Test status
Simulation time 188917460 ps
CPU time 0.65 seconds
Started Jan 24 10:48:29 PM PST 24
Finished Jan 24 10:48:31 PM PST 24
Peak memory 195000 kb
Host smart-48fd83d9-8b29-4e75-a1c5-a6ced48599e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897022859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2897022859
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2150748001
Short name T904
Test name
Test status
Simulation time 176825000 ps
CPU time 2.34 seconds
Started Jan 24 10:48:49 PM PST 24
Finished Jan 24 10:48:52 PM PST 24
Peak memory 197380 kb
Host smart-430bcfbd-3e82-4fc8-83c8-8a96e4ff65a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150748001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2150748001
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1885926905
Short name T97
Test name
Test status
Simulation time 12210472 ps
CPU time 0.64 seconds
Started Jan 24 10:48:31 PM PST 24
Finished Jan 24 10:48:32 PM PST 24
Peak memory 194928 kb
Host smart-2b545ec8-8a88-4e58-9c7d-c7fd87863a3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885926905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1885926905
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3254681262
Short name T883
Test name
Test status
Simulation time 87138889 ps
CPU time 1.34 seconds
Started Jan 24 10:48:30 PM PST 24
Finished Jan 24 10:48:32 PM PST 24
Peak memory 198348 kb
Host smart-0dee9525-e399-4bd6-8a8a-865cb5150daa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254681262 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3254681262
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2865119623
Short name T94
Test name
Test status
Simulation time 12740005 ps
CPU time 0.59 seconds
Started Jan 24 10:48:32 PM PST 24
Finished Jan 24 10:48:33 PM PST 24
Peak memory 194880 kb
Host smart-b4657621-f634-47e7-8161-3582b05e61e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865119623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2865119623
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2778183031
Short name T27
Test name
Test status
Simulation time 14161059 ps
CPU time 0.59 seconds
Started Jan 24 10:48:31 PM PST 24
Finished Jan 24 10:48:33 PM PST 24
Peak memory 193892 kb
Host smart-38c4d61c-d0c1-493d-8d60-401fb91da6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778183031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2778183031
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.893729983
Short name T88
Test name
Test status
Simulation time 69065383 ps
CPU time 0.89 seconds
Started Jan 24 10:48:33 PM PST 24
Finished Jan 24 10:48:34 PM PST 24
Peak memory 197624 kb
Host smart-f9760388-63e2-4f8d-bf25-f010b2a80403
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893729983 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.893729983
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1641290073
Short name T39
Test name
Test status
Simulation time 429752573 ps
CPU time 1.37 seconds
Started Jan 24 10:48:33 PM PST 24
Finished Jan 24 10:48:35 PM PST 24
Peak memory 198292 kb
Host smart-33e27973-2f09-410c-b53f-ea6f542dd870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641290073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1641290073
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1699377551
Short name T954
Test name
Test status
Simulation time 293384069 ps
CPU time 1.19 seconds
Started Jan 24 10:48:32 PM PST 24
Finished Jan 24 10:48:34 PM PST 24
Peak memory 198348 kb
Host smart-a12578b4-650f-4271-8c82-0cb1153c0a06
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699377551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1699377551
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3619926138
Short name T943
Test name
Test status
Simulation time 47184629 ps
CPU time 0.66 seconds
Started Jan 24 10:50:55 PM PST 24
Finished Jan 24 10:50:58 PM PST 24
Peak memory 194504 kb
Host smart-9ecce32b-db75-45f4-9cdb-d911f0955985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619926138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3619926138
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2697749779
Short name T131
Test name
Test status
Simulation time 40671450 ps
CPU time 0.63 seconds
Started Jan 24 11:59:49 PM PST 24
Finished Jan 24 11:59:52 PM PST 24
Peak memory 194012 kb
Host smart-c591d31e-0ee6-4387-a106-988fd52c7eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697749779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2697749779
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2971023458
Short name T89
Test name
Test status
Simulation time 44372936 ps
CPU time 0.6 seconds
Started Jan 24 10:50:55 PM PST 24
Finished Jan 24 10:50:58 PM PST 24
Peak memory 193872 kb
Host smart-b3e2e8b9-0d08-44de-ab60-274c7d0f9134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971023458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2971023458
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3393350978
Short name T83
Test name
Test status
Simulation time 37734815 ps
CPU time 0.58 seconds
Started Jan 24 10:50:50 PM PST 24
Finished Jan 24 10:50:52 PM PST 24
Peak memory 193908 kb
Host smart-784926b3-ab4d-43fd-8a51-3dedc49d5093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393350978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3393350978
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3567433162
Short name T960
Test name
Test status
Simulation time 18008346 ps
CPU time 0.62 seconds
Started Jan 25 02:08:51 AM PST 24
Finished Jan 25 02:08:53 AM PST 24
Peak memory 194012 kb
Host smart-6fd0c679-1ea2-4ca7-8a42-86fa3eaad202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567433162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3567433162
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3969219038
Short name T931
Test name
Test status
Simulation time 97867879 ps
CPU time 0.68 seconds
Started Jan 25 02:21:56 AM PST 24
Finished Jan 25 02:22:03 AM PST 24
Peak memory 194064 kb
Host smart-44aa2548-7890-471b-8279-9f8ccc07f4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969219038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3969219038
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3720314740
Short name T103
Test name
Test status
Simulation time 35308074 ps
CPU time 0.66 seconds
Started Jan 25 12:05:20 AM PST 24
Finished Jan 25 12:05:23 AM PST 24
Peak memory 194580 kb
Host smart-92bddf64-be0c-4edf-8e92-34bea29474e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720314740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3720314740
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3996412132
Short name T28
Test name
Test status
Simulation time 22370949 ps
CPU time 0.62 seconds
Started Jan 24 10:51:03 PM PST 24
Finished Jan 24 10:51:05 PM PST 24
Peak memory 193964 kb
Host smart-1ad7f967-537a-42d2-b202-87500d1fc43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996412132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3996412132
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2390234493
Short name T23
Test name
Test status
Simulation time 64885692 ps
CPU time 0.63 seconds
Started Jan 24 10:51:13 PM PST 24
Finished Jan 24 10:51:15 PM PST 24
Peak memory 194004 kb
Host smart-62fcb68a-cd93-4f7d-87bb-5c8eeea4704a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390234493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2390234493
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3685805849
Short name T889
Test name
Test status
Simulation time 60105658 ps
CPU time 0.59 seconds
Started Jan 24 10:51:12 PM PST 24
Finished Jan 24 10:51:13 PM PST 24
Peak memory 193904 kb
Host smart-8c0abca8-4d8d-4312-bc57-96b6af8ddc1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685805849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3685805849
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3711273499
Short name T918
Test name
Test status
Simulation time 40678932 ps
CPU time 1.27 seconds
Started Jan 24 10:48:47 PM PST 24
Finished Jan 24 10:48:49 PM PST 24
Peak memory 198284 kb
Host smart-48e9bace-1f6d-40bc-9bdd-5a6f6dd8967b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711273499 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3711273499
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1093251953
Short name T949
Test name
Test status
Simulation time 44115236 ps
CPU time 0.6 seconds
Started Jan 24 10:48:47 PM PST 24
Finished Jan 24 10:48:48 PM PST 24
Peak memory 193556 kb
Host smart-c054e6a7-5e8e-4e75-9be1-0342afc04d33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093251953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1093251953
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2763484123
Short name T132
Test name
Test status
Simulation time 19120760 ps
CPU time 0.67 seconds
Started Jan 24 10:48:46 PM PST 24
Finished Jan 24 10:48:48 PM PST 24
Peak memory 193984 kb
Host smart-4f10a5cd-f260-43e6-ac82-391505226ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763484123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2763484123
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1125939372
Short name T940
Test name
Test status
Simulation time 18371745 ps
CPU time 0.79 seconds
Started Jan 24 10:48:49 PM PST 24
Finished Jan 24 10:48:51 PM PST 24
Peak memory 196436 kb
Host smart-ce0b9dc5-e589-431b-84fb-7542870220b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125939372 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1125939372
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4259214587
Short name T11
Test name
Test status
Simulation time 144525112 ps
CPU time 2.11 seconds
Started Jan 25 01:19:51 AM PST 24
Finished Jan 25 01:19:57 AM PST 24
Peak memory 198268 kb
Host smart-572e3ddb-bad0-437d-9c30-a2c0ee7cfe60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259214587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4259214587
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3581794266
Short name T956
Test name
Test status
Simulation time 71594859 ps
CPU time 1.22 seconds
Started Jan 24 11:09:03 PM PST 24
Finished Jan 24 11:09:05 PM PST 24
Peak memory 198336 kb
Host smart-7ccb5821-90ba-484e-97ac-0091df496d48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581794266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3581794266
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.778297288
Short name T923
Test name
Test status
Simulation time 70202435 ps
CPU time 0.83 seconds
Started Jan 24 10:48:46 PM PST 24
Finished Jan 24 10:48:48 PM PST 24
Peak memory 198176 kb
Host smart-7975bb1f-b180-40b0-a279-175e5cd68400
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778297288 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.778297288
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2495651092
Short name T98
Test name
Test status
Simulation time 176053720 ps
CPU time 0.58 seconds
Started Jan 24 10:48:45 PM PST 24
Finished Jan 24 10:48:46 PM PST 24
Peak memory 193876 kb
Host smart-f8382187-dfa9-48af-82b4-84c1b43cb70f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495651092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2495651092
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2646107126
Short name T958
Test name
Test status
Simulation time 32483220 ps
CPU time 0.6 seconds
Started Jan 25 12:06:37 AM PST 24
Finished Jan 25 12:06:39 AM PST 24
Peak memory 193948 kb
Host smart-ae863b6c-87ff-489c-a509-b4eade2bc7aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646107126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2646107126
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.581463299
Short name T957
Test name
Test status
Simulation time 59904011 ps
CPU time 0.82 seconds
Started Jan 25 03:51:17 AM PST 24
Finished Jan 25 03:51:19 AM PST 24
Peak memory 197160 kb
Host smart-3214b340-8485-4db5-9b98-a4b966377657
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581463299 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.581463299
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.239372704
Short name T937
Test name
Test status
Simulation time 170272835 ps
CPU time 1.42 seconds
Started Jan 24 10:48:49 PM PST 24
Finished Jan 24 10:48:51 PM PST 24
Peak memory 198272 kb
Host smart-b58a7d8a-7502-4de1-a89e-e6be8f8c0b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239372704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.239372704
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.261267746
Short name T24
Test name
Test status
Simulation time 44212010 ps
CPU time 0.91 seconds
Started Jan 24 10:48:48 PM PST 24
Finished Jan 24 10:48:50 PM PST 24
Peak memory 197424 kb
Host smart-d1059f1a-5bf4-4733-ba18-a6957abe8f62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261267746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.261267746
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2768724728
Short name T122
Test name
Test status
Simulation time 22619855 ps
CPU time 0.87 seconds
Started Jan 24 10:48:51 PM PST 24
Finished Jan 24 10:48:53 PM PST 24
Peak memory 198176 kb
Host smart-e47330d6-71d4-4777-8aed-6b8939110513
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768724728 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2768724728
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3476206250
Short name T86
Test name
Test status
Simulation time 30358559 ps
CPU time 0.6 seconds
Started Jan 24 11:12:58 PM PST 24
Finished Jan 24 11:12:59 PM PST 24
Peak memory 195416 kb
Host smart-e2f6890f-0c3e-4d1c-977c-91adf663d9dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476206250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3476206250
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3878113813
Short name T888
Test name
Test status
Simulation time 27719159 ps
CPU time 0.66 seconds
Started Jan 24 10:48:56 PM PST 24
Finished Jan 24 10:48:57 PM PST 24
Peak memory 194596 kb
Host smart-cd61dc85-bdc3-4530-9c86-113a35a076d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878113813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3878113813
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.641447262
Short name T909
Test name
Test status
Simulation time 31497271 ps
CPU time 0.82 seconds
Started Jan 24 10:48:50 PM PST 24
Finished Jan 24 10:48:52 PM PST 24
Peak memory 197288 kb
Host smart-725b60e2-6cf1-439b-99fa-e96434bbefa5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641447262 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.641447262
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.260571816
Short name T894
Test name
Test status
Simulation time 255682234 ps
CPU time 2.71 seconds
Started Jan 24 10:48:56 PM PST 24
Finished Jan 24 10:49:00 PM PST 24
Peak memory 198260 kb
Host smart-b66354c8-3809-460e-b2b1-e56f1359f7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260571816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.260571816
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1863254731
Short name T934
Test name
Test status
Simulation time 289714488 ps
CPU time 0.91 seconds
Started Jan 24 10:49:11 PM PST 24
Finished Jan 24 10:49:13 PM PST 24
Peak memory 198204 kb
Host smart-9c17ee30-e421-4138-b499-ffdb0eb75b14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863254731 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1863254731
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2329285234
Short name T16
Test name
Test status
Simulation time 11433397 ps
CPU time 0.6 seconds
Started Jan 24 10:48:58 PM PST 24
Finished Jan 24 10:49:00 PM PST 24
Peak memory 195792 kb
Host smart-4c8d42f9-477d-47bf-85c3-4fc731f627f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329285234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2329285234
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.624420883
Short name T951
Test name
Test status
Simulation time 14644970 ps
CPU time 0.61 seconds
Started Jan 24 10:49:08 PM PST 24
Finished Jan 24 10:49:09 PM PST 24
Peak memory 193944 kb
Host smart-efc9ed43-5f02-4c2c-a44e-4362e2f249bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624420883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.624420883
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2608417132
Short name T930
Test name
Test status
Simulation time 78774183 ps
CPU time 0.93 seconds
Started Jan 24 10:48:59 PM PST 24
Finished Jan 24 10:49:02 PM PST 24
Peak memory 197668 kb
Host smart-89b3fe4a-2359-4eae-99e8-d686ffb78684
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608417132 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2608417132
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3072554859
Short name T899
Test name
Test status
Simulation time 116315904 ps
CPU time 1.76 seconds
Started Jan 24 10:49:08 PM PST 24
Finished Jan 24 10:49:11 PM PST 24
Peak memory 198344 kb
Host smart-fc0158a1-e344-4b4e-b8b3-ca7dd5295004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072554859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3072554859
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.815157057
Short name T47
Test name
Test status
Simulation time 123005259 ps
CPU time 1.49 seconds
Started Jan 24 10:49:11 PM PST 24
Finished Jan 24 10:49:13 PM PST 24
Peak memory 198176 kb
Host smart-52ed1c41-e246-4f3b-b66c-cf2a17b20171
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815157057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.815157057
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2773204737
Short name T925
Test name
Test status
Simulation time 31680180 ps
CPU time 0.93 seconds
Started Jan 24 10:49:18 PM PST 24
Finished Jan 24 10:49:27 PM PST 24
Peak memory 198164 kb
Host smart-b4f47102-ec53-43d9-9ad8-de390d5f2093
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773204737 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2773204737
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1136685731
Short name T32
Test name
Test status
Simulation time 45416110 ps
CPU time 0.6 seconds
Started Jan 24 10:49:20 PM PST 24
Finished Jan 24 10:49:26 PM PST 24
Peak memory 193960 kb
Host smart-6b5d36cd-3c6d-45f6-a090-f647902d5bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136685731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1136685731
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2212906099
Short name T118
Test name
Test status
Simulation time 53637606 ps
CPU time 0.86 seconds
Started Jan 24 10:49:24 PM PST 24
Finished Jan 24 10:49:32 PM PST 24
Peak memory 197100 kb
Host smart-72cec8a1-8418-4990-91eb-e0eafd000be7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212906099 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2212906099
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2768010801
Short name T104
Test name
Test status
Simulation time 576433442 ps
CPU time 2.68 seconds
Started Jan 24 10:49:19 PM PST 24
Finished Jan 24 10:49:28 PM PST 24
Peak memory 198320 kb
Host smart-3439f2ad-4671-4a77-a332-110194e936cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768010801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2768010801
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2104820010
Short name T40
Test name
Test status
Simulation time 424700314 ps
CPU time 1.34 seconds
Started Jan 24 10:49:19 PM PST 24
Finished Jan 24 10:49:27 PM PST 24
Peak memory 198332 kb
Host smart-98271547-67c0-4a2a-a892-67bf39c38f4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104820010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2104820010
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1792577863
Short name T823
Test name
Test status
Simulation time 32666807 ps
CPU time 0.55 seconds
Started Jan 24 01:21:08 PM PST 24
Finished Jan 24 01:22:15 PM PST 24
Peak memory 193980 kb
Host smart-860f8ca4-621c-4c8b-b362-9b5283676fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792577863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1792577863
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3889350766
Short name T430
Test name
Test status
Simulation time 66414104 ps
CPU time 0.66 seconds
Started Jan 24 01:21:08 PM PST 24
Finished Jan 24 01:22:15 PM PST 24
Peak memory 194204 kb
Host smart-8a4ad2d5-46f2-4403-9edb-98313b964d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889350766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3889350766
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2245953932
Short name T583
Test name
Test status
Simulation time 834151654 ps
CPU time 10.4 seconds
Started Jan 24 01:21:12 PM PST 24
Finished Jan 24 01:22:28 PM PST 24
Peak memory 196968 kb
Host smart-03356917-9525-4b32-aede-fca6ccb543a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245953932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2245953932
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.790777387
Short name T506
Test name
Test status
Simulation time 78543568 ps
CPU time 0.81 seconds
Started Jan 24 01:21:14 PM PST 24
Finished Jan 24 01:22:21 PM PST 24
Peak memory 196088 kb
Host smart-810f29d4-34d5-479c-a88e-eb310981569c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790777387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.790777387
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1797429377
Short name T835
Test name
Test status
Simulation time 76897935 ps
CPU time 1.23 seconds
Started Jan 24 01:21:06 PM PST 24
Finished Jan 24 01:22:14 PM PST 24
Peak memory 196100 kb
Host smart-18c10455-b229-4778-b121-04152eba18f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797429377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1797429377
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3245743206
Short name T716
Test name
Test status
Simulation time 186982731 ps
CPU time 2.1 seconds
Started Jan 24 01:21:08 PM PST 24
Finished Jan 24 01:22:17 PM PST 24
Peak memory 198128 kb
Host smart-54ab0c6f-ef64-48db-9a26-4e6e03856a81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245743206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3245743206
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2478857877
Short name T685
Test name
Test status
Simulation time 256285131 ps
CPU time 2.02 seconds
Started Jan 24 01:21:06 PM PST 24
Finished Jan 24 01:22:14 PM PST 24
Peak memory 197172 kb
Host smart-d3447c60-2c23-485f-9a12-b2a011ccd9c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478857877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2478857877
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2302677518
Short name T718
Test name
Test status
Simulation time 149456535 ps
CPU time 0.79 seconds
Started Jan 24 01:21:07 PM PST 24
Finished Jan 24 01:22:15 PM PST 24
Peak memory 196540 kb
Host smart-aa323a4a-5399-43e0-848a-f7ea404fb505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302677518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2302677518
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1275804377
Short name T662
Test name
Test status
Simulation time 40739750 ps
CPU time 0.94 seconds
Started Jan 24 01:21:08 PM PST 24
Finished Jan 24 01:22:16 PM PST 24
Peak memory 196828 kb
Host smart-51d416c8-6bb4-4f63-92e0-39de124e87b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275804377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1275804377
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3632548461
Short name T472
Test name
Test status
Simulation time 65449133 ps
CPU time 1.18 seconds
Started Jan 24 01:21:07 PM PST 24
Finished Jan 24 01:22:15 PM PST 24
Peak memory 198192 kb
Host smart-2c63d95d-4542-4b6e-97e6-94266fb335f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632548461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3632548461
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1795164498
Short name T664
Test name
Test status
Simulation time 19955146 ps
CPU time 0.67 seconds
Started Jan 24 01:21:12 PM PST 24
Finished Jan 24 01:22:20 PM PST 24
Peak memory 194276 kb
Host smart-2c2f08c6-cc84-4b3f-bd50-9966879d8730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795164498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1795164498
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.636467057
Short name T598
Test name
Test status
Simulation time 30138721 ps
CPU time 0.78 seconds
Started Jan 24 01:21:12 PM PST 24
Finished Jan 24 01:22:19 PM PST 24
Peak memory 195272 kb
Host smart-e9597085-ebf3-4012-9fc8-4b20bc561398
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636467057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.636467057
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1417750073
Short name T561
Test name
Test status
Simulation time 9558900323 ps
CPU time 121.65 seconds
Started Jan 24 01:21:10 PM PST 24
Finished Jan 24 01:24:19 PM PST 24
Peak memory 198384 kb
Host smart-e216f71d-5406-45a2-b3fc-5da0e12c2a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417750073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1417750073
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2553018349
Short name T488
Test name
Test status
Simulation time 13959499 ps
CPU time 0.56 seconds
Started Jan 24 01:21:21 PM PST 24
Finished Jan 24 01:22:27 PM PST 24
Peak memory 193996 kb
Host smart-977e6eb4-7b71-4e3b-bd1d-91e5b60a0949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553018349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2553018349
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3256566816
Short name T434
Test name
Test status
Simulation time 63474865 ps
CPU time 0.69 seconds
Started Jan 24 01:21:21 PM PST 24
Finished Jan 24 01:22:27 PM PST 24
Peak memory 194084 kb
Host smart-bece5527-c1ed-4165-bbdb-d9b734bbcc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256566816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3256566816
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1595106159
Short name T523
Test name
Test status
Simulation time 2889117052 ps
CPU time 23.7 seconds
Started Jan 24 01:21:22 PM PST 24
Finished Jan 24 01:22:51 PM PST 24
Peak memory 198336 kb
Host smart-5816fe76-de52-4b35-855d-05784b04478d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595106159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1595106159
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3830674345
Short name T77
Test name
Test status
Simulation time 44158080 ps
CPU time 0.74 seconds
Started Jan 24 01:21:28 PM PST 24
Finished Jan 24 01:22:32 PM PST 24
Peak memory 195928 kb
Host smart-7804338c-a6a6-43da-b56f-20fb3b7c7917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830674345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3830674345
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2234720080
Short name T225
Test name
Test status
Simulation time 70664734 ps
CPU time 1.24 seconds
Started Jan 24 01:21:26 PM PST 24
Finished Jan 24 01:22:31 PM PST 24
Peak memory 196240 kb
Host smart-cd2d1d97-9353-413a-be7b-8f11fe58e642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234720080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2234720080
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.498779219
Short name T684
Test name
Test status
Simulation time 25676010 ps
CPU time 1.01 seconds
Started Jan 24 01:21:22 PM PST 24
Finished Jan 24 01:22:28 PM PST 24
Peak memory 196548 kb
Host smart-17a9d47d-5ad6-4ca3-a59a-6b625d1ed0c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498779219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.498779219
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1096173932
Short name T323
Test name
Test status
Simulation time 94901390 ps
CPU time 2.72 seconds
Started Jan 24 01:21:28 PM PST 24
Finished Jan 24 01:22:34 PM PST 24
Peak memory 198212 kb
Host smart-1f4543ec-942c-46ec-893c-457750c5c419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096173932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1096173932
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.176813078
Short name T551
Test name
Test status
Simulation time 61637217 ps
CPU time 1.14 seconds
Started Jan 24 01:21:22 PM PST 24
Finished Jan 24 01:22:28 PM PST 24
Peak memory 196240 kb
Host smart-d3e274cc-5d1e-44a7-9574-b59b45d3eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176813078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.176813078
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3203231969
Short name T450
Test name
Test status
Simulation time 116403942 ps
CPU time 1.04 seconds
Started Jan 24 01:21:28 PM PST 24
Finished Jan 24 01:22:33 PM PST 24
Peak memory 196104 kb
Host smart-c1c68ccd-00aa-43fe-a084-0a3a12fc05e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203231969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3203231969
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2997587445
Short name T433
Test name
Test status
Simulation time 871849720 ps
CPU time 5.34 seconds
Started Jan 24 01:21:23 PM PST 24
Finished Jan 24 01:22:33 PM PST 24
Peak memory 198116 kb
Host smart-598a3e30-8480-4cfe-aa8c-2eb963c86445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997587445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2997587445
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2983804642
Short name T67
Test name
Test status
Simulation time 43031535 ps
CPU time 0.78 seconds
Started Jan 24 01:21:21 PM PST 24
Finished Jan 24 01:22:27 PM PST 24
Peak memory 213672 kb
Host smart-9655b0f7-1ad8-4c7b-a31d-73af7802342a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983804642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2983804642
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.4146483387
Short name T641
Test name
Test status
Simulation time 102014110 ps
CPU time 1.16 seconds
Started Jan 24 01:21:15 PM PST 24
Finished Jan 24 01:22:22 PM PST 24
Peak memory 196400 kb
Host smart-ed769c99-9a10-4606-8ce4-106724718363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146483387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.4146483387
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4041605049
Short name T607
Test name
Test status
Simulation time 44178698 ps
CPU time 0.9 seconds
Started Jan 24 01:21:10 PM PST 24
Finished Jan 24 01:22:18 PM PST 24
Peak memory 196352 kb
Host smart-af3b53fc-c973-486d-bce4-8d2ea016f980
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041605049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4041605049
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.9270866
Short name T412
Test name
Test status
Simulation time 53286333515 ps
CPU time 142.42 seconds
Started Jan 24 01:21:23 PM PST 24
Finished Jan 24 01:24:50 PM PST 24
Peak memory 198372 kb
Host smart-2c2d4b91-a44f-4335-b8d4-26cc96dd8840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9270866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio
_stress_all.9270866
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3331547704
Short name T343
Test name
Test status
Simulation time 358948681785 ps
CPU time 312.72 seconds
Started Jan 24 01:21:18 PM PST 24
Finished Jan 24 01:27:37 PM PST 24
Peak memory 206580 kb
Host smart-50bf25bf-4abe-4027-8be5-4ff48f9eec7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3331547704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3331547704
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.327148490
Short name T332
Test name
Test status
Simulation time 13404829 ps
CPU time 0.57 seconds
Started Jan 24 01:22:49 PM PST 24
Finished Jan 24 01:23:46 PM PST 24
Peak memory 193912 kb
Host smart-94899380-dc80-4353-b632-cbab5c467450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327148490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.327148490
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.4087278510
Short name T367
Test name
Test status
Simulation time 24753210 ps
CPU time 0.66 seconds
Started Jan 24 01:22:46 PM PST 24
Finished Jan 24 01:23:43 PM PST 24
Peak memory 194156 kb
Host smart-15bfb4fe-37c4-4367-9705-484619174c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087278510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.4087278510
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1266527060
Short name T350
Test name
Test status
Simulation time 797854671 ps
CPU time 23.81 seconds
Started Jan 24 01:50:22 PM PST 24
Finished Jan 24 01:50:58 PM PST 24
Peak memory 196448 kb
Host smart-eeb70cf7-fb13-405f-870b-48b73294a8c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266527060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1266527060
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2843955304
Short name T875
Test name
Test status
Simulation time 43435611 ps
CPU time 0.78 seconds
Started Jan 24 01:22:48 PM PST 24
Finished Jan 24 01:23:45 PM PST 24
Peak memory 196780 kb
Host smart-1dd7fd3e-6909-43c9-84cc-f7328cc0faba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843955304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2843955304
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2921910023
Short name T527
Test name
Test status
Simulation time 183952797 ps
CPU time 0.97 seconds
Started Jan 24 03:25:25 PM PST 24
Finished Jan 24 03:25:50 PM PST 24
Peak memory 196844 kb
Host smart-7a3dc493-7056-4bf1-a175-05a812356070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921910023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2921910023
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2915658369
Short name T249
Test name
Test status
Simulation time 97595530 ps
CPU time 2.37 seconds
Started Jan 24 01:22:51 PM PST 24
Finished Jan 24 01:23:48 PM PST 24
Peak memory 197032 kb
Host smart-810e4a36-d5a7-46aa-a879-0086229203b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915658369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2915658369
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.165375768
Short name T631
Test name
Test status
Simulation time 137317580 ps
CPU time 1.35 seconds
Started Jan 24 03:19:30 PM PST 24
Finished Jan 24 03:19:46 PM PST 24
Peak memory 197172 kb
Host smart-ea48f466-88b7-497f-8a7a-d551726242b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165375768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.165375768
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.286853096
Short name T306
Test name
Test status
Simulation time 56945849 ps
CPU time 1.03 seconds
Started Jan 24 01:22:51 PM PST 24
Finished Jan 24 01:23:47 PM PST 24
Peak memory 196176 kb
Host smart-e7cc03af-fd51-4f88-bacb-38af1d35af78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286853096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.286853096
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3986803961
Short name T235
Test name
Test status
Simulation time 237756123 ps
CPU time 3.28 seconds
Started Jan 24 01:22:50 PM PST 24
Finished Jan 24 01:23:48 PM PST 24
Peak memory 198192 kb
Host smart-af00de70-ed70-4f7b-8e98-f46003d17adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986803961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3986803961
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3384491131
Short name T584
Test name
Test status
Simulation time 215103066 ps
CPU time 1.15 seconds
Started Jan 24 01:22:49 PM PST 24
Finished Jan 24 01:23:46 PM PST 24
Peak memory 195792 kb
Host smart-76db70e7-6a00-407b-b7ac-5344cc3e797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384491131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3384491131
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2494729537
Short name T273
Test name
Test status
Simulation time 117059602 ps
CPU time 1.04 seconds
Started Jan 24 01:40:16 PM PST 24
Finished Jan 24 01:41:14 PM PST 24
Peak memory 195692 kb
Host smart-83028d7c-44f9-4a1e-bca7-65a407d18bcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494729537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2494729537
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2910237178
Short name T688
Test name
Test status
Simulation time 4031588306 ps
CPU time 111.95 seconds
Started Jan 24 01:22:51 PM PST 24
Finished Jan 24 01:25:38 PM PST 24
Peak memory 198204 kb
Host smart-2ef1cb28-fe7a-45f9-877e-23460b5358e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910237178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2910237178
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2512523260
Short name T811
Test name
Test status
Simulation time 254163762448 ps
CPU time 877.87 seconds
Started Jan 24 01:22:46 PM PST 24
Finished Jan 24 01:38:20 PM PST 24
Peak memory 198372 kb
Host smart-16767ac9-e03c-4a39-bead-83f915892d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2512523260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2512523260
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2660473635
Short name T863
Test name
Test status
Simulation time 18941507 ps
CPU time 0.57 seconds
Started Jan 24 01:23:02 PM PST 24
Finished Jan 24 01:23:54 PM PST 24
Peak memory 194652 kb
Host smart-da813a61-565a-4f8f-a78e-533146a61c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660473635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2660473635
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.771716348
Short name T345
Test name
Test status
Simulation time 85908221 ps
CPU time 0.87 seconds
Started Jan 24 02:10:52 PM PST 24
Finished Jan 24 02:11:55 PM PST 24
Peak memory 196252 kb
Host smart-8be7e225-7353-42e0-8580-bc114f174df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771716348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.771716348
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3994218602
Short name T873
Test name
Test status
Simulation time 412186791 ps
CPU time 20.35 seconds
Started Jan 24 01:23:02 PM PST 24
Finished Jan 24 01:24:14 PM PST 24
Peak memory 196440 kb
Host smart-933b9759-fbb4-43c2-bd47-db0e97ae9464
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994218602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3994218602
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2554803633
Short name T634
Test name
Test status
Simulation time 60508212 ps
CPU time 0.9 seconds
Started Jan 24 01:23:03 PM PST 24
Finished Jan 24 01:23:55 PM PST 24
Peak memory 196184 kb
Host smart-b40c42a2-33ef-4cdf-a908-81f3697c002e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554803633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2554803633
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2860750321
Short name T121
Test name
Test status
Simulation time 34351759 ps
CPU time 0.77 seconds
Started Jan 24 01:23:02 PM PST 24
Finished Jan 24 01:23:55 PM PST 24
Peak memory 195620 kb
Host smart-9329d48c-d480-4523-a236-1739217f6a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860750321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2860750321
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3445278812
Short name T687
Test name
Test status
Simulation time 134938088 ps
CPU time 2.1 seconds
Started Jan 24 01:23:05 PM PST 24
Finished Jan 24 01:23:58 PM PST 24
Peak memory 198212 kb
Host smart-ae558a83-b2e6-4482-ae60-295342efc095
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445278812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3445278812
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4290918305
Short name T113
Test name
Test status
Simulation time 63222235 ps
CPU time 2.02 seconds
Started Jan 24 01:33:07 PM PST 24
Finished Jan 24 01:33:34 PM PST 24
Peak memory 198188 kb
Host smart-2cc0cfd3-dfd3-46fa-8dfd-1fd66996ee26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290918305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4290918305
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3038463628
Short name T667
Test name
Test status
Simulation time 238992566 ps
CPU time 1.17 seconds
Started Jan 24 01:23:01 PM PST 24
Finished Jan 24 01:23:55 PM PST 24
Peak memory 197504 kb
Host smart-5dfb5c7e-1aac-494d-bdcd-43d91e8a7cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038463628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3038463628
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.907294516
Short name T509
Test name
Test status
Simulation time 50953643 ps
CPU time 1.01 seconds
Started Jan 24 01:23:05 PM PST 24
Finished Jan 24 01:23:57 PM PST 24
Peak memory 196112 kb
Host smart-e2e4e93c-d93c-43cf-824b-110f478ca81b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907294516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.907294516
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2007071745
Short name T768
Test name
Test status
Simulation time 100854509 ps
CPU time 4.42 seconds
Started Jan 24 01:22:59 PM PST 24
Finished Jan 24 01:23:57 PM PST 24
Peak memory 198160 kb
Host smart-9b29e310-8b8d-4ccd-a73b-77ad3aa255d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007071745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2007071745
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.514322505
Short name T337
Test name
Test status
Simulation time 35125041 ps
CPU time 1.09 seconds
Started Jan 24 01:22:56 PM PST 24
Finished Jan 24 01:23:51 PM PST 24
Peak memory 195648 kb
Host smart-09c942b6-f5e9-4e30-bc04-b42639ea7300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514322505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.514322505
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3994749069
Short name T483
Test name
Test status
Simulation time 194848951 ps
CPU time 1.04 seconds
Started Jan 24 01:44:23 PM PST 24
Finished Jan 24 01:44:40 PM PST 24
Peak memory 196376 kb
Host smart-f13681f4-f9f0-410c-b4a0-e0d4761fb7fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994749069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3994749069
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1509792073
Short name T369
Test name
Test status
Simulation time 40644511849 ps
CPU time 140.84 seconds
Started Jan 24 01:23:05 PM PST 24
Finished Jan 24 01:26:17 PM PST 24
Peak memory 198320 kb
Host smart-7632eb0f-29f9-4e53-9201-51d6e164fe8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509792073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1509792073
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1481300141
Short name T460
Test name
Test status
Simulation time 63063378743 ps
CPU time 539.94 seconds
Started Jan 24 01:49:46 PM PST 24
Finished Jan 24 01:58:49 PM PST 24
Peak memory 198376 kb
Host smart-3226fb3c-63b0-484c-916d-ca2ad7b56fe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1481300141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1481300141
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.222400134
Short name T771
Test name
Test status
Simulation time 14654188 ps
CPU time 0.58 seconds
Started Jan 24 01:23:10 PM PST 24
Finished Jan 24 01:24:02 PM PST 24
Peak memory 194892 kb
Host smart-3fce7fea-05d7-499b-b7dc-3ce0982c207c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222400134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.222400134
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.777492208
Short name T821
Test name
Test status
Simulation time 38574519 ps
CPU time 0.97 seconds
Started Jan 24 02:24:50 PM PST 24
Finished Jan 24 02:24:56 PM PST 24
Peak memory 196688 kb
Host smart-8731ee9e-6524-476c-93c5-af6811945079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777492208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.777492208
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3328503315
Short name T438
Test name
Test status
Simulation time 447648639 ps
CPU time 24.76 seconds
Started Jan 24 01:38:31 PM PST 24
Finished Jan 24 01:39:19 PM PST 24
Peak memory 197136 kb
Host smart-0972cff0-eb65-4791-886f-b7458acdf11a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328503315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3328503315
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3047726203
Short name T292
Test name
Test status
Simulation time 81219962 ps
CPU time 0.73 seconds
Started Jan 24 01:48:10 PM PST 24
Finished Jan 24 01:48:18 PM PST 24
Peak memory 194900 kb
Host smart-8f03bec1-f0fd-491c-a32b-56da95a04e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047726203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3047726203
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1767267785
Short name T797
Test name
Test status
Simulation time 153090984 ps
CPU time 0.79 seconds
Started Jan 24 01:23:09 PM PST 24
Finished Jan 24 01:24:00 PM PST 24
Peak memory 195492 kb
Host smart-c43e4a5c-1615-4f9b-8053-3ac9ba26e892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767267785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1767267785
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2919673273
Short name T804
Test name
Test status
Simulation time 277094722 ps
CPU time 2.84 seconds
Started Jan 24 01:23:14 PM PST 24
Finished Jan 24 01:24:08 PM PST 24
Peak memory 196436 kb
Host smart-54368755-37fa-4eae-b4b2-c1dad9c6cd84
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919673273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2919673273
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3498297058
Short name T742
Test name
Test status
Simulation time 120095897 ps
CPU time 1.3 seconds
Started Jan 24 02:13:43 PM PST 24
Finished Jan 24 02:13:54 PM PST 24
Peak memory 196864 kb
Host smart-2101cbfe-2b6d-4c99-b136-c79422f6e642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498297058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3498297058
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.326457471
Short name T228
Test name
Test status
Simulation time 35541900 ps
CPU time 0.94 seconds
Started Jan 24 01:23:19 PM PST 24
Finished Jan 24 01:24:10 PM PST 24
Peak memory 196796 kb
Host smart-a0ef7ea7-5569-4da2-ba1b-35e971dbf7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326457471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.326457471
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2094776946
Short name T764
Test name
Test status
Simulation time 118383547 ps
CPU time 1.2 seconds
Started Jan 24 01:23:15 PM PST 24
Finished Jan 24 01:24:07 PM PST 24
Peak memory 195868 kb
Host smart-dd16a4b5-1109-4dba-960d-9fbe5ba89bd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094776946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2094776946
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3295807599
Short name T553
Test name
Test status
Simulation time 1357634723 ps
CPU time 4.11 seconds
Started Jan 24 02:09:53 PM PST 24
Finished Jan 24 02:10:01 PM PST 24
Peak memory 198160 kb
Host smart-d2a018d6-4ed4-4a5e-867d-d1dedbf95973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295807599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3295807599
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1585590761
Short name T593
Test name
Test status
Simulation time 37929264 ps
CPU time 0.88 seconds
Started Jan 24 01:23:05 PM PST 24
Finished Jan 24 01:23:57 PM PST 24
Peak memory 196176 kb
Host smart-c8a0dd77-359d-4e6d-812a-ef0e0a27781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585590761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1585590761
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2168720996
Short name T795
Test name
Test status
Simulation time 43760716 ps
CPU time 1.19 seconds
Started Jan 24 01:32:36 PM PST 24
Finished Jan 24 01:33:13 PM PST 24
Peak memory 196584 kb
Host smart-d05de714-941a-4da0-8a96-e8198b13ad68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168720996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2168720996
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1043551739
Short name T674
Test name
Test status
Simulation time 29369713028 ps
CPU time 82.71 seconds
Started Jan 24 01:23:12 PM PST 24
Finished Jan 24 01:25:27 PM PST 24
Peak memory 198340 kb
Host smart-ce5ecf0b-915d-443f-bce4-8901db4b2428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043551739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1043551739
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2459891849
Short name T520
Test name
Test status
Simulation time 12830000 ps
CPU time 0.57 seconds
Started Jan 24 01:23:25 PM PST 24
Finished Jan 24 01:24:13 PM PST 24
Peak memory 193980 kb
Host smart-21d0b9e4-eaab-4a69-8f0a-8fdda10825d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459891849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2459891849
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4254136876
Short name T575
Test name
Test status
Simulation time 36675738 ps
CPU time 0.87 seconds
Started Jan 24 02:49:06 PM PST 24
Finished Jan 24 02:49:23 PM PST 24
Peak memory 196588 kb
Host smart-7f01206f-5210-4711-8ced-36a26fa6aba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254136876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4254136876
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2019972958
Short name T331
Test name
Test status
Simulation time 1159525897 ps
CPU time 21.13 seconds
Started Jan 24 01:23:25 PM PST 24
Finished Jan 24 01:24:33 PM PST 24
Peak memory 198164 kb
Host smart-d0b5154b-721c-4164-829b-b5da10a04ecf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019972958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2019972958
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1650038821
Short name T633
Test name
Test status
Simulation time 232829175 ps
CPU time 0.7 seconds
Started Jan 24 01:23:22 PM PST 24
Finished Jan 24 01:24:12 PM PST 24
Peak memory 194968 kb
Host smart-f9bf7e42-e967-4c8d-931d-8460a5ee2e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650038821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1650038821
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.936530004
Short name T248
Test name
Test status
Simulation time 68558085 ps
CPU time 1.06 seconds
Started Jan 24 01:23:11 PM PST 24
Finished Jan 24 01:24:04 PM PST 24
Peak memory 195960 kb
Host smart-ae2d48d8-3658-4124-86c3-2d0e0533de13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936530004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.936530004
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3352303163
Short name T650
Test name
Test status
Simulation time 54501369 ps
CPU time 2.15 seconds
Started Jan 24 01:23:24 PM PST 24
Finished Jan 24 01:24:14 PM PST 24
Peak memory 198088 kb
Host smart-97daa2b0-36e1-4834-a6e2-530679fdfaed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352303163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3352303163
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.132500795
Short name T251
Test name
Test status
Simulation time 188239712 ps
CPU time 2.76 seconds
Started Jan 24 01:23:11 PM PST 24
Finished Jan 24 01:24:05 PM PST 24
Peak memory 196520 kb
Host smart-2d77243c-298d-4ddf-88ff-29c7ef92896b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132500795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
132500795
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3043025600
Short name T589
Test name
Test status
Simulation time 128723712 ps
CPU time 1.21 seconds
Started Jan 24 01:23:15 PM PST 24
Finished Jan 24 01:24:07 PM PST 24
Peak memory 198104 kb
Host smart-a8b6b87b-e953-45a3-8e4a-814def660a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043025600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3043025600
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.651604955
Short name T501
Test name
Test status
Simulation time 29520249 ps
CPU time 1.17 seconds
Started Jan 24 01:33:16 PM PST 24
Finished Jan 24 01:33:39 PM PST 24
Peak memory 196680 kb
Host smart-6734ad0c-5051-4c9d-a7d3-d355e12c2ca1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651604955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.651604955
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2791641569
Short name T554
Test name
Test status
Simulation time 252737981 ps
CPU time 3.63 seconds
Started Jan 24 01:23:24 PM PST 24
Finished Jan 24 01:24:16 PM PST 24
Peak memory 198112 kb
Host smart-dda3e1ea-012e-4ca9-93f5-47016b3ea6dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791641569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2791641569
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3558818714
Short name T660
Test name
Test status
Simulation time 80454215 ps
CPU time 1.13 seconds
Started Jan 24 01:23:12 PM PST 24
Finished Jan 24 01:24:04 PM PST 24
Peak memory 195960 kb
Host smart-7a933ad3-35e9-4ed7-b8de-59a7d20b574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558818714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3558818714
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2778934529
Short name T601
Test name
Test status
Simulation time 319385146 ps
CPU time 1.06 seconds
Started Jan 24 01:40:15 PM PST 24
Finished Jan 24 01:41:13 PM PST 24
Peak memory 195884 kb
Host smart-d31667d3-567a-4030-93a4-bac11bcedf92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778934529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2778934529
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1643914863
Short name T747
Test name
Test status
Simulation time 8465827278 ps
CPU time 20.74 seconds
Started Jan 24 01:23:24 PM PST 24
Finished Jan 24 01:24:33 PM PST 24
Peak memory 198364 kb
Host smart-7cf68895-1c75-4d41-a7f8-520c865fbbec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643914863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1643914863
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1236999465
Short name T609
Test name
Test status
Simulation time 167297602867 ps
CPU time 1305.23 seconds
Started Jan 24 01:54:03 PM PST 24
Finished Jan 24 02:15:51 PM PST 24
Peak memory 198452 kb
Host smart-1619c4a5-85d9-4e80-965f-9f4e7ac93452
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1236999465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1236999465
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.297360602
Short name T510
Test name
Test status
Simulation time 20470570 ps
CPU time 0.54 seconds
Started Jan 24 01:23:38 PM PST 24
Finished Jan 24 01:24:23 PM PST 24
Peak memory 193992 kb
Host smart-8d415e01-bf59-413b-8b90-67bc083014fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297360602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.297360602
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1068775634
Short name T752
Test name
Test status
Simulation time 25830127 ps
CPU time 0.62 seconds
Started Jan 24 03:31:12 PM PST 24
Finished Jan 24 03:31:20 PM PST 24
Peak memory 194124 kb
Host smart-6767fa7b-0dcf-48a1-ab67-7dc653cd2eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068775634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1068775634
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1089184707
Short name T281
Test name
Test status
Simulation time 3535108053 ps
CPU time 15.65 seconds
Started Jan 24 01:37:43 PM PST 24
Finished Jan 24 01:38:27 PM PST 24
Peak memory 198324 kb
Host smart-59435753-2f4d-4a0c-9981-5927c7a22ac9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089184707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1089184707
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.674330265
Short name T686
Test name
Test status
Simulation time 41318309 ps
CPU time 0.63 seconds
Started Jan 24 01:23:26 PM PST 24
Finished Jan 24 01:24:13 PM PST 24
Peak memory 195316 kb
Host smart-f9b76de1-8963-4720-993e-8ad0fc1864a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674330265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.674330265
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2668976750
Short name T871
Test name
Test status
Simulation time 87903094 ps
CPU time 1.25 seconds
Started Jan 24 01:23:22 PM PST 24
Finished Jan 24 01:24:12 PM PST 24
Peak memory 196228 kb
Host smart-e695e7b9-29d6-4fa1-88db-6b640e480036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668976750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2668976750
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3705381373
Short name T443
Test name
Test status
Simulation time 105148032 ps
CPU time 2.24 seconds
Started Jan 24 01:23:24 PM PST 24
Finished Jan 24 01:24:14 PM PST 24
Peak memory 198184 kb
Host smart-b5c5ee44-bc32-486e-b364-085d03a653dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705381373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3705381373
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3006822579
Short name T437
Test name
Test status
Simulation time 63032284 ps
CPU time 1.88 seconds
Started Jan 24 01:23:24 PM PST 24
Finished Jan 24 01:24:14 PM PST 24
Peak memory 197284 kb
Host smart-f69bc16b-b192-4c67-96fd-c5f30dd895c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006822579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3006822579
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3210024536
Short name T833
Test name
Test status
Simulation time 72706608 ps
CPU time 1.18 seconds
Started Jan 24 01:23:26 PM PST 24
Finished Jan 24 01:24:14 PM PST 24
Peak memory 196680 kb
Host smart-37cbbdd1-6741-48c4-966b-7be9a4297a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210024536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3210024536
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1264035736
Short name T843
Test name
Test status
Simulation time 116064738 ps
CPU time 1.11 seconds
Started Jan 24 01:23:25 PM PST 24
Finished Jan 24 01:24:13 PM PST 24
Peak memory 196768 kb
Host smart-0732f6e6-1719-4e6d-835b-24b69adbd025
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264035736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1264035736
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2869636334
Short name T405
Test name
Test status
Simulation time 118420322 ps
CPU time 2.41 seconds
Started Jan 24 01:23:22 PM PST 24
Finished Jan 24 01:24:13 PM PST 24
Peak memory 198132 kb
Host smart-ca1411ae-ff46-4566-b8ff-67086e82c85b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869636334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2869636334
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.338294696
Short name T557
Test name
Test status
Simulation time 164506240 ps
CPU time 0.79 seconds
Started Jan 24 01:29:37 PM PST 24
Finished Jan 24 01:29:50 PM PST 24
Peak memory 195364 kb
Host smart-4f78f728-ffeb-4015-bd12-27a291517611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338294696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.338294696
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1606763948
Short name T475
Test name
Test status
Simulation time 38629737 ps
CPU time 1.22 seconds
Started Jan 24 01:23:23 PM PST 24
Finished Jan 24 01:24:13 PM PST 24
Peak memory 196340 kb
Host smart-6902ccb3-a974-4568-b81f-84e5df138ef4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606763948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1606763948
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.4019343706
Short name T577
Test name
Test status
Simulation time 12424810551 ps
CPU time 71.72 seconds
Started Jan 24 01:23:22 PM PST 24
Finished Jan 24 01:25:23 PM PST 24
Peak memory 198256 kb
Host smart-95b5b36b-b14b-492a-b6c3-3d97a8a79fc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019343706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.4019343706
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.418428165
Short name T410
Test name
Test status
Simulation time 22407080415 ps
CPU time 696.45 seconds
Started Jan 24 01:23:26 PM PST 24
Finished Jan 24 01:35:49 PM PST 24
Peak memory 198412 kb
Host smart-cde1344e-cc3c-4351-a517-0435cfded358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=418428165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.418428165
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2524754399
Short name T695
Test name
Test status
Simulation time 28537825 ps
CPU time 0.57 seconds
Started Jan 24 01:23:38 PM PST 24
Finished Jan 24 01:24:23 PM PST 24
Peak memory 194000 kb
Host smart-d19215e4-b897-45e1-b00b-3286ebbb312a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524754399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2524754399
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3371883487
Short name T452
Test name
Test status
Simulation time 34154487 ps
CPU time 0.8 seconds
Started Jan 24 01:23:37 PM PST 24
Finished Jan 24 01:24:22 PM PST 24
Peak memory 195540 kb
Host smart-8831d87a-9dc4-49e6-af9c-4a8a403eedd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371883487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3371883487
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2657254370
Short name T299
Test name
Test status
Simulation time 348473728 ps
CPU time 5.12 seconds
Started Jan 24 01:23:42 PM PST 24
Finished Jan 24 01:24:30 PM PST 24
Peak memory 196572 kb
Host smart-c669abcb-2905-4ac2-9cf1-07228d16242c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657254370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2657254370
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.842909467
Short name T696
Test name
Test status
Simulation time 622596971 ps
CPU time 1.04 seconds
Started Jan 24 01:23:42 PM PST 24
Finished Jan 24 01:24:26 PM PST 24
Peak memory 196612 kb
Host smart-e73af2e9-378e-4695-b000-2da41f283bfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842909467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.842909467
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3190716773
Short name T439
Test name
Test status
Simulation time 17188783 ps
CPU time 0.65 seconds
Started Jan 24 01:23:36 PM PST 24
Finished Jan 24 01:24:22 PM PST 24
Peak memory 194444 kb
Host smart-b0780775-12bc-4f1c-9fba-4f426d1dee1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190716773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3190716773
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2081873014
Short name T386
Test name
Test status
Simulation time 80559372 ps
CPU time 3.18 seconds
Started Jan 24 01:23:41 PM PST 24
Finished Jan 24 01:24:27 PM PST 24
Peak memory 198188 kb
Host smart-55a27044-affe-40fe-bfda-1456bf8db4a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081873014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2081873014
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4213906454
Short name T379
Test name
Test status
Simulation time 481845881 ps
CPU time 2.84 seconds
Started Jan 24 01:23:41 PM PST 24
Finished Jan 24 01:24:27 PM PST 24
Peak memory 198068 kb
Host smart-e23de4c5-7b74-41f6-bf20-9233080db39c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213906454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4213906454
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2653884542
Short name T563
Test name
Test status
Simulation time 56670632 ps
CPU time 1.15 seconds
Started Jan 24 01:23:42 PM PST 24
Finished Jan 24 01:24:26 PM PST 24
Peak memory 196832 kb
Host smart-7a6124bd-7d39-4a8d-9f75-072dbdb06b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653884542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2653884542
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4071626703
Short name T748
Test name
Test status
Simulation time 109642089 ps
CPU time 0.93 seconds
Started Jan 24 01:23:39 PM PST 24
Finished Jan 24 01:24:24 PM PST 24
Peak memory 196652 kb
Host smart-84c4f5f9-ad34-48a1-9971-a553ad4ca548
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071626703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4071626703
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2661304705
Short name T567
Test name
Test status
Simulation time 203892105 ps
CPU time 3.34 seconds
Started Jan 24 01:23:41 PM PST 24
Finished Jan 24 01:24:27 PM PST 24
Peak memory 198136 kb
Host smart-2ee8f30a-1c9b-450e-9bfe-37149004d57e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661304705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2661304705
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4047891558
Short name T254
Test name
Test status
Simulation time 247617401 ps
CPU time 1.24 seconds
Started Jan 24 01:23:41 PM PST 24
Finished Jan 24 01:24:25 PM PST 24
Peak memory 196940 kb
Host smart-b7a24fe3-6623-4318-aaad-94657a18c831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047891558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4047891558
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4051461437
Short name T371
Test name
Test status
Simulation time 344364299 ps
CPU time 1.39 seconds
Started Jan 24 01:23:40 PM PST 24
Finished Jan 24 01:24:25 PM PST 24
Peak memory 196996 kb
Host smart-3b9bc67f-df14-4ed2-b3b2-790ef1110bd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051461437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4051461437
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2905156843
Short name T591
Test name
Test status
Simulation time 119669215645 ps
CPU time 171.57 seconds
Started Jan 24 01:23:39 PM PST 24
Finished Jan 24 01:27:14 PM PST 24
Peak memory 198372 kb
Host smart-3f286889-f633-4d0a-9ad2-0c5ec5472511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905156843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2905156843
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.855534285
Short name T770
Test name
Test status
Simulation time 327719977149 ps
CPU time 2161.22 seconds
Started Jan 24 01:23:38 PM PST 24
Finished Jan 24 02:00:24 PM PST 24
Peak memory 198408 kb
Host smart-49b6b7a0-c762-4bb2-9dc3-d6a9e131de2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=855534285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.855534285
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1794015386
Short name T338
Test name
Test status
Simulation time 13492620 ps
CPU time 0.59 seconds
Started Jan 24 01:24:09 PM PST 24
Finished Jan 24 01:24:46 PM PST 24
Peak memory 193692 kb
Host smart-cd0f7806-200a-477b-9f1a-32a4209db309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794015386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1794015386
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2131331542
Short name T673
Test name
Test status
Simulation time 84610658 ps
CPU time 0.82 seconds
Started Jan 24 01:23:42 PM PST 24
Finished Jan 24 01:24:25 PM PST 24
Peak memory 196248 kb
Host smart-4db0e627-b129-452f-a91c-5ddce5f6e3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131331542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2131331542
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4248885311
Short name T727
Test name
Test status
Simulation time 885335221 ps
CPU time 7.75 seconds
Started Jan 24 01:24:01 PM PST 24
Finished Jan 24 01:24:47 PM PST 24
Peak memory 197096 kb
Host smart-c7596b66-3aa1-42ca-a188-3148d07814b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248885311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4248885311
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2277967897
Short name T760
Test name
Test status
Simulation time 191552376 ps
CPU time 0.74 seconds
Started Jan 24 01:24:03 PM PST 24
Finished Jan 24 01:24:41 PM PST 24
Peak memory 196004 kb
Host smart-99f739fd-4b5a-4f60-9874-163933ed833b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277967897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2277967897
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.35529674
Short name T76
Test name
Test status
Simulation time 376822301 ps
CPU time 1.11 seconds
Started Jan 24 01:23:56 PM PST 24
Finished Jan 24 01:24:37 PM PST 24
Peak memory 196872 kb
Host smart-ee1b6ad0-ee8e-4aa0-9b39-8b804379ee17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35529674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.35529674
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3383775680
Short name T648
Test name
Test status
Simulation time 322542594 ps
CPU time 3.13 seconds
Started Jan 24 01:24:02 PM PST 24
Finished Jan 24 01:24:43 PM PST 24
Peak memory 198244 kb
Host smart-f3d13b2f-3995-437c-8bf5-451d2ad2cf0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383775680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3383775680
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.288518613
Short name T316
Test name
Test status
Simulation time 1293727347 ps
CPU time 2.17 seconds
Started Jan 24 01:24:03 PM PST 24
Finished Jan 24 01:24:42 PM PST 24
Peak memory 198220 kb
Host smart-2f1c0238-7fae-41c8-935d-ab4ce47e4b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288518613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
288518613
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.490652274
Short name T532
Test name
Test status
Simulation time 313713947 ps
CPU time 0.93 seconds
Started Jan 24 01:23:42 PM PST 24
Finished Jan 24 01:24:25 PM PST 24
Peak memory 195944 kb
Host smart-5f34c007-20a0-4de7-b2df-34ded24a79af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490652274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.490652274
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3611276443
Short name T314
Test name
Test status
Simulation time 310041456 ps
CPU time 1.25 seconds
Started Jan 24 01:23:42 PM PST 24
Finished Jan 24 01:24:26 PM PST 24
Peak memory 195924 kb
Host smart-e8d49e6c-b8da-4e2e-a0e6-5ddbca9945a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611276443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3611276443
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2738993873
Short name T639
Test name
Test status
Simulation time 924684219 ps
CPU time 3.65 seconds
Started Jan 24 01:24:01 PM PST 24
Finished Jan 24 01:24:43 PM PST 24
Peak memory 198120 kb
Host smart-69257f8a-956c-46ba-9603-32ef21624f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738993873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2738993873
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.278029554
Short name T668
Test name
Test status
Simulation time 120201200 ps
CPU time 1.08 seconds
Started Jan 24 01:23:39 PM PST 24
Finished Jan 24 01:24:24 PM PST 24
Peak memory 195876 kb
Host smart-de6dc87b-1e71-4b96-a4cb-3a6c765dd84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278029554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.278029554
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1582119948
Short name T317
Test name
Test status
Simulation time 73178938 ps
CPU time 0.99 seconds
Started Jan 24 01:23:43 PM PST 24
Finished Jan 24 01:24:27 PM PST 24
Peak memory 195948 kb
Host smart-a172afcf-cc52-448a-abb5-1aa08fa15525
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582119948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1582119948
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3188988661
Short name T519
Test name
Test status
Simulation time 71891708123 ps
CPU time 89.14 seconds
Started Jan 24 01:24:09 PM PST 24
Finished Jan 24 01:26:14 PM PST 24
Peak memory 197984 kb
Host smart-55af8552-1389-413a-85a6-38c281cf2f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188988661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3188988661
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.4286602375
Short name T91
Test name
Test status
Simulation time 155895297607 ps
CPU time 415.88 seconds
Started Jan 24 01:24:01 PM PST 24
Finished Jan 24 01:31:35 PM PST 24
Peak memory 198456 kb
Host smart-785392f3-dcd7-49bf-a331-760ad361a70d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4286602375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.4286602375
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.28260957
Short name T595
Test name
Test status
Simulation time 16778483 ps
CPU time 0.56 seconds
Started Jan 24 01:24:05 PM PST 24
Finished Jan 24 01:24:43 PM PST 24
Peak memory 192700 kb
Host smart-f2cbc4de-443b-436c-a4cb-6650b42ed61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.28260957
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3325211764
Short name T786
Test name
Test status
Simulation time 77059080 ps
CPU time 0.73 seconds
Started Jan 24 01:24:09 PM PST 24
Finished Jan 24 01:24:46 PM PST 24
Peak memory 195960 kb
Host smart-ac2333a8-fa53-4a73-9c2a-1f3187432dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325211764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3325211764
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1312709804
Short name T700
Test name
Test status
Simulation time 3306108161 ps
CPU time 27.6 seconds
Started Jan 24 01:23:57 PM PST 24
Finished Jan 24 01:25:04 PM PST 24
Peak memory 198344 kb
Host smart-8e4dac76-3d7b-41e1-906e-db40419968db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312709804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1312709804
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2501118813
Short name T385
Test name
Test status
Simulation time 126149298 ps
CPU time 0.74 seconds
Started Jan 24 01:24:09 PM PST 24
Finished Jan 24 01:24:46 PM PST 24
Peak memory 195848 kb
Host smart-a5cf5a53-dce1-408f-8b2e-98a272386764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501118813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2501118813
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2172893588
Short name T738
Test name
Test status
Simulation time 90421123 ps
CPU time 0.89 seconds
Started Jan 24 01:24:01 PM PST 24
Finished Jan 24 01:24:40 PM PST 24
Peak memory 196864 kb
Host smart-4671c106-3e12-4254-8092-d09b84a7ade1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172893588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2172893588
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1086799975
Short name T544
Test name
Test status
Simulation time 38578826 ps
CPU time 1.6 seconds
Started Jan 24 01:24:06 PM PST 24
Finished Jan 24 01:24:44 PM PST 24
Peak memory 196736 kb
Host smart-e19869e3-b42a-43bb-a2ca-d0aa771a6ead
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086799975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1086799975
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.917830978
Short name T713
Test name
Test status
Simulation time 87894456 ps
CPU time 2.41 seconds
Started Jan 24 01:24:00 PM PST 24
Finished Jan 24 01:24:41 PM PST 24
Peak memory 197360 kb
Host smart-f91e7c5d-f7c6-4157-887e-96bb4b2037ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917830978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
917830978
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.644997473
Short name T325
Test name
Test status
Simulation time 164321658 ps
CPU time 1.13 seconds
Started Jan 24 01:24:02 PM PST 24
Finished Jan 24 01:24:41 PM PST 24
Peak memory 196748 kb
Host smart-9482bd4f-ca97-4989-93de-8629768558e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644997473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.644997473
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.420741610
Short name T857
Test name
Test status
Simulation time 69222635 ps
CPU time 1.29 seconds
Started Jan 24 01:24:01 PM PST 24
Finished Jan 24 01:24:41 PM PST 24
Peak memory 195992 kb
Host smart-649bdfd5-3444-4507-9fe0-5a3c948c5621
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420741610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.420741610
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3287516271
Short name T44
Test name
Test status
Simulation time 369654444 ps
CPU time 6.21 seconds
Started Jan 24 01:24:01 PM PST 24
Finished Jan 24 01:24:45 PM PST 24
Peak memory 198112 kb
Host smart-4f381a7c-1ce2-489d-ba6b-fab549d18665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287516271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3287516271
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2755321535
Short name T416
Test name
Test status
Simulation time 170391210 ps
CPU time 1.47 seconds
Started Jan 24 01:24:06 PM PST 24
Finished Jan 24 01:24:44 PM PST 24
Peak memory 196880 kb
Host smart-2a5dcfef-ebae-4016-a38d-aeba45024c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755321535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2755321535
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.270079212
Short name T714
Test name
Test status
Simulation time 329991981 ps
CPU time 1.28 seconds
Started Jan 24 01:24:00 PM PST 24
Finished Jan 24 01:24:40 PM PST 24
Peak memory 196892 kb
Host smart-901be7d0-1b75-4345-baa1-bb1e9b9e594c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270079212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.270079212
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2783056048
Short name T447
Test name
Test status
Simulation time 16736481651 ps
CPU time 53.75 seconds
Started Jan 24 01:24:04 PM PST 24
Finished Jan 24 01:25:34 PM PST 24
Peak memory 198392 kb
Host smart-d53f41ce-5028-491b-9aac-e52a18fc1671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783056048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2783056048
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1589948333
Short name T733
Test name
Test status
Simulation time 10043569305 ps
CPU time 333.82 seconds
Started Jan 24 01:24:09 PM PST 24
Finished Jan 24 01:30:19 PM PST 24
Peak memory 198404 kb
Host smart-a97ec2a1-576c-4cc0-ab6d-ee9e638fef11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1589948333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1589948333
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1298439801
Short name T391
Test name
Test status
Simulation time 76746340 ps
CPU time 0.59 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:24:52 PM PST 24
Peak memory 194128 kb
Host smart-390a7130-380f-423f-9d2a-fb1d551a5e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298439801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1298439801
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2649481940
Short name T699
Test name
Test status
Simulation time 28231282 ps
CPU time 0.73 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:24:52 PM PST 24
Peak memory 195024 kb
Host smart-06adcac6-a469-4e50-935a-154ab56346d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649481940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2649481940
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1976759373
Short name T757
Test name
Test status
Simulation time 587050466 ps
CPU time 7.16 seconds
Started Jan 24 01:24:16 PM PST 24
Finished Jan 24 01:24:57 PM PST 24
Peak memory 198188 kb
Host smart-e738b23b-9277-4ef9-b786-fef29ad9fd61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976759373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1976759373
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1379751198
Short name T268
Test name
Test status
Simulation time 60127344 ps
CPU time 0.61 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:24:52 PM PST 24
Peak memory 194428 kb
Host smart-22c4282a-133a-4fbf-b009-2539b1076584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379751198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1379751198
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2312162858
Short name T637
Test name
Test status
Simulation time 18027324 ps
CPU time 0.7 seconds
Started Jan 24 01:24:13 PM PST 24
Finished Jan 24 01:24:48 PM PST 24
Peak memory 195088 kb
Host smart-f12a96e6-728a-4009-891b-24b63b106aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312162858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2312162858
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.538235615
Short name T261
Test name
Test status
Simulation time 27223851 ps
CPU time 1.09 seconds
Started Jan 24 01:24:16 PM PST 24
Finished Jan 24 01:24:52 PM PST 24
Peak memory 197520 kb
Host smart-85189b65-8583-4516-acc8-b3342c1155ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538235615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.538235615
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1875495177
Short name T824
Test name
Test status
Simulation time 90427144 ps
CPU time 1.81 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:24:53 PM PST 24
Peak memory 195908 kb
Host smart-8401dd3b-4fd7-4ceb-ba58-d8a5033bef04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875495177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1875495177
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1603628429
Short name T722
Test name
Test status
Simulation time 124472211 ps
CPU time 0.85 seconds
Started Jan 24 01:24:16 PM PST 24
Finished Jan 24 01:24:50 PM PST 24
Peak memory 196468 kb
Host smart-d5aa8267-2de7-46e4-bff7-1feda8d08394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603628429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1603628429
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2305597279
Short name T418
Test name
Test status
Simulation time 105754711 ps
CPU time 0.75 seconds
Started Jan 24 01:24:15 PM PST 24
Finished Jan 24 01:24:50 PM PST 24
Peak memory 196272 kb
Host smart-ea455508-bfba-4107-83ca-525c466b4b66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305597279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2305597279
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3546488362
Short name T846
Test name
Test status
Simulation time 228448709 ps
CPU time 2.18 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:24:53 PM PST 24
Peak memory 198128 kb
Host smart-5e2c49d8-5bc1-4886-b60b-136aa8edb855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546488362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3546488362
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2024346747
Short name T578
Test name
Test status
Simulation time 33788665 ps
CPU time 0.91 seconds
Started Jan 24 01:24:16 PM PST 24
Finished Jan 24 01:24:51 PM PST 24
Peak memory 195296 kb
Host smart-61c7443d-f7f5-4bc4-b286-d3e6101862c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024346747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2024346747
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.401712910
Short name T573
Test name
Test status
Simulation time 86273142 ps
CPU time 1.2 seconds
Started Jan 24 01:24:17 PM PST 24
Finished Jan 24 01:24:52 PM PST 24
Peak memory 195768 kb
Host smart-39585047-fc41-4409-8420-75c39b345930
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401712910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.401712910
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1828752174
Short name T242
Test name
Test status
Simulation time 4282017202 ps
CPU time 106.08 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:26:37 PM PST 24
Peak memory 198304 kb
Host smart-8a931667-8846-4373-b9f7-810a75964083
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828752174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1828752174
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3494006072
Short name T477
Test name
Test status
Simulation time 111769614203 ps
CPU time 1537.67 seconds
Started Jan 24 01:24:18 PM PST 24
Finished Jan 24 01:50:29 PM PST 24
Peak memory 198408 kb
Host smart-6981ba66-1c60-4fa7-9cdf-b349d6fb808f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3494006072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3494006072
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4116459157
Short name T487
Test name
Test status
Simulation time 26573176 ps
CPU time 0.8 seconds
Started Jan 24 01:24:25 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 196068 kb
Host smart-a0dbf2da-8714-4189-9f36-ace187149311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116459157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4116459157
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.871905600
Short name T812
Test name
Test status
Simulation time 385696213 ps
CPU time 13.39 seconds
Started Jan 24 01:24:25 PM PST 24
Finished Jan 24 01:25:09 PM PST 24
Peak memory 196732 kb
Host smart-41a1e800-0c8e-4513-a3fe-14bd8b9ee52f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871905600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.871905600
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.493535005
Short name T115
Test name
Test status
Simulation time 243856874 ps
CPU time 0.86 seconds
Started Jan 24 01:24:25 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 197260 kb
Host smart-76489040-0765-4e68-90e3-a2a5545b6bcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493535005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.493535005
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1529914582
Short name T735
Test name
Test status
Simulation time 30739415 ps
CPU time 0.89 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 196120 kb
Host smart-7423658c-5c75-49eb-a24d-e4568b5e7699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529914582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1529914582
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3953212524
Short name T467
Test name
Test status
Simulation time 340425262 ps
CPU time 2.57 seconds
Started Jan 24 01:24:25 PM PST 24
Finished Jan 24 01:24:58 PM PST 24
Peak memory 197428 kb
Host smart-621b13f8-12d7-4acc-bc5d-7d70a2a36c82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953212524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3953212524
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.535964403
Short name T826
Test name
Test status
Simulation time 154445071 ps
CPU time 1 seconds
Started Jan 24 01:24:17 PM PST 24
Finished Jan 24 01:24:52 PM PST 24
Peak memory 196212 kb
Host smart-bce4ee0b-65b5-44e9-ab5d-a201993e7e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535964403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.535964403
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1879914138
Short name T524
Test name
Test status
Simulation time 29522463 ps
CPU time 0.63 seconds
Started Jan 24 01:24:25 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 194280 kb
Host smart-a1cbd979-e409-4197-a4c7-e9d5f3d91789
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879914138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1879914138
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.401662715
Short name T296
Test name
Test status
Simulation time 218298273 ps
CPU time 5.26 seconds
Started Jan 24 01:24:25 PM PST 24
Finished Jan 24 01:25:01 PM PST 24
Peak memory 198156 kb
Host smart-fd36d9f4-f892-46bf-a282-53bac6d01d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401662715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.401662715
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3444056783
Short name T739
Test name
Test status
Simulation time 39466676 ps
CPU time 1.04 seconds
Started Jan 24 01:24:16 PM PST 24
Finished Jan 24 01:24:51 PM PST 24
Peak memory 196432 kb
Host smart-57a3e253-b94d-4c91-a83f-d3d2ca6122d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444056783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3444056783
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1361459665
Short name T381
Test name
Test status
Simulation time 173595122 ps
CPU time 1.3 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 195692 kb
Host smart-3bff5509-fb0e-4ea8-8fc0-84db20b04f42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361459665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1361459665
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2565594303
Short name T802
Test name
Test status
Simulation time 28635931866 ps
CPU time 110.24 seconds
Started Jan 24 01:24:17 PM PST 24
Finished Jan 24 01:26:41 PM PST 24
Peak memory 198312 kb
Host smart-1146371b-d5f1-4054-983d-4652ccfb715b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565594303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2565594303
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1335963321
Short name T732
Test name
Test status
Simulation time 66675582811 ps
CPU time 242.72 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:28:58 PM PST 24
Peak memory 198452 kb
Host smart-a25cfff1-09f4-4811-9f70-941ac57ce98f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1335963321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1335963321
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.175272760
Short name T400
Test name
Test status
Simulation time 13805140 ps
CPU time 0.57 seconds
Started Jan 24 01:21:43 PM PST 24
Finished Jan 24 01:22:43 PM PST 24
Peak memory 193188 kb
Host smart-40089ad9-4f57-4c9f-9eab-089a265395a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175272760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.175272760
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.360629853
Short name T726
Test name
Test status
Simulation time 26930807 ps
CPU time 0.69 seconds
Started Jan 24 01:21:25 PM PST 24
Finished Jan 24 01:22:30 PM PST 24
Peak memory 194324 kb
Host smart-04100af8-6b82-4d59-bc2c-c7e34fd8aade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360629853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.360629853
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3108006177
Short name T869
Test name
Test status
Simulation time 712842575 ps
CPU time 20.28 seconds
Started Jan 24 01:21:31 PM PST 24
Finished Jan 24 01:22:53 PM PST 24
Peak memory 196956 kb
Host smart-7288d934-6b74-4249-9fe6-6106ab565b48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108006177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3108006177
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1425118456
Short name T659
Test name
Test status
Simulation time 37852216 ps
CPU time 0.75 seconds
Started Jan 24 01:21:31 PM PST 24
Finished Jan 24 01:22:34 PM PST 24
Peak memory 195904 kb
Host smart-ec43bd07-4d23-49ab-ae08-c268f7b9d00f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425118456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1425118456
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.543170607
Short name T734
Test name
Test status
Simulation time 34967788 ps
CPU time 0.95 seconds
Started Jan 24 01:21:26 PM PST 24
Finished Jan 24 01:22:31 PM PST 24
Peak memory 195972 kb
Host smart-edc8d4bc-b392-46a5-a13a-34a6eeaf066a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543170607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.543170607
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3685545858
Short name T761
Test name
Test status
Simulation time 72645425 ps
CPU time 1.05 seconds
Started Jan 24 01:21:31 PM PST 24
Finished Jan 24 01:22:35 PM PST 24
Peak memory 196140 kb
Host smart-8704cf01-13a5-4384-bb56-55aa9408361a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685545858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3685545858
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2552597266
Short name T528
Test name
Test status
Simulation time 142221604 ps
CPU time 2.4 seconds
Started Jan 24 01:21:27 PM PST 24
Finished Jan 24 01:22:34 PM PST 24
Peak memory 195984 kb
Host smart-c7eb29ce-327d-462c-9169-71c5ca3a8992
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552597266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2552597266
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.778503377
Short name T541
Test name
Test status
Simulation time 27645772 ps
CPU time 0.99 seconds
Started Jan 24 01:21:28 PM PST 24
Finished Jan 24 01:22:32 PM PST 24
Peak memory 196244 kb
Host smart-8f446921-ad13-4aed-bb13-c64054526022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778503377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.778503377
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2223723107
Short name T741
Test name
Test status
Simulation time 87291726 ps
CPU time 0.93 seconds
Started Jan 24 01:21:31 PM PST 24
Finished Jan 24 01:22:34 PM PST 24
Peak memory 196108 kb
Host smart-7e2c23dc-d02b-43c4-ae67-3edabbc3d8fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223723107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2223723107
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1801961467
Short name T621
Test name
Test status
Simulation time 479228690 ps
CPU time 4.84 seconds
Started Jan 24 01:21:26 PM PST 24
Finished Jan 24 01:22:35 PM PST 24
Peak memory 198184 kb
Host smart-5f227131-f26e-4633-9933-126a4e21c08f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801961467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1801961467
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2768741950
Short name T38
Test name
Test status
Simulation time 392957205 ps
CPU time 0.96 seconds
Started Jan 24 01:21:30 PM PST 24
Finished Jan 24 01:22:34 PM PST 24
Peak memory 214824 kb
Host smart-208cd9bd-2e54-4b9d-9838-b414aff4ef8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768741950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2768741950
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2509817877
Short name T702
Test name
Test status
Simulation time 26369181 ps
CPU time 0.8 seconds
Started Jan 24 01:21:31 PM PST 24
Finished Jan 24 01:22:34 PM PST 24
Peak memory 195368 kb
Host smart-71b2259f-4518-4788-a78e-416275669690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509817877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2509817877
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.518789177
Short name T515
Test name
Test status
Simulation time 52386740 ps
CPU time 1.38 seconds
Started Jan 24 01:21:25 PM PST 24
Finished Jan 24 01:22:31 PM PST 24
Peak memory 196680 kb
Host smart-ba0ff60d-f660-45ad-b886-bf923262b74a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518789177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.518789177
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3289573654
Short name T344
Test name
Test status
Simulation time 9024080264 ps
CPU time 29.49 seconds
Started Jan 24 01:21:27 PM PST 24
Finished Jan 24 01:23:00 PM PST 24
Peak memory 198300 kb
Host smart-ed1b19b5-718f-40f4-8760-82761e843881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289573654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3289573654
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.656846405
Short name T417
Test name
Test status
Simulation time 104997332363 ps
CPU time 427.74 seconds
Started Jan 24 01:21:27 PM PST 24
Finished Jan 24 01:29:39 PM PST 24
Peak memory 198412 kb
Host smart-4ad03e3a-175e-4cb8-a0e4-e838b0fe8f6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=656846405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.656846405
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.379269971
Short name T294
Test name
Test status
Simulation time 20567521 ps
CPU time 0.57 seconds
Started Jan 24 01:24:36 PM PST 24
Finished Jan 24 01:25:07 PM PST 24
Peak memory 193348 kb
Host smart-c8bab09c-13d6-44ed-9f8e-87e096c624b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379269971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.379269971
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.381174137
Short name T874
Test name
Test status
Simulation time 95070639 ps
CPU time 0.79 seconds
Started Jan 24 01:24:36 PM PST 24
Finished Jan 24 01:25:07 PM PST 24
Peak memory 195360 kb
Host smart-bc6651de-c987-4f4f-9066-45969f1f4338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381174137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.381174137
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1134406576
Short name T819
Test name
Test status
Simulation time 6673041951 ps
CPU time 25.95 seconds
Started Jan 24 01:24:34 PM PST 24
Finished Jan 24 01:25:31 PM PST 24
Peak memory 197124 kb
Host smart-e5b31e55-3205-4a0d-93ba-5fa91703edac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134406576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1134406576
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.163549508
Short name T56
Test name
Test status
Simulation time 77393334 ps
CPU time 0.96 seconds
Started Jan 24 01:24:34 PM PST 24
Finished Jan 24 01:25:06 PM PST 24
Peak memory 196728 kb
Host smart-38c28f6d-08e6-474e-8fe3-4cb033d7faaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163549508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.163549508
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.483370886
Short name T303
Test name
Test status
Simulation time 120411013 ps
CPU time 0.82 seconds
Started Jan 24 01:24:30 PM PST 24
Finished Jan 24 01:25:00 PM PST 24
Peak memory 195760 kb
Host smart-5e466830-bede-47ad-9cdc-dd11f138390f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483370886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.483370886
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2879476577
Short name T258
Test name
Test status
Simulation time 110879854 ps
CPU time 2.25 seconds
Started Jan 24 01:24:36 PM PST 24
Finished Jan 24 01:25:09 PM PST 24
Peak memory 197552 kb
Host smart-82967546-bc11-474e-a566-d6373ddce3ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879476577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2879476577
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2969952963
Short name T355
Test name
Test status
Simulation time 359258124 ps
CPU time 2.65 seconds
Started Jan 24 01:24:40 PM PST 24
Finished Jan 24 01:25:15 PM PST 24
Peak memory 196644 kb
Host smart-04ed74ed-3f48-4713-8f6a-1d78c743503b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969952963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2969952963
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.780891787
Short name T690
Test name
Test status
Simulation time 292546991 ps
CPU time 1 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 196804 kb
Host smart-deb5f3ca-b075-444e-9abe-a19f9182900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780891787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.780891787
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3393517221
Short name T622
Test name
Test status
Simulation time 20737755 ps
CPU time 0.81 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 196708 kb
Host smart-9f1f8752-9ca3-44f5-baba-c9c59d252522
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393517221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3393517221
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.631182943
Short name T257
Test name
Test status
Simulation time 197050123 ps
CPU time 2.85 seconds
Started Jan 24 01:24:32 PM PST 24
Finished Jan 24 01:25:05 PM PST 24
Peak memory 198112 kb
Host smart-fbd2e610-ca86-4c42-9d84-208ad2d1c094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631182943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.631182943
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4282116928
Short name T626
Test name
Test status
Simulation time 38808686 ps
CPU time 0.98 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 196652 kb
Host smart-56130f6a-5661-4964-a072-211c437d0325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282116928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4282116928
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1826042195
Short name T614
Test name
Test status
Simulation time 42751748 ps
CPU time 0.9 seconds
Started Jan 24 01:24:24 PM PST 24
Finished Jan 24 01:24:56 PM PST 24
Peak memory 196224 kb
Host smart-ddbd823f-3e37-4f7a-8aaf-483232cf69b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826042195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1826042195
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.76188900
Short name T866
Test name
Test status
Simulation time 7941420330 ps
CPU time 29.29 seconds
Started Jan 24 01:24:34 PM PST 24
Finished Jan 24 01:25:34 PM PST 24
Peak memory 198332 kb
Host smart-d68ba81d-5524-4fe2-b174-9f1378376472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76188900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gp
io_stress_all.76188900
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1144624518
Short name T427
Test name
Test status
Simulation time 228165904535 ps
CPU time 779.34 seconds
Started Jan 24 01:24:35 PM PST 24
Finished Jan 24 01:38:06 PM PST 24
Peak memory 198372 kb
Host smart-49d77230-a3a9-4473-b977-9cd3ad23cdb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1144624518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1144624518
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3331433649
Short name T388
Test name
Test status
Simulation time 11921325 ps
CPU time 0.57 seconds
Started Jan 24 01:24:48 PM PST 24
Finished Jan 24 01:25:21 PM PST 24
Peak memory 193976 kb
Host smart-d80a3a03-470d-451c-a487-9a52229dae6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331433649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3331433649
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1476436440
Short name T313
Test name
Test status
Simulation time 40848429 ps
CPU time 0.85 seconds
Started Jan 24 01:24:38 PM PST 24
Finished Jan 24 01:25:10 PM PST 24
Peak memory 195464 kb
Host smart-9ff39323-5ca7-4ace-ae1f-56d1b712f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476436440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1476436440
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4145982110
Short name T276
Test name
Test status
Simulation time 746220311 ps
CPU time 13.24 seconds
Started Jan 24 01:24:38 PM PST 24
Finished Jan 24 01:25:23 PM PST 24
Peak memory 195712 kb
Host smart-adda364d-1664-478a-8100-884b983447ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145982110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4145982110
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3073017439
Short name T454
Test name
Test status
Simulation time 306125103 ps
CPU time 0.95 seconds
Started Jan 24 01:24:48 PM PST 24
Finished Jan 24 01:25:21 PM PST 24
Peak memory 198036 kb
Host smart-36ceacd1-e10f-47fb-a1be-b5e035853e68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073017439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3073017439
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1805356331
Short name T701
Test name
Test status
Simulation time 417997673 ps
CPU time 1.12 seconds
Started Jan 24 01:24:35 PM PST 24
Finished Jan 24 01:25:07 PM PST 24
Peak memory 196664 kb
Host smart-992e94b9-d03c-4206-88e4-4e360135d09b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805356331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1805356331
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2585996752
Short name T576
Test name
Test status
Simulation time 83927730 ps
CPU time 3.32 seconds
Started Jan 24 01:24:34 PM PST 24
Finished Jan 24 01:25:09 PM PST 24
Peak memory 196580 kb
Host smart-8f74fd89-03e1-4624-81c2-f829ef7e92d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585996752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2585996752
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1564675976
Short name T669
Test name
Test status
Simulation time 478147401 ps
CPU time 3.62 seconds
Started Jan 24 01:24:37 PM PST 24
Finished Jan 24 01:25:12 PM PST 24
Peak memory 198256 kb
Host smart-5c6f3a66-3d44-48d9-a210-83be7cda62dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564675976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1564675976
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.436245232
Short name T234
Test name
Test status
Simulation time 72475564 ps
CPU time 0.9 seconds
Started Jan 24 01:24:40 PM PST 24
Finished Jan 24 01:25:13 PM PST 24
Peak memory 196152 kb
Host smart-8a662df5-e1b5-4ac1-9c9c-0f4a5fb66567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436245232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.436245232
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2592183352
Short name T326
Test name
Test status
Simulation time 132165608 ps
CPU time 0.76 seconds
Started Jan 24 01:24:36 PM PST 24
Finished Jan 24 01:25:08 PM PST 24
Peak memory 195628 kb
Host smart-46ff6280-facf-4326-bb96-75c875463dc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592183352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2592183352
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1287653236
Short name T395
Test name
Test status
Simulation time 440329115 ps
CPU time 5.51 seconds
Started Jan 24 01:24:33 PM PST 24
Finished Jan 24 01:25:09 PM PST 24
Peak memory 198160 kb
Host smart-5d82f8f0-7d56-432f-b135-5c04deaea7fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287653236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1287653236
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2886239376
Short name T356
Test name
Test status
Simulation time 206458654 ps
CPU time 1.37 seconds
Started Jan 24 01:24:39 PM PST 24
Finished Jan 24 01:25:12 PM PST 24
Peak memory 198144 kb
Host smart-b347bfc9-897d-4380-a05b-a9c4ddae687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886239376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2886239376
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.128483790
Short name T480
Test name
Test status
Simulation time 363135389 ps
CPU time 1.15 seconds
Started Jan 24 01:24:36 PM PST 24
Finished Jan 24 01:25:08 PM PST 24
Peak memory 196636 kb
Host smart-b10e0ae5-84ec-4df8-a310-b7eb8e8111fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128483790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.128483790
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1863073094
Short name T565
Test name
Test status
Simulation time 25159957092 ps
CPU time 179.58 seconds
Started Jan 24 01:24:41 PM PST 24
Finished Jan 24 01:28:13 PM PST 24
Peak memory 198300 kb
Host smart-165fbcf6-f758-4530-b58c-dc37fde4a5f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863073094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1863073094
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.718767525
Short name T555
Test name
Test status
Simulation time 111957377719 ps
CPU time 764.34 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:38:22 PM PST 24
Peak memory 206604 kb
Host smart-a82503d4-8938-4d57-baa4-67b66653e9c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=718767525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.718767525
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1237079364
Short name T321
Test name
Test status
Simulation time 21737096 ps
CPU time 0.63 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:25:40 PM PST 24
Peak memory 193988 kb
Host smart-bd254759-3a55-4718-b1f9-e1b88ed3bf61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237079364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1237079364
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2569890195
Short name T233
Test name
Test status
Simulation time 26658638 ps
CPU time 0.62 seconds
Started Jan 24 01:24:43 PM PST 24
Finished Jan 24 01:25:16 PM PST 24
Peak memory 194128 kb
Host smart-a1000c5c-2fbf-458a-aea9-8f86565f9f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569890195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2569890195
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.501013651
Short name T740
Test name
Test status
Simulation time 457229531 ps
CPU time 23.2 seconds
Started Jan 24 01:24:46 PM PST 24
Finished Jan 24 01:25:41 PM PST 24
Peak memory 195704 kb
Host smart-ddf02495-3454-47c0-8b88-3d7b50597778
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501013651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.501013651
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2738223695
Short name T817
Test name
Test status
Simulation time 100214930 ps
CPU time 0.62 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:25:40 PM PST 24
Peak memory 195252 kb
Host smart-645bb5be-f9b0-436e-a8e6-02a274d7f90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738223695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2738223695
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.52235805
Short name T619
Test name
Test status
Simulation time 50001813 ps
CPU time 1.27 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:25:41 PM PST 24
Peak memory 197348 kb
Host smart-05237ac8-9f5c-4cc9-9767-978bafd08898
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52235805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.52235805
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1654950752
Short name T615
Test name
Test status
Simulation time 36315254 ps
CPU time 0.94 seconds
Started Jan 24 01:24:44 PM PST 24
Finished Jan 24 01:25:18 PM PST 24
Peak memory 196000 kb
Host smart-3f4b21e8-02a0-4910-8a7d-63bc1cca657d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654950752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1654950752
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1207058530
Short name T351
Test name
Test status
Simulation time 124498399 ps
CPU time 3.46 seconds
Started Jan 24 01:24:49 PM PST 24
Finished Jan 24 01:25:25 PM PST 24
Peak memory 197288 kb
Host smart-6ecc6a49-a604-4421-b3f7-a260b21e4040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207058530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1207058530
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3989751062
Short name T599
Test name
Test status
Simulation time 16453295 ps
CPU time 0.61 seconds
Started Jan 24 01:24:43 PM PST 24
Finished Jan 24 01:25:17 PM PST 24
Peak memory 194348 kb
Host smart-f975dd30-429d-4b96-8b31-1f7f783fb9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989751062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3989751062
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1352414399
Short name T478
Test name
Test status
Simulation time 53803068 ps
CPU time 1.16 seconds
Started Jan 24 01:24:46 PM PST 24
Finished Jan 24 01:25:18 PM PST 24
Peak memory 196856 kb
Host smart-a0be1f2f-e07b-4099-9b1f-e7e47d36c2e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352414399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1352414399
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.674946958
Short name T772
Test name
Test status
Simulation time 1023385807 ps
CPU time 2.97 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:25:41 PM PST 24
Peak memory 198064 kb
Host smart-e903e459-1243-41b8-9606-48d9fb70c5f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674946958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.674946958
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.828480367
Short name T880
Test name
Test status
Simulation time 72345676 ps
CPU time 0.87 seconds
Started Jan 24 01:24:43 PM PST 24
Finished Jan 24 01:25:16 PM PST 24
Peak memory 197140 kb
Host smart-78de2023-b4ed-4dd6-b62b-8bda75f799dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828480367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.828480367
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2686743914
Short name T780
Test name
Test status
Simulation time 72308253 ps
CPU time 0.95 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:25:40 PM PST 24
Peak memory 197392 kb
Host smart-1b341c5a-eaf7-437d-9af3-29f6befb224d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686743914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2686743914
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.646176197
Short name T867
Test name
Test status
Simulation time 23130815605 ps
CPU time 74.15 seconds
Started Jan 24 01:24:46 PM PST 24
Finished Jan 24 01:26:32 PM PST 24
Peak memory 198312 kb
Host smart-05f23804-91f1-444a-b9e2-b542deac87c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646176197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.646176197
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.957290388
Short name T796
Test name
Test status
Simulation time 21503959046 ps
CPU time 365.88 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:31:44 PM PST 24
Peak memory 198452 kb
Host smart-6a748616-3530-401a-82dc-7f7a7bd4d595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=957290388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.957290388
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3844887108
Short name T473
Test name
Test status
Simulation time 24453034 ps
CPU time 0.58 seconds
Started Jan 24 01:24:56 PM PST 24
Finished Jan 24 01:25:28 PM PST 24
Peak memory 194156 kb
Host smart-bd4c1be4-3ed2-464f-a70b-aa603c76be55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844887108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3844887108
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2769754703
Short name T374
Test name
Test status
Simulation time 46628208 ps
CPU time 0.65 seconds
Started Jan 24 01:24:56 PM PST 24
Finished Jan 24 01:25:28 PM PST 24
Peak memory 193976 kb
Host smart-7c8e561a-9849-46f7-8fb7-5edde88eda60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769754703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2769754703
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1902500111
Short name T448
Test name
Test status
Simulation time 201350422 ps
CPU time 11.03 seconds
Started Jan 24 01:25:00 PM PST 24
Finished Jan 24 01:25:44 PM PST 24
Peak memory 196972 kb
Host smart-dfa1b605-3333-4029-aaa8-d17a62667408
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902500111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1902500111
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.839491039
Short name T872
Test name
Test status
Simulation time 33744664 ps
CPU time 0.72 seconds
Started Jan 24 01:24:52 PM PST 24
Finished Jan 24 01:25:25 PM PST 24
Peak memory 195612 kb
Host smart-3623eb9b-0dcb-4ae2-8f68-da86091e9d8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839491039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.839491039
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3992768623
Short name T644
Test name
Test status
Simulation time 47475282 ps
CPU time 0.86 seconds
Started Jan 24 01:25:00 PM PST 24
Finished Jan 24 01:25:34 PM PST 24
Peak memory 197512 kb
Host smart-357b7004-2a06-4f6f-8a26-a287f37ac1a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992768623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3992768623
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1641291705
Short name T542
Test name
Test status
Simulation time 65520873 ps
CPU time 2.52 seconds
Started Jan 24 01:24:54 PM PST 24
Finished Jan 24 01:25:27 PM PST 24
Peak memory 196596 kb
Host smart-d314533f-3cad-44b0-bdfb-cedab648406d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641291705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1641291705
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1195447283
Short name T602
Test name
Test status
Simulation time 79539822 ps
CPU time 1.85 seconds
Started Jan 24 01:24:53 PM PST 24
Finished Jan 24 01:25:27 PM PST 24
Peak memory 196272 kb
Host smart-a09a5f0c-112c-4957-b704-fae63f862fe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195447283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1195447283
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2130020281
Short name T455
Test name
Test status
Simulation time 91134586 ps
CPU time 1.06 seconds
Started Jan 24 01:24:44 PM PST 24
Finished Jan 24 01:25:18 PM PST 24
Peak memory 196792 kb
Host smart-edf9546a-c362-4a3e-81a7-362688fa4208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130020281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2130020281
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2164246878
Short name T624
Test name
Test status
Simulation time 101379315 ps
CPU time 1.11 seconds
Started Jan 24 01:24:46 PM PST 24
Finished Jan 24 01:25:19 PM PST 24
Peak memory 197068 kb
Host smart-2af01c58-ed7d-4e87-8037-ca0dbef89369
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164246878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2164246878
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3238766301
Short name T426
Test name
Test status
Simulation time 1646322893 ps
CPU time 5.29 seconds
Started Jan 24 01:24:54 PM PST 24
Finished Jan 24 01:25:31 PM PST 24
Peak memory 198176 kb
Host smart-1d7b9b26-f096-4a26-99dd-616bc606cba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238766301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3238766301
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2239789101
Short name T482
Test name
Test status
Simulation time 1326116730 ps
CPU time 1.26 seconds
Started Jan 24 01:24:43 PM PST 24
Finished Jan 24 01:25:17 PM PST 24
Peak memory 195564 kb
Host smart-d22e44aa-66df-4958-a9e3-eb87a4a85bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239789101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2239789101
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2179164431
Short name T832
Test name
Test status
Simulation time 29293324 ps
CPU time 0.87 seconds
Started Jan 24 01:24:46 PM PST 24
Finished Jan 24 01:25:19 PM PST 24
Peak memory 196228 kb
Host smart-63abd596-7c03-458f-a8d2-464ba6f42964
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179164431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2179164431
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.451845303
Short name T45
Test name
Test status
Simulation time 9823660056 ps
CPU time 118.31 seconds
Started Jan 24 01:25:00 PM PST 24
Finished Jan 24 01:27:32 PM PST 24
Peak memory 198236 kb
Host smart-17608267-2cac-4f82-be09-b0ad27770e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451845303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.451845303
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1837743174
Short name T79
Test name
Test status
Simulation time 69391418981 ps
CPU time 255.02 seconds
Started Jan 24 01:25:00 PM PST 24
Finished Jan 24 01:29:48 PM PST 24
Peak memory 198392 kb
Host smart-f4bd284a-7b14-41b3-833a-a137708dec52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1837743174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1837743174
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1397502021
Short name T754
Test name
Test status
Simulation time 124572839 ps
CPU time 0.55 seconds
Started Jan 24 01:25:06 PM PST 24
Finished Jan 24 01:25:44 PM PST 24
Peak memory 194160 kb
Host smart-b6315113-2293-4d83-a842-718763cbd98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397502021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1397502021
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3052365788
Short name T398
Test name
Test status
Simulation time 45260387 ps
CPU time 0.7 seconds
Started Jan 24 01:24:54 PM PST 24
Finished Jan 24 01:25:26 PM PST 24
Peak memory 194900 kb
Host smart-54b2fac3-5713-4da6-9b18-c68c36a694c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052365788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3052365788
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2885940175
Short name T574
Test name
Test status
Simulation time 3091825071 ps
CPU time 20.31 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:26:00 PM PST 24
Peak memory 196856 kb
Host smart-1d82a6de-7f7e-4d80-a029-0864db033813
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885940175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2885940175
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4143191877
Short name T382
Test name
Test status
Simulation time 76617179 ps
CPU time 0.78 seconds
Started Jan 24 01:24:53 PM PST 24
Finished Jan 24 01:25:26 PM PST 24
Peak memory 195920 kb
Host smart-465e7e19-8cb6-4856-a857-6f8910b792ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143191877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4143191877
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.764179278
Short name T736
Test name
Test status
Simulation time 76245208 ps
CPU time 1.25 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:25:40 PM PST 24
Peak memory 197304 kb
Host smart-37fc5d00-6e7e-4e0a-bb32-065dd491f6e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764179278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.764179278
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2987373693
Short name T588
Test name
Test status
Simulation time 110954719 ps
CPU time 2.19 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:25:41 PM PST 24
Peak memory 198024 kb
Host smart-6e299405-4235-499f-9a25-5e9005a4d586
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987373693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2987373693
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.875396661
Short name T370
Test name
Test status
Simulation time 246488572 ps
CPU time 1.43 seconds
Started Jan 24 01:24:57 PM PST 24
Finished Jan 24 01:25:30 PM PST 24
Peak memory 196360 kb
Host smart-0bd91dc6-b20d-4c62-b3a4-6bcae16f5dd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875396661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
875396661
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3350228592
Short name T408
Test name
Test status
Simulation time 179401603 ps
CPU time 0.76 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:25:40 PM PST 24
Peak memory 195580 kb
Host smart-0552122c-cab8-4ff6-90b9-3aa805420cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350228592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3350228592
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3179449908
Short name T778
Test name
Test status
Simulation time 24362273 ps
CPU time 0.98 seconds
Started Jan 24 01:24:54 PM PST 24
Finished Jan 24 01:25:27 PM PST 24
Peak memory 196644 kb
Host smart-435cbb2b-8c67-4f89-a4a3-d45630b73f5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179449908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3179449908
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3325778666
Short name T608
Test name
Test status
Simulation time 611274497 ps
CPU time 6.06 seconds
Started Jan 24 01:24:55 PM PST 24
Finished Jan 24 01:25:32 PM PST 24
Peak memory 198200 kb
Host smart-3d193af3-7737-422d-9c88-c24c97343935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325778666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3325778666
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4027811560
Short name T312
Test name
Test status
Simulation time 29736865 ps
CPU time 0.93 seconds
Started Jan 24 01:24:57 PM PST 24
Finished Jan 24 01:25:30 PM PST 24
Peak memory 195888 kb
Host smart-4535e2c2-c352-4d8e-97bb-abe0cbcc7b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027811560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4027811560
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3016688413
Short name T774
Test name
Test status
Simulation time 177257212 ps
CPU time 1.04 seconds
Started Jan 24 01:24:56 PM PST 24
Finished Jan 24 01:25:28 PM PST 24
Peak memory 195844 kb
Host smart-4bb8ee00-90bf-40ae-a2bc-31c56155f7dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016688413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3016688413
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3556254134
Short name T264
Test name
Test status
Simulation time 12843382190 ps
CPU time 84.21 seconds
Started Jan 24 01:24:57 PM PST 24
Finished Jan 24 01:26:53 PM PST 24
Peak memory 198328 kb
Host smart-f70b22c2-61dc-45a6-ab7f-f19faa753193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556254134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3556254134
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3213296990
Short name T822
Test name
Test status
Simulation time 82483228609 ps
CPU time 1218.17 seconds
Started Jan 24 01:25:08 PM PST 24
Finished Jan 24 01:46:04 PM PST 24
Peak memory 198404 kb
Host smart-80c75905-62c4-4dcf-aef1-bbcc59e2d188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3213296990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3213296990
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2446852709
Short name T661
Test name
Test status
Simulation time 36750686 ps
CPU time 0.56 seconds
Started Jan 24 01:25:07 PM PST 24
Finished Jan 24 01:25:45 PM PST 24
Peak memory 194684 kb
Host smart-cc1a623b-66c9-4c4d-a9f5-64a6ea9f5e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446852709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2446852709
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3470639561
Short name T820
Test name
Test status
Simulation time 90739863 ps
CPU time 0.7 seconds
Started Jan 24 01:25:02 PM PST 24
Finished Jan 24 01:25:37 PM PST 24
Peak memory 194884 kb
Host smart-fa8c9182-76bd-4e9d-aae5-2a3a2f203203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470639561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3470639561
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3153583626
Short name T330
Test name
Test status
Simulation time 1209691300 ps
CPU time 9.58 seconds
Started Jan 24 01:25:10 PM PST 24
Finished Jan 24 01:26:01 PM PST 24
Peak memory 197160 kb
Host smart-afd61c76-7535-4a5b-8f0b-08c154e4505b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153583626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3153583626
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.297782921
Short name T340
Test name
Test status
Simulation time 533901689 ps
CPU time 0.95 seconds
Started Jan 24 01:25:07 PM PST 24
Finished Jan 24 01:25:45 PM PST 24
Peak memory 196800 kb
Host smart-9150f820-6d4a-48b2-8124-ae01cdc3fa4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297782921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.297782921
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3268333385
Short name T495
Test name
Test status
Simulation time 126709397 ps
CPU time 0.83 seconds
Started Jan 24 01:25:09 PM PST 24
Finished Jan 24 01:25:52 PM PST 24
Peak memory 196240 kb
Host smart-0d0e4e1b-b95c-446f-be99-d90e241dd7a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268333385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3268333385
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1282519564
Short name T587
Test name
Test status
Simulation time 52587076 ps
CPU time 2.05 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:25:40 PM PST 24
Peak memory 196512 kb
Host smart-dd5cc482-a7c9-477b-8a58-bfa0dbc58d61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282519564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1282519564
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.534042189
Short name T341
Test name
Test status
Simulation time 139576271 ps
CPU time 1.32 seconds
Started Jan 24 01:25:06 PM PST 24
Finished Jan 24 01:25:44 PM PST 24
Peak memory 196960 kb
Host smart-f2f154e9-8f89-4ddb-a067-5a8f1dc85576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534042189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
534042189
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1849779509
Short name T571
Test name
Test status
Simulation time 118491107 ps
CPU time 0.86 seconds
Started Jan 24 01:25:11 PM PST 24
Finished Jan 24 01:25:53 PM PST 24
Peak memory 197304 kb
Host smart-9873720f-49b2-4709-990c-ba69fbb06c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849779509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1849779509
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4147683417
Short name T856
Test name
Test status
Simulation time 23756251 ps
CPU time 0.67 seconds
Started Jan 24 01:25:11 PM PST 24
Finished Jan 24 01:25:53 PM PST 24
Peak memory 194368 kb
Host smart-114aae4e-63f6-4118-9436-0cfb52f6df11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147683417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4147683417
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4071849457
Short name T596
Test name
Test status
Simulation time 662302969 ps
CPU time 2.42 seconds
Started Jan 24 02:04:17 PM PST 24
Finished Jan 24 02:05:12 PM PST 24
Peak memory 198096 kb
Host smart-6e105e6b-dc9f-4fce-adb5-722aace94acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071849457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4071849457
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3150798797
Short name T295
Test name
Test status
Simulation time 113803345 ps
CPU time 0.95 seconds
Started Jan 24 01:25:06 PM PST 24
Finished Jan 24 01:25:44 PM PST 24
Peak memory 196700 kb
Host smart-514d9bde-b888-40bf-872a-770c464795ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150798797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3150798797
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2538854646
Short name T658
Test name
Test status
Simulation time 80978133 ps
CPU time 0.92 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:25:39 PM PST 24
Peak memory 196992 kb
Host smart-84256f61-564b-4f01-9be9-ff8b38bd2070
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538854646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2538854646
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2158923249
Short name T597
Test name
Test status
Simulation time 13501826658 ps
CPU time 89.83 seconds
Started Jan 24 01:33:35 PM PST 24
Finished Jan 24 01:35:36 PM PST 24
Peak memory 198368 kb
Host smart-6604d23e-ced5-4a9f-89bd-fda6f83501d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158923249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2158923249
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2512859538
Short name T73
Test name
Test status
Simulation time 12881748606 ps
CPU time 448.2 seconds
Started Jan 24 01:25:05 PM PST 24
Finished Jan 24 01:33:08 PM PST 24
Peak memory 198432 kb
Host smart-f48f3449-784a-44fe-9e6c-e930cd655a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2512859538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2512859538
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1029366652
Short name T70
Test name
Test status
Simulation time 18309540 ps
CPU time 0.59 seconds
Started Jan 24 01:37:11 PM PST 24
Finished Jan 24 01:37:52 PM PST 24
Peak memory 193972 kb
Host smart-a296fd99-8724-4c45-a963-f4a1b62331dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029366652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1029366652
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2304308199
Short name T352
Test name
Test status
Simulation time 35364976 ps
CPU time 0.85 seconds
Started Jan 24 01:25:07 PM PST 24
Finished Jan 24 01:25:46 PM PST 24
Peak memory 197272 kb
Host smart-b2e5bc6e-0c90-4fe6-973d-140e4208c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304308199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2304308199
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1448034302
Short name T368
Test name
Test status
Simulation time 13950656433 ps
CPU time 19.78 seconds
Started Jan 24 01:39:19 PM PST 24
Finished Jan 24 01:39:42 PM PST 24
Peak memory 196884 kb
Host smart-c8e38771-40db-4e60-98f0-e0bb03dfd819
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448034302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1448034302
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2366742410
Short name T675
Test name
Test status
Simulation time 55870128 ps
CPU time 0.9 seconds
Started Jan 24 01:32:48 PM PST 24
Finished Jan 24 01:33:22 PM PST 24
Peak memory 197336 kb
Host smart-a5761a84-fb65-4d75-a2e6-75b27461d3c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366742410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2366742410
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2401342344
Short name T721
Test name
Test status
Simulation time 745965383 ps
CPU time 1.12 seconds
Started Jan 24 01:25:09 PM PST 24
Finished Jan 24 01:25:49 PM PST 24
Peak memory 196828 kb
Host smart-ca940a11-91c7-4fc6-aaf2-3e85e27ac8fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401342344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2401342344
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1245700457
Short name T486
Test name
Test status
Simulation time 97743382 ps
CPU time 3.65 seconds
Started Jan 24 01:25:09 PM PST 24
Finished Jan 24 01:25:52 PM PST 24
Peak memory 198184 kb
Host smart-41e1e7f7-8798-4bd9-9173-248224a6bed5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245700457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1245700457
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2457772165
Short name T715
Test name
Test status
Simulation time 571228320 ps
CPU time 2.21 seconds
Started Jan 24 01:25:08 PM PST 24
Finished Jan 24 01:25:48 PM PST 24
Peak memory 197076 kb
Host smart-c4318a53-b38b-4908-87de-b8f7cbcd54b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457772165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2457772165
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4024608593
Short name T435
Test name
Test status
Simulation time 97645514 ps
CPU time 1.2 seconds
Started Jan 24 01:25:07 PM PST 24
Finished Jan 24 01:25:45 PM PST 24
Peak memory 197144 kb
Host smart-d9c7f426-21de-4c58-84d1-64044f8cc87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024608593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4024608593
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2502619052
Short name T829
Test name
Test status
Simulation time 27699430 ps
CPU time 0.72 seconds
Started Jan 24 01:25:06 PM PST 24
Finished Jan 24 01:25:44 PM PST 24
Peak memory 195484 kb
Host smart-4f5801cc-98af-492b-ae0a-eb1d7155e09f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502619052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2502619052
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2227396824
Short name T444
Test name
Test status
Simulation time 488268720 ps
CPU time 1.56 seconds
Started Jan 24 01:25:19 PM PST 24
Finished Jan 24 01:26:07 PM PST 24
Peak memory 197924 kb
Host smart-574f0c3b-6b22-4ff7-a2cd-0e0089b73f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227396824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2227396824
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.23222424
Short name T75
Test name
Test status
Simulation time 86901236 ps
CPU time 0.69 seconds
Started Jan 24 01:25:04 PM PST 24
Finished Jan 24 01:25:39 PM PST 24
Peak memory 194312 kb
Host smart-0e74fb72-57ac-4a26-b6c9-492af0a801d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23222424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.23222424
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3719166756
Short name T710
Test name
Test status
Simulation time 139192100 ps
CPU time 1.09 seconds
Started Jan 24 01:25:11 PM PST 24
Finished Jan 24 01:25:54 PM PST 24
Peak memory 196740 kb
Host smart-7d79ed4b-2673-4e93-ad93-b064f5eb4d92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719166756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3719166756
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.322416060
Short name T730
Test name
Test status
Simulation time 3145680548 ps
CPU time 41.64 seconds
Started Jan 24 01:35:45 PM PST 24
Finished Jan 24 01:36:53 PM PST 24
Peak memory 198316 kb
Host smart-e7f9bd3c-d77c-4971-8c34-6d7cc67099d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322416060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.322416060
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1057849859
Short name T698
Test name
Test status
Simulation time 125413267316 ps
CPU time 846.53 seconds
Started Jan 24 01:25:16 PM PST 24
Finished Jan 24 01:40:08 PM PST 24
Peak memory 206608 kb
Host smart-324d21d8-afa4-45a8-ac45-acce8c543208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1057849859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1057849859
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3488806101
Short name T287
Test name
Test status
Simulation time 13168348 ps
CPU time 0.58 seconds
Started Jan 24 01:25:26 PM PST 24
Finished Jan 24 01:26:18 PM PST 24
Peak memory 194680 kb
Host smart-f8fb6b52-063d-46b5-9913-aeb2313cd08c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488806101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3488806101
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2773748222
Short name T298
Test name
Test status
Simulation time 265611087 ps
CPU time 0.7 seconds
Started Jan 24 01:25:24 PM PST 24
Finished Jan 24 01:26:14 PM PST 24
Peak memory 195884 kb
Host smart-cc61e478-d560-408e-9d76-c35246df68bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773748222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2773748222
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2439904557
Short name T850
Test name
Test status
Simulation time 824669111 ps
CPU time 19.84 seconds
Started Jan 24 01:25:19 PM PST 24
Finished Jan 24 01:26:25 PM PST 24
Peak memory 196856 kb
Host smart-39d377c5-26fd-4566-8bbf-f7c7971e85ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439904557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2439904557
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2496529873
Short name T262
Test name
Test status
Simulation time 188967823 ps
CPU time 0.77 seconds
Started Jan 24 01:25:25 PM PST 24
Finished Jan 24 01:26:16 PM PST 24
Peak memory 195976 kb
Host smart-9dfec230-c7f4-4718-84b8-488e19e54986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496529873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2496529873
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2592356553
Short name T582
Test name
Test status
Simulation time 191042109 ps
CPU time 0.91 seconds
Started Jan 24 01:25:20 PM PST 24
Finished Jan 24 01:26:08 PM PST 24
Peak memory 196556 kb
Host smart-d78a417e-a024-4233-b47e-fa07e864ab34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592356553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2592356553
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1668476988
Short name T537
Test name
Test status
Simulation time 52728362 ps
CPU time 1.51 seconds
Started Jan 24 01:25:25 PM PST 24
Finished Jan 24 01:26:17 PM PST 24
Peak memory 196448 kb
Host smart-808ff26f-79f5-48da-a494-6e4ecc3f58cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668476988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1668476988
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1626929050
Short name T791
Test name
Test status
Simulation time 453526582 ps
CPU time 2.38 seconds
Started Jan 24 01:28:50 PM PST 24
Finished Jan 24 01:29:12 PM PST 24
Peak memory 198228 kb
Host smart-f0aeb6cd-0e9f-4247-849e-3e38dfa6db4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626929050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1626929050
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3332465450
Short name T854
Test name
Test status
Simulation time 270366462 ps
CPU time 1.29 seconds
Started Jan 24 01:25:15 PM PST 24
Finished Jan 24 01:26:00 PM PST 24
Peak memory 197088 kb
Host smart-f45cd63b-e65b-4fb1-8335-5c1729502f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332465450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3332465450
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3028038561
Short name T329
Test name
Test status
Simulation time 291370083 ps
CPU time 1.36 seconds
Started Jan 24 01:50:05 PM PST 24
Finished Jan 24 01:50:08 PM PST 24
Peak memory 197124 kb
Host smart-5a97c351-4e5b-40bc-a12f-f462b2370544
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028038561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3028038561
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2953004025
Short name T600
Test name
Test status
Simulation time 109457515 ps
CPU time 4.91 seconds
Started Jan 24 02:21:54 PM PST 24
Finished Jan 24 02:22:52 PM PST 24
Peak memory 198156 kb
Host smart-877b95f7-7135-4680-ab46-73920e948f19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953004025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2953004025
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1226390859
Short name T311
Test name
Test status
Simulation time 139007253 ps
CPU time 1.34 seconds
Started Jan 24 01:25:18 PM PST 24
Finished Jan 24 01:26:05 PM PST 24
Peak memory 198116 kb
Host smart-8faebd24-1cd8-455d-86b5-5776c60f551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226390859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1226390859
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3717371304
Short name T849
Test name
Test status
Simulation time 83470774 ps
CPU time 1.24 seconds
Started Jan 24 01:25:20 PM PST 24
Finished Jan 24 01:26:08 PM PST 24
Peak memory 196940 kb
Host smart-46b1039d-b691-4954-8e06-b7781aa87878
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717371304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3717371304
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1222639205
Short name T365
Test name
Test status
Simulation time 1565773330 ps
CPU time 39.03 seconds
Started Jan 24 01:25:22 PM PST 24
Finished Jan 24 01:26:49 PM PST 24
Peak memory 198240 kb
Host smart-fa723c8e-940f-4827-ba80-8473c6d53228
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222639205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1222639205
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.352987028
Short name T334
Test name
Test status
Simulation time 154193906361 ps
CPU time 2254.34 seconds
Started Jan 24 01:25:33 PM PST 24
Finished Jan 24 02:03:58 PM PST 24
Peak memory 206652 kb
Host smart-167e32aa-883c-41c6-9d04-ab32ed73a600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=352987028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.352987028
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2485744063
Short name T445
Test name
Test status
Simulation time 26234108 ps
CPU time 0.58 seconds
Started Jan 24 01:25:38 PM PST 24
Finished Jan 24 01:26:28 PM PST 24
Peak memory 193968 kb
Host smart-98c4577d-35b5-4166-b255-057998fd6cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485744063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2485744063
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4011381469
Short name T322
Test name
Test status
Simulation time 25976858 ps
CPU time 0.67 seconds
Started Jan 24 01:25:27 PM PST 24
Finished Jan 24 01:26:19 PM PST 24
Peak memory 194092 kb
Host smart-27d2e6e4-0c51-42db-9abd-bcbc30789e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011381469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4011381469
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2839590154
Short name T705
Test name
Test status
Simulation time 2690685755 ps
CPU time 21.74 seconds
Started Jan 24 01:25:38 PM PST 24
Finished Jan 24 01:26:49 PM PST 24
Peak memory 196852 kb
Host smart-d9187da2-a325-41ed-a53e-f09a440a64a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839590154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2839590154
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2735586477
Short name T876
Test name
Test status
Simulation time 57390202 ps
CPU time 0.94 seconds
Started Jan 24 01:25:38 PM PST 24
Finished Jan 24 01:26:28 PM PST 24
Peak memory 197808 kb
Host smart-60e1eed6-dabf-42c2-8129-b5ed93dfe55e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735586477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2735586477
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.4031993046
Short name T224
Test name
Test status
Simulation time 25865189 ps
CPU time 0.73 seconds
Started Jan 24 01:25:30 PM PST 24
Finished Jan 24 01:26:22 PM PST 24
Peak memory 194396 kb
Host smart-20eae47a-e803-429a-80be-d8f22c106020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031993046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4031993046
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3016350794
Short name T783
Test name
Test status
Simulation time 20979914 ps
CPU time 0.93 seconds
Started Jan 24 01:25:35 PM PST 24
Finished Jan 24 01:26:26 PM PST 24
Peak memory 196272 kb
Host smart-036d437c-5741-420b-96ff-81cf6205e690
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016350794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3016350794
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.888831414
Short name T594
Test name
Test status
Simulation time 44009852 ps
CPU time 1.38 seconds
Started Jan 24 01:25:30 PM PST 24
Finished Jan 24 01:26:22 PM PST 24
Peak memory 196588 kb
Host smart-3273dfea-a0fa-4453-875e-10c0fa085e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888831414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
888831414
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3723154152
Short name T745
Test name
Test status
Simulation time 106075946 ps
CPU time 1.07 seconds
Started Jan 24 01:25:23 PM PST 24
Finished Jan 24 01:26:13 PM PST 24
Peak memory 198152 kb
Host smart-1c258fea-18c0-4c5d-b0ef-44d7c2d04b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723154152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3723154152
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2888503393
Short name T413
Test name
Test status
Simulation time 22330477 ps
CPU time 0.67 seconds
Started Jan 24 01:25:29 PM PST 24
Finished Jan 24 01:26:21 PM PST 24
Peak memory 195124 kb
Host smart-7dba809f-aeb2-4813-a03c-5146ea6acda5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888503393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2888503393
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3893427623
Short name T432
Test name
Test status
Simulation time 117763379 ps
CPU time 5.3 seconds
Started Jan 24 01:25:43 PM PST 24
Finished Jan 24 01:26:35 PM PST 24
Peak memory 198120 kb
Host smart-e04ea035-d574-41ef-927c-681845edb4dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893427623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3893427623
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2310571468
Short name T347
Test name
Test status
Simulation time 374990725 ps
CPU time 1.02 seconds
Started Jan 24 01:25:28 PM PST 24
Finished Jan 24 01:26:21 PM PST 24
Peak memory 195996 kb
Host smart-a21f99de-1c99-43fd-a706-f77ae8d48c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310571468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2310571468
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2598277570
Short name T709
Test name
Test status
Simulation time 111262906 ps
CPU time 1.1 seconds
Started Jan 24 01:25:33 PM PST 24
Finished Jan 24 01:26:24 PM PST 24
Peak memory 196668 kb
Host smart-303f0bca-cd41-48cd-9a9d-cfdf9d143a34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598277570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2598277570
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.961818212
Short name T239
Test name
Test status
Simulation time 46155309571 ps
CPU time 76.07 seconds
Started Jan 24 01:25:43 PM PST 24
Finished Jan 24 01:27:46 PM PST 24
Peak memory 198196 kb
Host smart-79529ede-1dea-4024-8fe8-5d6ddb9c85a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961818212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.961818212
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2436064472
Short name T868
Test name
Test status
Simulation time 1553717233529 ps
CPU time 1301.16 seconds
Started Jan 24 01:25:39 PM PST 24
Finished Jan 24 01:48:09 PM PST 24
Peak memory 198440 kb
Host smart-709c1114-b2eb-4a9d-b93f-c9c4648a6100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2436064472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2436064472
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4134819354
Short name T74
Test name
Test status
Simulation time 12437652 ps
CPU time 0.57 seconds
Started Jan 24 01:25:55 PM PST 24
Finished Jan 24 01:26:45 PM PST 24
Peak memory 193864 kb
Host smart-7bdd974f-d82a-4aa6-a3d7-4aa620199921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134819354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4134819354
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1056491010
Short name T366
Test name
Test status
Simulation time 108304110 ps
CPU time 0.78 seconds
Started Jan 24 01:25:38 PM PST 24
Finished Jan 24 01:26:28 PM PST 24
Peak memory 195508 kb
Host smart-90fe76d2-a1e8-49c7-9b44-d140a5b0f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056491010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1056491010
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3251764241
Short name T502
Test name
Test status
Simulation time 146883419 ps
CPU time 5.09 seconds
Started Jan 24 01:25:41 PM PST 24
Finished Jan 24 01:26:34 PM PST 24
Peak memory 196360 kb
Host smart-e79ce1e7-96b4-4c81-bc6d-323fd772ec8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251764241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3251764241
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1052357146
Short name T653
Test name
Test status
Simulation time 50319355 ps
CPU time 0.88 seconds
Started Jan 24 01:25:41 PM PST 24
Finished Jan 24 01:26:30 PM PST 24
Peak memory 196852 kb
Host smart-838b86ab-f0f7-4505-87a8-7c62ed19c90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052357146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1052357146
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3992125956
Short name T834
Test name
Test status
Simulation time 175290152 ps
CPU time 1.67 seconds
Started Jan 24 01:25:41 PM PST 24
Finished Jan 24 01:26:30 PM PST 24
Peak memory 196524 kb
Host smart-6090ff57-8a76-4000-8bb9-0d668b1a60c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992125956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3992125956
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1875816222
Short name T240
Test name
Test status
Simulation time 416468697 ps
CPU time 2.38 seconds
Started Jan 24 01:25:41 PM PST 24
Finished Jan 24 01:26:31 PM PST 24
Peak memory 196664 kb
Host smart-fa988371-0bb5-4332-b882-14bb9f3a6bdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875816222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1875816222
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2157484220
Short name T681
Test name
Test status
Simulation time 21669355 ps
CPU time 0.83 seconds
Started Jan 24 01:25:44 PM PST 24
Finished Jan 24 01:26:33 PM PST 24
Peak memory 197260 kb
Host smart-62190815-300a-471f-8274-1d3da5d8768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157484220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2157484220
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3258267235
Short name T828
Test name
Test status
Simulation time 77606676 ps
CPU time 0.93 seconds
Started Jan 24 01:25:43 PM PST 24
Finished Jan 24 01:26:31 PM PST 24
Peak memory 195832 kb
Host smart-44253829-8963-422d-9cd4-aeb491ab4efe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258267235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3258267235
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1301601148
Short name T654
Test name
Test status
Simulation time 106599051 ps
CPU time 1.57 seconds
Started Jan 24 01:25:43 PM PST 24
Finished Jan 24 01:26:31 PM PST 24
Peak memory 198136 kb
Host smart-f8fa572b-b0f4-4bc1-9ea0-dd2866d2fb08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301601148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1301601148
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1989838445
Short name T737
Test name
Test status
Simulation time 346781478 ps
CPU time 1.35 seconds
Started Jan 24 01:25:38 PM PST 24
Finished Jan 24 01:26:28 PM PST 24
Peak memory 196860 kb
Host smart-bab0cd16-1e61-4df6-a662-4f6bc8b95492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989838445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1989838445
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3870612519
Short name T302
Test name
Test status
Simulation time 499456544 ps
CPU time 1.32 seconds
Started Jan 24 01:25:39 PM PST 24
Finished Jan 24 01:26:29 PM PST 24
Peak memory 198168 kb
Host smart-fe1d3a38-e20c-4669-a401-905967624c74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870612519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3870612519
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3686184216
Short name T704
Test name
Test status
Simulation time 120745995793 ps
CPU time 195.82 seconds
Started Jan 24 01:25:51 PM PST 24
Finished Jan 24 01:29:54 PM PST 24
Peak memory 198356 kb
Host smart-1a72c726-dc5a-4c91-8960-93c79b9a9c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686184216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3686184216
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2161155908
Short name T512
Test name
Test status
Simulation time 30038682996 ps
CPU time 382.43 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:33:03 PM PST 24
Peak memory 198408 kb
Host smart-1492eecf-8f68-4a1d-b6c2-b4ae967b2d43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2161155908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2161155908
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2596773115
Short name T112
Test name
Test status
Simulation time 74382075 ps
CPU time 0.59 seconds
Started Jan 24 01:21:51 PM PST 24
Finished Jan 24 01:22:49 PM PST 24
Peak memory 194916 kb
Host smart-411f2a64-2e3c-495a-9c58-9a1141be5efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596773115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2596773115
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3915504514
Short name T285
Test name
Test status
Simulation time 81237375 ps
CPU time 0.75 seconds
Started Jan 24 01:21:38 PM PST 24
Finished Jan 24 01:22:39 PM PST 24
Peak memory 195492 kb
Host smart-9de01774-5ce5-4247-9c75-cd6aa4c4da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915504514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3915504514
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1593720972
Short name T428
Test name
Test status
Simulation time 454049688 ps
CPU time 13.53 seconds
Started Jan 24 01:21:44 PM PST 24
Finished Jan 24 01:22:57 PM PST 24
Peak memory 197284 kb
Host smart-ce003d5c-ebd0-4ad6-a8c6-817efce9a6c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593720972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1593720972
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.269221522
Short name T489
Test name
Test status
Simulation time 25630400 ps
CPU time 0.68 seconds
Started Jan 24 01:22:00 PM PST 24
Finished Jan 24 01:22:58 PM PST 24
Peak memory 194000 kb
Host smart-933b852a-adef-408a-a122-acf67c1be4f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269221522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.269221522
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3987017313
Short name T481
Test name
Test status
Simulation time 740485887 ps
CPU time 1.04 seconds
Started Jan 24 01:21:41 PM PST 24
Finished Jan 24 01:22:42 PM PST 24
Peak memory 196172 kb
Host smart-6061bdc1-b8b2-4c35-98d0-34eea1c6cd80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987017313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3987017313
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1408184508
Short name T860
Test name
Test status
Simulation time 45302424 ps
CPU time 1.72 seconds
Started Jan 24 01:21:40 PM PST 24
Finished Jan 24 01:22:42 PM PST 24
Peak memory 198164 kb
Host smart-8b322676-6262-42af-bc30-ec2519efe3d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408184508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1408184508
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3374463671
Short name T279
Test name
Test status
Simulation time 335132605 ps
CPU time 2.55 seconds
Started Jan 24 01:21:42 PM PST 24
Finished Jan 24 01:22:44 PM PST 24
Peak memory 197004 kb
Host smart-0915d74f-6781-4c48-a9b9-e05b0810f0b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374463671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3374463671
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.561236128
Short name T531
Test name
Test status
Simulation time 35328270 ps
CPU time 1.17 seconds
Started Jan 24 01:21:42 PM PST 24
Finished Jan 24 01:22:43 PM PST 24
Peak memory 197152 kb
Host smart-bcd7d64a-a8b4-42c3-a490-e0467f57f8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561236128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.561236128
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1157598316
Short name T346
Test name
Test status
Simulation time 51329332 ps
CPU time 1.09 seconds
Started Jan 24 01:21:42 PM PST 24
Finished Jan 24 01:22:42 PM PST 24
Peak memory 196052 kb
Host smart-7dc46b33-fc7c-4ebb-b61c-73d59e1b5e00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157598316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1157598316
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4085856950
Short name T320
Test name
Test status
Simulation time 24473748 ps
CPU time 1.15 seconds
Started Jan 24 01:21:47 PM PST 24
Finished Jan 24 01:22:46 PM PST 24
Peak memory 198148 kb
Host smart-5695b57e-c3d3-491d-aa97-06b1c8262179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085856950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4085856950
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4088284190
Short name T37
Test name
Test status
Simulation time 96947399 ps
CPU time 0.95 seconds
Started Jan 24 01:21:53 PM PST 24
Finished Jan 24 01:22:52 PM PST 24
Peak memory 214804 kb
Host smart-cfbd4b33-28ff-485d-a2d4-f400fcc32306
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088284190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4088284190
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1340394685
Short name T647
Test name
Test status
Simulation time 482583233 ps
CPU time 0.83 seconds
Started Jan 24 01:21:43 PM PST 24
Finished Jan 24 01:22:43 PM PST 24
Peak memory 195384 kb
Host smart-0edd1491-3af9-4250-9bd0-0484b8fc848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340394685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1340394685
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.827214959
Short name T711
Test name
Test status
Simulation time 36949584 ps
CPU time 0.92 seconds
Started Jan 24 01:21:44 PM PST 24
Finished Jan 24 01:22:44 PM PST 24
Peak memory 197320 kb
Host smart-f731a2c4-ecdb-4d48-9e90-2f77f4aa281c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827214959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.827214959
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3827848930
Short name T862
Test name
Test status
Simulation time 27196536795 ps
CPU time 174.98 seconds
Started Jan 24 01:22:00 PM PST 24
Finished Jan 24 01:25:52 PM PST 24
Peak memory 197968 kb
Host smart-feff75fd-e25c-4860-b713-345238d38d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827848930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3827848930
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1022627072
Short name T293
Test name
Test status
Simulation time 155477750735 ps
CPU time 666.47 seconds
Started Jan 24 01:21:53 PM PST 24
Finished Jan 24 01:33:57 PM PST 24
Peak memory 198424 kb
Host smart-403686ff-2237-4c66-a151-95879050636f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1022627072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1022627072
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3582262720
Short name T827
Test name
Test status
Simulation time 15711947 ps
CPU time 0.55 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:41 PM PST 24
Peak memory 193948 kb
Host smart-4d111cf6-6b2b-4446-99ff-02f5246e4b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582262720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3582262720
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2072890831
Short name T236
Test name
Test status
Simulation time 31162452 ps
CPU time 0.94 seconds
Started Jan 24 01:25:46 PM PST 24
Finished Jan 24 01:26:33 PM PST 24
Peak memory 196040 kb
Host smart-e84272f9-01e6-4007-ad5d-f8b2b46538db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072890831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2072890831
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2413322534
Short name T547
Test name
Test status
Simulation time 340431559 ps
CPU time 11.7 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:53 PM PST 24
Peak memory 196416 kb
Host smart-3d07bc7e-cd58-4d6f-91e8-3928031ff90f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413322534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2413322534
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4091717399
Short name T265
Test name
Test status
Simulation time 49850079 ps
CPU time 1.33 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:42 PM PST 24
Peak memory 197208 kb
Host smart-e707d12d-1fd7-407c-af36-c875cb875e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091717399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4091717399
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1892453534
Short name T767
Test name
Test status
Simulation time 71228980 ps
CPU time 2.73 seconds
Started Jan 24 01:25:49 PM PST 24
Finished Jan 24 01:26:40 PM PST 24
Peak memory 198188 kb
Host smart-2fe1ce92-0d2c-4f96-8912-d86ec52da45f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892453534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1892453534
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1662458021
Short name T301
Test name
Test status
Simulation time 103669233 ps
CPU time 2.81 seconds
Started Jan 24 01:25:50 PM PST 24
Finished Jan 24 01:26:40 PM PST 24
Peak memory 196084 kb
Host smart-2ba1c843-7308-4070-940e-dc9b67423745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662458021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1662458021
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1121817839
Short name T404
Test name
Test status
Simulation time 73697209 ps
CPU time 0.84 seconds
Started Jan 24 01:25:50 PM PST 24
Finished Jan 24 01:26:38 PM PST 24
Peak memory 196560 kb
Host smart-b1094944-4db9-4d64-8e61-3827e0760218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121817839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1121817839
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.173740093
Short name T71
Test name
Test status
Simulation time 15688028 ps
CPU time 0.69 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:42 PM PST 24
Peak memory 194472 kb
Host smart-57cd354f-a926-47c6-83bb-fa96e283a7b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173740093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.173740093
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2061980817
Short name T277
Test name
Test status
Simulation time 1427423747 ps
CPU time 5.72 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:47 PM PST 24
Peak memory 198164 kb
Host smart-950a0ba4-d796-4d05-b8fa-e11cb20dbded
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061980817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2061980817
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2260856562
Short name T315
Test name
Test status
Simulation time 590273230 ps
CPU time 1.08 seconds
Started Jan 24 01:35:07 PM PST 24
Finished Jan 24 01:35:32 PM PST 24
Peak memory 196660 kb
Host smart-6a144a5f-aed7-4076-a659-ad0e1d760435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260856562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2260856562
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1719141922
Short name T230
Test name
Test status
Simulation time 384210599 ps
CPU time 0.84 seconds
Started Jan 24 01:25:46 PM PST 24
Finished Jan 24 01:26:34 PM PST 24
Peak memory 195292 kb
Host smart-3b5e05ec-ca81-49a9-b0d1-b9bcd39021a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719141922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1719141922
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3241092463
Short name T579
Test name
Test status
Simulation time 81578706236 ps
CPU time 139.92 seconds
Started Jan 24 01:25:55 PM PST 24
Finished Jan 24 01:29:05 PM PST 24
Peak memory 198300 kb
Host smart-772bd910-a9c5-4fce-a069-57bd7c3d4dc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241092463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3241092463
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2007201521
Short name T803
Test name
Test status
Simulation time 120394074496 ps
CPU time 541.9 seconds
Started Jan 24 01:25:55 PM PST 24
Finished Jan 24 01:35:47 PM PST 24
Peak memory 198364 kb
Host smart-de1dd185-b20b-417c-8959-feaa3616857d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2007201521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2007201521
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2515809416
Short name T655
Test name
Test status
Simulation time 35286678 ps
CPU time 0.56 seconds
Started Jan 24 01:25:59 PM PST 24
Finished Jan 24 01:26:50 PM PST 24
Peak memory 194060 kb
Host smart-76d8b4b6-77be-4662-8d81-8bebdb10f4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515809416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2515809416
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.926705440
Short name T777
Test name
Test status
Simulation time 58817825 ps
CPU time 0.67 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:41 PM PST 24
Peak memory 194216 kb
Host smart-ee61c815-488b-46ab-9ea7-cdd01df73f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926705440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.926705440
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3036940892
Short name T55
Test name
Test status
Simulation time 340778712 ps
CPU time 16.78 seconds
Started Jan 24 01:25:49 PM PST 24
Finished Jan 24 01:26:53 PM PST 24
Peak memory 198172 kb
Host smart-92bfc2d4-7d8f-46f9-87dc-528850b1b6f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036940892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3036940892
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2044614167
Short name T244
Test name
Test status
Simulation time 24815881 ps
CPU time 0.58 seconds
Started Jan 24 01:25:51 PM PST 24
Finished Jan 24 01:26:40 PM PST 24
Peak memory 194980 kb
Host smart-c725595d-81e9-4e40-af27-fd3ea5e5eb94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044614167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2044614167
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4100460732
Short name T120
Test name
Test status
Simulation time 29139423 ps
CPU time 0.93 seconds
Started Jan 24 01:57:33 PM PST 24
Finished Jan 24 01:57:41 PM PST 24
Peak memory 196860 kb
Host smart-74e13b54-a66a-4e1a-915b-cdf2d57ad26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100460732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4100460732
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2145106317
Short name T362
Test name
Test status
Simulation time 88466374 ps
CPU time 1.01 seconds
Started Jan 24 01:25:51 PM PST 24
Finished Jan 24 01:26:39 PM PST 24
Peak memory 196304 kb
Host smart-512edd19-77b6-4a74-bd07-c40222e19458
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145106317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2145106317
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2535647153
Short name T290
Test name
Test status
Simulation time 191556042 ps
CPU time 1.27 seconds
Started Jan 24 01:25:50 PM PST 24
Finished Jan 24 01:26:39 PM PST 24
Peak memory 195944 kb
Host smart-40ac86c1-9475-4dcf-ac0c-eb74e87a603f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535647153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2535647153
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.954237234
Short name T652
Test name
Test status
Simulation time 80265216 ps
CPU time 0.95 seconds
Started Jan 24 01:25:52 PM PST 24
Finished Jan 24 01:26:41 PM PST 24
Peak memory 195940 kb
Host smart-7ee2473d-acfc-4df9-9a0b-9909acb7ab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954237234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.954237234
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3335088718
Short name T788
Test name
Test status
Simulation time 162325746 ps
CPU time 1.02 seconds
Started Jan 24 01:25:48 PM PST 24
Finished Jan 24 01:26:36 PM PST 24
Peak memory 196972 kb
Host smart-59364c4f-213a-4000-898b-1f640dd70917
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335088718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3335088718
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1989231892
Short name T793
Test name
Test status
Simulation time 335367203 ps
CPU time 4.09 seconds
Started Jan 24 01:52:00 PM PST 24
Finished Jan 24 01:52:09 PM PST 24
Peak memory 198088 kb
Host smart-3f217b45-ff9e-4d3b-b795-b2f07bceb371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989231892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1989231892
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1857402787
Short name T278
Test name
Test status
Simulation time 332800304 ps
CPU time 1.14 seconds
Started Jan 24 01:25:55 PM PST 24
Finished Jan 24 01:26:46 PM PST 24
Peak memory 195844 kb
Host smart-8a305136-066b-4200-9c8e-cae258c3e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857402787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1857402787
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2210459278
Short name T838
Test name
Test status
Simulation time 164804895 ps
CPU time 0.81 seconds
Started Jan 24 01:25:50 PM PST 24
Finished Jan 24 01:26:39 PM PST 24
Peak memory 195328 kb
Host smart-57840a9c-f9b7-43ff-be9a-88d325b94d26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210459278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2210459278
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2907718301
Short name T789
Test name
Test status
Simulation time 51120823059 ps
CPU time 181.42 seconds
Started Jan 24 01:25:51 PM PST 24
Finished Jan 24 01:29:40 PM PST 24
Peak memory 198336 kb
Host smart-ed43e51f-5977-4d76-92be-34184d53f558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907718301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2907718301
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1571964403
Short name T505
Test name
Test status
Simulation time 235596536845 ps
CPU time 2288.64 seconds
Started Jan 24 01:40:35 PM PST 24
Finished Jan 24 02:19:36 PM PST 24
Peak memory 198412 kb
Host smart-d58b533f-24cd-4507-8788-64a8cce1068b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1571964403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1571964403
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1988479952
Short name T500
Test name
Test status
Simulation time 23231787 ps
CPU time 0.56 seconds
Started Jan 24 01:26:02 PM PST 24
Finished Jan 24 01:26:54 PM PST 24
Peak memory 193868 kb
Host smart-bce24cc0-faae-4325-8bc4-b754b0e8af91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988479952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1988479952
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.185664189
Short name T476
Test name
Test status
Simulation time 145388113 ps
CPU time 0.71 seconds
Started Jan 24 01:26:02 PM PST 24
Finished Jan 24 01:26:54 PM PST 24
Peak memory 195280 kb
Host smart-c36e3173-325f-4970-a3a3-a9d3fe198d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185664189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.185664189
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.271835875
Short name T623
Test name
Test status
Simulation time 2773432140 ps
CPU time 19.72 seconds
Started Jan 24 01:26:01 PM PST 24
Finished Jan 24 01:27:13 PM PST 24
Peak memory 197136 kb
Host smart-a19af210-dfa4-40bd-b213-9a809f942d01
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271835875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.271835875
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.80107920
Short name T522
Test name
Test status
Simulation time 114157174 ps
CPU time 0.78 seconds
Started Jan 24 01:25:58 PM PST 24
Finished Jan 24 01:26:49 PM PST 24
Peak memory 195948 kb
Host smart-961e017a-79bf-47ad-bff9-d005796907fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80107920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.80107920
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1792133148
Short name T642
Test name
Test status
Simulation time 94298149 ps
CPU time 1.04 seconds
Started Jan 24 02:31:41 PM PST 24
Finished Jan 24 02:32:06 PM PST 24
Peak memory 197044 kb
Host smart-78ab6740-835c-4bdc-8e3b-69dde9bb8835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792133148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1792133148
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2945115339
Short name T635
Test name
Test status
Simulation time 547575573 ps
CPU time 3.32 seconds
Started Jan 24 01:25:58 PM PST 24
Finished Jan 24 01:26:52 PM PST 24
Peak memory 198220 kb
Host smart-3c32b6c3-12b6-4c6b-b770-c5259667cf44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945115339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2945115339
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1298744946
Short name T679
Test name
Test status
Simulation time 269579742 ps
CPU time 0.88 seconds
Started Jan 24 01:37:59 PM PST 24
Finished Jan 24 01:38:26 PM PST 24
Peak memory 194464 kb
Host smart-f42d8f68-bf11-40b2-9e9e-f8a369b112fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298744946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1298744946
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3471818135
Short name T393
Test name
Test status
Simulation time 67195185 ps
CPU time 1.2 seconds
Started Jan 24 01:25:57 PM PST 24
Finished Jan 24 01:26:49 PM PST 24
Peak memory 197164 kb
Host smart-3d3a4cf7-824d-4338-ba20-6ccc94d2eeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471818135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3471818135
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2673263094
Short name T682
Test name
Test status
Simulation time 60730585 ps
CPU time 0.61 seconds
Started Jan 24 01:26:03 PM PST 24
Finished Jan 24 01:26:58 PM PST 24
Peak memory 194332 kb
Host smart-2e70a0e5-61ac-4bf1-806f-20186e08b782
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673263094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2673263094
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.47872699
Short name T590
Test name
Test status
Simulation time 51247638 ps
CPU time 1.37 seconds
Started Jan 24 01:25:58 PM PST 24
Finished Jan 24 01:26:49 PM PST 24
Peak memory 198172 kb
Host smart-3ab472f4-70fe-4753-9ce9-20aa95d1dfd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47872699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.47872699
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2281961592
Short name T805
Test name
Test status
Simulation time 131336777 ps
CPU time 1.06 seconds
Started Jan 24 01:26:00 PM PST 24
Finished Jan 24 01:26:52 PM PST 24
Peak memory 195832 kb
Host smart-b061f7d4-8fe5-433e-adc6-37a3a44d6363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281961592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2281961592
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1450946385
Short name T755
Test name
Test status
Simulation time 45406278 ps
CPU time 0.79 seconds
Started Jan 24 01:26:04 PM PST 24
Finished Jan 24 01:26:58 PM PST 24
Peak memory 195296 kb
Host smart-5654c9bb-fb8b-4ec5-b6a6-17673bbc365b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450946385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1450946385
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2569917285
Short name T372
Test name
Test status
Simulation time 121074458077 ps
CPU time 1825.11 seconds
Started Jan 24 01:26:02 PM PST 24
Finished Jan 24 01:57:20 PM PST 24
Peak memory 198408 kb
Host smart-0b7af8f3-1b28-4800-9783-f9d49394b6af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2569917285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2569917285
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.68364036
Short name T879
Test name
Test status
Simulation time 48341011 ps
CPU time 0.58 seconds
Started Jan 24 01:26:09 PM PST 24
Finished Jan 24 01:27:08 PM PST 24
Peak memory 194668 kb
Host smart-2537de1f-0d4f-4c81-906f-ee24e3ea80a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68364036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.68364036
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.334875120
Short name T283
Test name
Test status
Simulation time 33381346 ps
CPU time 0.63 seconds
Started Jan 24 01:26:08 PM PST 24
Finished Jan 24 01:27:08 PM PST 24
Peak memory 194812 kb
Host smart-d3c0dab7-6fb9-4a3c-b356-98e45a196f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334875120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.334875120
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.132272280
Short name T844
Test name
Test status
Simulation time 1068950059 ps
CPU time 13.73 seconds
Started Jan 24 01:33:08 PM PST 24
Finished Jan 24 01:33:46 PM PST 24
Peak memory 197064 kb
Host smart-6dbe47bd-dba6-4b5b-bd0b-ff6c8fd3de19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132272280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.132272280
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1096440669
Short name T806
Test name
Test status
Simulation time 27240016 ps
CPU time 0.72 seconds
Started Jan 24 01:26:10 PM PST 24
Finished Jan 24 01:27:08 PM PST 24
Peak memory 194776 kb
Host smart-40a35a3b-885a-4745-b60b-763c3f40c0f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096440669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1096440669
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4148926008
Short name T402
Test name
Test status
Simulation time 90185045 ps
CPU time 0.86 seconds
Started Jan 24 01:33:17 PM PST 24
Finished Jan 24 01:33:39 PM PST 24
Peak memory 195788 kb
Host smart-c0ef25ad-869d-41d1-aa93-222afdc03bf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148926008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4148926008
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3074463771
Short name T492
Test name
Test status
Simulation time 297814474 ps
CPU time 3.05 seconds
Started Jan 24 01:26:13 PM PST 24
Finished Jan 24 01:27:14 PM PST 24
Peak memory 197448 kb
Host smart-2341182e-8ead-48b5-9600-209f2b2c1e08
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074463771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3074463771
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.466215662
Short name T378
Test name
Test status
Simulation time 2559152403 ps
CPU time 3.34 seconds
Started Jan 24 01:26:10 PM PST 24
Finished Jan 24 01:27:11 PM PST 24
Peak memory 198372 kb
Host smart-b4c01a63-eaae-43e4-97d3-2660a88859d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466215662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
466215662
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2676051441
Short name T383
Test name
Test status
Simulation time 47549538 ps
CPU time 1.29 seconds
Started Jan 24 01:26:12 PM PST 24
Finished Jan 24 01:27:12 PM PST 24
Peak memory 197224 kb
Host smart-8f8435bc-d855-4bdc-a266-e8f443dd9e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676051441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2676051441
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3635849644
Short name T255
Test name
Test status
Simulation time 82682530 ps
CPU time 0.88 seconds
Started Jan 24 01:26:16 PM PST 24
Finished Jan 24 01:27:15 PM PST 24
Peak memory 196036 kb
Host smart-36b6c349-85d1-470b-b9fe-3c6ccbda41da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635849644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3635849644
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2687579383
Short name T401
Test name
Test status
Simulation time 538737971 ps
CPU time 5.95 seconds
Started Jan 24 01:37:48 PM PST 24
Finished Jan 24 01:38:22 PM PST 24
Peak memory 198128 kb
Host smart-b8a2f891-989b-4bf1-bfa4-106fcfa96f92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687579383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2687579383
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2968073983
Short name T280
Test name
Test status
Simulation time 162083878 ps
CPU time 1.29 seconds
Started Jan 24 01:25:57 PM PST 24
Finished Jan 24 01:26:49 PM PST 24
Peak memory 196956 kb
Host smart-1214a3a3-9964-4eac-805d-b9b03805c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968073983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2968073983
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2352523809
Short name T342
Test name
Test status
Simulation time 55854982 ps
CPU time 0.91 seconds
Started Jan 24 01:26:14 PM PST 24
Finished Jan 24 01:27:13 PM PST 24
Peak memory 195760 kb
Host smart-3ee99ff7-a062-465f-9647-aeb327528661
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352523809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2352523809
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3643683206
Short name T392
Test name
Test status
Simulation time 14885165334 ps
CPU time 83.44 seconds
Started Jan 24 01:26:12 PM PST 24
Finished Jan 24 01:28:34 PM PST 24
Peak memory 198336 kb
Host smart-d21a74bf-48c2-4f29-82e3-a8d12b3e234b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643683206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3643683206
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2470378564
Short name T466
Test name
Test status
Simulation time 68972304232 ps
CPU time 422.81 seconds
Started Jan 24 01:26:14 PM PST 24
Finished Jan 24 01:34:15 PM PST 24
Peak memory 198260 kb
Host smart-f12c1a77-28da-4c53-9a73-72b3227d0d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2470378564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2470378564
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1343500456
Short name T507
Test name
Test status
Simulation time 22161386 ps
CPU time 0.56 seconds
Started Jan 24 01:26:21 PM PST 24
Finished Jan 24 01:27:20 PM PST 24
Peak memory 193984 kb
Host smart-d43302f2-1035-45ef-b8e1-fc95b1d2bc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343500456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1343500456
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4248761021
Short name T861
Test name
Test status
Simulation time 191357831 ps
CPU time 0.85 seconds
Started Jan 24 01:26:19 PM PST 24
Finished Jan 24 01:27:20 PM PST 24
Peak memory 196492 kb
Host smart-169d06b5-3647-44e2-8d6e-4c1ab446880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248761021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4248761021
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2179866471
Short name T357
Test name
Test status
Simulation time 3737464804 ps
CPU time 25.92 seconds
Started Jan 24 01:26:22 PM PST 24
Finished Jan 24 01:27:46 PM PST 24
Peak memory 197032 kb
Host smart-00e5a8d2-54bf-4a1d-804c-228d54621034
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179866471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2179866471
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1024082451
Short name T335
Test name
Test status
Simulation time 105431706 ps
CPU time 0.91 seconds
Started Jan 24 01:26:22 PM PST 24
Finished Jan 24 01:27:21 PM PST 24
Peak memory 196524 kb
Host smart-dfc3d849-f5fa-4dba-8b66-5b0a66ba9f95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024082451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1024082451
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1797315999
Short name T423
Test name
Test status
Simulation time 111183083 ps
CPU time 1.02 seconds
Started Jan 24 01:26:18 PM PST 24
Finished Jan 24 01:27:18 PM PST 24
Peak memory 196204 kb
Host smart-58c34403-05a1-498d-841e-ffe6c58a7ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797315999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1797315999
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2447384032
Short name T724
Test name
Test status
Simulation time 305074109 ps
CPU time 1.65 seconds
Started Jan 24 01:26:22 PM PST 24
Finished Jan 24 01:27:22 PM PST 24
Peak memory 196816 kb
Host smart-f1ce3ace-869c-4407-bb7e-86ecb7fc16e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447384032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2447384032
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3355437726
Short name T498
Test name
Test status
Simulation time 28073897 ps
CPU time 0.98 seconds
Started Jan 24 02:56:04 PM PST 24
Finished Jan 24 02:56:08 PM PST 24
Peak memory 195292 kb
Host smart-0950082b-cc4e-49d2-97e0-65bfbe2fb346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355437726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3355437726
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2226777485
Short name T394
Test name
Test status
Simulation time 58623890 ps
CPU time 1.27 seconds
Started Jan 24 01:26:11 PM PST 24
Finished Jan 24 01:27:10 PM PST 24
Peak memory 195992 kb
Host smart-a0b9d86f-6abc-4692-9d60-19faff54b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226777485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2226777485
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2135307338
Short name T725
Test name
Test status
Simulation time 35216623 ps
CPU time 0.88 seconds
Started Jan 24 01:26:16 PM PST 24
Finished Jan 24 01:27:15 PM PST 24
Peak memory 196628 kb
Host smart-92a900bc-14d5-4629-a435-25c3b63afd70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135307338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2135307338
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1417575448
Short name T807
Test name
Test status
Simulation time 1457937791 ps
CPU time 5.88 seconds
Started Jan 24 01:26:18 PM PST 24
Finished Jan 24 01:27:22 PM PST 24
Peak memory 198148 kb
Host smart-593f2c17-f751-4b45-83e7-ccaaf6b31343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417575448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1417575448
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3656740287
Short name T605
Test name
Test status
Simulation time 63976162 ps
CPU time 0.71 seconds
Started Jan 24 01:31:34 PM PST 24
Finished Jan 24 01:32:27 PM PST 24
Peak memory 195260 kb
Host smart-9f560bf9-bf89-48e8-9ee7-dec4ba8c7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656740287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3656740287
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1779418456
Short name T864
Test name
Test status
Simulation time 125822779 ps
CPU time 0.87 seconds
Started Jan 24 01:26:10 PM PST 24
Finished Jan 24 01:27:09 PM PST 24
Peak memory 196156 kb
Host smart-0f69c8e9-3733-4f3f-8610-aff001a51d08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779418456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1779418456
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4098896059
Short name T855
Test name
Test status
Simulation time 8200324868 ps
CPU time 24.21 seconds
Started Jan 24 01:26:18 PM PST 24
Finished Jan 24 01:27:41 PM PST 24
Peak memory 198372 kb
Host smart-073d5be0-8dfa-40da-990b-c6e4ed7bcd40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098896059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4098896059
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.4006318640
Short name T847
Test name
Test status
Simulation time 47330645374 ps
CPU time 317.39 seconds
Started Jan 24 01:26:20 PM PST 24
Finished Jan 24 01:32:36 PM PST 24
Peak memory 198392 kb
Host smart-db97731e-958d-43cf-9540-9cd615c6f0f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4006318640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.4006318640
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.609478041
Short name T59
Test name
Test status
Simulation time 10896013 ps
CPU time 0.58 seconds
Started Jan 24 01:26:31 PM PST 24
Finished Jan 24 01:27:26 PM PST 24
Peak memory 194000 kb
Host smart-4325fb31-c5ee-4a37-bc09-e904a71a39b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609478041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.609478041
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4108203560
Short name T288
Test name
Test status
Simulation time 152332481 ps
CPU time 0.87 seconds
Started Jan 24 01:26:34 PM PST 24
Finished Jan 24 01:27:27 PM PST 24
Peak memory 196040 kb
Host smart-cfcfbf4a-e77e-45e7-b060-030542e4669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108203560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4108203560
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1510238140
Short name T421
Test name
Test status
Simulation time 780749434 ps
CPU time 10.9 seconds
Started Jan 24 01:26:36 PM PST 24
Finished Jan 24 01:27:38 PM PST 24
Peak memory 196452 kb
Host smart-4f30ae83-8b44-4c5d-be9e-1e19dcc54eb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510238140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1510238140
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1428036950
Short name T485
Test name
Test status
Simulation time 73043780 ps
CPU time 0.99 seconds
Started Jan 24 01:26:34 PM PST 24
Finished Jan 24 01:27:27 PM PST 24
Peak memory 196528 kb
Host smart-57b511f6-c495-43b6-86f7-effe6b21f236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428036950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1428036950
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1581937922
Short name T361
Test name
Test status
Simulation time 160709850 ps
CPU time 1.12 seconds
Started Jan 24 01:26:35 PM PST 24
Finished Jan 24 01:27:28 PM PST 24
Peak memory 196632 kb
Host smart-291e0d6d-e008-49e4-ba19-4a6c59e71937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581937922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1581937922
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.861478504
Short name T663
Test name
Test status
Simulation time 57039667 ps
CPU time 1.77 seconds
Started Jan 24 01:26:34 PM PST 24
Finished Jan 24 01:27:28 PM PST 24
Peak memory 198068 kb
Host smart-52a0168f-5510-4694-a89b-5a44f89cc2f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861478504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.861478504
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.110315298
Short name T549
Test name
Test status
Simulation time 115245724 ps
CPU time 1.75 seconds
Started Jan 24 01:26:36 PM PST 24
Finished Jan 24 01:27:29 PM PST 24
Peak memory 196712 kb
Host smart-f418e312-3f48-4fc0-bfaf-86cde0060b6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110315298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
110315298
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2761501013
Short name T613
Test name
Test status
Simulation time 55788380 ps
CPU time 0.72 seconds
Started Jan 24 01:26:17 PM PST 24
Finished Jan 24 01:27:16 PM PST 24
Peak memory 196136 kb
Host smart-ff7a00b4-c38b-4da9-9bfc-3a71dd898237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761501013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2761501013
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4008985301
Short name T717
Test name
Test status
Simulation time 226082841 ps
CPU time 1.3 seconds
Started Jan 24 01:26:19 PM PST 24
Finished Jan 24 01:27:18 PM PST 24
Peak memory 198152 kb
Host smart-9fd68a19-8607-41ed-b176-02877d920251
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008985301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4008985301
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.974939217
Short name T781
Test name
Test status
Simulation time 216765310 ps
CPU time 2.57 seconds
Started Jan 24 01:26:36 PM PST 24
Finished Jan 24 01:27:29 PM PST 24
Peak memory 198108 kb
Host smart-547703ea-beb4-4553-9805-5707468131a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974939217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.974939217
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.284745106
Short name T465
Test name
Test status
Simulation time 99247283 ps
CPU time 0.96 seconds
Started Jan 24 01:26:20 PM PST 24
Finished Jan 24 01:27:20 PM PST 24
Peak memory 195364 kb
Host smart-77a515c0-10bb-4819-9a6d-e3df91af4c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284745106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.284745106
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.774271060
Short name T671
Test name
Test status
Simulation time 281639014 ps
CPU time 1.23 seconds
Started Jan 24 01:26:19 PM PST 24
Finished Jan 24 01:27:19 PM PST 24
Peak memory 197060 kb
Host smart-228b5e7c-b8ac-4b65-ac13-e027314b6502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774271060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.774271060
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3916785917
Short name T464
Test name
Test status
Simulation time 19160137941 ps
CPU time 129.75 seconds
Started Jan 24 01:26:39 PM PST 24
Finished Jan 24 01:29:37 PM PST 24
Peak memory 198204 kb
Host smart-ae7877e4-ba50-4ab4-aa49-f74f4c4d2cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916785917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3916785917
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2675711529
Short name T503
Test name
Test status
Simulation time 12500141719 ps
CPU time 93.27 seconds
Started Jan 24 01:26:36 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 198376 kb
Host smart-b4fdaf4c-6cab-4ee2-adb7-365facbdb714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2675711529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2675711529
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1432206908
Short name T396
Test name
Test status
Simulation time 23206813 ps
CPU time 0.57 seconds
Started Jan 24 01:26:44 PM PST 24
Finished Jan 24 01:27:31 PM PST 24
Peak memory 193948 kb
Host smart-510e1916-63aa-455e-a0a0-e349c271917a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432206908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1432206908
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3835086091
Short name T359
Test name
Test status
Simulation time 35940054 ps
CPU time 0.81 seconds
Started Jan 24 01:26:44 PM PST 24
Finished Jan 24 01:27:31 PM PST 24
Peak memory 195428 kb
Host smart-18295933-aae9-4b3e-9e7a-dccef5d48b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835086091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3835086091
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1699343557
Short name T677
Test name
Test status
Simulation time 506356954 ps
CPU time 19.69 seconds
Started Jan 24 01:26:41 PM PST 24
Finished Jan 24 01:27:48 PM PST 24
Peak memory 197168 kb
Host smart-5f3dec64-4dbd-495e-8b7b-534323784a77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699343557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1699343557
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1777974772
Short name T462
Test name
Test status
Simulation time 143280771 ps
CPU time 0.87 seconds
Started Jan 24 02:03:33 PM PST 24
Finished Jan 24 02:04:32 PM PST 24
Peak memory 196152 kb
Host smart-5eee6cc9-b131-40da-af26-4467a75c16e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777974772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1777974772
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1476441858
Short name T694
Test name
Test status
Simulation time 118024801 ps
CPU time 0.79 seconds
Started Jan 24 01:26:42 PM PST 24
Finished Jan 24 01:27:30 PM PST 24
Peak memory 195644 kb
Host smart-aaf4e77b-a5a5-4e14-b9ea-c008e3472b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476441858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1476441858
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3222514270
Short name T773
Test name
Test status
Simulation time 164674613 ps
CPU time 1.7 seconds
Started Jan 24 01:26:42 PM PST 24
Finished Jan 24 01:27:30 PM PST 24
Peak memory 196772 kb
Host smart-42102b70-f1eb-4514-a173-10f5896f3820
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222514270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3222514270
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1471303217
Short name T707
Test name
Test status
Simulation time 554606598 ps
CPU time 2.47 seconds
Started Jan 24 01:26:42 PM PST 24
Finished Jan 24 01:27:32 PM PST 24
Peak memory 197308 kb
Host smart-0f4845a9-8496-4799-b92c-5ff497a81824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471303217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1471303217
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4288603228
Short name T548
Test name
Test status
Simulation time 107300050 ps
CPU time 0.78 seconds
Started Jan 24 01:26:35 PM PST 24
Finished Jan 24 01:27:27 PM PST 24
Peak memory 195552 kb
Host smart-b32c7cd9-5bd8-46dc-9be8-aef01b45824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288603228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4288603228
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1207982216
Short name T881
Test name
Test status
Simulation time 50644113 ps
CPU time 1.12 seconds
Started Jan 24 01:26:33 PM PST 24
Finished Jan 24 01:27:27 PM PST 24
Peak memory 197304 kb
Host smart-fb32825c-fc10-48d5-a302-1976c4e68bfa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207982216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1207982216
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2935947606
Short name T384
Test name
Test status
Simulation time 88458873 ps
CPU time 3.61 seconds
Started Jan 24 01:26:43 PM PST 24
Finished Jan 24 01:27:33 PM PST 24
Peak memory 198064 kb
Host smart-86a5cfa7-d0a5-4cb1-b0eb-baca56967c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935947606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2935947606
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.478830535
Short name T354
Test name
Test status
Simulation time 157740567 ps
CPU time 1.21 seconds
Started Jan 24 01:26:35 PM PST 24
Finished Jan 24 01:27:28 PM PST 24
Peak memory 195620 kb
Host smart-73788134-5a62-4e71-8fa2-fb2cca4754db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478830535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.478830535
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1271797844
Short name T839
Test name
Test status
Simulation time 120276033 ps
CPU time 1.18 seconds
Started Jan 24 01:26:39 PM PST 24
Finished Jan 24 01:27:29 PM PST 24
Peak memory 195588 kb
Host smart-b40732a1-1642-47dd-bbcb-17a24e676238
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271797844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1271797844
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1326222191
Short name T324
Test name
Test status
Simulation time 51483804549 ps
CPU time 189.42 seconds
Started Jan 24 01:26:46 PM PST 24
Finished Jan 24 01:30:41 PM PST 24
Peak memory 198380 kb
Host smart-2b060fa0-bb8b-42f7-941f-cb93add45b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326222191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1326222191
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.4132870147
Short name T471
Test name
Test status
Simulation time 427068715316 ps
CPU time 1278.12 seconds
Started Jan 24 01:26:43 PM PST 24
Finished Jan 24 01:48:48 PM PST 24
Peak memory 198396 kb
Host smart-ec1bfb27-a195-44dc-97e3-8095a8c4aed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4132870147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.4132870147
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.294323039
Short name T375
Test name
Test status
Simulation time 16211280 ps
CPU time 0.64 seconds
Started Jan 24 02:45:18 PM PST 24
Finished Jan 24 02:45:41 PM PST 24
Peak memory 194940 kb
Host smart-8027f4f9-6d09-4a4e-91be-7252f15248ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294323039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.294323039
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1731355664
Short name T272
Test name
Test status
Simulation time 49840963 ps
CPU time 0.67 seconds
Started Jan 24 01:26:46 PM PST 24
Finished Jan 24 01:27:32 PM PST 24
Peak memory 194288 kb
Host smart-2cae66e9-f334-4c24-a261-c6c36eda4065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731355664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1731355664
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2978852888
Short name T762
Test name
Test status
Simulation time 548230799 ps
CPU time 7.28 seconds
Started Jan 24 02:33:20 PM PST 24
Finished Jan 24 02:33:52 PM PST 24
Peak memory 196864 kb
Host smart-24c5c67b-6cee-46b3-b0f1-42f8c9cdd0f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978852888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2978852888
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.276278075
Short name T518
Test name
Test status
Simulation time 716677744 ps
CPU time 1.03 seconds
Started Jan 24 01:26:47 PM PST 24
Finished Jan 24 01:27:33 PM PST 24
Peak memory 198028 kb
Host smart-9d01e918-5ecd-46ed-8f7f-fb9bb9403de2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276278075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.276278075
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1511529806
Short name T559
Test name
Test status
Simulation time 44046938 ps
CPU time 1.75 seconds
Started Jan 24 01:26:45 PM PST 24
Finished Jan 24 01:27:33 PM PST 24
Peak memory 196952 kb
Host smart-6b1d314a-55a9-4d84-a239-19088c7487b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511529806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1511529806
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3628583619
Short name T373
Test name
Test status
Simulation time 86403197 ps
CPU time 1.97 seconds
Started Jan 24 01:26:52 PM PST 24
Finished Jan 24 01:27:37 PM PST 24
Peak memory 196884 kb
Host smart-1c1300c8-3e84-46df-a553-ca6296b1a0d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628583619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3628583619
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.679994835
Short name T540
Test name
Test status
Simulation time 95608384 ps
CPU time 0.98 seconds
Started Jan 24 01:26:45 PM PST 24
Finished Jan 24 01:27:32 PM PST 24
Peak memory 196080 kb
Host smart-afd114b9-c17e-4d6c-8760-97c58e9cf5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679994835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.679994835
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.76274915
Short name T632
Test name
Test status
Simulation time 98399485 ps
CPU time 1.09 seconds
Started Jan 24 01:26:46 PM PST 24
Finished Jan 24 01:27:33 PM PST 24
Peak memory 196184 kb
Host smart-680b7330-ff4c-49d3-ab30-33ef61685b7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76274915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup_
pulldown.76274915
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2523672827
Short name T456
Test name
Test status
Simulation time 148715042 ps
CPU time 1.84 seconds
Started Jan 24 01:26:47 PM PST 24
Finished Jan 24 01:27:34 PM PST 24
Peak memory 198124 kb
Host smart-acd38e5f-5f57-4a3e-b1a8-33142717fe42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523672827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2523672827
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1883150794
Short name T825
Test name
Test status
Simulation time 221245760 ps
CPU time 1.21 seconds
Started Jan 24 01:26:43 PM PST 24
Finished Jan 24 01:27:31 PM PST 24
Peak memory 196548 kb
Host smart-f83351fc-ec2f-4c84-93ca-ad55b69aeaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883150794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1883150794
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.395074804
Short name T693
Test name
Test status
Simulation time 47849235 ps
CPU time 0.99 seconds
Started Jan 24 01:26:46 PM PST 24
Finished Jan 24 01:27:33 PM PST 24
Peak memory 195708 kb
Host smart-2e63d1b2-257e-4c9b-ba09-c1673b3b7a62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395074804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.395074804
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1957397604
Short name T259
Test name
Test status
Simulation time 16036635475 ps
CPU time 100.97 seconds
Started Jan 24 01:26:51 PM PST 24
Finished Jan 24 01:29:15 PM PST 24
Peak memory 198272 kb
Host smart-a8e610c8-2fdb-47ce-a0e1-5fbce3ee5264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957397604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1957397604
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3226984161
Short name T672
Test name
Test status
Simulation time 119095706217 ps
CPU time 1606.4 seconds
Started Jan 24 01:26:47 PM PST 24
Finished Jan 24 01:54:19 PM PST 24
Peak memory 198396 kb
Host smart-daa47e10-9503-4ed7-8b66-170c1064dddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3226984161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3226984161
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.4085257431
Short name T552
Test name
Test status
Simulation time 11029488 ps
CPU time 0.59 seconds
Started Jan 24 01:27:14 PM PST 24
Finished Jan 24 01:27:48 PM PST 24
Peak memory 193980 kb
Host smart-a3a44841-462a-40f8-9628-33aba278df5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085257431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.4085257431
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3748360367
Short name T759
Test name
Test status
Simulation time 18171151 ps
CPU time 0.64 seconds
Started Jan 24 01:26:53 PM PST 24
Finished Jan 24 01:27:37 PM PST 24
Peak memory 194088 kb
Host smart-e444a9d8-092c-4caf-89b8-51f6f63e2d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748360367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3748360367
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2213193827
Short name T526
Test name
Test status
Simulation time 2136088389 ps
CPU time 14.14 seconds
Started Jan 24 01:26:52 PM PST 24
Finished Jan 24 01:27:49 PM PST 24
Peak memory 196624 kb
Host smart-bae9b28c-19f1-48b0-8bc6-f6b96f3c5b94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213193827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2213193827
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2067217121
Short name T810
Test name
Test status
Simulation time 45607484 ps
CPU time 0.8 seconds
Started Jan 24 01:27:01 PM PST 24
Finished Jan 24 01:27:40 PM PST 24
Peak memory 196724 kb
Host smart-924df351-ad49-4b19-9e40-aaeea7da6b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067217121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2067217121
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2134229687
Short name T271
Test name
Test status
Simulation time 190926084 ps
CPU time 1.24 seconds
Started Jan 24 01:27:02 PM PST 24
Finished Jan 24 01:27:41 PM PST 24
Peak memory 197116 kb
Host smart-2e8c5571-6ed0-4770-9e4c-e7e70d8e10c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134229687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2134229687
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.566055509
Short name T124
Test name
Test status
Simulation time 171713108 ps
CPU time 1.44 seconds
Started Jan 24 01:26:54 PM PST 24
Finished Jan 24 01:27:38 PM PST 24
Peak memory 196296 kb
Host smart-7d10f9ac-d738-445e-b095-59ad77c2855a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566055509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.566055509
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3886977987
Short name T353
Test name
Test status
Simulation time 261589123 ps
CPU time 1.99 seconds
Started Jan 24 01:26:53 PM PST 24
Finished Jan 24 01:27:38 PM PST 24
Peak memory 197176 kb
Host smart-e206aea0-af14-42ed-9e32-a9a49a45af07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886977987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3886977987
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2748685496
Short name T678
Test name
Test status
Simulation time 175459286 ps
CPU time 0.97 seconds
Started Jan 24 01:26:51 PM PST 24
Finished Jan 24 01:27:35 PM PST 24
Peak memory 196036 kb
Host smart-9e67341a-d3c1-4e97-ac4f-746b7e856de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748685496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2748685496
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1270075641
Short name T818
Test name
Test status
Simulation time 23291880 ps
CPU time 0.88 seconds
Started Jan 24 01:26:54 PM PST 24
Finished Jan 24 01:27:37 PM PST 24
Peak memory 196620 kb
Host smart-cb1a0d55-ae11-4d6d-8fe6-6a2a410c97a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270075641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1270075641
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3515933610
Short name T267
Test name
Test status
Simulation time 1303658580 ps
CPU time 5.43 seconds
Started Jan 24 01:27:01 PM PST 24
Finished Jan 24 01:27:45 PM PST 24
Peak memory 198108 kb
Host smart-41c746b9-ed5d-4dcf-a98a-2f6457ce9839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515933610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3515933610
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3446250070
Short name T380
Test name
Test status
Simulation time 46723709 ps
CPU time 0.99 seconds
Started Jan 24 01:26:51 PM PST 24
Finished Jan 24 01:27:35 PM PST 24
Peak memory 196632 kb
Host smart-dea22ebd-ef32-4656-9c36-a31d93b382e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446250070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3446250070
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3762849021
Short name T245
Test name
Test status
Simulation time 48876760 ps
CPU time 0.94 seconds
Started Jan 24 01:26:52 PM PST 24
Finished Jan 24 01:27:36 PM PST 24
Peak memory 196692 kb
Host smart-4c560378-0d4e-42bc-8b77-28deae07e006
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762849021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3762849021
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4082317510
Short name T858
Test name
Test status
Simulation time 56553718573 ps
CPU time 154.25 seconds
Started Jan 24 01:26:51 PM PST 24
Finished Jan 24 01:30:08 PM PST 24
Peak memory 198404 kb
Host smart-810e9be9-78e9-4324-ae33-3915e375e22a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082317510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4082317510
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2386622456
Short name T643
Test name
Test status
Simulation time 97011137170 ps
CPU time 1482.83 seconds
Started Jan 24 01:27:03 PM PST 24
Finished Jan 24 01:52:23 PM PST 24
Peak memory 198440 kb
Host smart-2ad47d32-8c98-4a3a-803e-eb234492de66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2386622456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2386622456
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1696483527
Short name T627
Test name
Test status
Simulation time 13786442 ps
CPU time 0.64 seconds
Started Jan 24 01:53:15 PM PST 24
Finished Jan 24 01:53:29 PM PST 24
Peak memory 194892 kb
Host smart-181eec62-6e89-4ec2-a8a3-ed34383e652e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696483527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1696483527
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3752594093
Short name T611
Test name
Test status
Simulation time 37207186 ps
CPU time 0.82 seconds
Started Jan 24 01:27:13 PM PST 24
Finished Jan 24 01:27:48 PM PST 24
Peak memory 195600 kb
Host smart-d4d01313-f752-477d-8ea6-bb991237c3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752594093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3752594093
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4152632926
Short name T282
Test name
Test status
Simulation time 199283580 ps
CPU time 10.31 seconds
Started Jan 24 01:27:07 PM PST 24
Finished Jan 24 01:27:53 PM PST 24
Peak memory 198152 kb
Host smart-bc6a9f6e-a329-4e8e-b5db-74f05dc91202
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152632926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4152632926
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1565879969
Short name T463
Test name
Test status
Simulation time 473974830 ps
CPU time 0.69 seconds
Started Jan 24 01:27:15 PM PST 24
Finished Jan 24 01:27:49 PM PST 24
Peak memory 195500 kb
Host smart-a54dd98c-1919-4e61-9b99-54d4992c3e12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565879969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1565879969
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2993494340
Short name T731
Test name
Test status
Simulation time 147540512 ps
CPU time 1.11 seconds
Started Jan 24 01:27:05 PM PST 24
Finished Jan 24 01:27:43 PM PST 24
Peak memory 196016 kb
Host smart-c3cd7e9d-2b87-47b0-ba80-5ec37ccd8127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993494340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2993494340
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3250511887
Short name T776
Test name
Test status
Simulation time 236135647 ps
CPU time 1.59 seconds
Started Jan 24 01:27:14 PM PST 24
Finished Jan 24 01:27:49 PM PST 24
Peak memory 198224 kb
Host smart-31c3fb56-1705-4340-b7e6-704bbd27ecb7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250511887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3250511887
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3871072645
Short name T420
Test name
Test status
Simulation time 80214430 ps
CPU time 2.37 seconds
Started Jan 24 02:15:48 PM PST 24
Finished Jan 24 02:16:30 PM PST 24
Peak memory 198200 kb
Host smart-a24b7f0d-4ed0-414a-a740-35ec3e8d7c50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871072645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3871072645
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2663974540
Short name T446
Test name
Test status
Simulation time 23767263 ps
CPU time 0.72 seconds
Started Jan 24 01:27:14 PM PST 24
Finished Jan 24 01:27:48 PM PST 24
Peak memory 195448 kb
Host smart-81238fda-8ef2-442c-9769-f9d67d087766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663974540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2663974540
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3359099490
Short name T569
Test name
Test status
Simulation time 28975612 ps
CPU time 0.8 seconds
Started Jan 24 01:27:13 PM PST 24
Finished Jan 24 01:27:48 PM PST 24
Peak memory 196344 kb
Host smart-cd8959d9-f60e-4fd8-9850-72963d6c356e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359099490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3359099490
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3785053487
Short name T114
Test name
Test status
Simulation time 91475845 ps
CPU time 4.02 seconds
Started Jan 24 01:27:22 PM PST 24
Finished Jan 24 01:27:58 PM PST 24
Peak memory 198068 kb
Host smart-ec02f7f5-686d-4c92-9d82-6de61bced0aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785053487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3785053487
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3845304675
Short name T703
Test name
Test status
Simulation time 26040886 ps
CPU time 0.77 seconds
Started Jan 24 01:27:07 PM PST 24
Finished Jan 24 01:27:43 PM PST 24
Peak memory 195408 kb
Host smart-ff29779d-f099-4253-bc79-9314b5b8cce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845304675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3845304675
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1888401377
Short name T592
Test name
Test status
Simulation time 51751880 ps
CPU time 1.3 seconds
Started Jan 24 01:27:01 PM PST 24
Finished Jan 24 01:27:40 PM PST 24
Peak memory 196920 kb
Host smart-0230b9f6-c222-4668-9ade-61b8ac0c4f57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888401377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1888401377
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2328522758
Short name T859
Test name
Test status
Simulation time 10755050201 ps
CPU time 164.49 seconds
Started Jan 24 01:27:13 PM PST 24
Finished Jan 24 01:30:32 PM PST 24
Peak memory 198340 kb
Host smart-2f383965-64f1-4dea-b20d-781a517c8268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328522758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2328522758
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1072618894
Short name T333
Test name
Test status
Simulation time 394839590065 ps
CPU time 760.92 seconds
Started Jan 24 01:36:47 PM PST 24
Finished Jan 24 01:50:02 PM PST 24
Peak memory 206608 kb
Host smart-40670f90-ce7f-4cbb-8797-a86e1ebfc294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1072618894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1072618894
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.499633779
Short name T617
Test name
Test status
Simulation time 41515191 ps
CPU time 0.56 seconds
Started Jan 24 01:22:03 PM PST 24
Finished Jan 24 01:23:02 PM PST 24
Peak memory 193972 kb
Host smart-5a719c7c-8421-4f59-adec-5b710ff4464f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499633779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.499633779
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2542393545
Short name T580
Test name
Test status
Simulation time 155606062 ps
CPU time 0.89 seconds
Started Jan 24 01:21:51 PM PST 24
Finished Jan 24 01:22:50 PM PST 24
Peak memory 195968 kb
Host smart-8743be96-93db-4c2b-9fed-fd4632cfa01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542393545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2542393545
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1635581151
Short name T692
Test name
Test status
Simulation time 3988258855 ps
CPU time 26.22 seconds
Started Jan 24 01:21:48 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 197064 kb
Host smart-f105afbf-57bb-4a87-8b8c-85571a49ab0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635581151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1635581151
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4245254129
Short name T411
Test name
Test status
Simulation time 285956678 ps
CPU time 1 seconds
Started Jan 24 01:21:53 PM PST 24
Finished Jan 24 01:22:52 PM PST 24
Peak memory 196672 kb
Host smart-90da099a-4774-4027-8ae8-a1ed421033ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245254129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4245254129
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.418092775
Short name T431
Test name
Test status
Simulation time 65346734 ps
CPU time 0.8 seconds
Started Jan 24 01:22:00 PM PST 24
Finished Jan 24 01:22:58 PM PST 24
Peak memory 195052 kb
Host smart-ee513c12-beea-4edc-8544-84fb6ad1419c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418092775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.418092775
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.105793150
Short name T494
Test name
Test status
Simulation time 22416949 ps
CPU time 0.99 seconds
Started Jan 24 01:21:47 PM PST 24
Finished Jan 24 01:22:46 PM PST 24
Peak memory 197168 kb
Host smart-e5673c53-9e21-42cf-aad5-71adcec60e33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105793150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.105793150
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4212244095
Short name T790
Test name
Test status
Simulation time 119616333 ps
CPU time 1.53 seconds
Started Jan 24 01:21:48 PM PST 24
Finished Jan 24 01:22:47 PM PST 24
Peak memory 197012 kb
Host smart-153ebbeb-0299-4f4a-a88c-84db71662cdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212244095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4212244095
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3682583347
Short name T415
Test name
Test status
Simulation time 37939773 ps
CPU time 0.75 seconds
Started Jan 24 01:21:48 PM PST 24
Finished Jan 24 01:22:47 PM PST 24
Peak memory 195620 kb
Host smart-d7313c8f-9450-4f1c-8a75-58d93ccb1b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682583347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3682583347
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2895205442
Short name T680
Test name
Test status
Simulation time 49409702 ps
CPU time 0.77 seconds
Started Jan 24 01:21:51 PM PST 24
Finished Jan 24 01:22:49 PM PST 24
Peak memory 196340 kb
Host smart-4e1eaf94-a198-4a44-9ac7-1d3b416d2841
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895205442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2895205442
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4011820242
Short name T229
Test name
Test status
Simulation time 80680865 ps
CPU time 3.71 seconds
Started Jan 24 01:21:48 PM PST 24
Finished Jan 24 01:22:49 PM PST 24
Peak memory 198140 kb
Host smart-268b55f3-2222-4527-b64b-a3b6b1e08bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011820242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4011820242
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2106253577
Short name T68
Test name
Test status
Simulation time 50201331 ps
CPU time 0.8 seconds
Started Jan 24 01:21:53 PM PST 24
Finished Jan 24 01:22:52 PM PST 24
Peak memory 213640 kb
Host smart-6336a9bd-3a37-4eef-9450-3fd7ecbea0c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106253577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2106253577
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2585692133
Short name T318
Test name
Test status
Simulation time 69705814 ps
CPU time 0.75 seconds
Started Jan 24 01:22:00 PM PST 24
Finished Jan 24 01:22:58 PM PST 24
Peak memory 194104 kb
Host smart-c2f3e116-528b-482c-b999-2888344fa3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585692133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2585692133
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1964581697
Short name T250
Test name
Test status
Simulation time 40905893 ps
CPU time 1.16 seconds
Started Jan 24 01:21:49 PM PST 24
Finished Jan 24 01:22:47 PM PST 24
Peak memory 198036 kb
Host smart-2f15db0e-1fc1-41c5-b85d-77626d329cab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964581697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1964581697
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.362769209
Short name T568
Test name
Test status
Simulation time 9100719169 ps
CPU time 34.47 seconds
Started Jan 24 01:21:51 PM PST 24
Finished Jan 24 01:23:23 PM PST 24
Peak memory 198336 kb
Host smart-49ac3316-3d07-4856-9288-cbd30227b602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362769209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.362769209
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3164874920
Short name T697
Test name
Test status
Simulation time 63482003099 ps
CPU time 233.96 seconds
Started Jan 24 01:22:00 PM PST 24
Finished Jan 24 01:26:51 PM PST 24
Peak memory 206392 kb
Host smart-20d8eb7d-e609-4c41-8a53-c8444b77a882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3164874920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3164874920
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3011163298
Short name T269
Test name
Test status
Simulation time 102104467 ps
CPU time 0.57 seconds
Started Jan 24 01:27:28 PM PST 24
Finished Jan 24 01:28:00 PM PST 24
Peak memory 194568 kb
Host smart-598b72d4-8feb-4467-9874-9d55bdbbee11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011163298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3011163298
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1064177828
Short name T441
Test name
Test status
Simulation time 47313287 ps
CPU time 0.8 seconds
Started Jan 24 01:27:23 PM PST 24
Finished Jan 24 01:27:56 PM PST 24
Peak memory 195404 kb
Host smart-8510b793-165e-4be4-905b-daa814e12160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064177828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1064177828
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.246820777
Short name T499
Test name
Test status
Simulation time 1938164006 ps
CPU time 15.81 seconds
Started Jan 24 01:27:15 PM PST 24
Finished Jan 24 01:28:04 PM PST 24
Peak memory 195704 kb
Host smart-75f1bb37-6918-4097-aba9-86e577861204
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246820777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.246820777
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4219188988
Short name T852
Test name
Test status
Simulation time 70902915 ps
CPU time 0.69 seconds
Started Jan 24 01:27:23 PM PST 24
Finished Jan 24 01:27:56 PM PST 24
Peak memory 194720 kb
Host smart-9c87c289-c672-4e4f-9d0e-322cea46417f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219188988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4219188988
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1315083282
Short name T425
Test name
Test status
Simulation time 86697809 ps
CPU time 0.7 seconds
Started Jan 24 01:27:12 PM PST 24
Finished Jan 24 01:27:47 PM PST 24
Peak memory 194432 kb
Host smart-6c6c14ca-3360-45a1-a2f4-3fe9f1607564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315083282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1315083282
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2589179040
Short name T728
Test name
Test status
Simulation time 30427409 ps
CPU time 1.26 seconds
Started Jan 24 01:27:15 PM PST 24
Finished Jan 24 01:27:50 PM PST 24
Peak memory 196996 kb
Host smart-507c0067-5ba2-434c-bb6a-97ed4e89bc58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589179040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2589179040
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3907197409
Short name T564
Test name
Test status
Simulation time 59941439 ps
CPU time 1.9 seconds
Started Jan 24 01:27:21 PM PST 24
Finished Jan 24 01:27:56 PM PST 24
Peak memory 197168 kb
Host smart-cea7d382-1d0b-4b02-a8fe-bd5ba86a3f90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907197409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3907197409
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.4148267113
Short name T399
Test name
Test status
Simulation time 31754519 ps
CPU time 0.69 seconds
Started Jan 24 01:27:15 PM PST 24
Finished Jan 24 01:27:48 PM PST 24
Peak memory 195484 kb
Host smart-b1237591-3ad3-4d9b-8743-18e05c1918f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148267113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.4148267113
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2601457366
Short name T390
Test name
Test status
Simulation time 23507001 ps
CPU time 0.88 seconds
Started Jan 24 01:27:20 PM PST 24
Finished Jan 24 01:27:53 PM PST 24
Peak memory 196020 kb
Host smart-d68ac4f6-b41a-4ab8-b2eb-0206b36e1bfe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601457366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2601457366
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3726879550
Short name T275
Test name
Test status
Simulation time 146666575 ps
CPU time 1.65 seconds
Started Jan 24 01:27:26 PM PST 24
Finished Jan 24 01:27:59 PM PST 24
Peak memory 198140 kb
Host smart-8a16ac05-17e1-4acb-b4ea-a10ac72595ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726879550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3726879550
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2321660015
Short name T665
Test name
Test status
Simulation time 41976200 ps
CPU time 0.94 seconds
Started Jan 24 01:27:14 PM PST 24
Finished Jan 24 01:27:49 PM PST 24
Peak memory 197132 kb
Host smart-42b3d36c-0aad-47a1-bcbd-8bd7777ce88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321660015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2321660015
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.562644026
Short name T830
Test name
Test status
Simulation time 27823794 ps
CPU time 0.83 seconds
Started Jan 24 01:27:11 PM PST 24
Finished Jan 24 01:27:47 PM PST 24
Peak memory 195524 kb
Host smart-a084ae7e-4c9d-49db-a1df-bd431d23640d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562644026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.562644026
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3493228497
Short name T785
Test name
Test status
Simulation time 7227186679 ps
CPU time 89.49 seconds
Started Jan 24 01:27:25 PM PST 24
Finished Jan 24 01:29:26 PM PST 24
Peak memory 198300 kb
Host smart-7a73ae9b-4095-4f2a-8327-df903616a427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493228497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3493228497
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1431544797
Short name T813
Test name
Test status
Simulation time 31776442920 ps
CPU time 411.36 seconds
Started Jan 24 01:27:23 PM PST 24
Finished Jan 24 01:34:46 PM PST 24
Peak memory 198376 kb
Host smart-723e6211-77c5-4e9d-93b7-fd4f3e9c82f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1431544797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1431544797
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3128229917
Short name T798
Test name
Test status
Simulation time 37195301 ps
CPU time 0.58 seconds
Started Jan 24 01:27:31 PM PST 24
Finished Jan 24 01:28:03 PM PST 24
Peak memory 193968 kb
Host smart-3d8ceecf-ff34-46f7-9289-4d5b9dc76443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128229917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3128229917
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3215079896
Short name T440
Test name
Test status
Simulation time 26418157 ps
CPU time 0.72 seconds
Started Jan 24 01:27:23 PM PST 24
Finished Jan 24 01:27:56 PM PST 24
Peak memory 194928 kb
Host smart-d8d91c62-bc6e-4dc2-9493-92e84f0ca147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215079896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3215079896
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3330509870
Short name T513
Test name
Test status
Simulation time 499667724 ps
CPU time 24.46 seconds
Started Jan 24 01:27:22 PM PST 24
Finished Jan 24 01:28:19 PM PST 24
Peak memory 195696 kb
Host smart-cb48c3ba-3a59-492d-828b-72d518b481c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330509870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3330509870
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2021672587
Short name T562
Test name
Test status
Simulation time 130458874 ps
CPU time 0.71 seconds
Started Jan 24 01:27:28 PM PST 24
Finished Jan 24 01:28:00 PM PST 24
Peak memory 196700 kb
Host smart-3c47ce14-9167-4518-b53c-166d3bb04019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021672587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2021672587
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1579007487
Short name T461
Test name
Test status
Simulation time 143667610 ps
CPU time 1.23 seconds
Started Jan 24 01:27:23 PM PST 24
Finished Jan 24 01:27:57 PM PST 24
Peak memory 197064 kb
Host smart-8595e51f-c6ee-469f-b747-33891a2f5e56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579007487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1579007487
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2132315227
Short name T422
Test name
Test status
Simulation time 195368108 ps
CPU time 1.95 seconds
Started Jan 24 03:40:18 PM PST 24
Finished Jan 24 03:40:22 PM PST 24
Peak memory 196488 kb
Host smart-925dcf75-1cd9-4822-be64-379cfda7d6a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132315227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2132315227
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3886968423
Short name T470
Test name
Test status
Simulation time 124128670 ps
CPU time 1.43 seconds
Started Jan 24 02:52:11 PM PST 24
Finished Jan 24 02:52:16 PM PST 24
Peak memory 196020 kb
Host smart-57246db1-ef67-4949-95ec-900ac613059b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886968423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3886968423
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.343856722
Short name T237
Test name
Test status
Simulation time 52545255 ps
CPU time 1.2 seconds
Started Jan 24 01:27:27 PM PST 24
Finished Jan 24 01:28:00 PM PST 24
Peak memory 197144 kb
Host smart-0f08e590-156d-4795-a633-d5e7cc93a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343856722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.343856722
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1084861112
Short name T243
Test name
Test status
Simulation time 54427357 ps
CPU time 1.2 seconds
Started Jan 24 01:27:25 PM PST 24
Finished Jan 24 01:27:58 PM PST 24
Peak memory 197228 kb
Host smart-cbc8c5ec-ade5-4d1a-8d51-97f25cad3d33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084861112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1084861112
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2249418361
Short name T436
Test name
Test status
Simulation time 373817096 ps
CPU time 6.04 seconds
Started Jan 24 01:27:28 PM PST 24
Finished Jan 24 01:28:05 PM PST 24
Peak memory 198012 kb
Host smart-2966c255-8979-480d-bc0a-044ba100def6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249418361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2249418361
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.157268619
Short name T610
Test name
Test status
Simulation time 66452756 ps
CPU time 1.26 seconds
Started Jan 24 01:27:27 PM PST 24
Finished Jan 24 01:28:00 PM PST 24
Peak memory 197168 kb
Host smart-f9ef32e7-5d89-4d5b-95cb-a0382c4012d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157268619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.157268619
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1700097634
Short name T533
Test name
Test status
Simulation time 52712308 ps
CPU time 1.08 seconds
Started Jan 24 01:27:25 PM PST 24
Finished Jan 24 01:27:57 PM PST 24
Peak memory 195716 kb
Host smart-001f2fa4-3dfc-4bd8-9699-adc4bafd18c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700097634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1700097634
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3497039386
Short name T308
Test name
Test status
Simulation time 80522107209 ps
CPU time 2121.51 seconds
Started Jan 24 01:27:36 PM PST 24
Finished Jan 24 02:03:26 PM PST 24
Peak memory 198264 kb
Host smart-c190c732-2338-4836-85c2-681c05ea61d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3497039386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3497039386
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.189176986
Short name T882
Test name
Test status
Simulation time 14546940 ps
CPU time 0.56 seconds
Started Jan 24 01:27:42 PM PST 24
Finished Jan 24 01:28:10 PM PST 24
Peak memory 193904 kb
Host smart-c161f0d0-e5cd-4dfe-b4b5-7e1447a60892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189176986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.189176986
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4225164442
Short name T457
Test name
Test status
Simulation time 16899311 ps
CPU time 0.63 seconds
Started Jan 24 01:27:36 PM PST 24
Finished Jan 24 01:28:05 PM PST 24
Peak memory 194776 kb
Host smart-8aa82bf9-a0d3-4047-804a-35e15919abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225164442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4225164442
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2089394375
Short name T238
Test name
Test status
Simulation time 746059472 ps
CPU time 19.15 seconds
Started Jan 24 01:27:43 PM PST 24
Finished Jan 24 01:28:30 PM PST 24
Peak memory 196820 kb
Host smart-3a05711b-0795-4e61-a92a-75e2c6253896
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089394375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2089394375
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2875502218
Short name T319
Test name
Test status
Simulation time 83648720 ps
CPU time 1 seconds
Started Jan 24 01:27:39 PM PST 24
Finished Jan 24 01:28:08 PM PST 24
Peak memory 197236 kb
Host smart-de62d7df-27cc-457e-9117-7e064f5e1ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875502218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2875502218
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.541033401
Short name T227
Test name
Test status
Simulation time 53941146 ps
CPU time 1.18 seconds
Started Jan 24 01:27:32 PM PST 24
Finished Jan 24 01:28:04 PM PST 24
Peak memory 196128 kb
Host smart-62b034af-5c7a-408e-93b8-277ed069b447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541033401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.541033401
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.4197785165
Short name T560
Test name
Test status
Simulation time 32355685 ps
CPU time 1.02 seconds
Started Jan 24 01:27:40 PM PST 24
Finished Jan 24 01:28:09 PM PST 24
Peak memory 197024 kb
Host smart-91729c15-d635-46ea-8c46-5134b95f1c85
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197785165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.4197785165
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1468866403
Short name T720
Test name
Test status
Simulation time 168322583 ps
CPU time 3.27 seconds
Started Jan 24 01:27:33 PM PST 24
Finished Jan 24 01:28:07 PM PST 24
Peak memory 197440 kb
Host smart-9f7207c3-4aa5-4ee1-b279-0959a96cc4f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468866403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1468866403
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1704243235
Short name T517
Test name
Test status
Simulation time 17329923 ps
CPU time 0.78 seconds
Started Jan 24 02:16:32 PM PST 24
Finished Jan 24 02:17:04 PM PST 24
Peak memory 195456 kb
Host smart-156c8b66-c5a4-485a-9132-5cc1ceb8ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704243235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1704243235
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3995445280
Short name T474
Test name
Test status
Simulation time 59635728 ps
CPU time 1.1 seconds
Started Jan 24 01:27:32 PM PST 24
Finished Jan 24 01:28:04 PM PST 24
Peak memory 195976 kb
Host smart-23b1e633-924a-4fda-90a9-5934e456c302
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995445280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3995445280
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4018480817
Short name T558
Test name
Test status
Simulation time 150071432 ps
CPU time 2.46 seconds
Started Jan 24 01:27:42 PM PST 24
Finished Jan 24 01:28:12 PM PST 24
Peak memory 198072 kb
Host smart-9bcdaefc-02eb-4ff4-9b7b-189a826fc0ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018480817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4018480817
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1738362612
Short name T570
Test name
Test status
Simulation time 149592267 ps
CPU time 1.24 seconds
Started Jan 24 01:27:30 PM PST 24
Finished Jan 24 01:28:03 PM PST 24
Peak memory 196960 kb
Host smart-28d64181-2f38-4d93-8b7a-035e1c6d40bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738362612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1738362612
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2420756336
Short name T691
Test name
Test status
Simulation time 306109463 ps
CPU time 1.03 seconds
Started Jan 24 01:27:36 PM PST 24
Finished Jan 24 01:28:06 PM PST 24
Peak memory 195824 kb
Host smart-1761fc2c-bf42-4270-ab58-fb0e14f4d9fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420756336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2420756336
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2697884312
Short name T363
Test name
Test status
Simulation time 25137416874 ps
CPU time 92.69 seconds
Started Jan 24 02:30:40 PM PST 24
Finished Jan 24 02:32:22 PM PST 24
Peak memory 198360 kb
Host smart-e6dd687a-8143-43dd-8b64-87fbe2ea0ece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697884312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2697884312
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3122394939
Short name T490
Test name
Test status
Simulation time 46637245 ps
CPU time 0.64 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:33 PM PST 24
Peak memory 194580 kb
Host smart-fe73848f-d3b9-43f5-bafe-f8ef342da0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122394939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3122394939
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2861094747
Short name T782
Test name
Test status
Simulation time 80704793 ps
CPU time 0.68 seconds
Started Jan 24 01:27:40 PM PST 24
Finished Jan 24 01:28:09 PM PST 24
Peak memory 194228 kb
Host smart-15ff0b11-ce0a-4cad-ba0b-cd71d61efca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861094747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2861094747
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2730539859
Short name T349
Test name
Test status
Simulation time 810785226 ps
CPU time 19.41 seconds
Started Jan 24 01:32:45 PM PST 24
Finished Jan 24 01:33:38 PM PST 24
Peak memory 198192 kb
Host smart-a7c8dcff-e14e-44e8-97c6-9a3ee24bcec0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730539859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2730539859
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2687947628
Short name T853
Test name
Test status
Simulation time 95785450 ps
CPU time 0.7 seconds
Started Jan 24 01:27:55 PM PST 24
Finished Jan 24 01:28:25 PM PST 24
Peak memory 195388 kb
Host smart-60e6d034-b4d4-4953-9d3a-cbf85d4ec2a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687947628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2687947628
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4010254095
Short name T534
Test name
Test status
Simulation time 96240308 ps
CPU time 0.98 seconds
Started Jan 24 02:13:15 PM PST 24
Finished Jan 24 02:13:28 PM PST 24
Peak memory 196920 kb
Host smart-8cfbc11e-25ba-47ac-a349-e92f94fc85b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010254095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4010254095
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2161031273
Short name T719
Test name
Test status
Simulation time 58664323 ps
CPU time 2.34 seconds
Started Jan 24 01:33:20 PM PST 24
Finished Jan 24 01:33:44 PM PST 24
Peak memory 198244 kb
Host smart-865db291-f3b9-4a3c-b23f-562be15695c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161031273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2161031273
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.930588928
Short name T769
Test name
Test status
Simulation time 30639565 ps
CPU time 0.87 seconds
Started Jan 24 01:27:39 PM PST 24
Finished Jan 24 01:28:08 PM PST 24
Peak memory 194512 kb
Host smart-b39b77f5-5774-486f-9f5a-acac795a3944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930588928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
930588928
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2110194810
Short name T763
Test name
Test status
Simulation time 34200911 ps
CPU time 0.76 seconds
Started Jan 24 01:27:39 PM PST 24
Finished Jan 24 01:28:08 PM PST 24
Peak memory 195580 kb
Host smart-8333bde1-040a-4b67-a641-cd483a8db9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110194810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2110194810
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.650468091
Short name T581
Test name
Test status
Simulation time 115414021 ps
CPU time 1.09 seconds
Started Jan 24 01:27:42 PM PST 24
Finished Jan 24 01:28:11 PM PST 24
Peak memory 196672 kb
Host smart-6d37ca7b-f6f1-4ad6-a8c0-d5e9a7ea8ea6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650468091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.650468091
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1099315922
Short name T775
Test name
Test status
Simulation time 355966119 ps
CPU time 4.82 seconds
Started Jan 24 01:27:55 PM PST 24
Finished Jan 24 01:28:29 PM PST 24
Peak memory 198024 kb
Host smart-b231b52a-1c4b-418f-9416-fbef6177face
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099315922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1099315922
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1474041813
Short name T749
Test name
Test status
Simulation time 120528345 ps
CPU time 1.33 seconds
Started Jan 24 01:27:41 PM PST 24
Finished Jan 24 01:28:10 PM PST 24
Peak memory 197044 kb
Host smart-42374a87-5cb1-48ce-b57a-8d2647012e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474041813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1474041813
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1598246965
Short name T529
Test name
Test status
Simulation time 1267425294 ps
CPU time 1.2 seconds
Started Jan 24 01:27:45 PM PST 24
Finished Jan 24 01:28:13 PM PST 24
Peak memory 196664 kb
Host smart-443bf3f7-716a-4877-85ec-ccbd0b9ff853
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598246965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1598246965
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.642515389
Short name T744
Test name
Test status
Simulation time 26097796614 ps
CPU time 118.59 seconds
Started Jan 24 01:27:57 PM PST 24
Finished Jan 24 01:30:25 PM PST 24
Peak memory 198340 kb
Host smart-fb6f3a43-7b78-4c9c-877f-40936581641f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642515389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.642515389
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2255248195
Short name T78
Test name
Test status
Simulation time 78254696882 ps
CPU time 398.21 seconds
Started Jan 24 01:27:56 PM PST 24
Finished Jan 24 01:35:04 PM PST 24
Peak memory 198372 kb
Host smart-2dc0f3c6-fc0e-4370-8c18-4662b804358d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2255248195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2255248195
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2433541844
Short name T794
Test name
Test status
Simulation time 19628251 ps
CPU time 0.61 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:34 PM PST 24
Peak memory 193892 kb
Host smart-ff115c41-d5c4-49c8-998e-90722cdee2db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433541844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2433541844
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3373159929
Short name T629
Test name
Test status
Simulation time 25163360 ps
CPU time 0.81 seconds
Started Jan 24 01:27:53 PM PST 24
Finished Jan 24 01:28:23 PM PST 24
Peak memory 195400 kb
Host smart-931647a3-dc0a-4f66-8dc4-6a6af4a10f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373159929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3373159929
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3873500705
Short name T309
Test name
Test status
Simulation time 3886864768 ps
CPU time 27.79 seconds
Started Jan 24 01:27:57 PM PST 24
Finished Jan 24 01:28:54 PM PST 24
Peak memory 196856 kb
Host smart-3882cc41-7ebc-41f5-8242-d43e6b791157
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873500705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3873500705
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2437817951
Short name T756
Test name
Test status
Simulation time 149811303 ps
CPU time 0.95 seconds
Started Jan 24 01:27:56 PM PST 24
Finished Jan 24 01:28:26 PM PST 24
Peak memory 196952 kb
Host smart-c2fe0cbf-65cb-487d-a968-8c7c754259cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437817951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2437817951
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3250637299
Short name T424
Test name
Test status
Simulation time 278411773 ps
CPU time 1.14 seconds
Started Jan 24 01:27:55 PM PST 24
Finished Jan 24 01:28:25 PM PST 24
Peak memory 196228 kb
Host smart-da345a69-c686-40eb-aaf7-b20c10e6af37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250637299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3250637299
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1895229628
Short name T252
Test name
Test status
Simulation time 181245384 ps
CPU time 3.66 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:37 PM PST 24
Peak memory 198088 kb
Host smart-4e579723-e668-40ff-95c9-c6396edcc7f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895229628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1895229628
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2518350664
Short name T389
Test name
Test status
Simulation time 49131476 ps
CPU time 1.23 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:34 PM PST 24
Peak memory 194532 kb
Host smart-35f1e417-4820-40a2-a1df-1c1e7759d08c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518350664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2518350664
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1125803012
Short name T612
Test name
Test status
Simulation time 28128718 ps
CPU time 1.08 seconds
Started Jan 24 01:27:56 PM PST 24
Finished Jan 24 01:28:27 PM PST 24
Peak memory 196860 kb
Host smart-eaeb9474-80c9-44ae-bee6-350d573d2fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125803012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1125803012
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2329968781
Short name T514
Test name
Test status
Simulation time 103048959 ps
CPU time 1.26 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:34 PM PST 24
Peak memory 196960 kb
Host smart-d79f70bf-3aa0-4824-b995-c06b9077d0da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329968781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2329968781
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1509307511
Short name T657
Test name
Test status
Simulation time 488778628 ps
CPU time 4.28 seconds
Started Jan 24 01:27:54 PM PST 24
Finished Jan 24 01:28:27 PM PST 24
Peak memory 198140 kb
Host smart-04f0b253-ce8d-40f5-97f3-da979b03666e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509307511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1509307511
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.428252565
Short name T649
Test name
Test status
Simulation time 114183287 ps
CPU time 0.77 seconds
Started Jan 24 01:27:53 PM PST 24
Finished Jan 24 01:28:23 PM PST 24
Peak memory 195984 kb
Host smart-d3059d69-3bc5-4fe4-a917-56e40ae917a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428252565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.428252565
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.803043082
Short name T712
Test name
Test status
Simulation time 264172636 ps
CPU time 1.24 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:34 PM PST 24
Peak memory 194736 kb
Host smart-156ed928-a918-4e4d-98ab-4a4256d9de5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803043082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.803043082
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3153334583
Short name T525
Test name
Test status
Simulation time 2117494919 ps
CPU time 32.32 seconds
Started Jan 24 01:38:48 PM PST 24
Finished Jan 24 01:39:34 PM PST 24
Peak memory 198216 kb
Host smart-e96de8e9-4c93-4551-84f8-20d93e0a44f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153334583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3153334583
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.353228470
Short name T784
Test name
Test status
Simulation time 472157428330 ps
CPU time 826.68 seconds
Started Jan 24 01:27:54 PM PST 24
Finished Jan 24 01:42:09 PM PST 24
Peak memory 198412 kb
Host smart-ea768942-62ff-4cf0-9b34-c79b9d7126f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=353228470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.353228470
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2579328806
Short name T815
Test name
Test status
Simulation time 40628002 ps
CPU time 0.58 seconds
Started Jan 24 01:28:23 PM PST 24
Finished Jan 24 01:28:46 PM PST 24
Peak memory 194024 kb
Host smart-56c697a0-2d95-418d-b074-b8e06f40768f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579328806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2579328806
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4293684560
Short name T865
Test name
Test status
Simulation time 64062141 ps
CPU time 0.74 seconds
Started Jan 24 01:28:02 PM PST 24
Finished Jan 24 01:28:30 PM PST 24
Peak memory 195360 kb
Host smart-02a17bca-7677-4352-89ff-83ba5700d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293684560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4293684560
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1252880149
Short name T753
Test name
Test status
Simulation time 935250543 ps
CPU time 24.02 seconds
Started Jan 24 01:28:03 PM PST 24
Finished Jan 24 01:28:55 PM PST 24
Peak memory 196968 kb
Host smart-ba8467bb-ec60-407c-8a95-aa152890de24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252880149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1252880149
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1422743218
Short name T816
Test name
Test status
Simulation time 225124961 ps
CPU time 1.02 seconds
Started Jan 24 01:28:27 PM PST 24
Finished Jan 24 01:28:51 PM PST 24
Peak memory 196740 kb
Host smart-3c3027ff-17dd-46f1-8395-57a4d3987aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422743218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1422743218
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.600825135
Short name T497
Test name
Test status
Simulation time 64570341 ps
CPU time 1.11 seconds
Started Jan 24 01:45:40 PM PST 24
Finished Jan 24 01:45:46 PM PST 24
Peak memory 196852 kb
Host smart-4fe54f2a-357a-49de-8a8a-7942d6936833
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600825135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.600825135
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4280102259
Short name T247
Test name
Test status
Simulation time 149656782 ps
CPU time 1.79 seconds
Started Jan 24 01:28:05 PM PST 24
Finished Jan 24 01:28:35 PM PST 24
Peak memory 197148 kb
Host smart-2845b1be-5356-46c5-96b9-aba5c0747d64
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280102259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4280102259
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2498486825
Short name T297
Test name
Test status
Simulation time 984773179 ps
CPU time 2.22 seconds
Started Jan 24 03:22:01 PM PST 24
Finished Jan 24 03:22:08 PM PST 24
Peak memory 196648 kb
Host smart-9ae8a5b2-2da5-48ca-a0a0-f4c43f2f97b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498486825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2498486825
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2362788541
Short name T792
Test name
Test status
Simulation time 51048521 ps
CPU time 1.01 seconds
Started Jan 24 01:28:06 PM PST 24
Finished Jan 24 01:28:35 PM PST 24
Peak memory 196184 kb
Host smart-cdef3d65-b9c8-41a8-846b-842c0ef45ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362788541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2362788541
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4100847525
Short name T814
Test name
Test status
Simulation time 67557677 ps
CPU time 1.32 seconds
Started Jan 24 02:40:03 PM PST 24
Finished Jan 24 02:40:21 PM PST 24
Peak memory 195992 kb
Host smart-699292db-6e9f-45ae-b46e-82a34b17d6c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100847525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4100847525
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3526069304
Short name T286
Test name
Test status
Simulation time 1927052481 ps
CPU time 6.4 seconds
Started Jan 24 01:28:03 PM PST 24
Finished Jan 24 01:28:37 PM PST 24
Peak memory 198132 kb
Host smart-e9b72db9-7b5d-4f8a-8b56-b519bbec9c95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526069304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3526069304
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1980584695
Short name T604
Test name
Test status
Simulation time 178795827 ps
CPU time 1.43 seconds
Started Jan 24 01:28:03 PM PST 24
Finished Jan 24 01:28:32 PM PST 24
Peak memory 195752 kb
Host smart-7eb3e4f0-f846-466e-bc19-241466baa342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980584695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1980584695
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3013995761
Short name T403
Test name
Test status
Simulation time 209038278 ps
CPU time 1.15 seconds
Started Jan 24 02:05:46 PM PST 24
Finished Jan 24 02:06:38 PM PST 24
Peak memory 195952 kb
Host smart-5dc59363-2d18-490b-b1d2-cc9b343ddcad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013995761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3013995761
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.119170228
Short name T291
Test name
Test status
Simulation time 12798548539 ps
CPU time 148.38 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:31:28 PM PST 24
Peak memory 198220 kb
Host smart-92a19240-3b6a-41ef-a915-eb2847fd7660
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119170228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.119170228
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.396673795
Short name T419
Test name
Test status
Simulation time 82057719246 ps
CPU time 1204.35 seconds
Started Jan 24 01:28:24 PM PST 24
Finished Jan 24 01:48:51 PM PST 24
Peak memory 198452 kb
Host smart-d0c9c456-daf7-47a5-a167-e32f885afba2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=396673795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.396673795
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.816296849
Short name T546
Test name
Test status
Simulation time 16392218 ps
CPU time 0.58 seconds
Started Jan 24 01:28:24 PM PST 24
Finished Jan 24 01:28:47 PM PST 24
Peak memory 194208 kb
Host smart-a584a90b-4c0e-4cbe-9d96-a47e888d00a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816296849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.816296849
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3175830895
Short name T339
Test name
Test status
Simulation time 75096349 ps
CPU time 0.79 seconds
Started Jan 24 01:28:23 PM PST 24
Finished Jan 24 01:28:46 PM PST 24
Peak memory 195320 kb
Host smart-7c5b54c1-3502-4799-9433-5c334fb6b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175830895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3175830895
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1409402194
Short name T743
Test name
Test status
Simulation time 1222999848 ps
CPU time 15.46 seconds
Started Jan 24 01:28:25 PM PST 24
Finished Jan 24 01:29:03 PM PST 24
Peak memory 197012 kb
Host smart-b07452c8-66de-4d4c-984d-28dc3c20be9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409402194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1409402194
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.300840007
Short name T348
Test name
Test status
Simulation time 89413473 ps
CPU time 0.95 seconds
Started Jan 24 01:28:25 PM PST 24
Finished Jan 24 01:28:48 PM PST 24
Peak memory 196560 kb
Host smart-dfed459f-446b-4c5c-b08d-c1090e5262cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300840007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.300840007
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2565412725
Short name T226
Test name
Test status
Simulation time 89511308 ps
CPU time 1.42 seconds
Started Jan 24 01:28:25 PM PST 24
Finished Jan 24 01:28:49 PM PST 24
Peak memory 196024 kb
Host smart-ce088392-a0cf-4a67-962f-b428430de88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565412725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2565412725
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.828911232
Short name T845
Test name
Test status
Simulation time 131178191 ps
CPU time 0.88 seconds
Started Jan 24 01:28:26 PM PST 24
Finished Jan 24 01:28:49 PM PST 24
Peak memory 196196 kb
Host smart-49102f82-c7d8-40b8-8352-e78466ca38bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828911232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.828911232
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1431612983
Short name T442
Test name
Test status
Simulation time 68732044 ps
CPU time 1.62 seconds
Started Jan 24 01:28:27 PM PST 24
Finished Jan 24 01:28:52 PM PST 24
Peak memory 196852 kb
Host smart-990ed53a-4ea0-4399-a970-37cfd7e608a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431612983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1431612983
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.191695944
Short name T645
Test name
Test status
Simulation time 251478173 ps
CPU time 1.01 seconds
Started Jan 24 01:28:23 PM PST 24
Finished Jan 24 01:28:46 PM PST 24
Peak memory 196220 kb
Host smart-3c920e14-cf97-472c-bafd-1cd561f50645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191695944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.191695944
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3448856376
Short name T429
Test name
Test status
Simulation time 152484785 ps
CPU time 1.09 seconds
Started Jan 24 01:28:24 PM PST 24
Finished Jan 24 01:28:47 PM PST 24
Peak memory 196900 kb
Host smart-3ee6a784-f65d-4bde-8d21-474b2e9f5508
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448856376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3448856376
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.207647014
Short name T870
Test name
Test status
Simulation time 427543413 ps
CPU time 2.11 seconds
Started Jan 24 01:28:24 PM PST 24
Finished Jan 24 01:28:49 PM PST 24
Peak memory 198160 kb
Host smart-8c13eed9-9476-41dd-b934-fb10de2718c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207647014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.207647014
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.4001904215
Short name T377
Test name
Test status
Simulation time 55718453 ps
CPU time 1 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 196624 kb
Host smart-64b02a84-0d0b-4748-9b9f-ffd333e7911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001904215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.4001904215
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1296702799
Short name T656
Test name
Test status
Simulation time 101675845 ps
CPU time 1.04 seconds
Started Jan 24 01:28:23 PM PST 24
Finished Jan 24 01:28:46 PM PST 24
Peak memory 195884 kb
Host smart-e2d70146-1c4a-4923-9e67-928e581207ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296702799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1296702799
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2273425979
Short name T241
Test name
Test status
Simulation time 8570552717 ps
CPU time 150.26 seconds
Started Jan 24 01:28:26 PM PST 24
Finished Jan 24 01:31:19 PM PST 24
Peak memory 198340 kb
Host smart-77462639-16f8-49b4-b42f-d4bc9061224c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273425979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2273425979
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2616143024
Short name T545
Test name
Test status
Simulation time 29714508092 ps
CPU time 553.99 seconds
Started Jan 24 01:28:34 PM PST 24
Finished Jan 24 01:38:12 PM PST 24
Peak memory 198416 kb
Host smart-06af79e4-ff78-43ba-bdb0-2cc85660915f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2616143024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2616143024
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.691080173
Short name T620
Test name
Test status
Simulation time 43278826 ps
CPU time 0.58 seconds
Started Jan 24 01:28:27 PM PST 24
Finished Jan 24 01:28:51 PM PST 24
Peak memory 193852 kb
Host smart-3afdb96c-b1ab-47fa-9410-07a74a39aae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691080173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.691080173
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.841698051
Short name T628
Test name
Test status
Simulation time 18438082 ps
CPU time 0.74 seconds
Started Jan 24 01:28:34 PM PST 24
Finished Jan 24 01:28:58 PM PST 24
Peak memory 194380 kb
Host smart-9d1cfe18-e8a4-4ed5-8988-4b89976a73d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841698051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.841698051
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3732437692
Short name T397
Test name
Test status
Simulation time 1071649650 ps
CPU time 16.77 seconds
Started Jan 24 01:28:28 PM PST 24
Finished Jan 24 01:29:07 PM PST 24
Peak memory 196432 kb
Host smart-b5634fe4-0fed-40b6-8fb8-d58eb5a0f306
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732437692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3732437692
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2718768016
Short name T256
Test name
Test status
Simulation time 28457924 ps
CPU time 0.67 seconds
Started Jan 24 01:28:26 PM PST 24
Finished Jan 24 01:28:50 PM PST 24
Peak memory 195336 kb
Host smart-54a56012-4a15-4dce-b717-71b712db76e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718768016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2718768016
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.145715475
Short name T666
Test name
Test status
Simulation time 95842361 ps
CPU time 1.03 seconds
Started Jan 24 01:28:30 PM PST 24
Finished Jan 24 01:28:53 PM PST 24
Peak memory 196248 kb
Host smart-525fdca6-0288-4b89-b6bc-c53ee5d01ab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145715475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.145715475
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2299394957
Short name T125
Test name
Test status
Simulation time 93714445 ps
CPU time 1.94 seconds
Started Jan 24 01:28:29 PM PST 24
Finished Jan 24 01:28:54 PM PST 24
Peak memory 198164 kb
Host smart-1f3df665-b88f-45b2-b3c4-8cbe7260451c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299394957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2299394957
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1445618295
Short name T376
Test name
Test status
Simulation time 52587986 ps
CPU time 1.72 seconds
Started Jan 24 01:28:26 PM PST 24
Finished Jan 24 01:28:51 PM PST 24
Peak memory 195812 kb
Host smart-260ba05b-a644-4cc5-9999-5237be0a37ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445618295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1445618295
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2753340435
Short name T689
Test name
Test status
Simulation time 152690025 ps
CPU time 1.31 seconds
Started Jan 24 01:28:31 PM PST 24
Finished Jan 24 01:28:55 PM PST 24
Peak memory 197168 kb
Host smart-ed4fbfef-18f7-422c-bd86-3f91974fa4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753340435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2753340435
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.902546093
Short name T468
Test name
Test status
Simulation time 152411422 ps
CPU time 1.02 seconds
Started Jan 24 01:28:30 PM PST 24
Finished Jan 24 01:28:53 PM PST 24
Peak memory 196164 kb
Host smart-6040f2f6-7345-4ca4-9074-469e7b19d77e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902546093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.902546093
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2986583221
Short name T729
Test name
Test status
Simulation time 116124925 ps
CPU time 5.29 seconds
Started Jan 24 01:28:30 PM PST 24
Finished Jan 24 01:28:58 PM PST 24
Peak memory 198136 kb
Host smart-ed9e6390-2cfd-4d19-baa1-514e6d98fe51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986583221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2986583221
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2628927507
Short name T618
Test name
Test status
Simulation time 488131725 ps
CPU time 1.41 seconds
Started Jan 24 01:28:34 PM PST 24
Finished Jan 24 01:28:58 PM PST 24
Peak memory 196448 kb
Host smart-891e659e-f700-4ddb-95bf-86ede07f0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628927507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2628927507
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2637177770
Short name T274
Test name
Test status
Simulation time 65400568 ps
CPU time 1.08 seconds
Started Jan 24 01:28:27 PM PST 24
Finished Jan 24 01:28:51 PM PST 24
Peak memory 195956 kb
Host smart-f0288640-ce81-41ff-ba40-d388021be923
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637177770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2637177770
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3495508885
Short name T493
Test name
Test status
Simulation time 6043111413 ps
CPU time 148.29 seconds
Started Jan 24 01:28:30 PM PST 24
Finished Jan 24 01:31:21 PM PST 24
Peak memory 198332 kb
Host smart-b8107cd4-2b67-424a-ac63-6849e7205d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495508885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3495508885
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3700748705
Short name T387
Test name
Test status
Simulation time 110696221815 ps
CPU time 355.92 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:34:55 PM PST 24
Peak memory 198452 kb
Host smart-e5ede8ce-b404-42bc-b90d-ae5ad1e90f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3700748705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3700748705
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1964512633
Short name T840
Test name
Test status
Simulation time 39128767 ps
CPU time 0.56 seconds
Started Jan 24 01:28:40 PM PST 24
Finished Jan 24 01:29:03 PM PST 24
Peak memory 193848 kb
Host smart-c109e922-0912-40af-bbb3-c1f37b3c0fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964512633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1964512633
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4141349104
Short name T270
Test name
Test status
Simulation time 39087694 ps
CPU time 0.76 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 195284 kb
Host smart-c361ac85-5418-4d5f-a235-1266d5d6a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141349104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4141349104
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2432286169
Short name T328
Test name
Test status
Simulation time 397937887 ps
CPU time 19.28 seconds
Started Jan 24 01:28:39 PM PST 24
Finished Jan 24 01:29:22 PM PST 24
Peak memory 197032 kb
Host smart-6d95abc7-34dc-4018-8ca8-4209c02da79b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432286169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2432286169
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1829468320
Short name T458
Test name
Test status
Simulation time 72019895 ps
CPU time 1.25 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:01 PM PST 24
Peak memory 196652 kb
Host smart-45972e0c-c078-4eb0-94be-3b026f2eada5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829468320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1829468320
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3469875590
Short name T683
Test name
Test status
Simulation time 40018209 ps
CPU time 1.58 seconds
Started Jan 24 01:28:29 PM PST 24
Finished Jan 24 01:28:53 PM PST 24
Peak memory 196796 kb
Host smart-68f4e5a0-c801-4149-a8c8-b09a0d218505
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469875590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3469875590
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.49540325
Short name T223
Test name
Test status
Simulation time 246726727 ps
CPU time 2.19 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:01 PM PST 24
Peak memory 198192 kb
Host smart-4de3d184-fbd5-4bd7-b11e-631a2ea76887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49540325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.49540325
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3469057965
Short name T307
Test name
Test status
Simulation time 65780586 ps
CPU time 1.27 seconds
Started Jan 24 01:28:31 PM PST 24
Finished Jan 24 01:28:54 PM PST 24
Peak memory 198240 kb
Host smart-deb60707-6655-44e0-9dbb-59f43fe4e18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469057965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3469057965
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3369425000
Short name T521
Test name
Test status
Simulation time 149745450 ps
CPU time 0.89 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 195988 kb
Host smart-623f5ce2-0e04-44eb-9aa2-8af9a113fdf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369425000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3369425000
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3276646583
Short name T809
Test name
Test status
Simulation time 286375598 ps
CPU time 2.85 seconds
Started Jan 24 01:28:40 PM PST 24
Finished Jan 24 01:29:06 PM PST 24
Peak memory 197992 kb
Host smart-1c05a710-5a79-4e64-a1b2-a84e26c38a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276646583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3276646583
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2356091968
Short name T232
Test name
Test status
Simulation time 70841867 ps
CPU time 1.29 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:01 PM PST 24
Peak memory 198100 kb
Host smart-bf7e31fe-3ac1-482a-8a7b-16438808088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356091968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2356091968
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1942000331
Short name T459
Test name
Test status
Simulation time 69183826 ps
CPU time 1.35 seconds
Started Jan 24 01:28:37 PM PST 24
Finished Jan 24 01:29:00 PM PST 24
Peak memory 196868 kb
Host smart-b7240cd2-bed5-4858-b83b-7f6af09b1514
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942000331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1942000331
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.4241220959
Short name T310
Test name
Test status
Simulation time 5946140335 ps
CPU time 150.83 seconds
Started Jan 24 01:28:41 PM PST 24
Finished Jan 24 01:31:35 PM PST 24
Peak memory 198340 kb
Host smart-14b0bee2-f20f-4aa5-8608-dc057c3c17ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241220959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.4241220959
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2237365088
Short name T260
Test name
Test status
Simulation time 83395377245 ps
CPU time 695.57 seconds
Started Jan 24 02:58:38 PM PST 24
Finished Jan 24 03:10:20 PM PST 24
Peak memory 198476 kb
Host smart-4ba9994e-b853-4ab2-8854-b88cbda15419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2237365088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2237365088
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2035118529
Short name T57
Test name
Test status
Simulation time 14544009 ps
CPU time 0.57 seconds
Started Jan 24 01:38:01 PM PST 24
Finished Jan 24 01:38:28 PM PST 24
Peak memory 193984 kb
Host smart-350fc146-f01f-4050-9691-c3793db83a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035118529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2035118529
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1406440055
Short name T606
Test name
Test status
Simulation time 29889834 ps
CPU time 0.73 seconds
Started Jan 24 01:28:39 PM PST 24
Finished Jan 24 01:29:03 PM PST 24
Peak memory 194896 kb
Host smart-0e47affd-22b0-41d6-a786-ad8e8e15d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406440055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1406440055
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3859751073
Short name T530
Test name
Test status
Simulation time 346215518 ps
CPU time 17.03 seconds
Started Jan 24 01:28:39 PM PST 24
Finished Jan 24 01:29:19 PM PST 24
Peak memory 198164 kb
Host smart-abdc5ee8-c007-4c91-a3e4-bfce6e72c8f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859751073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3859751073
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3081743688
Short name T246
Test name
Test status
Simulation time 62554058 ps
CPU time 1.03 seconds
Started Jan 24 02:07:05 PM PST 24
Finished Jan 24 02:07:43 PM PST 24
Peak memory 197096 kb
Host smart-d4cac744-7ea5-46b4-bdaa-b331f83620a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081743688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3081743688
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1795007694
Short name T723
Test name
Test status
Simulation time 107599404 ps
CPU time 2.29 seconds
Started Jan 24 02:46:44 PM PST 24
Finished Jan 24 02:46:50 PM PST 24
Peak memory 198104 kb
Host smart-1379ef63-3502-47e2-8201-fba8ad6d811f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795007694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1795007694
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4269228920
Short name T765
Test name
Test status
Simulation time 125855849 ps
CPU time 2.24 seconds
Started Jan 24 01:28:39 PM PST 24
Finished Jan 24 01:29:04 PM PST 24
Peak memory 197292 kb
Host smart-892545c5-4ea4-4c13-9fb0-3d0aab26b158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269228920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4269228920
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3118900448
Short name T360
Test name
Test status
Simulation time 55225385 ps
CPU time 1.18 seconds
Started Jan 24 01:28:44 PM PST 24
Finished Jan 24 01:29:08 PM PST 24
Peak memory 196036 kb
Host smart-d217fec6-3ba8-40f1-b68d-b06a3ba4a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118900448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3118900448
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3184568217
Short name T511
Test name
Test status
Simulation time 21896496 ps
CPU time 0.8 seconds
Started Jan 24 01:28:45 PM PST 24
Finished Jan 24 01:29:08 PM PST 24
Peak memory 196308 kb
Host smart-ce5bd93a-35b4-4e8e-87be-897662ef15c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184568217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3184568217
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.156134248
Short name T479
Test name
Test status
Simulation time 334624349 ps
CPU time 5.41 seconds
Started Jan 24 01:28:39 PM PST 24
Finished Jan 24 01:29:08 PM PST 24
Peak memory 198144 kb
Host smart-53bda7b8-db4e-4cbe-87c4-b910fdc76356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156134248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.156134248
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3960023184
Short name T831
Test name
Test status
Simulation time 66223621 ps
CPU time 1.24 seconds
Started Jan 24 01:28:41 PM PST 24
Finished Jan 24 01:29:06 PM PST 24
Peak memory 196996 kb
Host smart-f392e748-7a88-4987-9fa8-4ea7a96a96ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960023184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3960023184
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.4218242471
Short name T877
Test name
Test status
Simulation time 185613466 ps
CPU time 0.77 seconds
Started Jan 24 01:28:43 PM PST 24
Finished Jan 24 01:29:07 PM PST 24
Peak memory 196032 kb
Host smart-3bc7438f-0d8c-47e5-9831-615fc9af88fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218242471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.4218242471
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3070238025
Short name T516
Test name
Test status
Simulation time 89082919190 ps
CPU time 219.84 seconds
Started Jan 24 03:02:45 PM PST 24
Finished Jan 24 03:06:38 PM PST 24
Peak memory 198344 kb
Host smart-d3928a66-3f61-4b01-9057-05c30aa06cf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070238025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3070238025
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.571158412
Short name T708
Test name
Test status
Simulation time 518158070753 ps
CPU time 673.48 seconds
Started Jan 24 01:28:41 PM PST 24
Finished Jan 24 01:40:17 PM PST 24
Peak memory 206676 kb
Host smart-20250198-5cc7-4a02-8825-ff21e9e1f34f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=571158412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.571158412
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.484309783
Short name T469
Test name
Test status
Simulation time 54553131 ps
CPU time 0.58 seconds
Started Jan 24 01:22:12 PM PST 24
Finished Jan 24 01:23:10 PM PST 24
Peak memory 194072 kb
Host smart-d94f7d71-131b-4d59-b126-6e9d344efa4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484309783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.484309783
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.482503546
Short name T646
Test name
Test status
Simulation time 104039934 ps
CPU time 0.83 seconds
Started Jan 24 01:22:08 PM PST 24
Finished Jan 24 01:23:08 PM PST 24
Peak memory 195400 kb
Host smart-2f634e31-23bd-4f0f-86fc-4c76f8869611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482503546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.482503546
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.145841015
Short name T409
Test name
Test status
Simulation time 1335899227 ps
CPU time 11.21 seconds
Started Jan 24 01:22:03 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 197036 kb
Host smart-bed60783-bd96-4b23-873b-9668698e7bb0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145841015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.145841015
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1960718348
Short name T706
Test name
Test status
Simulation time 60569339 ps
CPU time 0.85 seconds
Started Jan 24 01:22:12 PM PST 24
Finished Jan 24 01:23:11 PM PST 24
Peak memory 196660 kb
Host smart-3fc71fce-fa48-4229-9d85-c76b93df61de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960718348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1960718348
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1279558489
Short name T300
Test name
Test status
Simulation time 129419835 ps
CPU time 1.27 seconds
Started Jan 24 01:22:11 PM PST 24
Finished Jan 24 01:23:10 PM PST 24
Peak memory 196148 kb
Host smart-1faae732-477b-4fe0-afc3-0affb2fdf922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279558489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1279558489
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4198474910
Short name T123
Test name
Test status
Simulation time 25924631 ps
CPU time 1.07 seconds
Started Jan 24 01:38:28 PM PST 24
Finished Jan 24 01:38:52 PM PST 24
Peak memory 196468 kb
Host smart-435c52dd-81d5-4e15-9597-8e5d03c95488
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198474910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4198474910
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4016052986
Short name T253
Test name
Test status
Simulation time 173824658 ps
CPU time 3.23 seconds
Started Jan 24 01:22:01 PM PST 24
Finished Jan 24 01:23:01 PM PST 24
Peak memory 195968 kb
Host smart-7449f9e2-98a6-4bf1-bb46-cdff9cccdf20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016052986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4016052986
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3815123348
Short name T651
Test name
Test status
Simulation time 54577103 ps
CPU time 1.25 seconds
Started Jan 24 01:22:05 PM PST 24
Finished Jan 24 01:23:05 PM PST 24
Peak memory 197076 kb
Host smart-598d09d9-2b8a-4f04-90f7-1399ca44fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815123348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3815123348
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4217266436
Short name T535
Test name
Test status
Simulation time 43926451 ps
CPU time 0.99 seconds
Started Jan 24 01:22:04 PM PST 24
Finished Jan 24 01:23:04 PM PST 24
Peak memory 196856 kb
Host smart-9ca51be2-c5cf-411c-859a-567698781ea4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217266436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4217266436
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3101699686
Short name T496
Test name
Test status
Simulation time 3717306409 ps
CPU time 6.1 seconds
Started Jan 24 01:22:03 PM PST 24
Finished Jan 24 01:23:08 PM PST 24
Peak memory 198120 kb
Host smart-f7b16476-4171-4e79-85d7-6de100204b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101699686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3101699686
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3002726346
Short name T72
Test name
Test status
Simulation time 158719123 ps
CPU time 1.32 seconds
Started Jan 24 01:22:07 PM PST 24
Finished Jan 24 01:23:07 PM PST 24
Peak memory 195716 kb
Host smart-44b1817a-0986-406c-bb89-8cc0fa0bc226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002726346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3002726346
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1420144036
Short name T878
Test name
Test status
Simulation time 108275975 ps
CPU time 1.44 seconds
Started Jan 24 01:22:04 PM PST 24
Finished Jan 24 01:23:05 PM PST 24
Peak memory 195744 kb
Host smart-51906f52-f694-406c-8b71-bd2f901b8034
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420144036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1420144036
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2760305153
Short name T758
Test name
Test status
Simulation time 8103727837 ps
CPU time 209.98 seconds
Started Jan 24 01:22:07 PM PST 24
Finished Jan 24 01:26:36 PM PST 24
Peak memory 198416 kb
Host smart-fdbabff6-d2a9-400f-8035-2585c4b8d8fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760305153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2760305153
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2670580882
Short name T556
Test name
Test status
Simulation time 131883953977 ps
CPU time 392.72 seconds
Started Jan 24 01:22:04 PM PST 24
Finished Jan 24 01:29:35 PM PST 24
Peak memory 198456 kb
Host smart-a13d6f79-837a-4cd7-84a6-04d40a1e7685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2670580882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2670580882
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1370666763
Short name T451
Test name
Test status
Simulation time 13731004 ps
CPU time 0.57 seconds
Started Jan 24 01:22:22 PM PST 24
Finished Jan 24 01:23:18 PM PST 24
Peak memory 195668 kb
Host smart-690ea9b9-b659-4cee-b9c9-0a24e552a1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370666763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1370666763
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.573807859
Short name T670
Test name
Test status
Simulation time 22797066 ps
CPU time 0.74 seconds
Started Jan 24 01:22:21 PM PST 24
Finished Jan 24 01:23:18 PM PST 24
Peak memory 195448 kb
Host smart-ed25a28a-9edd-4ca8-bda9-399069a5e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573807859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.573807859
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3009185247
Short name T808
Test name
Test status
Simulation time 340179620 ps
CPU time 18.09 seconds
Started Jan 24 01:42:47 PM PST 24
Finished Jan 24 01:43:44 PM PST 24
Peak memory 197184 kb
Host smart-448e32e4-e7c2-47a9-8c89-36f049de91cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009185247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3009185247
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1708519601
Short name T453
Test name
Test status
Simulation time 30330383 ps
CPU time 0.7 seconds
Started Jan 24 01:35:50 PM PST 24
Finished Jan 24 01:36:18 PM PST 24
Peak memory 194708 kb
Host smart-eb966f5d-8fbb-4154-97fb-99fed221e819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708519601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1708519601
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2632458947
Short name T801
Test name
Test status
Simulation time 70919815 ps
CPU time 1.14 seconds
Started Jan 24 01:22:14 PM PST 24
Finished Jan 24 01:23:13 PM PST 24
Peak memory 196084 kb
Host smart-d9a8eb6a-915f-4d3d-831a-703079077320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632458947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2632458947
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2687437272
Short name T630
Test name
Test status
Simulation time 357282092 ps
CPU time 3.66 seconds
Started Jan 24 01:22:16 PM PST 24
Finished Jan 24 01:23:17 PM PST 24
Peak memory 198124 kb
Host smart-ec71e06c-dd55-4f93-a076-0e3f5069a1b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687437272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2687437272
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2052045249
Short name T848
Test name
Test status
Simulation time 186425066 ps
CPU time 1.59 seconds
Started Jan 24 01:22:21 PM PST 24
Finished Jan 24 01:23:18 PM PST 24
Peak memory 196288 kb
Host smart-f00861c5-4f36-4f48-b86f-5fa25976d5d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052045249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2052045249
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3265181242
Short name T842
Test name
Test status
Simulation time 51432515 ps
CPU time 1.05 seconds
Started Jan 24 01:22:13 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 196040 kb
Host smart-9e963db1-28df-40c8-a217-10f34017b2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265181242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3265181242
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.647481190
Short name T414
Test name
Test status
Simulation time 339049763 ps
CPU time 0.99 seconds
Started Jan 24 01:35:56 PM PST 24
Finished Jan 24 01:36:22 PM PST 24
Peak memory 196080 kb
Host smart-fad2d5ef-0173-4232-a42c-86264ad649d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647481190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.647481190
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2993752837
Short name T566
Test name
Test status
Simulation time 528134484 ps
CPU time 3.23 seconds
Started Jan 24 01:22:17 PM PST 24
Finished Jan 24 01:23:17 PM PST 24
Peak memory 198136 kb
Host smart-e100d5c6-03bf-4c3f-b4fb-a9f9a3fc8406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993752837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2993752837
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3321297462
Short name T538
Test name
Test status
Simulation time 54779516 ps
CPU time 1.05 seconds
Started Jan 24 01:22:12 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 196700 kb
Host smart-b57ce2dd-a497-40f9-aea7-b7da139a19f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321297462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3321297462
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1284009709
Short name T358
Test name
Test status
Simulation time 57729138 ps
CPU time 1.07 seconds
Started Jan 24 01:22:22 PM PST 24
Finished Jan 24 01:23:19 PM PST 24
Peak memory 196376 kb
Host smart-e08089fe-d48e-4868-b076-dd988508ccd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284009709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1284009709
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.100918423
Short name T625
Test name
Test status
Simulation time 41786921111 ps
CPU time 131.95 seconds
Started Jan 24 02:33:51 PM PST 24
Finished Jan 24 02:36:18 PM PST 24
Peak memory 198380 kb
Host smart-49101486-f380-4c75-9ac8-fd0cbbc0061d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100918423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.100918423
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2214712616
Short name T750
Test name
Test status
Simulation time 255385382757 ps
CPU time 937.67 seconds
Started Jan 24 01:22:12 PM PST 24
Finished Jan 24 01:38:48 PM PST 24
Peak memory 198308 kb
Host smart-1a16f6d8-3724-48d0-a89b-906dfd1c723a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2214712616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2214712616
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2552442110
Short name T766
Test name
Test status
Simulation time 13844035 ps
CPU time 0.58 seconds
Started Jan 24 01:22:26 PM PST 24
Finished Jan 24 01:23:23 PM PST 24
Peak memory 194104 kb
Host smart-d8be467e-390a-46d0-b9da-78d9a5b32fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552442110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2552442110
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.994666821
Short name T491
Test name
Test status
Simulation time 54355349 ps
CPU time 0.86 seconds
Started Jan 24 01:22:21 PM PST 24
Finished Jan 24 01:23:17 PM PST 24
Peak memory 195468 kb
Host smart-416d973e-1c2c-4705-ba92-c6210fdccc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994666821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.994666821
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3334253649
Short name T585
Test name
Test status
Simulation time 2686500769 ps
CPU time 25 seconds
Started Jan 24 01:22:13 PM PST 24
Finished Jan 24 01:23:36 PM PST 24
Peak memory 198272 kb
Host smart-c44597b5-afa2-4da7-b4ce-5879934aa3bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334253649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3334253649
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1971760772
Short name T572
Test name
Test status
Simulation time 42487914 ps
CPU time 0.79 seconds
Started Jan 24 01:22:21 PM PST 24
Finished Jan 24 01:23:17 PM PST 24
Peak memory 195836 kb
Host smart-6b83a14b-7621-442d-8c97-f956d4e3fabc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971760772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1971760772
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3920039010
Short name T638
Test name
Test status
Simulation time 98117085 ps
CPU time 0.91 seconds
Started Jan 24 01:27:02 PM PST 24
Finished Jan 24 01:27:41 PM PST 24
Peak memory 196624 kb
Host smart-a80fa904-ed04-437a-97e6-675fa00bc9d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920039010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3920039010
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2551995237
Short name T305
Test name
Test status
Simulation time 29393444 ps
CPU time 1.22 seconds
Started Jan 24 01:22:13 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 196864 kb
Host smart-d348a705-f1e7-4e69-bc13-8e3f8794cdf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551995237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2551995237
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.411294680
Short name T851
Test name
Test status
Simulation time 287196259 ps
CPU time 1.63 seconds
Started Jan 24 01:22:17 PM PST 24
Finished Jan 24 01:23:16 PM PST 24
Peak memory 196212 kb
Host smart-c931b8a6-66cf-4232-8cf1-2ab3133db456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411294680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.411294680
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3746204365
Short name T676
Test name
Test status
Simulation time 52413495 ps
CPU time 1.08 seconds
Started Jan 24 01:22:21 PM PST 24
Finished Jan 24 01:23:18 PM PST 24
Peak memory 196140 kb
Host smart-9fa29a1a-b855-4993-99c9-dd6cf860bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746204365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3746204365
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4045966548
Short name T799
Test name
Test status
Simulation time 66039633 ps
CPU time 0.75 seconds
Started Jan 24 01:22:14 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 195472 kb
Host smart-e4059262-9977-4b78-b0e5-916ba12d589a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045966548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4045966548
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3469324307
Short name T266
Test name
Test status
Simulation time 75961606 ps
CPU time 1.33 seconds
Started Jan 24 01:22:21 PM PST 24
Finished Jan 24 01:23:18 PM PST 24
Peak memory 198180 kb
Host smart-414b8c76-7b71-4697-bfc2-b6e77974839c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469324307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3469324307
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4199038460
Short name T836
Test name
Test status
Simulation time 73072013 ps
CPU time 1.26 seconds
Started Jan 24 01:22:13 PM PST 24
Finished Jan 24 01:23:12 PM PST 24
Peak memory 196016 kb
Host smart-d36522c6-fc65-4022-a418-8675a47cecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199038460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4199038460
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.669936473
Short name T616
Test name
Test status
Simulation time 29108246 ps
CPU time 0.84 seconds
Started Jan 24 01:22:18 PM PST 24
Finished Jan 24 01:23:15 PM PST 24
Peak memory 196152 kb
Host smart-23350d1c-28ff-4e36-b10d-c75f44e696f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669936473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.669936473
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.913536272
Short name T284
Test name
Test status
Simulation time 5551951406 ps
CPU time 78.82 seconds
Started Jan 24 01:27:00 PM PST 24
Finished Jan 24 01:28:58 PM PST 24
Peak memory 198372 kb
Host smart-0bc7bd9e-6f74-4345-9f32-d4b7dc5315c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913536272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.913536272
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1558871925
Short name T751
Test name
Test status
Simulation time 76805998997 ps
CPU time 1067.46 seconds
Started Jan 24 01:22:23 PM PST 24
Finished Jan 24 01:41:06 PM PST 24
Peak memory 198352 kb
Host smart-a0fca4dd-17f6-4671-bf67-68d184c21894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1558871925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1558871925
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4008061048
Short name T841
Test name
Test status
Simulation time 15288367 ps
CPU time 0.57 seconds
Started Jan 24 01:22:36 PM PST 24
Finished Jan 24 01:23:32 PM PST 24
Peak memory 194080 kb
Host smart-f197f938-bf51-44dd-b40a-73249a25805a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008061048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4008061048
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1021181341
Short name T837
Test name
Test status
Simulation time 63391776 ps
CPU time 0.71 seconds
Started Jan 24 02:40:42 PM PST 24
Finished Jan 24 02:40:53 PM PST 24
Peak memory 194316 kb
Host smart-03ea5279-14c2-43f6-9322-3ed417dfb8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021181341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1021181341
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4220267064
Short name T69
Test name
Test status
Simulation time 1028155150 ps
CPU time 10.07 seconds
Started Jan 24 02:35:00 PM PST 24
Finished Jan 24 02:35:14 PM PST 24
Peak memory 198168 kb
Host smart-c7494e55-fc89-42b0-8576-b3705bf1bd30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220267064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4220267064
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2177107598
Short name T263
Test name
Test status
Simulation time 837281290 ps
CPU time 0.99 seconds
Started Jan 24 01:22:38 PM PST 24
Finished Jan 24 01:23:35 PM PST 24
Peak memory 196752 kb
Host smart-7db043b6-e8d0-412e-858b-008b15ba82bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177107598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2177107598
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2540186695
Short name T289
Test name
Test status
Simulation time 470412368 ps
CPU time 1.4 seconds
Started Jan 24 01:57:17 PM PST 24
Finished Jan 24 01:57:21 PM PST 24
Peak memory 197048 kb
Host smart-1c0b1ddf-8fe6-4fc0-87b2-e6fe7affab50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540186695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2540186695
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1331381022
Short name T787
Test name
Test status
Simulation time 187569845 ps
CPU time 1.95 seconds
Started Jan 24 01:22:26 PM PST 24
Finished Jan 24 01:23:24 PM PST 24
Peak memory 198128 kb
Host smart-45c1c53d-b0f7-444e-839b-44d6498138b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331381022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1331381022
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2611539861
Short name T406
Test name
Test status
Simulation time 627602903 ps
CPU time 1.34 seconds
Started Jan 24 01:31:31 PM PST 24
Finished Jan 24 01:32:22 PM PST 24
Peak memory 196072 kb
Host smart-99c45a4b-ed83-4b69-b47d-a431a34bb557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611539861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2611539861
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.540129080
Short name T746
Test name
Test status
Simulation time 369373508 ps
CPU time 1.15 seconds
Started Jan 24 02:36:39 PM PST 24
Finished Jan 24 02:37:11 PM PST 24
Peak memory 196116 kb
Host smart-0175141e-edce-4487-b6d5-0c4021f4c066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540129080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.540129080
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3880806089
Short name T504
Test name
Test status
Simulation time 29503958 ps
CPU time 1.04 seconds
Started Jan 24 02:06:51 PM PST 24
Finished Jan 24 02:07:30 PM PST 24
Peak memory 196136 kb
Host smart-5385ea0c-8ee0-4848-8374-a7014fc1ab9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880806089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3880806089
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1574886959
Short name T364
Test name
Test status
Simulation time 78644639 ps
CPU time 3.48 seconds
Started Jan 24 01:22:36 PM PST 24
Finished Jan 24 01:23:36 PM PST 24
Peak memory 198116 kb
Host smart-23c2c0e3-7e05-4bd3-86c3-18f99195ec5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574886959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1574886959
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1369945027
Short name T636
Test name
Test status
Simulation time 75388823 ps
CPU time 1.34 seconds
Started Jan 24 01:39:00 PM PST 24
Finished Jan 24 01:39:09 PM PST 24
Peak memory 195812 kb
Host smart-0d89885f-6541-4730-b6ea-c40da3735b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369945027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1369945027
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.145533375
Short name T779
Test name
Test status
Simulation time 62815870 ps
CPU time 1.08 seconds
Started Jan 24 02:33:47 PM PST 24
Finished Jan 24 02:34:02 PM PST 24
Peak memory 195924 kb
Host smart-799f81cd-66d1-4ba2-bbae-730eada4764b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145533375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.145533375
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1920355284
Short name T327
Test name
Test status
Simulation time 12697368148 ps
CPU time 167.42 seconds
Started Jan 24 01:22:41 PM PST 24
Finished Jan 24 01:26:24 PM PST 24
Peak memory 198344 kb
Host smart-6838c136-10b4-4a7d-ab6f-898a7a4a5fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920355284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1920355284
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1995560775
Short name T800
Test name
Test status
Simulation time 22245217625 ps
CPU time 349.69 seconds
Started Jan 24 01:22:42 PM PST 24
Finished Jan 24 01:29:28 PM PST 24
Peak memory 198416 kb
Host smart-3fbab831-c8c0-41be-aae0-43399a244cbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1995560775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1995560775
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1910038239
Short name T603
Test name
Test status
Simulation time 13990830 ps
CPU time 0.6 seconds
Started Jan 24 01:39:21 PM PST 24
Finished Jan 24 01:39:25 PM PST 24
Peak memory 194196 kb
Host smart-000b7544-41bd-4d9a-8077-14f83006d0ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910038239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1910038239
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3714292497
Short name T550
Test name
Test status
Simulation time 22330254 ps
CPU time 0.73 seconds
Started Jan 24 01:36:02 PM PST 24
Finished Jan 24 01:36:34 PM PST 24
Peak memory 195048 kb
Host smart-83d0dd08-c578-4ab7-b740-941c236427c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714292497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3714292497
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2732501177
Short name T543
Test name
Test status
Simulation time 1116532307 ps
CPU time 17.48 seconds
Started Jan 24 01:22:47 PM PST 24
Finished Jan 24 01:24:01 PM PST 24
Peak memory 198168 kb
Host smart-de870524-0441-479c-99c3-2a636ad7550d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732501177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2732501177
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1396163865
Short name T304
Test name
Test status
Simulation time 72100242 ps
CPU time 0.66 seconds
Started Jan 24 01:22:47 PM PST 24
Finished Jan 24 01:23:43 PM PST 24
Peak memory 195484 kb
Host smart-26056e03-572e-4647-8960-898267ab64bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396163865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1396163865
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2280099895
Short name T449
Test name
Test status
Simulation time 375925841 ps
CPU time 1.17 seconds
Started Jan 24 01:35:18 PM PST 24
Finished Jan 24 01:35:42 PM PST 24
Peak memory 196972 kb
Host smart-0d799dc3-3ab4-4904-97ca-70c2cd4c0d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280099895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2280099895
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3975637738
Short name T539
Test name
Test status
Simulation time 159473665 ps
CPU time 2.19 seconds
Started Jan 24 02:15:05 PM PST 24
Finished Jan 24 02:15:44 PM PST 24
Peak memory 198184 kb
Host smart-7630a1a2-7589-4851-80b8-ccb61b4f658a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975637738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3975637738
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3372312566
Short name T586
Test name
Test status
Simulation time 170118293 ps
CPU time 1.8 seconds
Started Jan 24 01:22:47 PM PST 24
Finished Jan 24 01:23:45 PM PST 24
Peak memory 196096 kb
Host smart-08afee95-7916-4a43-9d77-ffbce0ecab31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372312566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3372312566
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3486034844
Short name T231
Test name
Test status
Simulation time 78652932 ps
CPU time 0.82 seconds
Started Jan 24 01:22:36 PM PST 24
Finished Jan 24 01:23:33 PM PST 24
Peak memory 195976 kb
Host smart-a9bf4b91-29c1-46df-aef4-e763c7f12c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486034844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3486034844
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2432603475
Short name T640
Test name
Test status
Simulation time 299856412 ps
CPU time 0.88 seconds
Started Jan 24 01:28:55 PM PST 24
Finished Jan 24 01:29:13 PM PST 24
Peak memory 197448 kb
Host smart-a74371f8-a48a-4c87-ab60-dc536947254f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432603475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2432603475
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3303394871
Short name T508
Test name
Test status
Simulation time 915672004 ps
CPU time 4.25 seconds
Started Jan 24 01:40:49 PM PST 24
Finished Jan 24 01:41:37 PM PST 24
Peak memory 198140 kb
Host smart-4030bd81-f47a-4974-bfa7-8eb9c18318fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303394871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3303394871
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2423634719
Short name T407
Test name
Test status
Simulation time 62274784 ps
CPU time 1.2 seconds
Started Jan 24 01:22:40 PM PST 24
Finished Jan 24 01:23:36 PM PST 24
Peak memory 196852 kb
Host smart-edda96f5-0119-4538-a547-5a4608f9e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423634719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2423634719
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.663282039
Short name T336
Test name
Test status
Simulation time 217038248 ps
CPU time 1.37 seconds
Started Jan 24 01:22:34 PM PST 24
Finished Jan 24 01:23:31 PM PST 24
Peak memory 196964 kb
Host smart-98d2aacc-477d-4aba-a67c-5e471bc1ba52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663282039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.663282039
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1163738765
Short name T484
Test name
Test status
Simulation time 4982355855 ps
CPU time 69.6 seconds
Started Jan 24 02:05:05 PM PST 24
Finished Jan 24 02:07:05 PM PST 24
Peak memory 198336 kb
Host smart-c7a96685-be13-4019-8953-7096404c584b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163738765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1163738765
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3027590427
Short name T536
Test name
Test status
Simulation time 35690122475 ps
CPU time 426.31 seconds
Started Jan 24 01:22:45 PM PST 24
Finished Jan 24 01:30:48 PM PST 24
Peak memory 198372 kb
Host smart-7969e653-0072-44b0-913f-0d2d662d2f49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3027590427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3027590427
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.215611164
Short name T52
Test name
Test status
Simulation time 128757730 ps
CPU time 1.02 seconds
Started Jan 24 10:56:12 PM PST 24
Finished Jan 24 10:56:14 PM PST 24
Peak memory 191392 kb
Host smart-d72be4d3-253a-424c-b623-071526789448
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=215611164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.215611164
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2419240615
Short name T205
Test name
Test status
Simulation time 45241450 ps
CPU time 0.95 seconds
Started Jan 24 10:56:14 PM PST 24
Finished Jan 24 10:56:15 PM PST 24
Peak memory 191144 kb
Host smart-56a9064f-4977-4ed5-a21e-9d373de43b9c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419240615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2419240615
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2814585830
Short name T206
Test name
Test status
Simulation time 199167982 ps
CPU time 1.33 seconds
Started Jan 24 11:37:30 PM PST 24
Finished Jan 24 11:37:33 PM PST 24
Peak memory 191420 kb
Host smart-77910f5d-8576-44f4-ab3f-ffdf15ea9ee1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2814585830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2814585830
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1268640243
Short name T144
Test name
Test status
Simulation time 114347657 ps
CPU time 1 seconds
Started Jan 24 10:56:27 PM PST 24
Finished Jan 24 10:56:29 PM PST 24
Peak memory 191316 kb
Host smart-4c96d572-55ec-48c3-a24a-839e75cafc13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268640243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1268640243
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2193989851
Short name T214
Test name
Test status
Simulation time 170034526 ps
CPU time 1.08 seconds
Started Jan 24 10:57:33 PM PST 24
Finished Jan 24 10:57:36 PM PST 24
Peak memory 191380 kb
Host smart-9e3e84d1-493b-4cfe-a3c9-a393be014006
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2193989851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2193989851
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4223977526
Short name T201
Test name
Test status
Simulation time 76358419 ps
CPU time 1.2 seconds
Started Jan 24 10:57:32 PM PST 24
Finished Jan 24 10:57:34 PM PST 24
Peak memory 191428 kb
Host smart-2a26f4e9-e77d-465e-84cb-4ab4ee8e752d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223977526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4223977526
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1395765328
Short name T196
Test name
Test status
Simulation time 579723425 ps
CPU time 0.92 seconds
Started Jan 24 10:57:32 PM PST 24
Finished Jan 24 10:57:33 PM PST 24
Peak memory 191160 kb
Host smart-eff29e68-a710-40ab-ac0b-262d2dc71d4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1395765328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1395765328
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1338535413
Short name T179
Test name
Test status
Simulation time 621090574 ps
CPU time 1.06 seconds
Started Jan 24 10:57:32 PM PST 24
Finished Jan 24 10:57:34 PM PST 24
Peak memory 196952 kb
Host smart-64cc170d-bb2d-4c79-8c65-f73a175c9c86
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338535413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1338535413
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2112415853
Short name T222
Test name
Test status
Simulation time 121034400 ps
CPU time 0.92 seconds
Started Jan 24 10:57:33 PM PST 24
Finished Jan 24 10:57:35 PM PST 24
Peak memory 197008 kb
Host smart-a8d7ac2c-3377-40b3-8e58-0db567ffe20b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2112415853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2112415853
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1635010878
Short name T197
Test name
Test status
Simulation time 47114107 ps
CPU time 0.97 seconds
Started Jan 24 10:57:32 PM PST 24
Finished Jan 24 10:57:34 PM PST 24
Peak memory 191332 kb
Host smart-7b2b6f73-8855-45bb-9051-8ffeda84610b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635010878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1635010878
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3686277371
Short name T156
Test name
Test status
Simulation time 206765690 ps
CPU time 1.09 seconds
Started Jan 25 02:13:14 AM PST 24
Finished Jan 25 02:13:16 AM PST 24
Peak memory 191396 kb
Host smart-213390c9-b7d7-486f-b863-21001c861cb9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3686277371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3686277371
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1533843710
Short name T139
Test name
Test status
Simulation time 142178091 ps
CPU time 1.19 seconds
Started Jan 24 10:57:51 PM PST 24
Finished Jan 24 10:57:53 PM PST 24
Peak memory 197104 kb
Host smart-dfbb583d-0ffb-47f9-b4b7-c2b6d54d6107
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533843710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1533843710
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1614098358
Short name T166
Test name
Test status
Simulation time 74046582 ps
CPU time 1.67 seconds
Started Jan 25 02:11:05 AM PST 24
Finished Jan 25 02:11:08 AM PST 24
Peak memory 191400 kb
Host smart-2c172e6f-eae0-4306-8cde-88e30426a215
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1614098358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1614098358
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3956985120
Short name T175
Test name
Test status
Simulation time 213404510 ps
CPU time 1.2 seconds
Started Jan 25 01:17:42 AM PST 24
Finished Jan 25 01:17:45 AM PST 24
Peak memory 191372 kb
Host smart-b7a65036-685e-475e-af37-3dc0846e5023
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956985120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3956985120
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1062200966
Short name T212
Test name
Test status
Simulation time 201498439 ps
CPU time 1.08 seconds
Started Jan 25 01:17:48 AM PST 24
Finished Jan 25 01:17:50 AM PST 24
Peak memory 191384 kb
Host smart-0c61b1aa-87ac-4bee-a9b1-827395d5ec68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1062200966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1062200966
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.262756038
Short name T169
Test name
Test status
Simulation time 94708047 ps
CPU time 1.32 seconds
Started Jan 24 10:57:53 PM PST 24
Finished Jan 24 10:57:55 PM PST 24
Peak memory 191384 kb
Host smart-d6dcc141-f05e-4b57-838d-e7ccee33e124
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262756038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.262756038
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3504236774
Short name T183
Test name
Test status
Simulation time 62904182 ps
CPU time 1.29 seconds
Started Jan 24 10:57:51 PM PST 24
Finished Jan 24 10:57:53 PM PST 24
Peak memory 197708 kb
Host smart-743a561d-626a-4e49-95ee-68597316812b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3504236774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3504236774
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1066250269
Short name T221
Test name
Test status
Simulation time 67874989 ps
CPU time 1.12 seconds
Started Jan 24 10:57:50 PM PST 24
Finished Jan 24 10:57:52 PM PST 24
Peak memory 191428 kb
Host smart-faffbba0-dbc7-42df-b320-14370bb147fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066250269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1066250269
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.793397621
Short name T219
Test name
Test status
Simulation time 30161694 ps
CPU time 0.85 seconds
Started Jan 24 10:57:52 PM PST 24
Finished Jan 24 10:57:53 PM PST 24
Peak memory 191156 kb
Host smart-74fdbc46-db50-49a0-b9a1-05e80ad18f31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=793397621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.793397621
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3420297595
Short name T134
Test name
Test status
Simulation time 113541901 ps
CPU time 1.24 seconds
Started Jan 24 10:57:54 PM PST 24
Finished Jan 24 10:57:57 PM PST 24
Peak memory 191344 kb
Host smart-32ecced5-8774-4997-8092-44db1b58774f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420297595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3420297595
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2465834931
Short name T157
Test name
Test status
Simulation time 260573641 ps
CPU time 1.09 seconds
Started Jan 24 10:58:07 PM PST 24
Finished Jan 24 10:58:09 PM PST 24
Peak memory 191364 kb
Host smart-1eb73f07-88ed-4874-8708-b3d635c7c0f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2465834931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2465834931
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3934255825
Short name T182
Test name
Test status
Simulation time 52964846 ps
CPU time 0.97 seconds
Started Jan 25 03:55:37 AM PST 24
Finished Jan 25 03:55:44 AM PST 24
Peak memory 191168 kb
Host smart-17e5cb33-4c7a-41e8-93a9-dcd56abbb9a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934255825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3934255825
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3879137385
Short name T153
Test name
Test status
Simulation time 395735797 ps
CPU time 1.27 seconds
Started Jan 25 04:11:34 AM PST 24
Finished Jan 25 04:11:37 AM PST 24
Peak memory 191380 kb
Host smart-7517d33a-8dbc-419e-a9cc-2825d971b67e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3879137385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3879137385
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.458251663
Short name T137
Test name
Test status
Simulation time 64283668 ps
CPU time 1.12 seconds
Started Jan 24 10:58:21 PM PST 24
Finished Jan 24 10:58:25 PM PST 24
Peak memory 197784 kb
Host smart-96fa234b-bd93-4847-81bc-d16d09567d93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458251663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.458251663
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.116953282
Short name T198
Test name
Test status
Simulation time 72031679 ps
CPU time 1.34 seconds
Started Jan 25 12:23:00 AM PST 24
Finished Jan 25 12:23:03 AM PST 24
Peak memory 197768 kb
Host smart-9b526224-69c5-4cbc-9a60-4ab48225204a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=116953282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.116953282
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.599919615
Short name T147
Test name
Test status
Simulation time 79878409 ps
CPU time 1.31 seconds
Started Jan 24 10:56:28 PM PST 24
Finished Jan 24 10:56:30 PM PST 24
Peak memory 191320 kb
Host smart-bf09bae2-e77d-4ad2-903e-03f038dd56aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599919615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.599919615
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.425995443
Short name T199
Test name
Test status
Simulation time 50933624 ps
CPU time 0.95 seconds
Started Jan 24 10:58:22 PM PST 24
Finished Jan 24 10:58:25 PM PST 24
Peak memory 191124 kb
Host smart-23639ab2-330f-40e9-a03f-21a85ea5b1f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=425995443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.425995443
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4132820998
Short name T202
Test name
Test status
Simulation time 157462314 ps
CPU time 1.23 seconds
Started Jan 24 10:58:22 PM PST 24
Finished Jan 24 10:58:25 PM PST 24
Peak memory 191356 kb
Host smart-4e1676f7-f6b9-43e3-bc3b-c5e9ef60b3a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132820998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4132820998
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2053704504
Short name T162
Test name
Test status
Simulation time 52773884 ps
CPU time 0.77 seconds
Started Jan 24 10:58:41 PM PST 24
Finished Jan 24 10:58:45 PM PST 24
Peak memory 191120 kb
Host smart-0e207173-e377-4434-94e9-291d0059e92e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2053704504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2053704504
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.565948241
Short name T170
Test name
Test status
Simulation time 435533633 ps
CPU time 1.34 seconds
Started Jan 24 10:58:36 PM PST 24
Finished Jan 24 10:58:41 PM PST 24
Peak memory 197744 kb
Host smart-84c5d65c-9f5a-478d-bbcf-744f4d688498
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565948241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.565948241
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1712848976
Short name T195
Test name
Test status
Simulation time 23344800 ps
CPU time 0.85 seconds
Started Jan 24 10:58:42 PM PST 24
Finished Jan 24 10:58:45 PM PST 24
Peak memory 191112 kb
Host smart-29ccb897-8a89-4292-b422-c191db7d6c87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712848976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1712848976
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1614435469
Short name T65
Test name
Test status
Simulation time 294788404 ps
CPU time 1.02 seconds
Started Jan 25 02:23:47 AM PST 24
Finished Jan 25 02:23:49 AM PST 24
Peak memory 191176 kb
Host smart-a7ef2129-ea61-401a-b26e-19c7f84000f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1614435469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1614435469
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.240262755
Short name T165
Test name
Test status
Simulation time 111857961 ps
CPU time 1.23 seconds
Started Jan 25 03:11:46 AM PST 24
Finished Jan 25 03:11:48 AM PST 24
Peak memory 197788 kb
Host smart-60807537-133b-4a93-967e-f51013e4c994
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240262755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.240262755
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1917790949
Short name T167
Test name
Test status
Simulation time 71662549 ps
CPU time 1.43 seconds
Started Jan 24 10:58:43 PM PST 24
Finished Jan 24 10:58:46 PM PST 24
Peak memory 191340 kb
Host smart-a22556dc-bc49-414c-a064-5f9e21666d59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1917790949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1917790949
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1183598417
Short name T210
Test name
Test status
Simulation time 48952530 ps
CPU time 1.1 seconds
Started Jan 25 12:02:41 AM PST 24
Finished Jan 25 12:02:44 AM PST 24
Peak memory 191372 kb
Host smart-6fe07b7c-ad43-4adc-bf54-db63a735f34f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183598417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1183598417
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.979750725
Short name T215
Test name
Test status
Simulation time 202316240 ps
CPU time 1.11 seconds
Started Jan 24 10:58:38 PM PST 24
Finished Jan 24 10:58:41 PM PST 24
Peak memory 191360 kb
Host smart-2aab3165-28a0-4158-881f-67b62045cba9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=979750725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.979750725
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2445219979
Short name T186
Test name
Test status
Simulation time 70944643 ps
CPU time 1.34 seconds
Started Jan 24 10:59:22 PM PST 24
Finished Jan 24 10:59:29 PM PST 24
Peak memory 191316 kb
Host smart-688d7db1-75fe-4f81-8704-b8336508f3ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445219979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2445219979
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2531447328
Short name T62
Test name
Test status
Simulation time 136395815 ps
CPU time 1.24 seconds
Started Jan 24 10:59:21 PM PST 24
Finished Jan 24 10:59:24 PM PST 24
Peak memory 191380 kb
Host smart-27a89c22-e69f-4158-a721-a93ec4a89a78
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2531447328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2531447328
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.549260172
Short name T176
Test name
Test status
Simulation time 213966587 ps
CPU time 1.44 seconds
Started Jan 24 10:59:21 PM PST 24
Finished Jan 24 10:59:24 PM PST 24
Peak memory 197744 kb
Host smart-faf3be03-c096-421f-b1f3-0146c0f59b79
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549260172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.549260172
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4124610333
Short name T163
Test name
Test status
Simulation time 197801632 ps
CPU time 1.52 seconds
Started Jan 24 10:59:34 PM PST 24
Finished Jan 24 10:59:37 PM PST 24
Peak memory 191404 kb
Host smart-49ee691e-2034-4b8e-8b0c-aa7a5ded2360
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4124610333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4124610333
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2600236747
Short name T138
Test name
Test status
Simulation time 49039456 ps
CPU time 1.34 seconds
Started Jan 24 10:59:33 PM PST 24
Finished Jan 24 10:59:36 PM PST 24
Peak memory 191428 kb
Host smart-c0afc3bb-7b8a-451d-9b13-df89d2ed7dd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600236747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2600236747
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3444128044
Short name T66
Test name
Test status
Simulation time 29676231 ps
CPU time 0.77 seconds
Started Jan 24 11:16:09 PM PST 24
Finished Jan 24 11:16:12 PM PST 24
Peak memory 191192 kb
Host smart-17ba32aa-ae13-44ea-8181-1320116d1a0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3444128044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3444128044
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1455203134
Short name T145
Test name
Test status
Simulation time 151121229 ps
CPU time 0.93 seconds
Started Jan 24 10:59:35 PM PST 24
Finished Jan 24 10:59:38 PM PST 24
Peak memory 191128 kb
Host smart-e358983a-0bf6-47c5-91cd-1365f1d86db0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455203134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1455203134
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2425425695
Short name T154
Test name
Test status
Simulation time 46753461 ps
CPU time 1.28 seconds
Started Jan 24 10:59:32 PM PST 24
Finished Jan 24 10:59:36 PM PST 24
Peak memory 191400 kb
Host smart-8c069207-7690-4676-ab1d-4ebfa30f9b39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2425425695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2425425695
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4205645425
Short name T171
Test name
Test status
Simulation time 31169219 ps
CPU time 1.02 seconds
Started Jan 24 10:59:36 PM PST 24
Finished Jan 24 10:59:39 PM PST 24
Peak memory 191332 kb
Host smart-00ecb4ee-09e9-4fc0-82c7-b34f4adad5ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205645425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4205645425
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4123832267
Short name T64
Test name
Test status
Simulation time 38373627 ps
CPU time 1.13 seconds
Started Jan 24 10:56:25 PM PST 24
Finished Jan 24 10:56:27 PM PST 24
Peak memory 197700 kb
Host smart-623f6364-6348-41be-854f-10dc6a401673
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4123832267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.4123832267
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3774323385
Short name T149
Test name
Test status
Simulation time 121076421 ps
CPU time 1.55 seconds
Started Jan 24 10:56:40 PM PST 24
Finished Jan 24 10:56:45 PM PST 24
Peak memory 191360 kb
Host smart-98fe093b-0017-4b55-b008-ef0479b3c724
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774323385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3774323385
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3835875515
Short name T158
Test name
Test status
Simulation time 1194483045 ps
CPU time 1.39 seconds
Started Jan 24 10:59:35 PM PST 24
Finished Jan 24 10:59:39 PM PST 24
Peak memory 191324 kb
Host smart-4432cc24-e6dc-4422-9994-7d850110a57c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3835875515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3835875515
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1560898593
Short name T188
Test name
Test status
Simulation time 159121368 ps
CPU time 0.84 seconds
Started Jan 25 01:21:15 AM PST 24
Finished Jan 25 01:21:16 AM PST 24
Peak memory 195772 kb
Host smart-8eb1e193-7b0e-455e-b05e-2093a20bef70
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560898593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1560898593
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.127325029
Short name T204
Test name
Test status
Simulation time 289293230 ps
CPU time 1.41 seconds
Started Jan 24 10:59:33 PM PST 24
Finished Jan 24 10:59:36 PM PST 24
Peak memory 191360 kb
Host smart-bf00832c-2f16-41fa-9dd7-07c542c1804d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=127325029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.127325029
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.308961358
Short name T193
Test name
Test status
Simulation time 39595168 ps
CPU time 1.24 seconds
Started Jan 24 11:22:14 PM PST 24
Finished Jan 24 11:22:17 PM PST 24
Peak memory 191364 kb
Host smart-6e383ce4-60cb-448c-ae5f-cd9d2a5c2825
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308961358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.308961358
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4204274338
Short name T159
Test name
Test status
Simulation time 47319428 ps
CPU time 1.02 seconds
Started Jan 24 11:15:29 PM PST 24
Finished Jan 24 11:15:32 PM PST 24
Peak memory 191420 kb
Host smart-1e6cda3b-b8fd-4af7-a7ca-e14db67e6c72
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4204274338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4204274338
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2488454167
Short name T184
Test name
Test status
Simulation time 63076628 ps
CPU time 1.28 seconds
Started Jan 24 10:59:45 PM PST 24
Finished Jan 24 10:59:47 PM PST 24
Peak memory 191316 kb
Host smart-a31c57a4-e799-4905-9d58-eab93ea6fc89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488454167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2488454167
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.277604684
Short name T140
Test name
Test status
Simulation time 114194759 ps
CPU time 0.98 seconds
Started Jan 24 11:34:55 PM PST 24
Finished Jan 24 11:34:58 PM PST 24
Peak memory 191188 kb
Host smart-a3811636-bd22-4e30-b308-3debf7518ad7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=277604684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.277604684
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2197264523
Short name T60
Test name
Test status
Simulation time 197884414 ps
CPU time 1.03 seconds
Started Jan 24 10:59:48 PM PST 24
Finished Jan 24 10:59:49 PM PST 24
Peak memory 191356 kb
Host smart-1a7b0d63-2b5a-4b5a-96f7-72423225cae6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197264523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2197264523
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.949799708
Short name T81
Test name
Test status
Simulation time 85521194 ps
CPU time 0.92 seconds
Started Jan 24 11:00:01 PM PST 24
Finished Jan 24 11:00:03 PM PST 24
Peak memory 191360 kb
Host smart-87551f57-ed6d-48ab-86f1-ece7a6fd762d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=949799708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.949799708
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3716552508
Short name T181
Test name
Test status
Simulation time 40759187 ps
CPU time 1.05 seconds
Started Jan 25 01:20:15 AM PST 24
Finished Jan 25 01:20:17 AM PST 24
Peak memory 196852 kb
Host smart-edcf82e6-5b24-4073-bd1c-703b69443282
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716552508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3716552508
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4290880770
Short name T146
Test name
Test status
Simulation time 60355452 ps
CPU time 1.48 seconds
Started Jan 25 12:59:56 AM PST 24
Finished Jan 25 12:59:58 AM PST 24
Peak memory 197804 kb
Host smart-ae167518-0a72-4529-9341-d24486268a92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4290880770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4290880770
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2946912841
Short name T148
Test name
Test status
Simulation time 39261049 ps
CPU time 1.13 seconds
Started Jan 24 11:00:02 PM PST 24
Finished Jan 24 11:00:04 PM PST 24
Peak memory 191372 kb
Host smart-c08b5a66-f9ee-4e73-9cdd-3580459fb020
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946912841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2946912841
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1729121713
Short name T177
Test name
Test status
Simulation time 245448957 ps
CPU time 1.07 seconds
Started Jan 24 11:19:06 PM PST 24
Finished Jan 24 11:19:10 PM PST 24
Peak memory 191188 kb
Host smart-8415fcc6-ed45-43c8-bb10-2b827ff37da4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1729121713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1729121713
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1054691755
Short name T216
Test name
Test status
Simulation time 55284442 ps
CPU time 1.22 seconds
Started Jan 25 01:00:03 AM PST 24
Finished Jan 25 01:00:05 AM PST 24
Peak memory 191392 kb
Host smart-b05a4c37-46cc-4546-9698-437b91893bb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054691755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1054691755
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.121839128
Short name T53
Test name
Test status
Simulation time 230632172 ps
CPU time 0.85 seconds
Started Jan 24 11:01:14 PM PST 24
Finished Jan 24 11:01:16 PM PST 24
Peak memory 195868 kb
Host smart-1c54bfb9-18df-43e5-9a1b-708a0373abce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=121839128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.121839128
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2676745803
Short name T143
Test name
Test status
Simulation time 329438167 ps
CPU time 1.06 seconds
Started Jan 24 11:27:40 PM PST 24
Finished Jan 24 11:27:43 PM PST 24
Peak memory 197484 kb
Host smart-ac4b7096-6585-49dd-a8fa-da08eaeecd28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676745803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2676745803
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.260126292
Short name T161
Test name
Test status
Simulation time 473034891 ps
CPU time 1.34 seconds
Started Jan 24 11:01:32 PM PST 24
Finished Jan 24 11:01:35 PM PST 24
Peak memory 191372 kb
Host smart-c0dd4c23-deee-4083-a22a-31f8444fe621
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=260126292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.260126292
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929054729
Short name T209
Test name
Test status
Simulation time 146841964 ps
CPU time 1.19 seconds
Started Jan 24 11:01:34 PM PST 24
Finished Jan 24 11:01:45 PM PST 24
Peak memory 197740 kb
Host smart-61344135-57dd-47d1-9ec7-49c31a8705d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929054729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.929054729
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.805131697
Short name T207
Test name
Test status
Simulation time 90355921 ps
CPU time 1.35 seconds
Started Jan 24 11:01:32 PM PST 24
Finished Jan 24 11:01:35 PM PST 24
Peak memory 191392 kb
Host smart-9c29272c-56c7-4b85-8478-1306c4a14e8c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=805131697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.805131697
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.740212713
Short name T189
Test name
Test status
Simulation time 33092798 ps
CPU time 1.06 seconds
Started Jan 24 11:01:33 PM PST 24
Finished Jan 24 11:01:40 PM PST 24
Peak memory 197128 kb
Host smart-93ee6291-a961-47fb-8bbc-74f7867e5d4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740212713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.740212713
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3483251922
Short name T155
Test name
Test status
Simulation time 132308272 ps
CPU time 0.84 seconds
Started Jan 24 10:56:45 PM PST 24
Finished Jan 24 10:56:48 PM PST 24
Peak memory 195708 kb
Host smart-0d1aad6b-f450-419c-a62c-1b05ff152228
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483251922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3483251922
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3424223525
Short name T194
Test name
Test status
Simulation time 124517033 ps
CPU time 0.99 seconds
Started Jan 24 11:01:32 PM PST 24
Finished Jan 24 11:01:39 PM PST 24
Peak memory 196856 kb
Host smart-949f2ba9-9d49-4e39-a4ed-9c9845d20864
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3424223525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3424223525
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.711229277
Short name T150
Test name
Test status
Simulation time 47000168 ps
CPU time 1.22 seconds
Started Jan 24 11:01:32 PM PST 24
Finished Jan 24 11:01:39 PM PST 24
Peak memory 191408 kb
Host smart-6a0dd014-697a-45c5-83cd-2ab98e023945
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711229277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.711229277
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.464911582
Short name T178
Test name
Test status
Simulation time 76858545 ps
CPU time 1.19 seconds
Started Jan 24 11:01:32 PM PST 24
Finished Jan 24 11:01:35 PM PST 24
Peak memory 191320 kb
Host smart-dd90d7df-1e52-4831-ad65-255445aafb61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=464911582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.464911582
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2900387121
Short name T218
Test name
Test status
Simulation time 611620769 ps
CPU time 1.42 seconds
Started Jan 24 11:01:32 PM PST 24
Finished Jan 24 11:01:35 PM PST 24
Peak memory 197812 kb
Host smart-9670f1a0-97ec-4392-9e1c-ed93f5499c09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900387121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2900387121
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.404468224
Short name T142
Test name
Test status
Simulation time 48941402 ps
CPU time 0.93 seconds
Started Jan 24 11:01:52 PM PST 24
Finished Jan 24 11:01:57 PM PST 24
Peak memory 191148 kb
Host smart-437a5fb3-9825-4f6b-a96d-656199e6b9c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=404468224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.404468224
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3935222626
Short name T136
Test name
Test status
Simulation time 172528894 ps
CPU time 1.31 seconds
Started Jan 25 05:32:06 AM PST 24
Finished Jan 25 05:32:09 AM PST 24
Peak memory 191472 kb
Host smart-7caeccaf-e520-4090-a688-43bc6339d148
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935222626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3935222626
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.729557456
Short name T63
Test name
Test status
Simulation time 47266559 ps
CPU time 1.23 seconds
Started Jan 24 11:01:53 PM PST 24
Finished Jan 24 11:01:58 PM PST 24
Peak memory 191332 kb
Host smart-8a52b615-67ce-4661-ae2f-447f563fff23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=729557456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.729557456
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2622840987
Short name T187
Test name
Test status
Simulation time 198073789 ps
CPU time 1.28 seconds
Started Jan 25 12:15:34 AM PST 24
Finished Jan 25 12:15:36 AM PST 24
Peak memory 191372 kb
Host smart-27050937-b0a5-4837-98b3-ab349a241284
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622840987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2622840987
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3493235858
Short name T173
Test name
Test status
Simulation time 55097658 ps
CPU time 1.06 seconds
Started Jan 24 11:01:53 PM PST 24
Finished Jan 24 11:01:58 PM PST 24
Peak memory 191228 kb
Host smart-1cd3a215-94eb-4726-a391-48cd42d2f9c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3493235858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3493235858
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3690772807
Short name T185
Test name
Test status
Simulation time 54466334 ps
CPU time 1.59 seconds
Started Jan 24 11:01:53 PM PST 24
Finished Jan 24 11:01:58 PM PST 24
Peak memory 191384 kb
Host smart-245f4288-6b7c-46d2-baeb-694f6b6baeb9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690772807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3690772807
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.702544694
Short name T191
Test name
Test status
Simulation time 87256698 ps
CPU time 1.36 seconds
Started Jan 24 11:01:50 PM PST 24
Finished Jan 24 11:01:57 PM PST 24
Peak memory 191364 kb
Host smart-65dee581-5188-421a-b9fb-2e50217fbda9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=702544694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.702544694
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.96229549
Short name T208
Test name
Test status
Simulation time 224201037 ps
CPU time 1.16 seconds
Started Jan 24 11:01:53 PM PST 24
Finished Jan 24 11:01:58 PM PST 24
Peak memory 191140 kb
Host smart-ebdcaa63-7eb0-4916-8aff-4ba5139aa359
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96229549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.96229549
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1452451746
Short name T211
Test name
Test status
Simulation time 78559244 ps
CPU time 1.53 seconds
Started Jan 24 11:01:52 PM PST 24
Finished Jan 24 11:01:58 PM PST 24
Peak memory 191352 kb
Host smart-84de6ae8-4a62-4d61-913d-8604a3f4fff8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1452451746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1452451746
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1552258074
Short name T180
Test name
Test status
Simulation time 50902569 ps
CPU time 1.43 seconds
Started Jan 24 11:01:53 PM PST 24
Finished Jan 24 11:01:58 PM PST 24
Peak memory 197756 kb
Host smart-7a233545-9804-48a6-8580-b320f494c15a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552258074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1552258074
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3469833133
Short name T213
Test name
Test status
Simulation time 77911149 ps
CPU time 1.4 seconds
Started Jan 25 03:56:39 AM PST 24
Finished Jan 25 03:56:42 AM PST 24
Peak memory 191384 kb
Host smart-1c7c4948-f4c6-42a8-afe3-54119e9a3e80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3469833133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3469833133
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1399514611
Short name T200
Test name
Test status
Simulation time 221856420 ps
CPU time 1.15 seconds
Started Jan 24 11:01:50 PM PST 24
Finished Jan 24 11:01:57 PM PST 24
Peak memory 196952 kb
Host smart-30d100a7-c23e-4709-be13-8c5458bb4317
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399514611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1399514611
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1830426687
Short name T164
Test name
Test status
Simulation time 285213502 ps
CPU time 1.33 seconds
Started Jan 25 02:26:18 AM PST 24
Finished Jan 25 02:26:22 AM PST 24
Peak memory 191400 kb
Host smart-83ffb4ed-6464-4d6b-986c-5d93feb9728c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1830426687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1830426687
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1790593549
Short name T192
Test name
Test status
Simulation time 86420159 ps
CPU time 1.43 seconds
Started Jan 24 11:27:42 PM PST 24
Finished Jan 24 11:27:45 PM PST 24
Peak memory 191412 kb
Host smart-d5bfd4d2-92d7-4d18-8b6e-ecaf5ea739b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790593549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1790593549
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1508566080
Short name T151
Test name
Test status
Simulation time 63648220 ps
CPU time 1.22 seconds
Started Jan 24 11:02:11 PM PST 24
Finished Jan 24 11:02:14 PM PST 24
Peak memory 191364 kb
Host smart-7275a9aa-df35-415c-a43f-07aa38bdd4da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1508566080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1508566080
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.810618377
Short name T168
Test name
Test status
Simulation time 54361848 ps
CPU time 0.99 seconds
Started Jan 24 11:02:33 PM PST 24
Finished Jan 24 11:02:59 PM PST 24
Peak memory 191356 kb
Host smart-884a99b2-1fa3-432c-86b6-e74aebe879d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810618377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.810618377
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1403648717
Short name T203
Test name
Test status
Simulation time 51303354 ps
CPU time 0.72 seconds
Started Jan 24 10:56:45 PM PST 24
Finished Jan 24 10:56:48 PM PST 24
Peak memory 194664 kb
Host smart-5a81b428-b659-450e-8a4a-f9a58aba5ba1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1403648717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1403648717
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359431123
Short name T160
Test name
Test status
Simulation time 45421194 ps
CPU time 1 seconds
Started Jan 24 11:34:00 PM PST 24
Finished Jan 24 11:34:03 PM PST 24
Peak memory 191360 kb
Host smart-74ffd6ab-e2ab-44a4-b7e5-c991728f7003
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359431123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3359431123
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3949554349
Short name T174
Test name
Test status
Simulation time 92047747 ps
CPU time 1.42 seconds
Started Jan 24 10:56:54 PM PST 24
Finished Jan 24 10:56:56 PM PST 24
Peak memory 191340 kb
Host smart-cd9ff6ae-5b36-4000-bc39-7237c6ad9b5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3949554349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3949554349
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3768045313
Short name T190
Test name
Test status
Simulation time 98628614 ps
CPU time 1.28 seconds
Started Jan 24 10:56:49 PM PST 24
Finished Jan 24 10:56:51 PM PST 24
Peak memory 197772 kb
Host smart-84e75707-ccb2-40a2-a5b5-e764c7f01868
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768045313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3768045313
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2595472421
Short name T217
Test name
Test status
Simulation time 101565196 ps
CPU time 0.86 seconds
Started Jan 24 10:56:50 PM PST 24
Finished Jan 24 10:56:52 PM PST 24
Peak memory 191152 kb
Host smart-fdd98950-045f-4967-85b2-a7b4528ba011
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2595472421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2595472421
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2554995016
Short name T152
Test name
Test status
Simulation time 123571094 ps
CPU time 0.84 seconds
Started Jan 24 10:57:02 PM PST 24
Finished Jan 24 10:57:04 PM PST 24
Peak memory 191152 kb
Host smart-226becc8-1bc2-4cde-8e80-6a0ef4a82162
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554995016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2554995016
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3398718830
Short name T220
Test name
Test status
Simulation time 64327133 ps
CPU time 0.98 seconds
Started Jan 24 10:57:08 PM PST 24
Finished Jan 24 10:57:09 PM PST 24
Peak memory 197064 kb
Host smart-ffbf00e7-f030-437e-aade-ca97986dc5a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3398718830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3398718830
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3425850180
Short name T141
Test name
Test status
Simulation time 171570823 ps
CPU time 0.8 seconds
Started Jan 24 10:57:02 PM PST 24
Finished Jan 24 10:57:03 PM PST 24
Peak memory 191156 kb
Host smart-cc670145-3489-40c0-9bb9-417be215eab3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425850180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3425850180
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1678289672
Short name T172
Test name
Test status
Simulation time 169079409 ps
CPU time 1.05 seconds
Started Jan 24 10:57:17 PM PST 24
Finished Jan 24 10:57:19 PM PST 24
Peak memory 197136 kb
Host smart-bb1f523c-22a6-4c7f-aa26-c87ae3a4aa50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1678289672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1678289672
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2567312391
Short name T135
Test name
Test status
Simulation time 44581550 ps
CPU time 1.18 seconds
Started Jan 24 10:57:18 PM PST 24
Finished Jan 24 10:57:20 PM PST 24
Peak memory 197688 kb
Host smart-4ca3f5f0-8fcc-4a99-9106-8c5d444f92f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567312391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2567312391
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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