Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	21132638	1			T16	8		T1	12		T11	1
all_values[1]	21132638	1			T16	8		T1	12		T11	1
all_values[2]	21132638	1			T16	8		T1	12		T11	1
all_values[3]	21132638	1			T16	8		T1	12		T11	1
all_values[4]	21132638	1			T16	8		T1	12		T11	1
all_values[5]	21132638	1			T16	8		T1	12		T11	1
all_values[6]	21132638	1			T16	8		T1	12		T11	1
all_values[7]	21132638	1			T16	8		T1	12		T11	1
all_values[8]	21132638	1			T16	8		T1	12		T11	1
all_values[9]	21132638	1			T16	8		T1	12		T11	1
all_values[10]	21132638	1			T16	8		T1	12		T11	1
all_values[11]	21132638	1			T16	8		T1	12		T11	1
all_values[12]	21132638	1			T16	8		T1	12		T11	1
all_values[13]	21132638	1			T16	8		T1	12		T11	1
all_values[14]	21132638	1			T16	8		T1	12		T11	1
all_values[15]	21132638	1			T16	8		T1	12		T11	1
all_values[16]	21132638	1			T16	8		T1	12		T11	1
all_values[17]	21132638	1			T16	8		T1	12		T11	1
all_values[18]	21132638	1			T16	8		T1	12		T11	1
all_values[19]	21132638	1			T16	8		T1	12		T11	1
all_values[20]	21132638	1			T16	8		T1	12		T11	1
all_values[21]	21132638	1			T16	8		T1	12		T11	1
all_values[22]	21132638	1			T16	8		T1	12		T11	1
all_values[23]	21132638	1			T16	8		T1	12		T11	1
all_values[24]	21132638	1			T16	8		T1	12		T11	1
all_values[25]	21132638	1			T16	8		T1	12		T11	1
all_values[26]	21132638	1			T16	8		T1	12		T11	1
all_values[27]	21132638	1			T16	8		T1	12		T11	1
all_values[28]	21132638	1			T16	8		T1	12		T11	1
all_values[29]	21132638	1			T16	8		T1	12		T11	1
all_values[30]	21132638	1			T16	8		T1	12		T11	1
all_values[31]	21132638	1			T16	8		T1	12		T11	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373327063

1

T16

192

T1

309

T11

32

auto[1]

302917353

1

T16

64

T1

75

T2

320

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126105491

1

T16

187

T1

274

T11

32

auto[1]

550138925

1

T16

69

T1

110

T2

391

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3067747	1			T16	2		T1	11		T11	1
all_values[0]	auto[0]	auto[1]	8590079	1			T16	2		T1	1		T2	6
all_values[0]	auto[1]	auto[0]	875564	1			T16	4		T2	8		T3	1
all_values[0]	auto[1]	auto[1]	8599248	1			T2	2		T4	2		T12	1
all_values[1]	auto[0]	auto[0]	3078133	1			T16	6		T1	8		T11	1
all_values[1]	auto[0]	auto[1]	8591752	1			T16	2		T1	4		T2	5
all_values[1]	auto[1]	auto[0]	859032	1			T2	7		T5	5		T6	3
all_values[1]	auto[1]	auto[1]	8603721	1			T2	7		T4	2		T12	13
all_values[2]	auto[0]	auto[0]	3063282	1			T16	2		T1	7		T11	1
all_values[2]	auto[0]	auto[1]	8582729	1			T16	2		T2	7		T3	1
all_values[2]	auto[1]	auto[0]	872748	1			T16	4		T1	2		T2	7
all_values[2]	auto[1]	auto[1]	8613879	1			T1	3		T2	2		T4	4
all_values[3]	auto[0]	auto[0]	3070503	1			T16	6		T1	7		T11	1
all_values[3]	auto[0]	auto[1]	8620709	1			T16	2		T2	8		T17	2
all_values[3]	auto[1]	auto[0]	863333	1			T2	4		T4	1		T12	13
all_values[3]	auto[1]	auto[1]	8578093	1			T1	5		T2	6		T4	2
all_values[4]	auto[0]	auto[0]	3065247	1			T16	2		T1	7		T11	1
all_values[4]	auto[0]	auto[1]	8595093	1			T16	2		T1	5		T2	6
all_values[4]	auto[1]	auto[0]	873878	1			T16	4		T2	5		T12	1
all_values[4]	auto[1]	auto[1]	8598420	1			T2	6		T3	1		T4	1
all_values[5]	auto[0]	auto[0]	3071660	1			T16	2		T1	7		T11	1
all_values[5]	auto[0]	auto[1]	8602781	1			T16	2		T2	5		T17	3
all_values[5]	auto[1]	auto[0]	879823	1			T16	4		T2	6		T3	1
all_values[5]	auto[1]	auto[1]	8578374	1			T1	5		T2	5		T5	4
all_values[6]	auto[0]	auto[0]	3066515	1			T16	4		T1	12		T11	1
all_values[6]	auto[0]	auto[1]	8603361	1			T2	8		T3	1		T4	3
all_values[6]	auto[1]	auto[0]	881118	1			T16	4		T2	6		T12	13
all_values[6]	auto[1]	auto[1]	8581644	1			T2	5		T4	2		T5	4
all_values[7]	auto[0]	auto[0]	3066533	1			T16	6		T1	7		T11	1
all_values[7]	auto[0]	auto[1]	8595697	1			T16	2		T2	6		T4	1
all_values[7]	auto[1]	auto[0]	879029	1			T1	1		T2	8		T6	1
all_values[7]	auto[1]	auto[1]	8591379	1			T1	4		T2	4		T3	1
all_values[8]	auto[0]	auto[0]	3063615	1			T16	4		T1	9		T11	1
all_values[8]	auto[0]	auto[1]	8547792	1			T1	3		T2	7		T3	1
all_values[8]	auto[1]	auto[0]	867432	1			T16	4		T4	3		T12	1
all_values[8]	auto[1]	auto[1]	8653799	1			T2	6		T4	1		T12	12
all_values[9]	auto[0]	auto[0]	3074400	1			T16	8		T1	7		T11	1
all_values[9]	auto[0]	auto[1]	8542111	1			T2	7		T3	1		T4	5
all_values[9]	auto[1]	auto[0]	877962	1			T1	5		T2	8		T17	1
all_values[9]	auto[1]	auto[1]	8638165	1			T2	5		T7	1		T17	2
all_values[10]	auto[0]	auto[0]	3067106	1			T16	6		T1	7		T11	1
all_values[10]	auto[0]	auto[1]	8600179	1			T16	2		T2	12		T5	5
all_values[10]	auto[1]	auto[0]	875363	1			T2	5		T4	1		T13	1
all_values[10]	auto[1]	auto[1]	8589990	1			T1	5		T2	1		T3	1
all_values[11]	auto[0]	auto[0]	3062811	1			T16	2		T1	7		T11	1
all_values[11]	auto[0]	auto[1]	8592855	1			T16	2		T2	8		T3	1
all_values[11]	auto[1]	auto[0]	883489	1			T16	3		T1	5		T2	2
all_values[11]	auto[1]	auto[1]	8593483	1			T16	1		T2	10		T4	3
all_values[12]	auto[0]	auto[0]	3067688	1			T16	2		T1	7		T11	1
all_values[12]	auto[0]	auto[1]	8615618	1			T16	6		T2	7		T4	5
all_values[12]	auto[1]	auto[0]	871678	1			T2	6		T3	1		T12	13
all_values[12]	auto[1]	auto[1]	8577654	1			T1	5		T2	4		T5	4
all_values[13]	auto[0]	auto[0]	3062192	1			T16	2		T1	7		T11	1
all_values[13]	auto[0]	auto[1]	8603439	1			T16	6		T2	9		T3	1
all_values[13]	auto[1]	auto[0]	868603	1			T2	3		T6	2		T26	1
all_values[13]	auto[1]	auto[1]	8598404	1			T1	5		T2	3		T12	1
all_values[14]	auto[0]	auto[0]	3063108	1			T16	2		T1	7		T11	1
all_values[14]	auto[0]	auto[1]	8627861	1			T16	2		T1	5		T2	8
all_values[14]	auto[1]	auto[0]	885649	1			T16	4		T2	5		T17	3
all_values[14]	auto[1]	auto[1]	8556020	1			T2	6		T4	1		T12	13
all_values[15]	auto[0]	auto[0]	3068629	1			T16	2		T1	7		T11	1
all_values[15]	auto[0]	auto[1]	8610102	1			T16	2		T2	7		T4	1
all_values[15]	auto[1]	auto[0]	869320	1			T16	4		T1	1		T2	5
all_values[15]	auto[1]	auto[1]	8584587	1			T1	4		T2	4		T3	1
all_values[16]	auto[0]	auto[0]	3065497	1			T16	6		T1	7		T11	1
all_values[16]	auto[0]	auto[1]	8572691	1			T16	2		T1	5		T2	5
all_values[16]	auto[1]	auto[0]	872429	1			T2	5		T12	1		T5	1
all_values[16]	auto[1]	auto[1]	8622021	1			T2	5		T4	2		T6	3
all_values[17]	auto[0]	auto[0]	3053034	1			T16	6		T1	7		T11	1
all_values[17]	auto[0]	auto[1]	8643406	1			T16	2		T1	5		T2	16
all_values[17]	auto[1]	auto[0]	871751	1			T2	1		T4	1		T17	4
all_values[17]	auto[1]	auto[1]	8564447	1			T2	3		T4	2		T5	4
all_values[18]	auto[0]	auto[0]	3075688	1			T16	6		T1	7		T11	1
all_values[18]	auto[0]	auto[1]	8596256	1			T16	2		T1	5		T2	9
all_values[18]	auto[1]	auto[0]	870913	1			T2	4		T3	1		T12	14
all_values[18]	auto[1]	auto[1]	8589781	1			T2	6		T4	3		T17	4
all_values[19]	auto[0]	auto[0]	3062329	1			T16	4		T1	7		T11	1
all_values[19]	auto[0]	auto[1]	8612285	1			T16	4		T1	5		T2	3
all_values[19]	auto[1]	auto[0]	870880	1			T2	9		T17	2		T67	1
all_values[19]	auto[1]	auto[1]	8587144	1			T2	6		T4	3		T12	1
all_values[20]	auto[0]	auto[0]	3077122	1			T16	4		T1	7		T11	1
all_values[20]	auto[0]	auto[1]	8592958	1			T1	5		T2	9		T3	1
all_values[20]	auto[1]	auto[0]	879183	1			T16	4		T2	4		T12	13
all_values[20]	auto[1]	auto[1]	8583375	1			T2	4		T5	4		T7	2
all_values[21]	auto[0]	auto[0]	3062770	1			T16	2		T1	12		T11	1
all_values[21]	auto[0]	auto[1]	8600718	1			T16	2		T2	8		T4	2
all_values[21]	auto[1]	auto[0]	887565	1			T16	4		T2	9		T12	1
all_values[21]	auto[1]	auto[1]	8581585	1			T2	1		T3	1		T4	3
all_values[22]	auto[0]	auto[0]	3075007	1			T16	6		T1	7		T11	1
all_values[22]	auto[0]	auto[1]	8593164	1			T16	2		T2	8		T4	4
all_values[22]	auto[1]	auto[0]	876980	1			T1	1		T2	5		T12	14
all_values[22]	auto[1]	auto[1]	8587487	1			T1	4		T2	7		T4	1
all_values[23]	auto[0]	auto[0]	3066823	1			T16	6		T1	8		T11	1
all_values[23]	auto[0]	auto[1]	8631673	1			T16	2		T1	4		T2	10
all_values[23]	auto[1]	auto[0]	879639	1			T2	6		T3	1		T12	13
all_values[23]	auto[1]	auto[1]	8554503	1			T2	3		T4	1		T5	2
all_values[24]	auto[0]	auto[0]	3067334	1			T16	8		T1	8		T11	1
all_values[24]	auto[0]	auto[1]	8602252	1			T1	4		T2	8		T3	1
all_values[24]	auto[1]	auto[0]	871060	1			T2	6		T12	1		T7	3
all_values[24]	auto[1]	auto[1]	8591992	1			T2	5		T4	3		T13	1
all_values[25]	auto[0]	auto[0]	3062092	1			T16	6		T1	7		T11	1
all_values[25]	auto[0]	auto[1]	8633229	1			T16	2		T1	5		T2	7
all_values[25]	auto[1]	auto[0]	865176	1			T2	4		T3	1		T12	13
all_values[25]	auto[1]	auto[1]	8572141	1			T2	5		T12	1		T5	4
all_values[26]	auto[0]	auto[0]	3076079	1			T16	2		T1	12		T11	1
all_values[26]	auto[0]	auto[1]	8587569	1			T16	2		T2	9		T4	5
all_values[26]	auto[1]	auto[0]	861331	1			T16	4		T2	8		T3	1
all_values[26]	auto[1]	auto[1]	8607659	1			T2	4		T5	4		T6	3
all_values[27]	auto[0]	auto[0]	3070914	1			T16	4		T1	7		T11	1
all_values[27]	auto[0]	auto[1]	8600218	1			T2	7		T4	1		T17	2
all_values[27]	auto[1]	auto[0]	867201	1			T1	5		T2	8		T6	1
all_values[27]	auto[1]	auto[1]	8594305	1			T16	4		T2	4		T3	1
all_values[28]	auto[0]	auto[0]	3061924	1			T16	2		T1	7		T11	1
all_values[28]	auto[0]	auto[1]	8593722	1			T16	2		T2	6		T3	1
all_values[28]	auto[1]	auto[0]	873803	1			T16	1		T2	4		T13	1
all_values[28]	auto[1]	auto[1]	8603189	1			T16	3		T1	5		T2	6
all_values[29]	auto[0]	auto[0]	3066553	1			T16	6		T1	7		T11	1
all_values[29]	auto[0]	auto[1]	8573508	1			T16	2		T2	6		T3	1
all_values[29]	auto[1]	auto[0]	864327	1			T1	2		T2	5		T6	1
all_values[29]	auto[1]	auto[1]	8628250	1			T1	3		T2	7		T4	3
all_values[30]	auto[0]	auto[0]	3073940	1			T16	2		T1	7		T11	1
all_values[30]	auto[0]	auto[1]	8643382	1			T16	2		T2	7		T3	1
all_values[30]	auto[1]	auto[0]	871408	1			T16	4		T2	2		T12	1
all_values[30]	auto[1]	auto[1]	8543908	1			T1	5		T2	3		T4	1
all_values[31]	auto[0]	auto[0]	3065708	1			T16	3		T1	11		T11	1
all_values[31]	auto[0]	auto[1]	8565891	1			T16	1		T1	1		T2	11
all_values[31]	auto[1]	auto[0]	875841	1			T16	4		T2	9		T17	1
all_values[31]	auto[1]	auto[1]	8625198	1			T2	1		T5	4		T6	3