Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6274781	1			T16	11		T1	11		T11	1
all_pins[1]	6274781	1			T16	11		T1	11		T11	1
all_pins[2]	6274781	1			T16	11		T1	11		T11	1
all_pins[3]	6274781	1			T16	11		T1	11		T11	1
all_pins[4]	6274781	1			T16	11		T1	11		T11	1
all_pins[5]	6274781	1			T16	11		T1	11		T11	1
all_pins[6]	6274781	1			T16	11		T1	11		T11	1
all_pins[7]	6274781	1			T16	11		T1	11		T11	1
all_pins[8]	6274781	1			T16	11		T1	11		T11	1
all_pins[9]	6274781	1			T16	11		T1	11		T11	1
all_pins[10]	6274781	1			T16	11		T1	11		T11	1
all_pins[11]	6274781	1			T16	11		T1	11		T11	1
all_pins[12]	6274781	1			T16	11		T1	11		T11	1
all_pins[13]	6274781	1			T16	11		T1	11		T11	1
all_pins[14]	6274781	1			T16	11		T1	11		T11	1
all_pins[15]	6274781	1			T16	11		T1	11		T11	1
all_pins[16]	6274781	1			T16	11		T1	11		T11	1
all_pins[17]	6274781	1			T16	11		T1	11		T11	1
all_pins[18]	6274781	1			T16	11		T1	11		T11	1
all_pins[19]	6274781	1			T16	11		T1	11		T11	1
all_pins[20]	6274781	1			T16	11		T1	11		T11	1
all_pins[21]	6274781	1			T16	11		T1	11		T11	1
all_pins[22]	6274781	1			T16	11		T1	11		T11	1
all_pins[23]	6274781	1			T16	11		T1	11		T11	1
all_pins[24]	6274781	1			T16	11		T1	11		T11	1
all_pins[25]	6274781	1			T16	11		T1	11		T11	1
all_pins[26]	6274781	1			T16	11		T1	11		T11	1
all_pins[27]	6274781	1			T16	11		T1	11		T11	1
all_pins[28]	6274781	1			T16	11		T1	11		T11	1
all_pins[29]	6274781	1			T16	11		T1	11		T11	1
all_pins[30]	6274781	1			T16	11		T1	11		T11	1
all_pins[31]	6274781	1			T16	11		T1	11		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	124489556	1			T16	285		T1	240		T11	32
values[0x1]	76303436	1			T16	67		T1	112		T2	360
transitions[0x0=>0x1]	45651417	1			T16	44		T1	65		T2	262
transitions[0x1=>0x0]	45651257	1			T16	44		T1	65		T2	262

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3889823	1			T16	11		T1	10		T11	1
all_pins[0]	values[0x1]	2384958	1			T1	1		T2	4		T4	2
all_pins[0]	transitions[0x0=>0x1]	1473137	1			T1	1		T2	3		T4	2
all_pins[0]	transitions[0x1=>0x0]	1473238	1			T16	5		T1	1		T2	2
all_pins[1]	values[0x0]	3891018	1			T16	11		T1	8		T11	1
all_pins[1]	values[0x1]	2383763	1			T1	3		T2	16		T4	2
all_pins[1]	transitions[0x0=>0x1]	1425083	1			T1	2		T2	12		T12	3
all_pins[1]	transitions[0x1=>0x0]	1426278	1			T12	3		T6	4		T7	1
all_pins[2]	values[0x0]	3882602	1			T16	7		T1	6		T11	1
all_pins[2]	values[0x1]	2392179	1			T16	4		T1	5		T2	11
all_pins[2]	transitions[0x0=>0x1]	1428897	1			T16	4		T1	4		T2	8
all_pins[2]	transitions[0x1=>0x0]	1420481	1			T1	2		T2	13		T12	6
all_pins[3]	values[0x0]	3888077	1			T16	11		T1	4		T11	1
all_pins[3]	values[0x1]	2386704	1			T1	7		T2	11		T4	4
all_pins[3]	transitions[0x0=>0x1]	1425244	1			T1	2		T2	7		T4	2
all_pins[3]	transitions[0x1=>0x0]	1430719	1			T16	4		T2	7		T4	3
all_pins[4]	values[0x0]	3885988	1			T16	11		T1	9		T11	1
all_pins[4]	values[0x1]	2388793	1			T1	2		T2	15		T3	2
all_pins[4]	transitions[0x0=>0x1]	1426816	1			T2	13		T3	2		T12	3
all_pins[4]	transitions[0x1=>0x0]	1424727	1			T1	5		T2	9		T4	2
all_pins[5]	values[0x0]	3899391	1			T16	7		T1	9		T11	1
all_pins[5]	values[0x1]	2375390	1			T16	4		T1	2		T2	8
all_pins[5]	transitions[0x0=>0x1]	1418698	1			T16	4		T1	2		T2	5
all_pins[5]	transitions[0x1=>0x0]	1432101	1			T1	2		T2	12		T3	2
all_pins[6]	values[0x0]	3899024	1			T16	9		T1	10		T11	1
all_pins[6]	values[0x1]	2375757	1			T16	2		T1	1		T2	15
all_pins[6]	transitions[0x0=>0x1]	1424659	1			T2	14		T4	2		T12	4
all_pins[6]	transitions[0x1=>0x0]	1424292	1			T16	2		T1	1		T2	7
all_pins[7]	values[0x0]	3890789	1			T16	11		T1	3		T11	1
all_pins[7]	values[0x1]	2383992	1			T1	8		T2	12		T3	1
all_pins[7]	transitions[0x0=>0x1]	1427980	1			T1	7		T2	7		T3	1
all_pins[7]	transitions[0x1=>0x0]	1419745	1			T16	2		T2	10		T12	5
all_pins[8]	values[0x0]	3882943	1			T16	6		T1	9		T11	1
all_pins[8]	values[0x1]	2391838	1			T16	5		T1	2		T2	11
all_pins[8]	transitions[0x0=>0x1]	1431285	1			T16	5		T1	1		T2	5
all_pins[8]	transitions[0x1=>0x0]	1423439	1			T1	7		T2	6		T3	1
all_pins[9]	values[0x0]	3886005	1			T16	11		T1	8		T11	1
all_pins[9]	values[0x1]	2388776	1			T1	3		T2	12		T12	4
all_pins[9]	transitions[0x0=>0x1]	1424469	1			T1	1		T2	10		T12	2
all_pins[9]	transitions[0x1=>0x0]	1427531	1			T16	5		T2	9		T4	1
all_pins[10]	values[0x0]	3894316	1			T16	11		T1	3		T11	1
all_pins[10]	values[0x1]	2380465	1			T1	8		T2	11		T3	2
all_pins[10]	transitions[0x0=>0x1]	1419537	1			T1	7		T2	7		T3	2
all_pins[10]	transitions[0x1=>0x0]	1427848	1			T1	2		T2	8		T12	2
all_pins[11]	values[0x0]	3890158	1			T16	4		T1	6		T11	1
all_pins[11]	values[0x1]	2384623	1			T16	7		T1	5		T2	21
all_pins[11]	transitions[0x0=>0x1]	1428070	1			T16	7		T2	17		T4	2
all_pins[11]	transitions[0x1=>0x0]	1423912	1			T1	3		T2	7		T3	2
all_pins[12]	values[0x0]	3903234	1			T16	11		T1	5		T11	1
all_pins[12]	values[0x1]	2371547	1			T1	6		T2	13		T12	5
all_pins[12]	transitions[0x0=>0x1]	1415162	1			T1	2		T2	9		T12	1
all_pins[12]	transitions[0x1=>0x0]	1428238	1			T16	7		T1	1		T2	17
all_pins[13]	values[0x0]	3887690	1			T16	11		T1	7		T11	1
all_pins[13]	values[0x1]	2387091	1			T1	4		T2	9		T12	5
all_pins[13]	transitions[0x0=>0x1]	1426625	1			T2	7		T12	3		T5	2
all_pins[13]	transitions[0x1=>0x0]	1411081	1			T1	2		T2	11		T12	3
all_pins[14]	values[0x0]	3889792	1			T16	8		T1	9		T11	1
all_pins[14]	values[0x1]	2384989	1			T16	3		T1	2		T2	15
all_pins[14]	transitions[0x0=>0x1]	1426122	1			T16	3		T1	2		T2	11
all_pins[14]	transitions[0x1=>0x0]	1428224	1			T1	4		T2	5		T12	4
all_pins[15]	values[0x0]	3890112	1			T16	7		T1	4		T11	1
all_pins[15]	values[0x1]	2384669	1			T16	4		T1	7		T2	9
all_pins[15]	transitions[0x0=>0x1]	1423264	1			T16	1		T1	7		T2	4
all_pins[15]	transitions[0x1=>0x0]	1423584	1			T1	2		T2	10		T4	2
all_pins[16]	values[0x0]	3882792	1			T16	11		T1	9		T11	1
all_pins[16]	values[0x1]	2391989	1			T1	2		T2	13		T4	2
all_pins[16]	transitions[0x0=>0x1]	1428520	1			T1	2		T2	11		T12	2
all_pins[16]	transitions[0x1=>0x0]	1421200	1			T16	4		T1	7		T2	7
all_pins[17]	values[0x0]	3887247	1			T16	11		T1	11		T11	1
all_pins[17]	values[0x1]	2387534	1			T2	8		T4	4		T12	6
all_pins[17]	transitions[0x0=>0x1]	1424708	1			T2	6		T4	4		T12	3
all_pins[17]	transitions[0x1=>0x0]	1429163	1			T1	2		T2	11		T4	2
all_pins[18]	values[0x0]	3889434	1			T16	11		T1	9		T11	1
all_pins[18]	values[0x1]	2385347	1			T1	2		T2	14		T4	3
all_pins[18]	transitions[0x0=>0x1]	1422560	1			T1	2		T2	14		T4	1
all_pins[18]	transitions[0x1=>0x0]	1424747	1			T2	8		T4	2		T12	4
all_pins[19]	values[0x0]	3890248	1			T16	11		T1	10		T11	1
all_pins[19]	values[0x1]	2384533	1			T1	1		T2	16		T4	5
all_pins[19]	transitions[0x0=>0x1]	1425147	1			T2	9		T4	3		T12	4
all_pins[19]	transitions[0x1=>0x0]	1425961	1			T1	1		T2	7		T4	1
all_pins[20]	values[0x0]	3892745	1			T16	10		T1	9		T11	1
all_pins[20]	values[0x1]	2382036	1			T16	1		T1	2		T2	11
all_pins[20]	transitions[0x0=>0x1]	1424248	1			T16	1		T1	1		T2	7
all_pins[20]	transitions[0x1=>0x0]	1426745	1			T2	12		T4	5		T12	4
all_pins[21]	values[0x0]	3892244	1			T16	5		T1	10		T11	1
all_pins[21]	values[0x1]	2382537	1			T16	6		T1	1		T2	7
all_pins[21]	transitions[0x0=>0x1]	1425413	1			T16	5		T1	1		T2	7
all_pins[21]	transitions[0x1=>0x0]	1424912	1			T1	2		T2	11		T12	2
all_pins[22]	values[0x0]	3892567	1			T16	11		T1	7		T11	1
all_pins[22]	values[0x1]	2382214	1			T1	4		T2	12		T4	2
all_pins[22]	transitions[0x0=>0x1]	1423708	1			T1	4		T2	11		T12	2
all_pins[22]	transitions[0x1=>0x0]	1424031	1			T16	6		T1	1		T2	6
all_pins[23]	values[0x0]	3888138	1			T16	11		T1	8		T11	1
all_pins[23]	values[0x1]	2386643	1			T1	3		T2	7		T4	1
all_pins[23]	transitions[0x0=>0x1]	1428031	1			T1	3		T2	5		T12	3
all_pins[23]	transitions[0x1=>0x0]	1423602	1			T1	4		T2	10		T4	1
all_pins[24]	values[0x0]	3891442	1			T16	11		T1	10		T11	1
all_pins[24]	values[0x1]	2383339	1			T1	1		T2	10		T4	4
all_pins[24]	transitions[0x0=>0x1]	1427685	1			T2	9		T4	3		T12	2
all_pins[24]	transitions[0x1=>0x0]	1430989	1			T1	2		T2	6		T12	6
all_pins[25]	values[0x0]	3891659	1			T16	11		T1	9		T11	1
all_pins[25]	values[0x1]	2383122	1			T1	2		T2	12		T12	9
all_pins[25]	transitions[0x0=>0x1]	1424411	1			T1	2		T2	5		T12	7
all_pins[25]	transitions[0x1=>0x0]	1424628	1			T1	1		T2	3		T4	4
all_pins[26]	values[0x0]	3888484	1			T16	7		T1	11		T11	1
all_pins[26]	values[0x1]	2386297	1			T16	4		T2	12		T12	10
all_pins[26]	transitions[0x0=>0x1]	1425388	1			T16	4		T2	8		T12	2
all_pins[26]	transitions[0x1=>0x0]	1422213	1			T1	2		T2	8		T12	1
all_pins[27]	values[0x0]	3892926	1			T16	2		T1	5		T11	1
all_pins[27]	values[0x1]	2381855	1			T16	9		T1	6		T2	10
all_pins[27]	transitions[0x0=>0x1]	1425049	1			T16	5		T1	6		T2	5
all_pins[27]	transitions[0x1=>0x0]	1429491	1			T2	7		T12	8		T6	4
all_pins[28]	values[0x0]	3892952	1			T16	3		T1	3		T11	1
all_pins[28]	values[0x1]	2381829	1			T16	8		T1	8		T2	13
all_pins[28]	transitions[0x0=>0x1]	1422523	1			T1	3		T2	12		T4	4
all_pins[28]	transitions[0x1=>0x0]	1422549	1			T16	1		T1	1		T2	9
all_pins[29]	values[0x0]	3885662	1			T16	11		T1	3		T11	1
all_pins[29]	values[0x1]	2389119	1			T1	8		T2	12		T4	5
all_pins[29]	transitions[0x0=>0x1]	1429544	1			T1	1		T2	8		T4	3
all_pins[29]	transitions[0x1=>0x0]	1422254	1			T16	8		T1	1		T2	9
all_pins[30]	values[0x0]	3890492	1			T16	6		T1	6		T11	1
all_pins[30]	values[0x1]	2384289	1			T16	5		T1	5		T2	7
all_pins[30]	transitions[0x0=>0x1]	1423826	1			T16	5		T1	2		T2	3
all_pins[30]	transitions[0x1=>0x0]	1428656	1			T1	5		T2	8		T4	3
all_pins[31]	values[0x0]	3889562	1			T16	6		T1	10		T11	1
all_pins[31]	values[0x1]	2385219	1			T16	5		T1	1		T2	3
all_pins[31]	transitions[0x0=>0x1]	1425608	1			T2	3		T12	5		T5	6
all_pins[31]	transitions[0x1=>0x0]	1424678	1			T1	4		T2	7		T4	2