Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	21132638	1			T16	8		T1	12		T11	1
all_values[1]	21132638	1			T16	8		T1	12		T11	1
all_values[2]	21132638	1			T16	8		T1	12		T11	1
all_values[3]	21132638	1			T16	8		T1	12		T11	1
all_values[4]	21132638	1			T16	8		T1	12		T11	1
all_values[5]	21132638	1			T16	8		T1	12		T11	1
all_values[6]	21132638	1			T16	8		T1	12		T11	1
all_values[7]	21132638	1			T16	8		T1	12		T11	1
all_values[8]	21132638	1			T16	8		T1	12		T11	1
all_values[9]	21132638	1			T16	8		T1	12		T11	1
all_values[10]	21132638	1			T16	8		T1	12		T11	1
all_values[11]	21132638	1			T16	8		T1	12		T11	1
all_values[12]	21132638	1			T16	8		T1	12		T11	1
all_values[13]	21132638	1			T16	8		T1	12		T11	1
all_values[14]	21132638	1			T16	8		T1	12		T11	1
all_values[15]	21132638	1			T16	8		T1	12		T11	1
all_values[16]	21132638	1			T16	8		T1	12		T11	1
all_values[17]	21132638	1			T16	8		T1	12		T11	1
all_values[18]	21132638	1			T16	8		T1	12		T11	1
all_values[19]	21132638	1			T16	8		T1	12		T11	1
all_values[20]	21132638	1			T16	8		T1	12		T11	1
all_values[21]	21132638	1			T16	8		T1	12		T11	1
all_values[22]	21132638	1			T16	8		T1	12		T11	1
all_values[23]	21132638	1			T16	8		T1	12		T11	1
all_values[24]	21132638	1			T16	8		T1	12		T11	1
all_values[25]	21132638	1			T16	8		T1	12		T11	1
all_values[26]	21132638	1			T16	8		T1	12		T11	1
all_values[27]	21132638	1			T16	8		T1	12		T11	1
all_values[28]	21132638	1			T16	8		T1	12		T11	1
all_values[29]	21132638	1			T16	8		T1	12		T11	1
all_values[30]	21132638	1			T16	8		T1	12		T11	1
all_values[31]	21132638	1			T16	8		T1	12		T11	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373327063

1

T16

192

T1

309

T11

32

auto[1]

302917353

1

T16

64

T1

75

T2

320

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126105491

1

T16

187

T1

274

T11

32

auto[1]

550138925

1

T16

69

T1

110

T2

391

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668548826

1

T16

256

T1

384

T11

32

auto[1]

7695590

1

T17

47

T18

151

T14

103

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3067747	1			T16	2		T1	11		T11	1
all_values[0]	auto[0]	auto[0]	auto[1]	8469139	1			T16	2		T1	1		T2	6
all_values[0]	auto[0]	auto[1]	auto[0]	875564	1			T16	4		T2	8		T3	1
all_values[0]	auto[0]	auto[1]	auto[1]	8479496	1			T2	2		T4	2		T12	1
all_values[0]	auto[1]	auto[0]	auto[1]	120940	1			T18	1		T14	2		T95	3
all_values[0]	auto[1]	auto[1]	auto[1]	119752	1			T17	1		T18	5		T95	3
all_values[1]	auto[0]	auto[0]	auto[0]	3078133	1			T16	6		T1	8		T11	1
all_values[1]	auto[0]	auto[0]	auto[1]	8471512	1			T16	2		T1	4		T2	5
all_values[1]	auto[0]	auto[1]	auto[0]	859032	1			T2	7		T5	5		T6	3
all_values[1]	auto[0]	auto[1]	auto[1]	8483716	1			T2	7		T4	2		T12	13
all_values[1]	auto[1]	auto[0]	auto[1]	120240	1			T17	1		T18	3		T14	1
all_values[1]	auto[1]	auto[1]	auto[1]	120005	1			T17	1		T18	2		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	3063282	1			T16	2		T1	7		T11	1
all_values[2]	auto[0]	auto[0]	auto[1]	8462608	1			T16	2		T2	7		T3	1
all_values[2]	auto[0]	auto[1]	auto[0]	872748	1			T16	4		T1	2		T2	7
all_values[2]	auto[0]	auto[1]	auto[1]	8493053	1			T1	3		T2	2		T4	4
all_values[2]	auto[1]	auto[0]	auto[1]	120121	1			T17	1		T18	1		T15	1
all_values[2]	auto[1]	auto[1]	auto[1]	120826	1			T17	1		T14	3		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	3070503	1			T16	6		T1	7		T11	1
all_values[3]	auto[0]	auto[0]	auto[1]	8500179	1			T16	2		T2	8		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	863333	1			T2	4		T4	1		T12	13
all_values[3]	auto[0]	auto[1]	auto[1]	8458331	1			T1	5		T2	6		T4	2
all_values[3]	auto[1]	auto[0]	auto[1]	120530	1			T17	1		T18	3		T14	3
all_values[3]	auto[1]	auto[1]	auto[1]	119762	1			T17	2		T18	1		T14	1
all_values[4]	auto[0]	auto[0]	auto[0]	3065247	1			T16	2		T1	7		T11	1
all_values[4]	auto[0]	auto[0]	auto[1]	8474715	1			T16	2		T1	5		T2	6
all_values[4]	auto[0]	auto[1]	auto[0]	873878	1			T16	4		T2	5		T12	1
all_values[4]	auto[0]	auto[1]	auto[1]	8477561	1			T2	6		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	auto[1]	120378	1			T17	1		T18	2		T14	1
all_values[4]	auto[1]	auto[1]	auto[1]	120859	1			T18	3		T14	3		T15	3
all_values[5]	auto[0]	auto[0]	auto[0]	3071660	1			T16	2		T1	7		T11	1
all_values[5]	auto[0]	auto[0]	auto[1]	8482340	1			T16	2		T2	5		T17	2
all_values[5]	auto[0]	auto[1]	auto[0]	879823	1			T16	4		T2	6		T3	1
all_values[5]	auto[0]	auto[1]	auto[1]	8458233	1			T1	5		T2	5		T5	4
all_values[5]	auto[1]	auto[0]	auto[1]	120441	1			T17	1		T18	3		T14	3
all_values[5]	auto[1]	auto[1]	auto[1]	120141	1			T18	3		T14	1		T15	1
all_values[6]	auto[0]	auto[0]	auto[0]	3066515	1			T16	4		T1	12		T11	1
all_values[6]	auto[0]	auto[0]	auto[1]	8483077	1			T2	8		T3	1		T4	3
all_values[6]	auto[0]	auto[1]	auto[0]	881118	1			T16	4		T2	6		T12	13
all_values[6]	auto[0]	auto[1]	auto[1]	8461692	1			T2	5		T4	2		T5	4
all_values[6]	auto[1]	auto[0]	auto[1]	120284	1			T17	1		T18	4		T14	2
all_values[6]	auto[1]	auto[1]	auto[1]	119952	1			T17	1		T18	2		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	3066533	1			T16	6		T1	7		T11	1
all_values[7]	auto[0]	auto[0]	auto[1]	8475241	1			T16	2		T2	6		T4	1
all_values[7]	auto[0]	auto[1]	auto[0]	879029	1			T1	1		T2	8		T6	1
all_values[7]	auto[0]	auto[1]	auto[1]	8471491	1			T1	4		T2	4		T3	1
all_values[7]	auto[1]	auto[0]	auto[1]	120456	1			T17	1		T18	3		T14	2
all_values[7]	auto[1]	auto[1]	auto[1]	119888	1			T18	2		T14	3		T15	1
all_values[8]	auto[0]	auto[0]	auto[0]	3063615	1			T16	4		T1	9		T11	1
all_values[8]	auto[0]	auto[0]	auto[1]	8426825	1			T1	3		T2	7		T3	1
all_values[8]	auto[0]	auto[1]	auto[0]	867432	1			T16	4		T4	3		T12	1
all_values[8]	auto[0]	auto[1]	auto[1]	8534314	1			T2	6		T4	1		T12	12
all_values[8]	auto[1]	auto[0]	auto[1]	120967	1			T17	1		T18	3		T14	1
all_values[8]	auto[1]	auto[1]	auto[1]	119485	1			T17	1		T18	1		T14	3
all_values[9]	auto[0]	auto[0]	auto[0]	3074400	1			T16	8		T1	7		T11	1
all_values[9]	auto[0]	auto[0]	auto[1]	8421277	1			T2	7		T3	1		T4	5
all_values[9]	auto[0]	auto[1]	auto[0]	877962	1			T1	5		T2	8		T17	1
all_values[9]	auto[0]	auto[1]	auto[1]	8518482	1			T2	5		T7	1		T17	2
all_values[9]	auto[1]	auto[0]	auto[1]	120834	1			T17	1		T18	5		T14	2
all_values[9]	auto[1]	auto[1]	auto[1]	119683	1			T18	1		T14	1		T15	3
all_values[10]	auto[0]	auto[0]	auto[0]	3067106	1			T16	6		T1	7		T11	1
all_values[10]	auto[0]	auto[0]	auto[1]	8479581	1			T16	2		T2	12		T5	5
all_values[10]	auto[0]	auto[1]	auto[0]	875363	1			T2	5		T4	1		T13	1
all_values[10]	auto[0]	auto[1]	auto[1]	8470306	1			T1	5		T2	1		T3	1
all_values[10]	auto[1]	auto[0]	auto[1]	120598	1			T17	2		T18	3		T14	2
all_values[10]	auto[1]	auto[1]	auto[1]	119684	1			T18	3		T14	2		T15	5
all_values[11]	auto[0]	auto[0]	auto[0]	3062811	1			T16	2		T1	7		T11	1
all_values[11]	auto[0]	auto[0]	auto[1]	8472849	1			T16	2		T2	8		T3	1
all_values[11]	auto[0]	auto[1]	auto[0]	883489	1			T16	3		T1	5		T2	2
all_values[11]	auto[0]	auto[1]	auto[1]	8473282	1			T16	1		T2	10		T4	3
all_values[11]	auto[1]	auto[0]	auto[1]	120006	1			T17	1		T18	4		T14	2
all_values[11]	auto[1]	auto[1]	auto[1]	120201	1			T17	2		T14	3		T15	4
all_values[12]	auto[0]	auto[0]	auto[0]	3067688	1			T16	2		T1	7		T11	1
all_values[12]	auto[0]	auto[0]	auto[1]	8494271	1			T16	6		T2	7		T4	5
all_values[12]	auto[0]	auto[1]	auto[0]	871678	1			T2	6		T3	1		T12	13
all_values[12]	auto[0]	auto[1]	auto[1]	8458237	1			T1	5		T2	4		T5	4
all_values[12]	auto[1]	auto[0]	auto[1]	121347	1			T17	1		T18	3		T15	2
all_values[12]	auto[1]	auto[1]	auto[1]	119417	1			T18	1		T14	3		T15	4
all_values[13]	auto[0]	auto[0]	auto[0]	3062192	1			T16	2		T1	7		T11	1
all_values[13]	auto[0]	auto[0]	auto[1]	8483444	1			T16	6		T2	9		T3	1
all_values[13]	auto[0]	auto[1]	auto[0]	868603	1			T2	3		T6	2		T26	1
all_values[13]	auto[0]	auto[1]	auto[1]	8478210	1			T1	5		T2	3		T12	1
all_values[13]	auto[1]	auto[0]	auto[1]	119995	1			T18	2		T14	3		T95	1
all_values[13]	auto[1]	auto[1]	auto[1]	120194	1			T18	3		T15	2		T95	2
all_values[14]	auto[0]	auto[0]	auto[0]	3063108	1			T16	2		T1	7		T11	1
all_values[14]	auto[0]	auto[0]	auto[1]	8506791	1			T16	2		T1	5		T2	8
all_values[14]	auto[0]	auto[1]	auto[0]	885649	1			T16	4		T2	5		T17	3
all_values[14]	auto[0]	auto[1]	auto[1]	8435960	1			T2	6		T4	1		T12	13
all_values[14]	auto[1]	auto[0]	auto[1]	121070	1			T17	1		T18	3		T14	2
all_values[14]	auto[1]	auto[1]	auto[1]	120060	1			T17	2		T18	1		T14	2
all_values[15]	auto[0]	auto[0]	auto[0]	3068629	1			T16	2		T1	7		T11	1
all_values[15]	auto[0]	auto[0]	auto[1]	8489710	1			T16	2		T2	7		T4	1
all_values[15]	auto[0]	auto[1]	auto[0]	869320	1			T16	4		T1	1		T2	5
all_values[15]	auto[0]	auto[1]	auto[1]	8464240	1			T1	4		T2	4		T3	1
all_values[15]	auto[1]	auto[0]	auto[1]	120392	1			T18	2		T14	1		T15	4
all_values[15]	auto[1]	auto[1]	auto[1]	120347	1			T18	2		T14	4		T15	1
all_values[16]	auto[0]	auto[0]	auto[0]	3065497	1			T16	6		T1	7		T11	1
all_values[16]	auto[0]	auto[0]	auto[1]	8452431	1			T16	2		T1	5		T2	5
all_values[16]	auto[0]	auto[1]	auto[0]	872429	1			T2	5		T12	1		T5	1
all_values[16]	auto[0]	auto[1]	auto[1]	8501259	1			T2	5		T4	2		T6	3
all_values[16]	auto[1]	auto[0]	auto[1]	120260	1			T18	2		T14	2		T15	3
all_values[16]	auto[1]	auto[1]	auto[1]	120762	1			T18	1		T15	3		T95	2
all_values[17]	auto[0]	auto[0]	auto[0]	3053034	1			T16	6		T1	7		T11	1
all_values[17]	auto[0]	auto[0]	auto[1]	8523223	1			T16	2		T1	5		T2	16
all_values[17]	auto[0]	auto[1]	auto[0]	871751	1			T2	1		T4	1		T17	4
all_values[17]	auto[0]	auto[1]	auto[1]	8444923	1			T2	3		T4	2		T5	4
all_values[17]	auto[1]	auto[0]	auto[1]	120183	1			T18	3		T14	1		T15	2
all_values[17]	auto[1]	auto[1]	auto[1]	119524	1			T17	1		T18	1		T14	4
all_values[18]	auto[0]	auto[0]	auto[0]	3075688	1			T16	6		T1	7		T11	1
all_values[18]	auto[0]	auto[0]	auto[1]	8475839	1			T16	2		T1	5		T2	9
all_values[18]	auto[0]	auto[1]	auto[0]	870913	1			T2	4		T3	1		T12	14
all_values[18]	auto[0]	auto[1]	auto[1]	8470167	1			T2	6		T4	3		T17	4
all_values[18]	auto[1]	auto[0]	auto[1]	120417	1			T17	2		T18	2		T14	1
all_values[18]	auto[1]	auto[1]	auto[1]	119614	1			T18	1		T14	2		T15	2
all_values[19]	auto[0]	auto[0]	auto[0]	3062329	1			T16	4		T1	7		T11	1
all_values[19]	auto[0]	auto[0]	auto[1]	8491900	1			T16	4		T1	5		T2	3
all_values[19]	auto[0]	auto[1]	auto[0]	870880	1			T2	9		T17	2		T67	1
all_values[19]	auto[0]	auto[1]	auto[1]	8466932	1			T2	6		T4	3		T12	1
all_values[19]	auto[1]	auto[0]	auto[1]	120385	1			T17	2		T18	2		T14	2
all_values[19]	auto[1]	auto[1]	auto[1]	120212	1			T17	1		T18	4		T14	1
all_values[20]	auto[0]	auto[0]	auto[0]	3077122	1			T16	4		T1	7		T11	1
all_values[20]	auto[0]	auto[0]	auto[1]	8472496	1			T1	5		T2	9		T3	1
all_values[20]	auto[0]	auto[1]	auto[0]	879183	1			T16	4		T2	4		T12	13
all_values[20]	auto[0]	auto[1]	auto[1]	8463798	1			T2	4		T5	4		T7	2
all_values[20]	auto[1]	auto[0]	auto[1]	120462	1			T18	2		T14	2		T15	1
all_values[20]	auto[1]	auto[1]	auto[1]	119577	1			T18	2		T15	2		T95	2
all_values[21]	auto[0]	auto[0]	auto[0]	3062770	1			T16	2		T1	12		T11	1
all_values[21]	auto[0]	auto[0]	auto[1]	8480171	1			T16	2		T2	8		T4	2
all_values[21]	auto[0]	auto[1]	auto[0]	887565	1			T16	4		T2	9		T12	1
all_values[21]	auto[0]	auto[1]	auto[1]	8461690	1			T2	1		T3	1		T4	3
all_values[21]	auto[1]	auto[0]	auto[1]	120547	1			T17	2		T18	2		T14	1
all_values[21]	auto[1]	auto[1]	auto[1]	119895	1			T18	1		T14	1		T95	1
all_values[22]	auto[0]	auto[0]	auto[0]	3075007	1			T16	6		T1	7		T11	1
all_values[22]	auto[0]	auto[0]	auto[1]	8472813	1			T16	2		T2	8		T4	4
all_values[22]	auto[0]	auto[1]	auto[0]	876980	1			T1	1		T2	5		T12	14
all_values[22]	auto[0]	auto[1]	auto[1]	8467504	1			T1	4		T2	7		T4	1
all_values[22]	auto[1]	auto[0]	auto[1]	120351	1			T17	1		T18	4		T14	1
all_values[22]	auto[1]	auto[1]	auto[1]	119983	1			T17	1		T18	2		T15	1
all_values[23]	auto[0]	auto[0]	auto[0]	3066823	1			T16	6		T1	8		T11	1
all_values[23]	auto[0]	auto[0]	auto[1]	8511153	1			T16	2		T1	4		T2	10
all_values[23]	auto[0]	auto[1]	auto[0]	879639	1			T2	6		T3	1		T12	13
all_values[23]	auto[0]	auto[1]	auto[1]	8434343	1			T2	3		T4	1		T5	2
all_values[23]	auto[1]	auto[0]	auto[1]	120520	1			T18	3		T14	1		T15	3
all_values[23]	auto[1]	auto[1]	auto[1]	120160	1			T18	2		T14	3		T15	2
all_values[24]	auto[0]	auto[0]	auto[0]	3067334	1			T16	8		T1	8		T11	1
all_values[24]	auto[0]	auto[0]	auto[1]	8481917	1			T1	4		T2	8		T3	1
all_values[24]	auto[0]	auto[1]	auto[0]	871060	1			T2	6		T12	1		T7	3
all_values[24]	auto[0]	auto[1]	auto[1]	8472172	1			T2	5		T4	3		T13	1
all_values[24]	auto[1]	auto[0]	auto[1]	120335	1			T17	2		T18	3		T14	3
all_values[24]	auto[1]	auto[1]	auto[1]	119820	1			T18	2		T14	1		T15	2
all_values[25]	auto[0]	auto[0]	auto[0]	3062092	1			T16	6		T1	7		T11	1
all_values[25]	auto[0]	auto[0]	auto[1]	8512708	1			T16	2		T1	5		T2	7
all_values[25]	auto[0]	auto[1]	auto[0]	865176	1			T2	4		T3	1		T12	13
all_values[25]	auto[0]	auto[1]	auto[1]	8452007	1			T2	5		T12	1		T5	4
all_values[25]	auto[1]	auto[0]	auto[1]	120521	1			T17	1		T18	4		T14	1
all_values[25]	auto[1]	auto[1]	auto[1]	120134	1			T18	1		T14	3		T15	1
all_values[26]	auto[0]	auto[0]	auto[0]	3076079	1			T16	2		T1	12		T11	1
all_values[26]	auto[0]	auto[0]	auto[1]	8467386	1			T16	2		T2	9		T4	5
all_values[26]	auto[0]	auto[1]	auto[0]	861331	1			T16	4		T2	8		T3	1
all_values[26]	auto[0]	auto[1]	auto[1]	8487459	1			T2	4		T5	4		T6	3
all_values[26]	auto[1]	auto[0]	auto[1]	120183	1			T18	2		T14	3		T15	2
all_values[26]	auto[1]	auto[1]	auto[1]	120200	1			T17	1		T18	2		T14	1
all_values[27]	auto[0]	auto[0]	auto[0]	3070914	1			T16	4		T1	7		T11	1
all_values[27]	auto[0]	auto[0]	auto[1]	8479750	1			T2	7		T4	1		T17	1
all_values[27]	auto[0]	auto[1]	auto[0]	867201	1			T1	5		T2	8		T6	1
all_values[27]	auto[0]	auto[1]	auto[1]	8474658	1			T16	4		T2	4		T3	1
all_values[27]	auto[1]	auto[0]	auto[1]	120468	1			T17	1		T18	3		T14	1
all_values[27]	auto[1]	auto[1]	auto[1]	119647	1			T18	2		T15	2		T95	1
all_values[28]	auto[0]	auto[0]	auto[0]	3061924	1			T16	2		T1	7		T11	1
all_values[28]	auto[0]	auto[0]	auto[1]	8473291	1			T16	2		T2	6		T3	1
all_values[28]	auto[0]	auto[1]	auto[0]	873803	1			T16	1		T2	4		T13	1
all_values[28]	auto[0]	auto[1]	auto[1]	8482912	1			T16	3		T1	5		T2	6
all_values[28]	auto[1]	auto[0]	auto[1]	120431	1			T18	1		T14	1		T15	2
all_values[28]	auto[1]	auto[1]	auto[1]	120277	1			T17	2		T18	4		T14	1
all_values[29]	auto[0]	auto[0]	auto[0]	3066553	1			T16	6		T1	7		T11	1
all_values[29]	auto[0]	auto[0]	auto[1]	8452483	1			T16	2		T2	6		T3	1
all_values[29]	auto[0]	auto[1]	auto[0]	864327	1			T1	2		T2	5		T6	1
all_values[29]	auto[0]	auto[1]	auto[1]	8508824	1			T1	3		T2	7		T4	3
all_values[29]	auto[1]	auto[0]	auto[1]	121025	1			T17	1		T18	3		T14	2
all_values[29]	auto[1]	auto[1]	auto[1]	119426	1			T17	2		T18	5		T14	1
all_values[30]	auto[0]	auto[0]	auto[0]	3073940	1			T16	2		T1	7		T11	1
all_values[30]	auto[0]	auto[0]	auto[1]	8522695	1			T16	2		T2	7		T3	1
all_values[30]	auto[0]	auto[1]	auto[0]	871408	1			T16	4		T2	2		T12	1
all_values[30]	auto[0]	auto[1]	auto[1]	8424118	1			T1	5		T2	3		T4	1
all_values[30]	auto[1]	auto[0]	auto[1]	120687	1			T18	2		T14	3		T95	2
all_values[30]	auto[1]	auto[1]	auto[1]	119790	1			T17	1		T18	4		T14	1
all_values[31]	auto[0]	auto[0]	auto[0]	3065708	1			T16	3		T1	11		T11	1
all_values[31]	auto[0]	auto[0]	auto[1]	8444950	1			T16	1		T1	1		T2	11
all_values[31]	auto[0]	auto[1]	auto[0]	875841	1			T16	4		T2	9		T17	1
all_values[31]	auto[0]	auto[1]	auto[1]	8505200	1			T2	1		T5	4		T6	3
all_values[31]	auto[1]	auto[0]	auto[1]	120941	1			T17	1		T18	3		T14	1
all_values[31]	auto[1]	auto[1]	auto[1]	119998	1			T18	1		T15	2		T95	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal