Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[1]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[2]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[3]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[4]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[5]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[6]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[7]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[8]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[9]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[10]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[11]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[12]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[13]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[14]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[15]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[16]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[17]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[18]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[19]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[20]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[21]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[22]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[23]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[24]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[25]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[26]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[27]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[28]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[29]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[30]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[31]	20865764	1			T16	8		T1	12		T11	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417463130

1

T16

256

T1

384

T11

32

auto[1]

250241318

1

T35

3040

T36

5341

T37

5640

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

530883694

1

T16

256

T1

384

T11

32

auto[1]

136820754

1

T35

3197

T36

4251

T37

8488

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

490336324

1

T16

256

T1

384

T11

32

auto[1]

177368124

1

T35

3425

T36

4202

T37

8659

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7905829	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5262999	1			T35	42		T36	100		T37	38
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2147215	1			T35	48		T36	68		T37	116
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2989938	1			T35	60		T36	63		T37	150
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	429400	1			T48	126		T98	58		T99	24
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2130383	1			T35	44		T36	72		T37	153
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7898807	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5274527	1			T35	39		T36	116		T37	34
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2153332	1			T35	56		T36	76		T37	124
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2979631	1			T35	39		T36	63		T37	115
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	426455	1			T48	158		T98	58		T99	25
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2133012	1			T35	40		T36	64		T37	156
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7894944	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5272503	1			T35	39		T36	99		T37	43
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2155061	1			T35	42		T36	81		T37	144
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2982193	1			T35	64		T36	52		T37	110
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	425365	1			T48	144		T98	34		T99	30
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2135698	1			T35	55		T36	72		T37	153
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7919796	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5264767	1			T35	47		T36	98		T37	43
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2150247	1			T35	60		T36	64		T37	128
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2980111	1			T35	50		T36	66		T37	135
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	423447	1			T48	128		T98	51		T99	24
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2127396	1			T35	37		T36	57		T37	136
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7907375	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5269732	1			T35	39		T36	97		T37	42
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2152936	1			T35	26		T36	60		T37	108
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2982785	1			T35	70		T36	63		T37	122
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	426985	1			T48	152		T98	48		T99	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2125951	1			T35	46		T36	96		T37	173
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7902885	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5269369	1			T35	49		T36	89		T37	34
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2151975	1			T35	62		T36	74		T37	126
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2981450	1			T35	52		T36	69		T37	133
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	424944	1			T48	126		T98	40		T99	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2135141	1			T35	59		T36	62		T37	154
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7919649	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5262102	1			T35	50		T36	105		T37	42
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2150647	1			T35	36		T36	86		T37	123
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2981049	1			T35	56		T36	49		T37	134
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	425487	1			T48	150		T98	38		T99	24
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2126830	1			T35	64		T36	58		T37	126
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7901745	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5269279	1			T35	48		T36	99		T37	40
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2147930	1			T35	30		T36	63		T37	100
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2985123	1			T35	62		T36	66		T37	171
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	426597	1			T48	96		T98	42		T99	36
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2135090	1			T35	46		T36	74		T37	128
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7897562	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5267770	1			T35	43		T36	114		T37	36
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2151474	1			T35	61		T36	66		T37	139
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2987778	1			T35	52		T36	50		T37	118
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	428385	1			T48	112		T98	34		T99	22
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2132795	1			T35	36		T36	58		T37	142
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7899014	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5273020	1			T35	35		T36	104		T37	38
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2152478	1			T35	50		T36	92		T37	137
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2983849	1			T35	41		T36	59		T37	116
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	424545	1			T48	122		T98	44		T99	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2132858	1			T35	82		T36	52		T37	128
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7915586	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5257143	1			T35	40		T36	100		T37	43
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2144426	1			T35	40		T36	70		T37	116
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2984878	1			T35	63		T36	77		T37	139
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	426496	1			T48	166		T98	42		T99	22
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2137235	1			T35	64		T36	54		T37	120
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7902545	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5265645	1			T35	47		T36	103		T37	34
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2149666	1			T35	50		T36	55		T37	116
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2985909	1			T35	53		T36	70		T37	130
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	424961	1			T48	96		T98	44		T99	28
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2137038	1			T35	66		T36	74		T37	185
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7911198	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5254768	1			T35	42		T36	98		T37	31
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2155771	1			T35	44		T36	70		T37	106
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2980243	1			T35	54		T36	54		T37	158
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	427802	1			T48	160		T98	33		T99	31
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2135982	1			T35	49		T36	70		T37	142
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7915495	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5254574	1			T35	45		T36	95		T37	47
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2147842	1			T35	53		T36	63		T37	140
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2991199	1			T35	48		T36	66		T37	96
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	426282	1			T48	127		T98	36		T99	31
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2130372	1			T35	56		T36	62		T37	172
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7910841	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5257851	1			T35	34		T36	108		T37	44
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2150581	1			T35	36		T36	65		T37	120
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2984495	1			T35	46		T36	68		T37	146
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	428433	1			T48	146		T98	36		T99	42
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2133563	1			T35	45		T36	56		T37	121
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7910862	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5257118	1			T35	45		T36	98		T37	44
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2156761	1			T35	28		T36	58		T37	150
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2983371	1			T35	74		T36	62		T37	114
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	426580	1			T48	176		T98	43		T99	28
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2131072	1			T35	69		T36	58		T37	102
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7916990	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5263833	1			T35	43		T36	93		T37	39
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2143087	1			T35	47		T36	88		T37	93
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2993258	1			T35	74		T36	52		T37	152
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	425924	1			T48	102		T98	56		T99	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2122672	1			T35	54		T36	68		T37	136
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7923652	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5262080	1			T35	45		T36	97		T37	42
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2143569	1			T35	60		T36	64		T37	182
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2989873	1			T35	59		T36	71		T37	105
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	426629	1			T48	156		T98	40		T99	24
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2119961	1			T35	48		T36	52		T37	126
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7914101	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5264570	1			T35	44		T36	104		T37	32
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2142995	1			T35	30		T36	86		T37	142
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2990708	1			T35	56		T36	65		T37	113
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	426452	1			T48	111		T98	41		T99	39
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2126938	1			T35	63		T36	58		T37	126
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7914301	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5261891	1			T35	47		T36	117		T37	28
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2143129	1			T35	75		T36	36		T37	94
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2995453	1			T35	50		T36	91		T37	134
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	426339	1			T48	126		T98	34		T99	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2124651	1			T35	34		T36	80		T37	158
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7924492	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5252250	1			T35	43		T36	103		T37	43
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2135287	1			T35	50		T36	44		T37	131
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2991202	1			T35	37		T36	58		T37	134
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	429496	1			T48	110		T98	58		T99	36
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2133037	1			T35	54		T36	65		T37	138
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7916844	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5263481	1			T35	50		T36	95		T37	37
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2149594	1			T35	52		T36	80		T37	130
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2985032	1			T35	47		T36	58		T37	130
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	427867	1			T48	113		T98	49		T99	33
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2122946	1			T35	72		T36	61		T37	134
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7922521	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5262417	1			T35	42		T36	92		T37	48
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2140496	1			T35	52		T36	50		T37	98
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2995074	1			T35	72		T36	81		T37	150
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	424052	1			T48	118		T98	31		T99	32
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2121204	1			T35	40		T36	62		T37	150
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7907805	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5267188	1			T35	43		T36	108		T37	40
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2137212	1			T35	42		T36	74		T37	118
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3000688	1			T35	52		T36	69		T37	153
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	426382	1			T48	158		T98	40		T99	28
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2126489	1			T35	67		T36	78		T37	150
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7927304	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5259120	1			T35	38		T36	91		T37	45
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2146711	1			T35	54		T36	53		T37	148
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2983540	1			T35	61		T36	68		T37	138
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	424295	1			T48	117		T98	38		T99	30
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2124794	1			T35	34		T36	84		T37	113
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7905762	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5270233	1			T35	44		T36	106		T37	36
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2141336	1			T35	53		T36	38		T37	97
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2997327	1			T35	68		T36	89		T37	156
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	428401	1			T48	154		T98	36		T99	28
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2122705	1			T35	32		T36	74		T37	160
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7911775	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5268569	1			T35	39		T36	100		T37	48
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2140314	1			T35	37		T36	72		T37	160
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2994755	1			T35	60		T36	75		T37	127
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	427512	1			T48	112		T98	45		T99	16
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2122839	1			T35	56		T36	60		T37	124
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7895471	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5273128	1			T35	46		T36	114		T37	37
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2146136	1			T35	62		T36	76		T37	175
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2993595	1			T35	53		T36	60		T37	134
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	427037	1			T48	98		T98	34		T99	30
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2130397	1			T35	38		T36	40		T37	102
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7917684	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5262080	1			T35	36		T36	92		T37	33
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2148141	1			T35	47		T36	74		T37	173
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2989429	1			T35	42		T36	70		T37	100
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	426650	1			T48	118		T98	44		T99	22
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2121780	1			T35	50		T36	74		T37	116
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7912845	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5270686	1			T35	44		T36	108		T37	43
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2142260	1			T35	56		T36	82		T37	130
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2993503	1			T35	40		T36	50		T37	145
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	425311	1			T48	150		T98	47		T99	12
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2121159	1			T35	44		T36	66		T37	126
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7907271	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5277584	1			T35	49		T36	100		T37	37
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2147452	1			T35	48		T36	46		T37	104
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2981852	1			T35	58		T36	88		T37	186
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	427270	1			T48	156		T98	40		T99	27
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2124335	1			T35	61		T36	79		T37	121
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7909873	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5269956	1			T35	39		T36	100		T37	46
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2145206	1			T35	46		T36	79		T37	147
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2989748	1			T35	48		T36	62		T37	142
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	427817	1			T48	130		T98	30		T99	29
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2123164	1			T35	59		T36	58		T37	102

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal