Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[1]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[2]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[3]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[4]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[5]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[6]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[7]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[8]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[9]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[10]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[11]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[12]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[13]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[14]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[15]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[16]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[17]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[18]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[19]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[20]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[21]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[22]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[23]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[24]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[25]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[26]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[27]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[28]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[29]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[30]	20865764	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[31]	20865764	1			T16	8		T1	12		T11	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417463130

1

T16

256

T1

384

T11

32

auto[1]

250241318

1

T35

3040

T36

5341

T37

5640

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417452095

1

T16

198

T1

304

T11

32

auto[1]

250252353

1

T16

58

T1

80

T2

190

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	12660820	1			T16	3		T1	11		T11	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	381822	1			T35	14		T36	17		T37	32
bins_for_gpio_bits[0]	auto[1]	auto[0]	382162	1			T16	5		T1	1		T2	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	7440960	1			T35	72		T36	155		T37	159
bins_for_gpio_bits[1]	auto[0]	auto[0]	12649697	1			T16	7		T1	7		T11	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	381732	1			T35	11		T36	19		T37	33
bins_for_gpio_bits[1]	auto[1]	auto[0]	382073	1			T16	1		T1	5		T2	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	7452262	1			T35	68		T36	161		T37	157
bins_for_gpio_bits[2]	auto[0]	auto[0]	12650736	1			T16	7		T1	10		T11	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	381124	1			T35	14		T36	16		T37	35
bins_for_gpio_bits[2]	auto[1]	auto[0]	381462	1			T16	1		T1	2		T2	10
bins_for_gpio_bits[2]	auto[1]	auto[1]	7452442	1			T35	80		T36	155		T37	161
bins_for_gpio_bits[3]	auto[0]	auto[0]	12668661	1			T16	8		T1	10		T11	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	381144	1			T35	14		T36	15		T37	34
bins_for_gpio_bits[3]	auto[1]	auto[0]	381493	1			T1	2		T2	6		T12	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	7434466	1			T35	70		T36	140		T37	145
bins_for_gpio_bits[4]	auto[0]	auto[0]	12661693	1			T16	3		T1	8		T11	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	381054	1			T35	11		T36	19		T37	37
bins_for_gpio_bits[4]	auto[1]	auto[0]	381403	1			T16	5		T1	4		T2	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	7441614	1			T35	74		T36	174		T37	178
bins_for_gpio_bits[5]	auto[0]	auto[0]	12654383	1			T16	8		T1	9		T11	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	381582	1			T35	17		T36	16		T37	36
bins_for_gpio_bits[5]	auto[1]	auto[0]	381927	1			T1	3		T2	5		T12	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	7447872	1			T35	91		T36	135		T37	152
bins_for_gpio_bits[6]	auto[0]	auto[0]	12670124	1			T16	8		T1	11		T11	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	380889	1			T35	17		T36	17		T37	31
bins_for_gpio_bits[6]	auto[1]	auto[0]	381221	1			T1	1		T2	5		T4	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	7433530	1			T35	97		T36	146		T37	137
bins_for_gpio_bits[7]	auto[0]	auto[0]	12653136	1			T16	7		T1	8		T11	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	381321	1			T35	11		T36	21		T37	33
bins_for_gpio_bits[7]	auto[1]	auto[0]	381662	1			T16	1		T1	4		T2	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	7449645	1			T35	83		T36	152		T37	135
bins_for_gpio_bits[8]	auto[0]	auto[0]	12655237	1			T16	8		T1	10		T11	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	381246	1			T35	11		T36	12		T37	38
bins_for_gpio_bits[8]	auto[1]	auto[0]	381577	1			T1	2		T2	7		T4	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	7447704	1			T35	68		T36	160		T37	140
bins_for_gpio_bits[9]	auto[0]	auto[0]	12653600	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	381433	1			T35	15		T36	18		T37	35
bins_for_gpio_bits[9]	auto[1]	auto[0]	381741	1			T2	7		T4	2		T5	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	7448990	1			T35	102		T36	138		T37	131
bins_for_gpio_bits[10]	auto[0]	auto[0]	12662652	1			T16	6		T1	6		T11	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	381867	1			T35	16		T36	15		T37	33
bins_for_gpio_bits[10]	auto[1]	auto[0]	382238	1			T16	2		T1	6		T2	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	7439007	1			T35	88		T36	139		T37	130
bins_for_gpio_bits[11]	auto[0]	auto[0]	12655976	1			T16	7		T1	8		T11	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	381816	1			T35	15		T36	18		T37	34
bins_for_gpio_bits[11]	auto[1]	auto[0]	382144	1			T16	1		T1	4		T2	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	7445828	1			T35	98		T36	159		T37	185
bins_for_gpio_bits[12]	auto[0]	auto[0]	12665627	1			T16	5		T1	12		T11	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	381299	1			T35	14		T36	13		T37	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	381585	1			T16	3		T2	7		T5	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	7437253	1			T35	77		T36	155		T37	138
bins_for_gpio_bits[13]	auto[0]	auto[0]	12672721	1			T16	5		T1	11		T11	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	381434	1			T35	13		T36	14		T37	38
bins_for_gpio_bits[13]	auto[1]	auto[0]	381815	1			T16	3		T1	1		T2	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	7429794	1			T35	88		T36	143		T37	181
bins_for_gpio_bits[14]	auto[0]	auto[0]	12664252	1			T16	6		T1	12		T11	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	381265	1			T35	10		T36	14		T37	31
bins_for_gpio_bits[14]	auto[1]	auto[0]	381665	1			T16	2		T2	6		T4	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	7438582	1			T35	69		T36	150		T37	134
bins_for_gpio_bits[15]	auto[0]	auto[0]	12669199	1			T16	7		T1	9		T11	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	381443	1			T35	13		T36	17		T37	28
bins_for_gpio_bits[15]	auto[1]	auto[0]	381795	1			T16	1		T1	3		T2	9
bins_for_gpio_bits[15]	auto[1]	auto[1]	7433327	1			T35	101		T36	139		T37	118
bins_for_gpio_bits[16]	auto[0]	auto[0]	12671048	1			T16	4		T1	12		T11	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	381918	1			T35	16		T36	16		T37	36
bins_for_gpio_bits[16]	auto[1]	auto[0]	382287	1			T16	4		T2	5		T3	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	7430511	1			T35	81		T36	145		T37	139
bins_for_gpio_bits[17]	auto[0]	auto[0]	12675212	1			T16	5		T1	12		T11	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	381561	1			T35	15		T36	12		T37	35
bins_for_gpio_bits[17]	auto[1]	auto[0]	381882	1			T16	3		T2	8		T5	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	7427109	1			T35	78		T36	137		T37	133
bins_for_gpio_bits[18]	auto[0]	auto[0]	12666271	1			T16	3		T1	7		T11	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	381188	1			T35	12		T36	15		T37	32
bins_for_gpio_bits[18]	auto[1]	auto[0]	381533	1			T16	5		T1	5		T2	3
bins_for_gpio_bits[18]	auto[1]	auto[1]	7436772	1			T35	95		T36	147		T37	126
bins_for_gpio_bits[19]	auto[0]	auto[0]	12670997	1			T16	5		T1	11		T11	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	381544	1			T35	13		T36	17		T37	32
bins_for_gpio_bits[19]	auto[1]	auto[0]	381886	1			T16	3		T1	1		T2	10
bins_for_gpio_bits[19]	auto[1]	auto[1]	7431337	1			T35	68		T36	180		T37	154
bins_for_gpio_bits[20]	auto[0]	auto[0]	12669057	1			T16	4		T1	12		T11	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	381568	1			T35	14		T36	11		T37	34
bins_for_gpio_bits[20]	auto[1]	auto[0]	381924	1			T16	4		T2	5		T4	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	7433215	1			T35	83		T36	157		T37	147
bins_for_gpio_bits[21]	auto[0]	auto[0]	12669659	1			T16	5		T1	12		T11	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	381471	1			T35	13		T36	16		T37	39
bins_for_gpio_bits[21]	auto[1]	auto[0]	381811	1			T16	3		T2	3		T12	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	7432823	1			T35	109		T36	140		T37	132
bins_for_gpio_bits[22]	auto[0]	auto[0]	12676785	1			T16	8		T1	7		T11	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	380958	1			T35	11		T36	14		T37	35
bins_for_gpio_bits[22]	auto[1]	auto[0]	381306	1			T1	5		T2	7		T3	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	7426715	1			T35	71		T36	140		T37	163
bins_for_gpio_bits[23]	auto[0]	auto[0]	12663055	1			T16	6		T1	8		T11	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	382308	1			T35	13		T36	19		T37	40
bins_for_gpio_bits[23]	auto[1]	auto[0]	382650	1			T16	2		T1	4		T2	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	7437751	1			T35	97		T36	167		T37	150
bins_for_gpio_bits[24]	auto[0]	auto[0]	12675928	1			T16	8		T1	7		T11	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	381284	1			T35	10		T36	16		T37	32
bins_for_gpio_bits[24]	auto[1]	auto[0]	381627	1			T1	5		T2	6		T4	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	7426925	1			T35	62		T36	159		T37	126
bins_for_gpio_bits[25]	auto[0]	auto[0]	12662556	1			T16	6		T1	7		T11	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	381492	1			T35	10		T36	15		T37	33
bins_for_gpio_bits[25]	auto[1]	auto[0]	381869	1			T16	2		T1	5		T2	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	7439847	1			T35	66		T36	165		T37	163
bins_for_gpio_bits[26]	auto[0]	auto[0]	12664945	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	381537	1			T35	15		T36	20		T37	35
bins_for_gpio_bits[26]	auto[1]	auto[0]	381899	1			T2	7		T4	1		T12	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	7437383	1			T35	80		T36	140		T37	137
bins_for_gpio_bits[27]	auto[0]	auto[0]	12652695	1			T16	4		T1	12		T11	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	382138	1			T35	13		T36	15		T37	29
bins_for_gpio_bits[27]	auto[1]	auto[0]	382507	1			T16	4		T2	5		T4	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	7448424	1			T35	71		T36	139		T37	110
bins_for_gpio_bits[28]	auto[0]	auto[0]	12673214	1			T16	6		T1	3		T11	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	381722	1			T35	12		T36	22		T37	30
bins_for_gpio_bits[28]	auto[1]	auto[0]	382040	1			T16	2		T1	9		T2	5
bins_for_gpio_bits[28]	auto[1]	auto[1]	7428788	1			T35	74		T36	144		T37	119
bins_for_gpio_bits[29]	auto[0]	auto[0]	12666773	1			T16	8		T1	5		T11	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	381475	1			T35	13		T36	17		T37	32
bins_for_gpio_bits[29]	auto[1]	auto[0]	381835	1			T1	7		T2	5		T4	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	7435681	1			T35	75		T36	157		T37	137
bins_for_gpio_bits[30]	auto[0]	auto[0]	12655464	1			T16	8		T1	12		T11	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	380780	1			T35	11		T36	16		T37	32
bins_for_gpio_bits[30]	auto[1]	auto[0]	381111	1			T2	2		T12	2		T5	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	7448409	1			T35	99		T36	163		T37	126
bins_for_gpio_bits[31]	auto[0]	auto[0]	12663078	1			T16	7		T1	11		T11	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	381429	1			T35	13		T36	20		T37	31
bins_for_gpio_bits[31]	auto[1]	auto[0]	381749	1			T16	1		T1	1		T2	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	7439508	1			T35	85		T36	138		T37	117