Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11657826 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9474812 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905589 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227049 |
1 |
|
|
T68 |
1 |
|
T10 |
1 |
|
T71 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11656047 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9476591 |
1 |
|
|
T2 |
7 |
|
T4 |
2 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4114680 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T67 |
2 |
| auto[1] |
auto[0] |
auto[1] |
610276 |
1 |
|
|
T10 |
1 |
|
T71 |
1 |
|
T72 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4134862 |
1 |
|
|
T2 |
4 |
|
T12 |
1 |
|
T67 |
1 |
| auto[1] |
auto[1] |
auto[1] |
616773 |
1 |
|
|
T68 |
1 |
|
T92 |
8 |
|
T93 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669885 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462753 |
1 |
|
|
T2 |
14 |
|
T4 |
2 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19900500 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1232138 |
1 |
|
|
T1 |
1 |
|
T88 |
1 |
|
T92 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11624700 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9507938 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4140031 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
615169 |
1 |
|
|
T1 |
1 |
|
T92 |
7 |
|
T93 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4135769 |
1 |
|
|
T2 |
7 |
|
T4 |
2 |
|
T68 |
1 |
| auto[1] |
auto[1] |
auto[1] |
616969 |
1 |
|
|
T88 |
1 |
|
T92 |
5 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11667285 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9465353 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19910451 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1222187 |
1 |
|
|
T71 |
1 |
|
T87 |
1 |
|
T100 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11679456 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9453182 |
1 |
|
|
T2 |
7 |
|
T4 |
1 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4118903 |
1 |
|
|
T2 |
6 |
|
T12 |
1 |
|
T7 |
2 |
| auto[1] |
auto[0] |
auto[1] |
610514 |
1 |
|
|
T71 |
1 |
|
T100 |
1 |
|
T74 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4112092 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
611673 |
1 |
|
|
T87 |
1 |
|
T92 |
6 |
|
T93 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655666 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9476972 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19910458 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1222180 |
1 |
|
|
T16 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11692004 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9440634 |
1 |
|
|
T16 |
4 |
|
T2 |
8 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4121712 |
1 |
|
|
T2 |
7 |
|
T4 |
2 |
|
T5 |
3 |
| auto[1] |
auto[0] |
auto[1] |
614818 |
1 |
|
|
T5 |
1 |
|
T68 |
1 |
|
T73 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4096742 |
1 |
|
|
T16 |
3 |
|
T2 |
1 |
|
T4 |
2 |
| auto[1] |
auto[1] |
auto[1] |
607362 |
1 |
|
|
T16 |
1 |
|
T4 |
1 |
|
T67 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11683306 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9449332 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19903149 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1229489 |
1 |
|
|
T16 |
1 |
|
T5 |
1 |
|
T71 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11644324 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9488314 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4139112 |
1 |
|
|
T16 |
3 |
|
T2 |
2 |
|
T4 |
5 |
| auto[1] |
auto[0] |
auto[1] |
616481 |
1 |
|
|
T16 |
1 |
|
T87 |
1 |
|
T88 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4119713 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T5 |
3 |
| auto[1] |
auto[1] |
auto[1] |
613008 |
1 |
|
|
T5 |
1 |
|
T71 |
1 |
|
T92 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11665631 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9467007 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905875 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1226763 |
1 |
|
|
T16 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11666061 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9466577 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4133395 |
1 |
|
|
T16 |
3 |
|
T2 |
7 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
618111 |
1 |
|
|
T16 |
1 |
|
T4 |
1 |
|
T87 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4106419 |
1 |
|
|
T2 |
3 |
|
T12 |
1 |
|
T6 |
2 |
| auto[1] |
auto[1] |
auto[1] |
608652 |
1 |
|
|
T6 |
1 |
|
T101 |
1 |
|
T73 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11690969 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9441669 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19904974 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227664 |
1 |
|
|
T67 |
1 |
|
T92 |
11 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11653901 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9478737 |
1 |
|
|
T2 |
8 |
|
T5 |
1 |
|
T13 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4152795 |
1 |
|
|
T2 |
5 |
|
T67 |
1 |
|
T26 |
1 |
| auto[1] |
auto[0] |
auto[1] |
619477 |
1 |
|
|
T67 |
1 |
|
T92 |
7 |
|
T93 |
6 |
| auto[1] |
auto[1] |
auto[0] |
4098278 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
608187 |
1 |
|
|
T92 |
4 |
|
T27 |
1 |
|
T93 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11678731 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9453907 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19909042 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1223596 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11679834 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9452804 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4131253 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
613414 |
1 |
|
|
T6 |
1 |
|
T71 |
1 |
|
T88 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4097955 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
610182 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T68 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11638188 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9494450 |
1 |
|
|
T2 |
10 |
|
T4 |
2 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19904431 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1228207 |
1 |
|
|
T4 |
1 |
|
T101 |
1 |
|
T86 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11639954 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9492684 |
1 |
|
|
T1 |
5 |
|
T2 |
13 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4139543 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
615981 |
1 |
|
|
T4 |
1 |
|
T86 |
1 |
|
T92 |
5 |
| auto[1] |
auto[1] |
auto[0] |
4124934 |
1 |
|
|
T2 |
4 |
|
T5 |
1 |
|
T6 |
3 |
| auto[1] |
auto[1] |
auto[1] |
612226 |
1 |
|
|
T101 |
1 |
|
T87 |
1 |
|
T88 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11696440 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9436198 |
1 |
|
|
T2 |
4 |
|
T4 |
3 |
|
T5 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19909325 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1223313 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T69 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11693203 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9439435 |
1 |
|
|
T2 |
11 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4111801 |
1 |
|
|
T2 |
8 |
|
T12 |
1 |
|
T6 |
3 |
| auto[1] |
auto[0] |
auto[1] |
613681 |
1 |
|
|
T10 |
1 |
|
T69 |
1 |
|
T86 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4104321 |
1 |
|
|
T2 |
3 |
|
T4 |
3 |
|
T5 |
3 |
| auto[1] |
auto[1] |
auto[1] |
609632 |
1 |
|
|
T5 |
1 |
|
T73 |
1 |
|
T100 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11671944 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9460694 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19906892 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1225746 |
1 |
|
|
T4 |
2 |
|
T86 |
2 |
|
T88 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11670429 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462209 |
1 |
|
|
T2 |
9 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4104645 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T10 |
2 |
| auto[1] |
auto[0] |
auto[1] |
609802 |
1 |
|
|
T4 |
1 |
|
T86 |
2 |
|
T88 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4131818 |
1 |
|
|
T2 |
5 |
|
T12 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
615944 |
1 |
|
|
T4 |
1 |
|
T92 |
4 |
|
T93 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674614 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9458024 |
1 |
|
|
T2 |
15 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19913619 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1219019 |
1 |
|
|
T16 |
2 |
|
T5 |
2 |
|
T101 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11718268 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9414370 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4104591 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
611758 |
1 |
|
|
T16 |
2 |
|
T5 |
2 |
|
T72 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4090760 |
1 |
|
|
T2 |
7 |
|
T12 |
1 |
|
T7 |
2 |
| auto[1] |
auto[1] |
auto[1] |
607261 |
1 |
|
|
T101 |
1 |
|
T73 |
2 |
|
T92 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11646011 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9486627 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19913062 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1219576 |
1 |
|
|
T67 |
1 |
|
T68 |
1 |
|
T92 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11712980 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9419658 |
1 |
|
|
T2 |
7 |
|
T7 |
2 |
|
T67 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4102220 |
1 |
|
|
T2 |
6 |
|
T7 |
1 |
|
T67 |
2 |
| auto[1] |
auto[0] |
auto[1] |
611025 |
1 |
|
|
T68 |
1 |
|
T92 |
5 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4097862 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T19 |
4 |
| auto[1] |
auto[1] |
auto[1] |
608551 |
1 |
|
|
T67 |
1 |
|
T92 |
11 |
|
T93 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11670080 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462558 |
1 |
|
|
T16 |
4 |
|
T2 |
8 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19904895 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227743 |
1 |
|
|
T87 |
1 |
|
T92 |
11 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11656847 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9475791 |
1 |
|
|
T1 |
5 |
|
T2 |
13 |
|
T4 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4135195 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
615898 |
1 |
|
|
T92 |
4 |
|
T27 |
1 |
|
T93 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4112853 |
1 |
|
|
T2 |
6 |
|
T5 |
1 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[1] |
611845 |
1 |
|
|
T87 |
1 |
|
T92 |
7 |
|
T93 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663488 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9469150 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19910946 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1221692 |
1 |
|
|
T5 |
1 |
|
T72 |
1 |
|
T92 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11698800 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9433838 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4104629 |
1 |
|
|
T1 |
5 |
|
T2 |
4 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
610057 |
1 |
|
|
T5 |
1 |
|
T72 |
1 |
|
T92 |
7 |
| auto[1] |
auto[1] |
auto[0] |
4107517 |
1 |
|
|
T16 |
4 |
|
T2 |
3 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
611635 |
1 |
|
|
T92 |
7 |
|
T93 |
3 |
|
T91 |
2871 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11668171 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9464467 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19914573 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1218065 |
1 |
|
|
T1 |
1 |
|
T67 |
1 |
|
T10 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11708247 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9424391 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T4 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4114849 |
1 |
|
|
T2 |
5 |
|
T4 |
2 |
|
T5 |
1 |
| auto[1] |
auto[0] |
auto[1] |
611843 |
1 |
|
|
T10 |
1 |
|
T72 |
1 |
|
T88 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4091477 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
606222 |
1 |
|
|
T1 |
1 |
|
T67 |
1 |
|
T71 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11698496 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9434142 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19892829 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1239809 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T88 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11597638 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9535000 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4158267 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T4 |
4 |
| auto[1] |
auto[0] |
auto[1] |
621991 |
1 |
|
|
T1 |
1 |
|
T88 |
2 |
|
T74 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4136924 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
4 |
| auto[1] |
auto[1] |
auto[1] |
617818 |
1 |
|
|
T5 |
1 |
|
T92 |
11 |
|
T93 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669586 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9463052 |
1 |
|
|
T2 |
11 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19915242 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1217396 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T68 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11717057 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9415581 |
1 |
|
|
T2 |
10 |
|
T4 |
2 |
|
T5 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4100908 |
1 |
|
|
T2 |
6 |
|
T5 |
4 |
|
T6 |
2 |
| auto[1] |
auto[0] |
auto[1] |
608943 |
1 |
|
|
T6 |
1 |
|
T68 |
1 |
|
T71 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4097277 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[1] |
608453 |
1 |
|
|
T4 |
1 |
|
T88 |
3 |
|
T92 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11695321 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9437317 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T12 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19906924 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1225714 |
1 |
|
|
T4 |
1 |
|
T72 |
1 |
|
T73 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11666649 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9465989 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4139212 |
1 |
|
|
T16 |
4 |
|
T2 |
5 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
615720 |
1 |
|
|
T4 |
1 |
|
T88 |
2 |
|
T92 |
9 |
| auto[1] |
auto[1] |
auto[0] |
4101063 |
1 |
|
|
T2 |
5 |
|
T7 |
1 |
|
T10 |
3 |
| auto[1] |
auto[1] |
auto[1] |
609994 |
1 |
|
|
T72 |
1 |
|
T73 |
1 |
|
T92 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663648 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9468990 |
1 |
|
|
T16 |
4 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905455 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227183 |
1 |
|
|
T4 |
1 |
|
T73 |
1 |
|
T87 |
2 |