Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11654114 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9478524 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4121977 |
1 |
|
|
T1 |
5 |
|
T2 |
4 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
612436 |
1 |
|
|
T4 |
1 |
|
T73 |
1 |
|
T87 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4129364 |
1 |
|
|
T16 |
4 |
|
T2 |
7 |
|
T6 |
3 |
| auto[1] |
auto[1] |
auto[1] |
614747 |
1 |
|
|
T87 |
1 |
|
T88 |
2 |
|
T92 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |