Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669885 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462753 |
1 |
|
|
T2 |
14 |
|
T4 |
2 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15418534 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5714104 |
1 |
|
|
T2 |
8 |
|
T4 |
4 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11687068 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9445570 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1864952 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T68 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2851807 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T67 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1866514 |
1 |
|
|
T2 |
1 |
|
T73 |
2 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2862297 |
1 |
|
|
T2 |
5 |
|
T4 |
2 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11667285 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9465353 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15411456 |
1 |
|
|
T16 |
8 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
5721182 |
1 |
|
|
T1 |
2 |
|
T2 |
11 |
|
T4 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11677200 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9455438 |
1 |
|
|
T1 |
5 |
|
T2 |
13 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1876069 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T67 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2882035 |
1 |
|
|
T2 |
10 |
|
T5 |
1 |
|
T9 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1858187 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T67 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2839147 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T4 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655666 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9476972 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15399934 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5732704 |
1 |
|
|
T16 |
2 |
|
T2 |
14 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674072 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9458566 |
1 |
|
|
T16 |
2 |
|
T2 |
15 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1868720 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T9 |
5 |
| auto[1] |
auto[0] |
auto[1] |
2866967 |
1 |
|
|
T16 |
2 |
|
T2 |
6 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1857142 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T26 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2865737 |
1 |
|
|
T2 |
8 |
|
T4 |
1 |
|
T6 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11683306 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9449332 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15401718 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
5730920 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11677829 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9454809 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1867845 |
1 |
|
|
T2 |
3 |
|
T19 |
2 |
|
T71 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2871835 |
1 |
|
|
T16 |
2 |
|
T2 |
4 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1856044 |
1 |
|
|
T7 |
1 |
|
T33 |
2 |
|
T92 |
47 |
| auto[1] |
auto[1] |
auto[1] |
2859085 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T5 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11665631 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9467007 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15394994 |
1 |
|
|
T16 |
7 |
|
T1 |
8 |
|
T11 |
1 |
| auto[1] |
5737644 |
1 |
|
|
T16 |
1 |
|
T1 |
4 |
|
T2 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661196 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9471442 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1871848 |
1 |
|
|
T16 |
1 |
|
T2 |
1 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2876199 |
1 |
|
|
T16 |
1 |
|
T2 |
5 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1861950 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T9 |
8 |
| auto[1] |
auto[1] |
auto[1] |
2861445 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11690969 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9441669 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15417102 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
5715536 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11691271 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9441367 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1863262 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T68 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2862167 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1862569 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2853369 |
1 |
|
|
T2 |
6 |
|
T6 |
3 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11678731 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9453907 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15407869 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5724769 |
1 |
|
|
T16 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11687391 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9445247 |
1 |
|
|
T16 |
2 |
|
T2 |
13 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1860949 |
1 |
|
|
T16 |
1 |
|
T2 |
2 |
|
T9 |
5 |
| auto[1] |
auto[0] |
auto[1] |
2871173 |
1 |
|
|
T16 |
1 |
|
T2 |
6 |
|
T7 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1859529 |
1 |
|
|
T2 |
2 |
|
T4 |
2 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2853596 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T4 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11638188 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9494450 |
1 |
|
|
T2 |
10 |
|
T4 |
2 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15408418 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
5724220 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11682684 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9449954 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1864715 |
1 |
|
|
T4 |
1 |
|
T67 |
1 |
|
T86 |
5 |
| auto[1] |
auto[0] |
auto[1] |
2846520 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1861019 |
1 |
|
|
T2 |
1 |
|
T68 |
1 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2877700 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T6 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11696440 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9436198 |
1 |
|
|
T2 |
4 |
|
T4 |
3 |
|
T5 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15377990 |
1 |
|
|
T16 |
7 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
5754648 |
1 |
|
|
T16 |
1 |
|
T1 |
5 |
|
T2 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11644046 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9488592 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1881361 |
1 |
|
|
T16 |
1 |
|
T2 |
2 |
|
T5 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2900205 |
1 |
|
|
T16 |
1 |
|
T1 |
5 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[0] |
1852583 |
1 |
|
|
T7 |
2 |
|
T19 |
1 |
|
T73 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2854443 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T5 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11671944 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9460694 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15397430 |
1 |
|
|
T16 |
8 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
5735208 |
1 |
|
|
T1 |
2 |
|
T2 |
15 |
|
T6 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11677097 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9455541 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1864227 |
1 |
|
|
T16 |
2 |
|
T1 |
3 |
|
T6 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2878000 |
1 |
|
|
T1 |
2 |
|
T2 |
9 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1856106 |
1 |
|
|
T33 |
3 |
|
T30 |
1 |
|
T92 |
38 |
| auto[1] |
auto[1] |
auto[1] |
2857208 |
1 |
|
|
T2 |
6 |
|
T26 |
1 |
|
T19 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674614 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9458024 |
1 |
|
|
T2 |
15 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15385470 |
1 |
|
|
T16 |
8 |
|
T1 |
8 |
|
T11 |
1 |
| auto[1] |
5747168 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T4 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11649699 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9482939 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1865806 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T26 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2872395 |
1 |
|
|
T1 |
4 |
|
T4 |
2 |
|
T9 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1869965 |
1 |
|
|
T2 |
3 |
|
T67 |
1 |
|
T101 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2874773 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11646011 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9486627 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15398981 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5733657 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669941 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462697 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1854420 |
1 |
|
|
T2 |
3 |
|
T13 |
1 |
|
T20 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2848303 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1874620 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2885354 |
1 |
|
|
T2 |
2 |
|
T4 |
2 |
|
T67 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11670080 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462558 |
1 |
|
|
T16 |
4 |
|
T2 |
8 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15400350 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
5732288 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11666453 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9466185 |
1 |
|
|
T1 |
5 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1868566 |
1 |
|
|
T2 |
2 |
|
T19 |
1 |
|
T83 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2862716 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1865331 |
1 |
|
|
T20 |
1 |
|
T87 |
2 |
|
T88 |
3 |
| auto[1] |
auto[1] |
auto[1] |
2869572 |
1 |
|
|
T2 |
3 |
|
T5 |
4 |
|
T7 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663488 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9469150 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15393804 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5738834 |
1 |
|
|
T16 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11673488 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9459150 |
1 |
|
|
T16 |
2 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1860357 |
1 |
|
|
T16 |
1 |
|
T5 |
2 |
|
T68 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2866809 |
1 |
|
|
T16 |
1 |
|
T2 |
8 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1859959 |
1 |
|
|
T2 |
2 |
|
T73 |
1 |
|
T33 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2872025 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11668171 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9464467 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15418813 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5713825 |
1 |
|
|
T16 |
2 |
|
T2 |
9 |
|
T4 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11703287 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9429351 |
1 |
|
|
T16 |
2 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1865329 |
1 |
|
|
T3 |
1 |
|
T71 |
1 |
|
T20 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2869706 |
1 |
|
|
T16 |
2 |
|
T2 |
5 |
|
T4 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1850197 |
1 |
|
|
T2 |
1 |
|
T104 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2844119 |
1 |
|
|
T2 |
4 |
|
T26 |
1 |
|
T19 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |