Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11698496 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9434142 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15411861 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5720777 |
1 |
|
|
T16 |
2 |
|
T2 |
10 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11686733 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9445905 |
1 |
|
|
T16 |
2 |
|
T2 |
12 |
|
T5 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1861963 |
1 |
|
|
T2 |
2 |
|
T19 |
2 |
|
T83 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2854299 |
1 |
|
|
T16 |
2 |
|
T2 |
7 |
|
T67 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1863165 |
1 |
|
|
T5 |
3 |
|
T101 |
1 |
|
T33 |
3 |
| auto[1] |
auto[1] |
auto[1] |
2866478 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669586 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9463052 |
1 |
|
|
T2 |
11 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15388323 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5744315 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T4 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11653137 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9479501 |
1 |
|
|
T2 |
13 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1879304 |
1 |
|
|
T2 |
1 |
|
T68 |
2 |
|
T9 |
5 |
| auto[1] |
auto[0] |
auto[1] |
2879382 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1855882 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2864933 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T26 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11695321 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9437317 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T12 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15388245 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
5744393 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669828 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9462810 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1862403 |
1 |
|
|
T16 |
2 |
|
T1 |
4 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
2879883 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1856014 |
1 |
|
|
T2 |
1 |
|
T10 |
1 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2864510 |
1 |
|
|
T2 |
4 |
|
T12 |
1 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663648 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9468990 |
1 |
|
|
T16 |
4 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15376347 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5756291 |
1 |
|
|
T16 |
2 |
|
T2 |
10 |
|
T4 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11647968 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9484670 |
1 |
|
|
T16 |
2 |
|
T2 |
12 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1862247 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T7 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2875039 |
1 |
|
|
T16 |
2 |
|
T2 |
7 |
|
T4 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1866132 |
1 |
|
|
T67 |
1 |
|
T9 |
4 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2881252 |
1 |
|
|
T2 |
3 |
|
T6 |
3 |
|
T7 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11671132 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9461506 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15390872 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5741766 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655778 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9476860 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1866011 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T101 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2862917 |
1 |
|
|
T2 |
5 |
|
T67 |
1 |
|
T19 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1869083 |
1 |
|
|
T2 |
2 |
|
T5 |
2 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2878849 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655646 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9476992 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15394294 |
1 |
|
|
T16 |
6 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
5738344 |
1 |
|
|
T16 |
2 |
|
T1 |
1 |
|
T2 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659862 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9472776 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1866645 |
1 |
|
|
T2 |
1 |
|
T83 |
1 |
|
T20 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2865678 |
1 |
|
|
T16 |
2 |
|
T2 |
5 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1867787 |
1 |
|
|
T1 |
4 |
|
T67 |
1 |
|
T10 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2872666 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T4 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11640061 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9492577 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15417921 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5714717 |
1 |
|
|
T16 |
2 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11691458 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9441180 |
1 |
|
|
T16 |
2 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1860174 |
1 |
|
|
T2 |
1 |
|
T68 |
1 |
|
T9 |
3 |
| auto[1] |
auto[0] |
auto[1] |
2847368 |
1 |
|
|
T16 |
2 |
|
T2 |
5 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1866289 |
1 |
|
|
T68 |
1 |
|
T19 |
1 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2867349 |
1 |
|
|
T2 |
6 |
|
T5 |
4 |
|
T6 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11691212 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9441426 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15365307 |
1 |
|
|
T16 |
6 |
|
T1 |
9 |
|
T11 |
1 |
| auto[1] |
5767331 |
1 |
|
|
T16 |
2 |
|
T1 |
3 |
|
T2 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11627659 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9504979 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1872321 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2894398 |
1 |
|
|
T16 |
2 |
|
T2 |
5 |
|
T67 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1865327 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T20 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2872933 |
1 |
|
|
T1 |
3 |
|
T2 |
4 |
|
T4 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11717322 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9415316 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15396632 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
5736006 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664473 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9468165 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1879652 |
1 |
|
|
T67 |
1 |
|
T71 |
1 |
|
T73 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2902944 |
1 |
|
|
T16 |
2 |
|
T2 |
6 |
|
T3 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1852507 |
1 |
|
|
T6 |
1 |
|
T73 |
1 |
|
T33 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2833062 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11631599 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9501039 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T5 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15426624 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5706014 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11710784 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9421854 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1856169 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2856595 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1859671 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2849419 |
1 |
|
|
T6 |
1 |
|
T7 |
2 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660340 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9472298 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15405416 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5727222 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11683122 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9449516 |
1 |
|
|
T2 |
8 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1855675 |
1 |
|
|
T2 |
1 |
|
T9 |
5 |
|
T19 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2859492 |
1 |
|
|
T2 |
3 |
|
T4 |
3 |
|
T67 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1866619 |
1 |
|
|
T2 |
2 |
|
T67 |
2 |
|
T71 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2867730 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674441 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9458197 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15429837 |
1 |
|
|
T16 |
6 |
|
T1 |
8 |
|
T11 |
1 |
| auto[1] |
5702801 |
1 |
|
|
T16 |
2 |
|
T1 |
4 |
|
T2 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11718054 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9414584 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1861848 |
1 |
|
|
T2 |
2 |
|
T9 |
6 |
|
T105 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2857054 |
1 |
|
|
T16 |
2 |
|
T2 |
4 |
|
T67 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1849935 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T10 |
2 |
| auto[1] |
auto[1] |
auto[1] |
2845747 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T6 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669876 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462762 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T4 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15400612 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5732026 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11673674 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9458964 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1870780 |
1 |
|
|
T4 |
1 |
|
T12 |
1 |
|
T19 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2877763 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1856158 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2854263 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T5 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662230 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9470408 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15412200 |
1 |
|
|
T16 |
7 |
|
T1 |
8 |
|
T11 |
1 |
| auto[1] |
5720438 |
1 |
|
|
T16 |
1 |
|
T1 |
4 |
|
T2 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11692937 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9439701 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1859508 |
1 |
|
|
T16 |
1 |
|
T4 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2863605 |
1 |
|
|
T16 |
1 |
|
T2 |
6 |
|
T67 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1859755 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
2856833 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T4 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11611407 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9521231 |
1 |
|
|
T16 |
4 |
|
T2 |
6 |
|
T4 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15404840 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5727798 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T5 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11687905 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9444733 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T5 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1845366 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T67 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2846805 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T5 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1871569 |
1 |
|
|
T10 |
1 |
|
T73 |
5 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2880993 |
1 |
|
|
T2 |
5 |
|
T67 |
1 |
|
T68 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |