Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11616511 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9516127 |
1 |
|
|
T1 |
5 |
|
T2 |
13 |
|
T7 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15408365 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
5724273 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11682106 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9450532 |
1 |
|
|
T2 |
11 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1855893 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T6 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2845417 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1870366 |
1 |
|
|
T2 |
1 |
|
T67 |
1 |
|
T10 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2878856 |
1 |
|
|
T2 |
4 |
|
T7 |
1 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11657826 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9474812 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19908091 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1224547 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669923 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9462715 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4128422 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
612351 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[0] |
4109746 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[1] |
612196 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T92 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669885 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462753 |
1 |
|
|
T2 |
14 |
|
T4 |
2 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19908550 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1224088 |
1 |
|
|
T16 |
1 |
|
T2 |
3 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11682075 |
1 |
|
|
T16 |
2 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9450563 |
1 |
|
|
T16 |
6 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4113190 |
1 |
|
|
T16 |
5 |
|
T1 |
5 |
|
T2 |
5 |
| auto[1] |
auto[0] |
auto[1] |
610799 |
1 |
|
|
T16 |
1 |
|
T2 |
1 |
|
T19 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4113285 |
1 |
|
|
T2 |
4 |
|
T4 |
2 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[1] |
613289 |
1 |
|
|
T2 |
2 |
|
T12 |
2 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11667285 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9465353 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19904185 |
1 |
|
|
T16 |
7 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1228453 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11648334 |
1 |
|
|
T16 |
2 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
9484304 |
1 |
|
|
T16 |
6 |
|
T1 |
2 |
|
T2 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4133078 |
1 |
|
|
T16 |
5 |
|
T2 |
7 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
614614 |
1 |
|
|
T16 |
1 |
|
T2 |
2 |
|
T5 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4122773 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
613839 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T68 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655666 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9476972 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19903606 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1229032 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T9 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655581 |
1 |
|
|
T16 |
8 |
|
T1 |
9 |
|
T11 |
1 |
| auto[1] |
9477057 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4127187 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
3 |
| auto[1] |
auto[0] |
auto[1] |
616316 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T9 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4120838 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
612716 |
1 |
|
|
T2 |
1 |
|
T71 |
1 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11683306 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9449332 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19904001 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1228637 |
1 |
|
|
T16 |
2 |
|
T2 |
3 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652278 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9480360 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4123512 |
1 |
|
|
T16 |
2 |
|
T2 |
4 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
614126 |
1 |
|
|
T16 |
2 |
|
T2 |
3 |
|
T69 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4128211 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[1] |
614511 |
1 |
|
|
T7 |
1 |
|
T19 |
2 |
|
T102 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11665631 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9467007 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19907927 |
1 |
|
|
T16 |
5 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1224711 |
1 |
|
|
T16 |
3 |
|
T1 |
1 |
|
T2 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11686744 |
1 |
|
|
T16 |
2 |
|
T1 |
9 |
|
T11 |
1 |
| auto[1] |
9445894 |
1 |
|
|
T16 |
6 |
|
T1 |
3 |
|
T2 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4104199 |
1 |
|
|
T16 |
3 |
|
T2 |
6 |
|
T4 |
4 |
| auto[1] |
auto[0] |
auto[1] |
611846 |
1 |
|
|
T16 |
3 |
|
T2 |
3 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4116984 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T5 |
4 |
| auto[1] |
auto[1] |
auto[1] |
612865 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11690969 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9441669 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19907401 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1225237 |
1 |
|
|
T2 |
2 |
|
T12 |
4 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662925 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9469713 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4157375 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
619651 |
1 |
|
|
T2 |
2 |
|
T68 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4087101 |
1 |
|
|
T2 |
3 |
|
T12 |
9 |
|
T6 |
2 |
| auto[1] |
auto[1] |
auto[1] |
605586 |
1 |
|
|
T12 |
4 |
|
T5 |
1 |
|
T67 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11678731 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9453907 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19902749 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1229889 |
1 |
|
|
T16 |
1 |
|
T68 |
1 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11643416 |
1 |
|
|
T16 |
2 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9489222 |
1 |
|
|
T16 |
6 |
|
T2 |
7 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4140137 |
1 |
|
|
T16 |
1 |
|
T2 |
6 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
616887 |
1 |
|
|
T16 |
1 |
|
T19 |
2 |
|
T69 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4119196 |
1 |
|
|
T16 |
4 |
|
T2 |
1 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
613002 |
1 |
|
|
T68 |
1 |
|
T73 |
1 |
|
T34 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11638188 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9494450 |
1 |
|
|
T2 |
10 |
|
T4 |
2 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19900504 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1232134 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11634999 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9497639 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4132622 |
1 |
|
|
T1 |
5 |
|
T2 |
4 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
616666 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4132883 |
1 |
|
|
T2 |
2 |
|
T4 |
2 |
|
T6 |
2 |
| auto[1] |
auto[1] |
auto[1] |
615468 |
1 |
|
|
T2 |
1 |
|
T68 |
1 |
|
T19 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11696440 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9436198 |
1 |
|
|
T2 |
4 |
|
T4 |
3 |
|
T5 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905088 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227550 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11656840 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9475798 |
1 |
|
|
T1 |
5 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4147732 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
619615 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4100516 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[1] |
607935 |
1 |
|
|
T7 |
1 |
|
T19 |
1 |
|
T33 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11671944 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9460694 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905335 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1227303 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655069 |
1 |
|
|
T16 |
8 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
9477569 |
1 |
|
|
T1 |
2 |
|
T2 |
11 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4133217 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
614254 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4117049 |
1 |
|
|
T2 |
5 |
|
T4 |
2 |
|
T12 |
14 |
| auto[1] |
auto[1] |
auto[1] |
613049 |
1 |
|
|
T33 |
3 |
|
T34 |
1 |
|
T92 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674614 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9458024 |
1 |
|
|
T2 |
15 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19906503 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1226135 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674087 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9458551 |
1 |
|
|
T1 |
5 |
|
T2 |
11 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4132917 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
616003 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4099499 |
1 |
|
|
T2 |
5 |
|
T4 |
3 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
610132 |
1 |
|
|
T2 |
1 |
|
T67 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11646011 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9486627 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19906979 |
1 |
|
|
T16 |
7 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1225659 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11676270 |
1 |
|
|
T16 |
6 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9456368 |
1 |
|
|
T16 |
2 |
|
T1 |
5 |
|
T2 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4111577 |
1 |
|
|
T16 |
1 |
|
T2 |
9 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
613551 |
1 |
|
|
T16 |
1 |
|
T2 |
2 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4119132 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T7 |
2 |
| auto[1] |
auto[1] |
auto[1] |
612108 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T33 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11670080 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462558 |
1 |
|
|
T16 |
4 |
|
T2 |
8 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905369 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227269 |
1 |
|
|
T2 |
2 |
|
T19 |
3 |
|
T83 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11654828 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9477810 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4138932 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T4 |
4 |
| auto[1] |
auto[0] |
auto[1] |
615446 |
1 |
|
|
T2 |
1 |
|
T19 |
3 |
|
T83 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4111609 |
1 |
|
|
T2 |
1 |
|
T12 |
13 |
|
T7 |
2 |
| auto[1] |
auto[1] |
auto[1] |
611823 |
1 |
|
|
T2 |
1 |
|
T20 |
1 |
|
T87 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |