Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663488 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9469150 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19918908 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1213730 |
1 |
|
|
T12 |
4 |
|
T68 |
1 |
|
T9 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11747469 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9385169 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4100962 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
609352 |
1 |
|
|
T12 |
4 |
|
T68 |
1 |
|
T9 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4070477 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
604378 |
1 |
|
|
T19 |
1 |
|
T73 |
1 |
|
T33 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11668171 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9464467 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19910202 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1222436 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T5 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11688999 |
1 |
|
|
T16 |
8 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
9443639 |
1 |
|
|
T1 |
2 |
|
T2 |
14 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4115693 |
1 |
|
|
T2 |
3 |
|
T4 |
4 |
|
T5 |
3 |
| auto[1] |
auto[0] |
auto[1] |
612515 |
1 |
|
|
T2 |
3 |
|
T5 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4105510 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[1] |
609921 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11698496 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9434142 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19906198 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1226440 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T67 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669985 |
1 |
|
|
T16 |
6 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462653 |
1 |
|
|
T16 |
2 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4117558 |
1 |
|
|
T16 |
2 |
|
T2 |
6 |
|
T4 |
3 |
| auto[1] |
auto[0] |
auto[1] |
613930 |
1 |
|
|
T7 |
1 |
|
T9 |
3 |
|
T72 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4118655 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[1] |
612510 |
1 |
|
|
T6 |
1 |
|
T67 |
1 |
|
T71 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669586 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9463052 |
1 |
|
|
T2 |
11 |
|
T4 |
3 |
|
T12 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19901941 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1230697 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11636383 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9496255 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4140076 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
616823 |
1 |
|
|
T1 |
1 |
|
T9 |
3 |
|
T10 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4125482 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
613874 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T67 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11695321 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9437317 |
1 |
|
|
T2 |
9 |
|
T3 |
1 |
|
T12 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19910959 |
1 |
|
|
T16 |
7 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1221679 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11703541 |
1 |
|
|
T16 |
2 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
9429097 |
1 |
|
|
T16 |
6 |
|
T1 |
2 |
|
T2 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4104493 |
1 |
|
|
T16 |
5 |
|
T1 |
1 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
611204 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4102925 |
1 |
|
|
T2 |
4 |
|
T12 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
610475 |
1 |
|
|
T2 |
1 |
|
T10 |
1 |
|
T19 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663648 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9468990 |
1 |
|
|
T16 |
4 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905239 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1227399 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T5 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661772 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9470866 |
1 |
|
|
T2 |
5 |
|
T4 |
4 |
|
T12 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4107426 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
610417 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4136041 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T7 |
1 |
| auto[1] |
auto[1] |
auto[1] |
616982 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T19 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11671132 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9461506 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19909351 |
1 |
|
|
T16 |
7 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1223287 |
1 |
|
|
T16 |
1 |
|
T2 |
3 |
|
T6 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11682734 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9449904 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4132411 |
1 |
|
|
T2 |
6 |
|
T4 |
2 |
|
T9 |
5 |
| auto[1] |
auto[0] |
auto[1] |
615411 |
1 |
|
|
T2 |
1 |
|
T9 |
2 |
|
T72 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4094206 |
1 |
|
|
T16 |
3 |
|
T1 |
5 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[1] |
607876 |
1 |
|
|
T16 |
1 |
|
T2 |
2 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11655646 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9476992 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905195 |
1 |
|
|
T16 |
7 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1227443 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11645796 |
1 |
|
|
T16 |
2 |
|
T1 |
9 |
|
T11 |
1 |
| auto[1] |
9486842 |
1 |
|
|
T16 |
6 |
|
T1 |
3 |
|
T2 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4138940 |
1 |
|
|
T16 |
2 |
|
T2 |
4 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
615766 |
1 |
|
|
T4 |
1 |
|
T19 |
1 |
|
T83 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4120459 |
1 |
|
|
T16 |
3 |
|
T1 |
2 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[1] |
611677 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11640061 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9492577 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905768 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1226870 |
1 |
|
|
T12 |
1 |
|
T67 |
1 |
|
T9 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661267 |
1 |
|
|
T16 |
2 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
9471371 |
1 |
|
|
T16 |
6 |
|
T1 |
2 |
|
T2 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4106448 |
1 |
|
|
T16 |
6 |
|
T2 |
5 |
|
T4 |
1 |
| auto[1] |
auto[0] |
auto[1] |
609832 |
1 |
|
|
T12 |
1 |
|
T67 |
1 |
|
T9 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4138053 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
2 |
| auto[1] |
auto[1] |
auto[1] |
617038 |
1 |
|
|
T10 |
1 |
|
T19 |
2 |
|
T33 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11691212 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9441426 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T4 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19902868 |
1 |
|
|
T16 |
8 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
1229770 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T67 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11651176 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9481462 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T4 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4128880 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
615287 |
1 |
|
|
T2 |
2 |
|
T67 |
1 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4122812 |
1 |
|
|
T1 |
3 |
|
T2 |
3 |
|
T4 |
3 |
| auto[1] |
auto[1] |
auto[1] |
614483 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11717322 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9415316 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19903349 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1229289 |
1 |
|
|
T2 |
1 |
|
T12 |
2 |
|
T72 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11647946 |
1 |
|
|
T16 |
2 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9484692 |
1 |
|
|
T16 |
6 |
|
T1 |
5 |
|
T2 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4158575 |
1 |
|
|
T16 |
2 |
|
T2 |
5 |
|
T4 |
3 |
| auto[1] |
auto[0] |
auto[1] |
620051 |
1 |
|
|
T2 |
1 |
|
T12 |
2 |
|
T72 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4096828 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[1] |
609238 |
1 |
|
|
T92 |
5 |
|
T93 |
3 |
|
T91 |
2552 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11631599 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9501039 |
1 |
|
|
T16 |
4 |
|
T2 |
10 |
|
T5 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905997 |
1 |
|
|
T16 |
7 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1226641 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652778 |
1 |
|
|
T16 |
2 |
|
T1 |
9 |
|
T11 |
1 |
| auto[1] |
9479860 |
1 |
|
|
T16 |
6 |
|
T1 |
3 |
|
T2 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4110397 |
1 |
|
|
T16 |
1 |
|
T1 |
2 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
609865 |
1 |
|
|
T16 |
1 |
|
T1 |
1 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4142822 |
1 |
|
|
T16 |
4 |
|
T2 |
3 |
|
T5 |
4 |
| auto[1] |
auto[1] |
auto[1] |
616776 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T73 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660340 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9472298 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19909861 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1222777 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T19 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11690372 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9442266 |
1 |
|
|
T2 |
10 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4090009 |
1 |
|
|
T2 |
4 |
|
T5 |
4 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
607798 |
1 |
|
|
T2 |
2 |
|
T19 |
2 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4129480 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
1 |
| auto[1] |
auto[1] |
auto[1] |
614979 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T101 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11674441 |
1 |
|
|
T16 |
4 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9458197 |
1 |
|
|
T16 |
4 |
|
T1 |
5 |
|
T2 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19911702 |
1 |
|
|
T16 |
8 |
|
T1 |
11 |
|
T11 |
1 |
| auto[1] |
1220936 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11699023 |
1 |
|
|
T16 |
4 |
|
T1 |
10 |
|
T11 |
1 |
| auto[1] |
9433615 |
1 |
|
|
T16 |
4 |
|
T1 |
2 |
|
T2 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4117094 |
1 |
|
|
T2 |
3 |
|
T4 |
3 |
|
T7 |
2 |
| auto[1] |
auto[0] |
auto[1] |
611096 |
1 |
|
|
T9 |
2 |
|
T69 |
3 |
|
T105 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4095585 |
1 |
|
|
T16 |
4 |
|
T1 |
1 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[1] |
609840 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11669876 |
1 |
|
|
T16 |
4 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
9462762 |
1 |
|
|
T16 |
4 |
|
T2 |
11 |
|
T4 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19905966 |
1 |
|
|
T16 |
8 |
|
T1 |
12 |
|
T11 |
1 |
| auto[1] |
1226672 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663698 |
1 |
|
|
T16 |
8 |
|
T1 |
7 |
|
T11 |
1 |
| auto[1] |
9468940 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T4 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4136475 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T4 |
2 |
| auto[1] |
auto[0] |
auto[1] |
617708 |
1 |
|
|
T12 |
1 |
|
T68 |
1 |
|
T69 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4105793 |
1 |
|
|
T2 |
6 |
|
T4 |
1 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[1] |
608964 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |