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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 100.00


Total test records in report: 970
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T763 /workspace/coverage/default/38.gpio_random_dout_din.943356861 Feb 07 05:06:49 PM PST 24 Feb 07 05:06:51 PM PST 24 402220580 ps
T764 /workspace/coverage/default/16.gpio_filter_stress.169520621 Feb 07 05:05:09 PM PST 24 Feb 07 05:05:26 PM PST 24 298436974 ps
T765 /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3016139388 Feb 07 05:06:09 PM PST 24 Feb 07 05:06:13 PM PST 24 185939118 ps
T766 /workspace/coverage/default/29.gpio_smoke.939407455 Feb 07 05:06:17 PM PST 24 Feb 07 05:06:18 PM PST 24 82427287 ps
T767 /workspace/coverage/default/30.gpio_random_dout_din.2861259390 Feb 07 05:06:14 PM PST 24 Feb 07 05:06:16 PM PST 24 59356416 ps
T768 /workspace/coverage/default/46.gpio_alert_test.1920069442 Feb 07 05:07:22 PM PST 24 Feb 07 05:07:28 PM PST 24 29436825 ps
T769 /workspace/coverage/default/8.gpio_full_random.4006059111 Feb 07 05:04:44 PM PST 24 Feb 07 05:04:45 PM PST 24 33746467 ps
T770 /workspace/coverage/default/8.gpio_intr_rand_pgm.1760975220 Feb 07 05:04:45 PM PST 24 Feb 07 05:04:47 PM PST 24 54520245 ps
T771 /workspace/coverage/default/18.gpio_smoke.495380118 Feb 07 05:05:21 PM PST 24 Feb 07 05:05:23 PM PST 24 41222303 ps
T772 /workspace/coverage/default/45.gpio_intr_rand_pgm.2569250934 Feb 07 05:07:27 PM PST 24 Feb 07 05:07:35 PM PST 24 95703022 ps
T773 /workspace/coverage/default/28.gpio_intr_rand_pgm.1434410397 Feb 07 05:06:09 PM PST 24 Feb 07 05:06:11 PM PST 24 39141807 ps
T774 /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3003080765 Feb 07 05:05:59 PM PST 24 Feb 07 05:06:01 PM PST 24 28927789 ps
T775 /workspace/coverage/default/24.gpio_full_random.4110283568 Feb 07 05:05:53 PM PST 24 Feb 07 05:05:55 PM PST 24 62846990 ps
T776 /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3977899269 Feb 07 05:06:56 PM PST 24 Feb 07 05:27:08 PM PST 24 185917035770 ps
T777 /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2359637789 Feb 07 05:04:45 PM PST 24 Feb 07 05:04:47 PM PST 24 97022789 ps
T778 /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1097458399 Feb 07 05:07:02 PM PST 24 Feb 07 05:07:04 PM PST 24 140839866 ps
T779 /workspace/coverage/default/18.gpio_stress_all.2888473489 Feb 07 05:05:26 PM PST 24 Feb 07 05:07:43 PM PST 24 4739417021 ps
T780 /workspace/coverage/default/44.gpio_full_random.1577731869 Feb 07 05:07:21 PM PST 24 Feb 07 05:07:29 PM PST 24 292283087 ps
T781 /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1754140582 Feb 07 05:04:08 PM PST 24 Feb 07 05:04:09 PM PST 24 25220944 ps
T782 /workspace/coverage/default/10.gpio_intr_rand_pgm.1565999730 Feb 07 05:05:00 PM PST 24 Feb 07 05:05:02 PM PST 24 107025614 ps
T783 /workspace/coverage/default/32.gpio_smoke.2281812488 Feb 07 05:06:20 PM PST 24 Feb 07 05:06:22 PM PST 24 41438525 ps
T784 /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4162739908 Feb 07 05:06:03 PM PST 24 Feb 07 05:06:06 PM PST 24 195514760 ps
T785 /workspace/coverage/default/18.gpio_alert_test.3786934177 Feb 07 05:05:28 PM PST 24 Feb 07 05:05:32 PM PST 24 43852295 ps
T786 /workspace/coverage/default/17.gpio_random_dout_din.640128506 Feb 07 05:05:26 PM PST 24 Feb 07 05:05:28 PM PST 24 30979441 ps
T787 /workspace/coverage/default/37.gpio_alert_test.3054390153 Feb 07 05:06:45 PM PST 24 Feb 07 05:06:47 PM PST 24 22935957 ps
T788 /workspace/coverage/default/2.gpio_full_random.4244694954 Feb 07 05:04:12 PM PST 24 Feb 07 05:04:13 PM PST 24 136139138 ps
T789 /workspace/coverage/default/24.gpio_filter_stress.419869358 Feb 07 05:05:53 PM PST 24 Feb 07 05:06:17 PM PST 24 439933058 ps
T790 /workspace/coverage/default/38.gpio_stress_all.1848470555 Feb 07 05:06:52 PM PST 24 Feb 07 05:08:02 PM PST 24 5787011241 ps
T791 /workspace/coverage/default/1.gpio_random_dout_din.175612979 Feb 07 05:03:54 PM PST 24 Feb 07 05:03:56 PM PST 24 92920454 ps
T792 /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3460988647 Feb 07 05:05:24 PM PST 24 Feb 07 05:05:29 PM PST 24 49426829 ps
T793 /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2068486308 Feb 07 05:07:21 PM PST 24 Feb 07 05:07:29 PM PST 24 65008726 ps
T794 /workspace/coverage/default/8.gpio_alert_test.2106838380 Feb 07 05:04:46 PM PST 24 Feb 07 05:04:47 PM PST 24 16907774 ps
T795 /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4081646134 Feb 07 05:04:34 PM PST 24 Feb 07 05:04:38 PM PST 24 246644347 ps
T52 /workspace/coverage/default/0.gpio_sec_cm.3924601218 Feb 07 05:03:55 PM PST 24 Feb 07 05:03:57 PM PST 24 65724841 ps
T796 /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1223995455 Feb 07 05:04:15 PM PST 24 Feb 07 05:04:17 PM PST 24 123634988 ps
T797 /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3114830634 Feb 07 05:05:26 PM PST 24 Feb 07 05:33:22 PM PST 24 223664799722 ps
T798 /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2052253837 Feb 07 05:07:07 PM PST 24 Feb 07 05:07:11 PM PST 24 30137232 ps
T799 /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2852203501 Feb 07 05:04:43 PM PST 24 Feb 07 05:04:47 PM PST 24 69991640 ps
T800 /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3436490238 Feb 07 05:04:48 PM PST 24 Feb 07 05:04:50 PM PST 24 229824937 ps
T801 /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.866577154 Feb 07 05:05:07 PM PST 24 Feb 07 05:05:09 PM PST 24 442768422 ps
T53 /workspace/coverage/default/3.gpio_sec_cm.2207001579 Feb 07 05:04:25 PM PST 24 Feb 07 05:04:27 PM PST 24 215287623 ps
T802 /workspace/coverage/default/13.gpio_intr_rand_pgm.4251375550 Feb 07 05:05:01 PM PST 24 Feb 07 05:05:02 PM PST 24 17561349 ps
T803 /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1487835348 Feb 07 05:06:14 PM PST 24 Feb 07 05:06:16 PM PST 24 111741192 ps
T804 /workspace/coverage/default/21.gpio_alert_test.4124691259 Feb 07 05:05:46 PM PST 24 Feb 07 05:05:48 PM PST 24 12649001 ps
T805 /workspace/coverage/default/16.gpio_smoke.3466416861 Feb 07 05:05:10 PM PST 24 Feb 07 05:05:14 PM PST 24 35521329 ps
T806 /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.53141921 Feb 07 05:07:08 PM PST 24 Feb 07 05:07:12 PM PST 24 21173568 ps
T807 /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3979194985 Feb 07 05:05:15 PM PST 24 Feb 07 05:05:17 PM PST 24 20579279 ps
T808 /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3537652969 Feb 07 05:06:47 PM PST 24 Feb 07 05:06:49 PM PST 24 34579615 ps
T809 /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1661605208 Feb 07 05:05:19 PM PST 24 Feb 07 05:20:32 PM PST 24 178519585403 ps
T810 /workspace/coverage/default/21.gpio_stress_all.3854712543 Feb 07 05:05:44 PM PST 24 Feb 07 05:08:26 PM PST 24 116734669660 ps
T811 /workspace/coverage/default/38.gpio_smoke.3325510645 Feb 07 05:06:51 PM PST 24 Feb 07 05:06:52 PM PST 24 100605507 ps
T812 /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1562270700 Feb 07 05:05:48 PM PST 24 Feb 07 05:07:21 PM PST 24 65699548690 ps
T813 /workspace/coverage/default/4.gpio_rand_intr_trigger.339558981 Feb 07 05:04:14 PM PST 24 Feb 07 05:04:18 PM PST 24 564206462 ps
T814 /workspace/coverage/default/1.gpio_alert_test.223888238 Feb 07 05:04:14 PM PST 24 Feb 07 05:04:15 PM PST 24 31019667 ps
T815 /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.840179569 Feb 07 05:07:37 PM PST 24 Feb 07 05:07:46 PM PST 24 479093218 ps
T816 /workspace/coverage/default/28.gpio_rand_intr_trigger.2577953265 Feb 07 05:06:14 PM PST 24 Feb 07 05:06:16 PM PST 24 109715822 ps
T817 /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2094071263 Feb 07 05:05:46 PM PST 24 Feb 07 05:05:48 PM PST 24 45916460 ps
T818 /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3851279605 Feb 07 05:06:49 PM PST 24 Feb 07 05:06:51 PM PST 24 156599349 ps
T819 /workspace/coverage/default/43.gpio_rand_intr_trigger.1060780321 Feb 07 05:07:06 PM PST 24 Feb 07 05:07:14 PM PST 24 212434738 ps
T820 /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2324349963 Feb 07 05:05:57 PM PST 24 Feb 07 05:06:01 PM PST 24 323966007 ps
T821 /workspace/coverage/default/46.gpio_filter_stress.3663150099 Feb 07 05:07:22 PM PST 24 Feb 07 05:07:36 PM PST 24 1173568938 ps
T822 /workspace/coverage/default/34.gpio_stress_all.1249611231 Feb 07 05:06:27 PM PST 24 Feb 07 05:10:07 PM PST 24 18215540880 ps
T823 /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.858514117 Feb 07 05:06:42 PM PST 24 Feb 07 05:06:44 PM PST 24 70889059 ps
T824 /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2457788083 Feb 07 05:04:26 PM PST 24 Feb 07 05:04:31 PM PST 24 135432844 ps
T825 /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.503021909 Feb 07 05:05:45 PM PST 24 Feb 07 05:32:39 PM PST 24 85426842621 ps
T826 /workspace/coverage/default/35.gpio_smoke.308281499 Feb 07 05:06:23 PM PST 24 Feb 07 05:06:30 PM PST 24 85245626 ps
T827 /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.523768925 Feb 07 05:06:13 PM PST 24 Feb 07 05:06:14 PM PST 24 59332874 ps
T828 /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2377411369 Feb 07 05:07:05 PM PST 24 Feb 07 05:07:15 PM PST 24 968728797 ps
T829 /workspace/coverage/default/44.gpio_rand_intr_trigger.1804502941 Feb 07 05:07:10 PM PST 24 Feb 07 05:07:17 PM PST 24 191915724 ps
T830 /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1172997101 Feb 07 05:05:53 PM PST 24 Feb 07 05:05:56 PM PST 24 226242953 ps
T831 /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.206691915 Feb 07 05:05:47 PM PST 24 Feb 07 05:05:49 PM PST 24 227749934 ps
T832 /workspace/coverage/default/28.gpio_alert_test.1679754419 Feb 07 05:06:09 PM PST 24 Feb 07 05:06:11 PM PST 24 20770697 ps
T833 /workspace/coverage/default/39.gpio_intr_rand_pgm.2139408752 Feb 07 05:07:05 PM PST 24 Feb 07 05:07:11 PM PST 24 196460635 ps
T834 /workspace/coverage/default/14.gpio_alert_test.3797355307 Feb 07 05:05:09 PM PST 24 Feb 07 05:05:13 PM PST 24 12749120 ps
T835 /workspace/coverage/default/25.gpio_filter_stress.3422876376 Feb 07 05:05:57 PM PST 24 Feb 07 05:06:08 PM PST 24 1325878448 ps
T836 /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2081606560 Feb 07 05:06:10 PM PST 24 Feb 07 05:06:14 PM PST 24 75853657 ps
T837 /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2391192601 Feb 07 05:07:27 PM PST 24 Feb 07 05:07:35 PM PST 24 59722490 ps
T838 /workspace/coverage/default/6.gpio_smoke.2229937690 Feb 07 05:04:43 PM PST 24 Feb 07 05:04:45 PM PST 24 124862176 ps
T839 /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3712444727 Feb 07 05:07:12 PM PST 24 Feb 07 05:07:21 PM PST 24 1017216196 ps
T840 /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3254872467 Feb 07 05:07:13 PM PST 24 Feb 07 05:15:53 PM PST 24 72913498231 ps
T841 /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3726306086 Feb 07 05:04:38 PM PST 24 Feb 07 05:04:39 PM PST 24 21864769 ps
T842 /workspace/coverage/default/23.gpio_filter_stress.4145956479 Feb 07 05:05:49 PM PST 24 Feb 07 05:06:09 PM PST 24 562180550 ps
T843 /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3683714865 Feb 07 05:05:13 PM PST 24 Feb 07 05:05:16 PM PST 24 135209173 ps
T844 /workspace/coverage/default/36.gpio_intr_rand_pgm.2143922840 Feb 07 05:06:49 PM PST 24 Feb 07 05:06:51 PM PST 24 62307609 ps
T845 /workspace/coverage/default/17.gpio_filter_stress.489894130 Feb 07 05:05:21 PM PST 24 Feb 07 05:05:43 PM PST 24 2698020216 ps
T846 /workspace/coverage/default/21.gpio_smoke.1218921664 Feb 07 05:05:42 PM PST 24 Feb 07 05:05:44 PM PST 24 33331092 ps
T847 /workspace/coverage/default/18.gpio_filter_stress.2120533823 Feb 07 05:05:27 PM PST 24 Feb 07 05:05:54 PM PST 24 420760412 ps
T848 /workspace/coverage/default/19.gpio_stress_all.3220035318 Feb 07 05:05:36 PM PST 24 Feb 07 05:07:35 PM PST 24 7399210169 ps
T849 /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.889186234 Feb 07 05:06:12 PM PST 24 Feb 07 05:06:13 PM PST 24 60167395 ps
T850 /workspace/coverage/default/19.gpio_intr_rand_pgm.3963480107 Feb 07 05:05:36 PM PST 24 Feb 07 05:05:37 PM PST 24 28567865 ps
T851 /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1877070716 Feb 07 05:07:02 PM PST 24 Feb 07 05:07:06 PM PST 24 281289802 ps
T852 /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3822414765 Feb 07 05:04:27 PM PST 24 Feb 07 05:04:29 PM PST 24 183271420 ps
T853 /workspace/coverage/default/8.gpio_smoke.3267248945 Feb 07 05:04:49 PM PST 24 Feb 07 05:04:52 PM PST 24 85646568 ps
T854 /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4100798347 Feb 07 05:05:28 PM PST 24 Feb 07 05:05:32 PM PST 24 222448849 ps
T855 /workspace/coverage/default/22.gpio_rand_intr_trigger.265511621 Feb 07 05:05:48 PM PST 24 Feb 07 05:05:52 PM PST 24 510243893 ps
T856 /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.147433925 Feb 07 05:07:08 PM PST 24 Feb 07 05:07:13 PM PST 24 337831673 ps
T857 /workspace/coverage/default/2.gpio_random_dout_din.1413756262 Feb 07 05:04:12 PM PST 24 Feb 07 05:04:14 PM PST 24 63225598 ps
T858 /workspace/coverage/default/38.gpio_rand_intr_trigger.2932077663 Feb 07 05:06:51 PM PST 24 Feb 07 05:06:55 PM PST 24 185284888 ps
T859 /workspace/coverage/default/5.gpio_full_random.821268984 Feb 07 05:04:29 PM PST 24 Feb 07 05:04:31 PM PST 24 68114694 ps
T860 /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3664755917 Feb 07 05:07:23 PM PST 24 Feb 07 05:07:33 PM PST 24 370522202 ps
T861 /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.426683058 Feb 07 05:05:20 PM PST 24 Feb 07 05:05:22 PM PST 24 91957552 ps
T862 /workspace/coverage/default/25.gpio_smoke.3116852867 Feb 07 05:05:58 PM PST 24 Feb 07 05:06:00 PM PST 24 87427394 ps
T863 /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3786374513 Feb 07 05:06:43 PM PST 24 Feb 07 05:06:47 PM PST 24 59944982 ps
T864 /workspace/coverage/default/3.gpio_rand_intr_trigger.2135901792 Feb 07 05:04:14 PM PST 24 Feb 07 05:04:18 PM PST 24 104922145 ps
T865 /workspace/coverage/default/18.gpio_rand_intr_trigger.3904721972 Feb 07 05:05:27 PM PST 24 Feb 07 05:05:32 PM PST 24 422715839 ps
T866 /workspace/coverage/default/48.gpio_stress_all.974770945 Feb 07 05:07:31 PM PST 24 Feb 07 05:09:39 PM PST 24 18232613331 ps
T867 /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4048120213 Feb 07 05:06:10 PM PST 24 Feb 07 05:06:11 PM PST 24 27606163 ps
T868 /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3131966298 Feb 07 05:05:02 PM PST 24 Feb 07 05:05:05 PM PST 24 1820911722 ps
T869 /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3935060794 Feb 07 05:07:13 PM PST 24 Feb 07 05:07:19 PM PST 24 274479598 ps
T870 /workspace/coverage/default/13.gpio_stress_all.2834234144 Feb 07 05:05:03 PM PST 24 Feb 07 05:06:57 PM PST 24 7313605699 ps
T871 /workspace/coverage/default/6.gpio_full_random.3918648076 Feb 07 05:04:43 PM PST 24 Feb 07 05:04:44 PM PST 24 51455609 ps
T872 /workspace/coverage/default/29.gpio_alert_test.1904399380 Feb 07 05:06:12 PM PST 24 Feb 07 05:06:14 PM PST 24 54249015 ps
T873 /workspace/coverage/default/43.gpio_stress_all.1208912674 Feb 07 05:07:21 PM PST 24 Feb 07 05:10:15 PM PST 24 30200743453 ps
T874 /workspace/coverage/default/46.gpio_stress_all.1182283226 Feb 07 05:07:24 PM PST 24 Feb 07 05:08:10 PM PST 24 14376711291 ps
T875 /workspace/coverage/default/21.gpio_full_random.1681369506 Feb 07 05:05:53 PM PST 24 Feb 07 05:05:54 PM PST 24 207083404 ps
T876 /workspace/coverage/default/9.gpio_alert_test.2295731546 Feb 07 05:05:01 PM PST 24 Feb 07 05:05:02 PM PST 24 12789521 ps
T877 /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3463482506 Feb 07 05:04:16 PM PST 24 Feb 07 05:15:30 PM PST 24 67017679201 ps
T878 /workspace/coverage/default/25.gpio_rand_intr_trigger.13838464 Feb 07 05:06:00 PM PST 24 Feb 07 05:06:03 PM PST 24 120021019 ps
T879 /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.904672056 Feb 07 05:06:25 PM PST 24 Feb 07 05:06:31 PM PST 24 224740345 ps
T880 /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1562404081 Feb 07 05:07:23 PM PST 24 Feb 07 05:07:30 PM PST 24 340213524 ps
T881 /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.864039799 Feb 07 05:06:25 PM PST 24 Feb 07 05:16:20 PM PST 24 86220193321 ps
T882 /workspace/coverage/default/32.gpio_filter_stress.2225698345 Feb 07 05:06:27 PM PST 24 Feb 07 05:06:42 PM PST 24 1723074239 ps
T883 /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3790870584 Feb 07 05:05:24 PM PST 24 Feb 07 05:05:28 PM PST 24 19863943 ps
T884 /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.82456036 Feb 07 05:04:18 PM PST 24 Feb 07 05:04:22 PM PST 24 147468594 ps
T885 /workspace/coverage/default/9.gpio_smoke.1374964552 Feb 07 05:04:46 PM PST 24 Feb 07 05:04:48 PM PST 24 182351366 ps
T886 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2691071729 Feb 07 01:41:26 PM PST 24 Feb 07 01:41:27 PM PST 24 40981805 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3809756390 Feb 07 01:40:38 PM PST 24 Feb 07 01:40:46 PM PST 24 54745146 ps
T887 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.211624882 Feb 07 01:41:18 PM PST 24 Feb 07 01:41:20 PM PST 24 167368416 ps
T888 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3877121162 Feb 07 01:41:25 PM PST 24 Feb 07 01:41:28 PM PST 24 72688209 ps
T889 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.766142801 Feb 07 01:41:04 PM PST 24 Feb 07 01:41:06 PM PST 24 35359645 ps
T76 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3401325955 Feb 07 01:40:40 PM PST 24 Feb 07 01:40:46 PM PST 24 32688901 ps
T890 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.198504059 Feb 07 01:41:08 PM PST 24 Feb 07 01:41:10 PM PST 24 48366472 ps
T891 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3700108018 Feb 07 01:41:04 PM PST 24 Feb 07 01:41:05 PM PST 24 35910221 ps
T892 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3177969610 Feb 07 01:41:34 PM PST 24 Feb 07 01:41:35 PM PST 24 37729312 ps
T893 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3107338661 Feb 07 01:41:08 PM PST 24 Feb 07 01:41:10 PM PST 24 121312508 ps
T894 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3430897071 Feb 07 01:40:56 PM PST 24 Feb 07 01:41:02 PM PST 24 420691127 ps
T895 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3647587638 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:37 PM PST 24 23407925 ps
T896 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4062962960 Feb 07 01:40:46 PM PST 24 Feb 07 01:40:59 PM PST 24 3327343122 ps
T897 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2783525736 Feb 07 01:41:23 PM PST 24 Feb 07 01:41:26 PM PST 24 159474666 ps
T90 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2401629382 Feb 07 01:41:38 PM PST 24 Feb 07 01:41:40 PM PST 24 76527947 ps
T898 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2069019348 Feb 07 01:40:54 PM PST 24 Feb 07 01:40:59 PM PST 24 27001114 ps
T899 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3715946626 Feb 07 01:41:26 PM PST 24 Feb 07 01:41:27 PM PST 24 17234136 ps
T900 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2426493488 Feb 07 01:41:34 PM PST 24 Feb 07 01:41:36 PM PST 24 36675936 ps
T901 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3233851634 Feb 07 01:41:33 PM PST 24 Feb 07 01:41:35 PM PST 24 277638804 ps
T902 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1141291428 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:37 PM PST 24 18237829 ps
T903 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1233686260 Feb 07 01:41:32 PM PST 24 Feb 07 01:41:34 PM PST 24 31051147 ps
T904 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2993205973 Feb 07 01:40:54 PM PST 24 Feb 07 01:40:59 PM PST 24 26361016 ps
T905 /workspace/coverage/cover_reg_top/20.gpio_intr_test.820032664 Feb 07 01:41:35 PM PST 24 Feb 07 01:41:37 PM PST 24 12454617 ps
T906 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3945509455 Feb 07 01:41:18 PM PST 24 Feb 07 01:41:21 PM PST 24 51473081 ps
T25 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.606882192 Feb 07 01:40:42 PM PST 24 Feb 07 01:40:47 PM PST 24 1578506605 ps
T907 /workspace/coverage/cover_reg_top/46.gpio_intr_test.480380141 Feb 07 01:41:35 PM PST 24 Feb 07 01:41:36 PM PST 24 31785002 ps
T908 /workspace/coverage/cover_reg_top/21.gpio_intr_test.583934444 Feb 07 01:41:35 PM PST 24 Feb 07 01:41:37 PM PST 24 11878957 ps
T909 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.220091841 Feb 07 01:40:55 PM PST 24 Feb 07 01:41:00 PM PST 24 40203442 ps
T910 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1726611704 Feb 07 01:41:28 PM PST 24 Feb 07 01:41:31 PM PST 24 161078897 ps
T911 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.559216380 Feb 07 01:40:42 PM PST 24 Feb 07 01:40:50 PM PST 24 177360528 ps
T85 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2712160027 Feb 07 01:40:55 PM PST 24 Feb 07 01:40:59 PM PST 24 14155910 ps
T912 /workspace/coverage/cover_reg_top/15.gpio_intr_test.564682053 Feb 07 01:41:28 PM PST 24 Feb 07 01:41:29 PM PST 24 14672902 ps
T913 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4170278638 Feb 07 01:41:19 PM PST 24 Feb 07 01:41:21 PM PST 24 54510775 ps
T914 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1284979660 Feb 07 01:42:54 PM PST 24 Feb 07 01:42:59 PM PST 24 44894850 ps
T94 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2756071055 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:39 PM PST 24 150665115 ps
T915 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3625707053 Feb 07 01:40:48 PM PST 24 Feb 07 01:40:57 PM PST 24 93003036 ps
T916 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.645514650 Feb 07 01:40:46 PM PST 24 Feb 07 01:40:56 PM PST 24 25824697 ps
T917 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4047995549 Feb 07 01:41:11 PM PST 24 Feb 07 01:41:13 PM PST 24 30678240 ps
T918 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3105112232 Feb 07 01:41:28 PM PST 24 Feb 07 01:41:32 PM PST 24 535064477 ps
T919 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3374470717 Feb 07 01:41:34 PM PST 24 Feb 07 01:41:36 PM PST 24 23161027 ps
T920 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3423704865 Feb 07 01:41:27 PM PST 24 Feb 07 01:41:28 PM PST 24 27977152 ps
T921 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3372543525 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:38 PM PST 24 35772651 ps
T922 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1822094118 Feb 07 01:41:32 PM PST 24 Feb 07 01:41:33 PM PST 24 14738486 ps
T923 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3792577546 Feb 07 01:41:38 PM PST 24 Feb 07 01:41:40 PM PST 24 20295437 ps
T924 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4189508816 Feb 07 01:41:18 PM PST 24 Feb 07 01:41:21 PM PST 24 365501685 ps
T925 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.387606543 Feb 07 01:40:43 PM PST 24 Feb 07 01:40:56 PM PST 24 558864799 ps
T926 /workspace/coverage/cover_reg_top/11.gpio_intr_test.48157774 Feb 07 01:41:18 PM PST 24 Feb 07 01:41:20 PM PST 24 56684250 ps
T927 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3778086247 Feb 07 01:40:40 PM PST 24 Feb 07 01:40:46 PM PST 24 64810755 ps
T928 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1286652941 Feb 07 01:41:24 PM PST 24 Feb 07 01:41:26 PM PST 24 31825829 ps
T929 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.205304125 Feb 07 01:41:37 PM PST 24 Feb 07 01:41:39 PM PST 24 288896503 ps
T930 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2864523186 Feb 07 01:41:37 PM PST 24 Feb 07 01:41:39 PM PST 24 13892340 ps
T931 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4044053866 Feb 07 01:40:35 PM PST 24 Feb 07 01:40:47 PM PST 24 205867346 ps
T932 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3996701538 Feb 07 01:40:42 PM PST 24 Feb 07 01:40:50 PM PST 24 24680125 ps
T933 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2259983934 Feb 07 01:41:07 PM PST 24 Feb 07 01:41:09 PM PST 24 16527910 ps
T934 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1268026754 Feb 07 01:41:33 PM PST 24 Feb 07 01:41:35 PM PST 24 27115882 ps
T935 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2770764077 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:37 PM PST 24 23842025 ps
T77 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1961833584 Feb 07 01:40:44 PM PST 24 Feb 07 01:40:55 PM PST 24 56796761 ps
T936 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2747829852 Feb 07 01:41:32 PM PST 24 Feb 07 01:41:34 PM PST 24 71328157 ps
T937 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3359398683 Feb 07 01:41:27 PM PST 24 Feb 07 01:41:29 PM PST 24 116580265 ps
T938 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3998975846 Feb 07 01:42:56 PM PST 24 Feb 07 01:43:04 PM PST 24 18689867 ps
T939 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3966956502 Feb 07 01:42:55 PM PST 24 Feb 07 01:43:05 PM PST 24 246409681 ps
T940 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4273403619 Feb 07 01:40:55 PM PST 24 Feb 07 01:40:59 PM PST 24 23780833 ps
T941 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1320499025 Feb 07 01:41:33 PM PST 24 Feb 07 01:41:35 PM PST 24 102889137 ps
T942 /workspace/coverage/cover_reg_top/25.gpio_intr_test.361633013 Feb 07 01:41:34 PM PST 24 Feb 07 01:41:35 PM PST 24 11244173 ps
T943 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3560287621 Feb 07 01:41:17 PM PST 24 Feb 07 01:41:19 PM PST 24 15447913 ps
T944 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.51599519 Feb 07 01:41:04 PM PST 24 Feb 07 01:41:06 PM PST 24 289086824 ps
T945 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2751156152 Feb 07 01:41:33 PM PST 24 Feb 07 01:41:34 PM PST 24 74649612 ps
T946 /workspace/coverage/cover_reg_top/3.gpio_intr_test.211663133 Feb 07 01:40:51 PM PST 24 Feb 07 01:40:56 PM PST 24 15634973 ps
T947 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1229631033 Feb 07 01:41:37 PM PST 24 Feb 07 01:41:38 PM PST 24 15115368 ps
T948 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2813953036 Feb 07 01:40:46 PM PST 24 Feb 07 01:40:58 PM PST 24 145566786 ps
T949 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3765744161 Feb 07 01:41:17 PM PST 24 Feb 07 01:41:19 PM PST 24 44991794 ps
T950 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2389514677 Feb 07 01:41:29 PM PST 24 Feb 07 01:41:30 PM PST 24 104835346 ps
T951 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3892260271 Feb 07 01:41:38 PM PST 24 Feb 07 01:41:40 PM PST 24 13883828 ps
T952 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1428885442 Feb 07 01:40:44 PM PST 24 Feb 07 01:40:55 PM PST 24 103836341 ps
T953 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2653484950 Feb 07 01:41:26 PM PST 24 Feb 07 01:41:28 PM PST 24 102355100 ps
T954 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2129311530 Feb 07 01:40:46 PM PST 24 Feb 07 01:40:58 PM PST 24 176559989 ps
T955 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3434160616 Feb 07 01:41:34 PM PST 24 Feb 07 01:41:36 PM PST 24 218818623 ps
T956 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2265873887 Feb 07 01:41:37 PM PST 24 Feb 07 01:41:40 PM PST 24 169202649 ps
T957 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2755214376 Feb 07 01:41:37 PM PST 24 Feb 07 01:41:39 PM PST 24 13541220 ps
T78 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3989273967 Feb 07 01:40:49 PM PST 24 Feb 07 01:40:56 PM PST 24 14582489 ps
T958 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3191560214 Feb 07 01:40:56 PM PST 24 Feb 07 01:41:00 PM PST 24 26018148 ps
T959 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.275544409 Feb 07 01:40:55 PM PST 24 Feb 07 01:41:00 PM PST 24 135787438 ps
T960 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3842690164 Feb 07 01:41:34 PM PST 24 Feb 07 01:41:35 PM PST 24 35782882 ps
T961 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1940076773 Feb 07 01:40:57 PM PST 24 Feb 07 01:41:01 PM PST 24 13379247 ps
T962 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.860279212 Feb 07 01:41:24 PM PST 24 Feb 07 01:41:25 PM PST 24 174331755 ps
T963 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1219456932 Feb 07 01:40:55 PM PST 24 Feb 07 01:41:00 PM PST 24 227557860 ps
T80 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2091357119 Feb 07 01:41:41 PM PST 24 Feb 07 01:41:43 PM PST 24 13343336 ps
T964 /workspace/coverage/cover_reg_top/45.gpio_intr_test.588568142 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:38 PM PST 24 66570641 ps
T965 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2757252810 Feb 07 01:41:36 PM PST 24 Feb 07 01:41:37 PM PST 24 21545531 ps
T966 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2040544665 Feb 07 01:41:01 PM PST 24 Feb 07 01:41:03 PM PST 24 101920792 ps
T967 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1118286684 Feb 07 01:41:35 PM PST 24 Feb 07 01:41:37 PM PST 24 42239812 ps
T79 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.914024469 Feb 07 01:40:51 PM PST 24 Feb 07 01:40:56 PM PST 24 44726283 ps
T968 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1457760526 Feb 07 01:42:35 PM PST 24 Feb 07 01:42:37 PM PST 24 18887683 ps
T969 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.794672050 Feb 07 01:40:55 PM PST 24 Feb 07 01:41:00 PM PST 24 111060706 ps
T970 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2206899291 Feb 07 01:41:26 PM PST 24 Feb 07 01:41:28 PM PST 24 116214293 ps

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2188624189
Short name T2
Test name
Test status
Simulation time 151479364 ps
CPU time 1.4 seconds
Started Feb 07 01:42:55 PM PST 24
Finished Feb 07 01:43:05 PM PST 24
Peak memory 197328 kb
Host smart-3f26c6b4-c9cc-4fa9-9dd5-00108e3c1ec1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188624189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2188624189
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1681355817
Short name T37
Test name
Test status
Simulation time 221884774 ps
CPU time 1.21 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:47:02 PM PST 24
Peak memory 198048 kb
Host smart-ae7138bd-edbf-456a-b020-779716ea4151
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681355817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1681355817
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/default/33.gpio_full_random.1089393775
Short name T27
Test name
Test status
Simulation time 51009334 ps
CPU time 0.94 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 196612 kb
Host smart-c408e2e5-009c-40f6-8e67-fd0dcdbfb5cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089393775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1089393775
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.756719763
Short name T107
Test name
Test status
Simulation time 120664208 ps
CPU time 2.66 seconds
Started Feb 07 05:04:57 PM PST 24
Finished Feb 07 05:05:00 PM PST 24
Peak memory 197868 kb
Host smart-5e5fca32-b4c0-4805-b5c9-40ce0ce89ae3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756719763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.756719763
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.428635941
Short name T11
Test name
Test status
Simulation time 149080482 ps
CPU time 2.07 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 197908 kb
Host smart-549b8e3a-d08f-4166-920f-92a7c9ec3cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428635941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.428635941
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1044253339
Short name T7
Test name
Test status
Simulation time 44930713 ps
CPU time 0.75 seconds
Started Feb 07 01:40:49 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 195828 kb
Host smart-97fe2021-c83d-4eb6-b992-cde7093adc6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044253339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1044253339
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3558076766
Short name T18
Test name
Test status
Simulation time 15213856 ps
CPU time 0.63 seconds
Started Feb 07 01:41:10 PM PST 24
Finished Feb 07 01:41:12 PM PST 24
Peak memory 194380 kb
Host smart-cd463a2e-4cb3-40ed-ab5c-a6424763586b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558076766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3558076766
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.841544819
Short name T63
Test name
Test status
Simulation time 775839649453 ps
CPU time 2529.39 seconds
Started Feb 07 05:05:54 PM PST 24
Finished Feb 07 05:48:05 PM PST 24
Peak memory 198004 kb
Host smart-27b97b1b-b6e3-4a5d-969e-0a060dd0c613
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=841544819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.841544819
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.511845496
Short name T33
Test name
Test status
Simulation time 189264256 ps
CPU time 1.41 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:57 PM PST 24
Peak memory 197920 kb
Host smart-bff66c19-165a-4353-b2e1-4f05a81c8046
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511845496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.511845496
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3813784280
Short name T21
Test name
Test status
Simulation time 73589012 ps
CPU time 0.85 seconds
Started Feb 07 05:04:26 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 213316 kb
Host smart-3c2f07e6-8ade-4b15-9fb4-b6f7d3543666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813784280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3813784280
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1878215261
Short name T104
Test name
Test status
Simulation time 38715537 ps
CPU time 1.1 seconds
Started Feb 07 01:41:31 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 197852 kb
Host smart-5f1d5c20-411e-45f8-8210-b64a0631c98e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878215261 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1878215261
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4079110204
Short name T98
Test name
Test status
Simulation time 163131347 ps
CPU time 0.85 seconds
Started Feb 07 01:46:53 PM PST 24
Finished Feb 07 01:46:55 PM PST 24
Peak memory 195500 kb
Host smart-c7335951-5d22-4046-98cc-7170b712bd8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4079110204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4079110204
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.500376202
Short name T1
Test name
Test status
Simulation time 113866663 ps
CPU time 0.85 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 196156 kb
Host smart-2a9b94c6-0b93-4035-a8d8-12224aeac19e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500376202 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.500376202
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.786244374
Short name T10
Test name
Test status
Simulation time 73204252 ps
CPU time 0.76 seconds
Started Feb 07 01:40:41 PM PST 24
Finished Feb 07 01:40:49 PM PST 24
Peak memory 196016 kb
Host smart-20cf799c-c64b-4dd7-84a3-684943fdd96c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786244374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.786244374
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2554139644
Short name T41
Test name
Test status
Simulation time 99615892 ps
CPU time 0.67 seconds
Started Feb 07 05:05:38 PM PST 24
Finished Feb 07 05:05:39 PM PST 24
Peak memory 193992 kb
Host smart-aa4eb65f-ef70-4ae4-9cd1-132d49b338f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554139644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2554139644
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3860728469
Short name T92
Test name
Test status
Simulation time 242602346 ps
CPU time 1.7 seconds
Started Feb 07 05:05:03 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 195548 kb
Host smart-0fd2ea0b-ff25-40c0-9810-d162c956b43f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860728469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3860728469
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.516234898
Short name T81
Test name
Test status
Simulation time 51642910 ps
CPU time 0.63 seconds
Started Feb 07 01:41:41 PM PST 24
Finished Feb 07 01:41:42 PM PST 24
Peak memory 193672 kb
Host smart-b6e9b882-057e-467f-9b5b-8109c51ebdce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516234898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.516234898
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.606882192
Short name T25
Test name
Test status
Simulation time 1578506605 ps
CPU time 1.76 seconds
Started Feb 07 01:40:42 PM PST 24
Finished Feb 07 01:40:47 PM PST 24
Peak memory 197980 kb
Host smart-30732a36-b068-4296-9083-9d15ef251821
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606882192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.606882192
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3010137125
Short name T73
Test name
Test status
Simulation time 120291818 ps
CPU time 0.83 seconds
Started Feb 07 01:40:36 PM PST 24
Finished Feb 07 01:40:45 PM PST 24
Peak memory 196056 kb
Host smart-96f8a644-adf9-4c82-948e-eeaad8f56d89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010137125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3010137125
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.184009682
Short name T121
Test name
Test status
Simulation time 648912291 ps
CPU time 3.15 seconds
Started Feb 07 01:40:44 PM PST 24
Finished Feb 07 01:40:57 PM PST 24
Peak memory 197120 kb
Host smart-55a007c9-fb6a-435b-a806-697627ef4a9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184009682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.184009682
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3989273967
Short name T78
Test name
Test status
Simulation time 14582489 ps
CPU time 0.6 seconds
Started Feb 07 01:40:49 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 194372 kb
Host smart-21b67dd4-7b7a-4beb-88b3-adb03fd49b8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989273967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3989273967
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1382802928
Short name T103
Test name
Test status
Simulation time 39558849 ps
CPU time 1.02 seconds
Started Feb 07 01:40:36 PM PST 24
Finished Feb 07 01:40:45 PM PST 24
Peak memory 197804 kb
Host smart-22e005a8-41c1-497c-b2b2-1782bbfc6023
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382802928 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1382802928
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3844985375
Short name T125
Test name
Test status
Simulation time 22969864 ps
CPU time 0.55 seconds
Started Feb 07 01:40:36 PM PST 24
Finished Feb 07 01:40:45 PM PST 24
Peak memory 194548 kb
Host smart-89cfa401-ab83-471e-98c9-037c353f1825
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844985375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3844985375
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2347535022
Short name T17
Test name
Test status
Simulation time 12608503 ps
CPU time 0.61 seconds
Started Feb 07 01:40:45 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 193636 kb
Host smart-708062e0-aa7b-4e59-adfc-6c8388e38b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347535022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2347535022
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3809756390
Short name T89
Test name
Test status
Simulation time 54745146 ps
CPU time 0.73 seconds
Started Feb 07 01:40:38 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 196072 kb
Host smart-2ced8e37-8a7e-4a84-94d1-9b5e266fcf55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809756390 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3809756390
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4044053866
Short name T931
Test name
Test status
Simulation time 205867346 ps
CPU time 2.82 seconds
Started Feb 07 01:40:35 PM PST 24
Finished Feb 07 01:40:47 PM PST 24
Peak memory 197924 kb
Host smart-b0f34b4e-f90c-4cbf-a16a-313398fd88d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044053866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4044053866
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.845911556
Short name T19
Test name
Test status
Simulation time 1745640920 ps
CPU time 1.48 seconds
Started Feb 07 01:40:36 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 197892 kb
Host smart-8b3ad732-46fd-4141-aae8-bc18d65ddb7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845911556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.845911556
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2062225956
Short name T70
Test name
Test status
Simulation time 757817406 ps
CPU time 3.39 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 196648 kb
Host smart-c764b3b9-51e9-4c79-bd31-56cf6969e770
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062225956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2062225956
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1710485452
Short name T24
Test name
Test status
Simulation time 35582872 ps
CPU time 0.64 seconds
Started Feb 07 01:40:41 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 195256 kb
Host smart-fd403c89-9d36-455b-8819-488a6f74010c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710485452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1710485452
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3778086247
Short name T927
Test name
Test status
Simulation time 64810755 ps
CPU time 0.85 seconds
Started Feb 07 01:40:40 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 197752 kb
Host smart-123dc11c-c573-44f5-9e65-d0add32afedd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778086247 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3778086247
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2301378777
Short name T6
Test name
Test status
Simulation time 15691884 ps
CPU time 0.62 seconds
Started Feb 07 01:40:45 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 194912 kb
Host smart-bf9bbb41-583e-4269-b961-49b138d88db6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301378777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2301378777
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1428885442
Short name T952
Test name
Test status
Simulation time 103836341 ps
CPU time 0.61 seconds
Started Feb 07 01:40:44 PM PST 24
Finished Feb 07 01:40:55 PM PST 24
Peak memory 193788 kb
Host smart-5039ed62-454f-4071-b30e-5dcafc0ae0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428885442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1428885442
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.686313818
Short name T32
Test name
Test status
Simulation time 237860462 ps
CPU time 2.75 seconds
Started Feb 07 01:40:42 PM PST 24
Finished Feb 07 01:40:52 PM PST 24
Peak memory 197952 kb
Host smart-1f98b0d1-1d22-4ef2-b19c-81b0526ff2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686313818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.686313818
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3107338661
Short name T893
Test name
Test status
Simulation time 121312508 ps
CPU time 0.82 seconds
Started Feb 07 01:41:08 PM PST 24
Finished Feb 07 01:41:10 PM PST 24
Peak memory 197852 kb
Host smart-5fadd1e0-c178-41e5-890c-e226fd871a13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107338661 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3107338661
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3480382926
Short name T67
Test name
Test status
Simulation time 17029455 ps
CPU time 0.6 seconds
Started Feb 07 01:41:11 PM PST 24
Finished Feb 07 01:41:13 PM PST 24
Peak memory 194436 kb
Host smart-4261e67f-e85d-4c0a-8dde-e5f0ca001054
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480382926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3480382926
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2066794305
Short name T95
Test name
Test status
Simulation time 143451372 ps
CPU time 0.61 seconds
Started Feb 07 01:41:06 PM PST 24
Finished Feb 07 01:41:08 PM PST 24
Peak memory 193684 kb
Host smart-dc13416f-dc85-41c7-b094-d0a9f97641a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066794305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2066794305
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2259983934
Short name T933
Test name
Test status
Simulation time 16527910 ps
CPU time 0.7 seconds
Started Feb 07 01:41:07 PM PST 24
Finished Feb 07 01:41:09 PM PST 24
Peak memory 195472 kb
Host smart-b4350878-5d74-4643-b44c-4c1e6af5d875
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259983934 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2259983934
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.98719020
Short name T64
Test name
Test status
Simulation time 198480281 ps
CPU time 1.85 seconds
Started Feb 07 01:41:05 PM PST 24
Finished Feb 07 01:41:08 PM PST 24
Peak memory 197872 kb
Host smart-47ea1878-d864-417b-877e-3d419b8a89d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98719020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.98719020
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3365010398
Short name T34
Test name
Test status
Simulation time 228394214 ps
CPU time 0.87 seconds
Started Feb 07 01:41:13 PM PST 24
Finished Feb 07 01:41:15 PM PST 24
Peak memory 197704 kb
Host smart-690c2f60-d97f-4ec0-9a68-3659bee96ade
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365010398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3365010398
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.211624882
Short name T887
Test name
Test status
Simulation time 167368416 ps
CPU time 1.03 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:20 PM PST 24
Peak memory 197832 kb
Host smart-f65faea5-f4e4-4602-88f7-30c6dfc6cb7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211624882 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.211624882
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.766142801
Short name T889
Test name
Test status
Simulation time 35359645 ps
CPU time 0.62 seconds
Started Feb 07 01:41:04 PM PST 24
Finished Feb 07 01:41:06 PM PST 24
Peak memory 194448 kb
Host smart-05af6bc5-7724-4fca-8e03-87c62f60f634
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766142801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.766142801
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.48157774
Short name T926
Test name
Test status
Simulation time 56684250 ps
CPU time 0.6 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:20 PM PST 24
Peak memory 193700 kb
Host smart-0c1e2f1f-c68c-434a-9cab-3ef5e98757e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48157774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.48157774
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3998975846
Short name T938
Test name
Test status
Simulation time 18689867 ps
CPU time 0.64 seconds
Started Feb 07 01:42:56 PM PST 24
Finished Feb 07 01:43:04 PM PST 24
Peak memory 195096 kb
Host smart-4c30afee-fcc4-430e-b0b5-39547b4b2c6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998975846 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3998975846
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2783525736
Short name T897
Test name
Test status
Simulation time 159474666 ps
CPU time 2.14 seconds
Started Feb 07 01:41:23 PM PST 24
Finished Feb 07 01:41:26 PM PST 24
Peak memory 197904 kb
Host smart-970bf0ad-5ae7-462d-8e91-85521cc9da50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783525736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2783525736
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3945509455
Short name T906
Test name
Test status
Simulation time 51473081 ps
CPU time 0.89 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 197100 kb
Host smart-7c5c7617-9d66-4042-9a20-d9a1aa52e3b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945509455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3945509455
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4170278638
Short name T913
Test name
Test status
Simulation time 54510775 ps
CPU time 1.02 seconds
Started Feb 07 01:41:19 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 197836 kb
Host smart-9adeb68c-13dd-4283-a9a4-da1d1d31b85c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170278638 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4170278638
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.128998421
Short name T5
Test name
Test status
Simulation time 45598178 ps
CPU time 0.63 seconds
Started Feb 07 01:41:23 PM PST 24
Finished Feb 07 01:41:24 PM PST 24
Peak memory 195036 kb
Host smart-608d0673-fd5a-422e-9e16-c3e7ec4617b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128998421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.128998421
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3560287621
Short name T943
Test name
Test status
Simulation time 15447913 ps
CPU time 0.6 seconds
Started Feb 07 01:41:17 PM PST 24
Finished Feb 07 01:41:19 PM PST 24
Peak memory 194348 kb
Host smart-57497cc2-5425-4445-bcb8-461704fc7370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560287621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3560287621
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2848961719
Short name T69
Test name
Test status
Simulation time 27181435 ps
CPU time 0.9 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:20 PM PST 24
Peak memory 197048 kb
Host smart-18b67f55-1a12-4dca-92bd-b68ec3038965
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848961719 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2848961719
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.4217396605
Short name T30
Test name
Test status
Simulation time 1878140014 ps
CPU time 1.48 seconds
Started Feb 07 01:41:17 PM PST 24
Finished Feb 07 01:41:19 PM PST 24
Peak memory 197920 kb
Host smart-fc5059ff-406d-4930-9298-f5668287e42f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217396605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.4217396605
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3765744161
Short name T949
Test name
Test status
Simulation time 44991794 ps
CPU time 0.83 seconds
Started Feb 07 01:41:17 PM PST 24
Finished Feb 07 01:41:19 PM PST 24
Peak memory 197824 kb
Host smart-7db1a6a3-1c77-4a0b-b807-80d226508fc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765744161 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3765744161
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3264741424
Short name T68
Test name
Test status
Simulation time 20652802 ps
CPU time 0.61 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:20 PM PST 24
Peak memory 195364 kb
Host smart-11be7431-0ea1-4fce-93fd-19c880ac9c97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264741424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3264741424
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1822094118
Short name T922
Test name
Test status
Simulation time 14738486 ps
CPU time 0.58 seconds
Started Feb 07 01:41:32 PM PST 24
Finished Feb 07 01:41:33 PM PST 24
Peak memory 193640 kb
Host smart-f995f639-b721-43e9-8a61-a933142e28c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822094118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1822094118
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3919837652
Short name T12
Test name
Test status
Simulation time 19641164 ps
CPU time 0.74 seconds
Started Feb 07 01:41:17 PM PST 24
Finished Feb 07 01:41:19 PM PST 24
Peak memory 196024 kb
Host smart-3fc7ffbb-352e-4df0-b403-d757403adad7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919837652 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3919837652
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3107146006
Short name T65
Test name
Test status
Simulation time 86963257 ps
CPU time 1.89 seconds
Started Feb 07 01:41:25 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 197936 kb
Host smart-cf4334e6-06af-4692-8e83-1739d464bd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107146006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3107146006
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4189508816
Short name T924
Test name
Test status
Simulation time 365501685 ps
CPU time 1.39 seconds
Started Feb 07 01:41:18 PM PST 24
Finished Feb 07 01:41:21 PM PST 24
Peak memory 197912 kb
Host smart-73f021c6-b295-4796-8eb1-0dd1e000b0aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189508816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4189508816
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1697201330
Short name T13
Test name
Test status
Simulation time 20366039 ps
CPU time 1.07 seconds
Started Feb 07 01:41:27 PM PST 24
Finished Feb 07 01:41:29 PM PST 24
Peak memory 197964 kb
Host smart-e085976d-5eb0-462b-8f92-865ab5612d09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697201330 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1697201330
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1558333391
Short name T71
Test name
Test status
Simulation time 37655460 ps
CPU time 0.61 seconds
Started Feb 07 01:41:31 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 194488 kb
Host smart-f686d3fb-0615-4189-8538-c1a05b20e2ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558333391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1558333391
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4156207113
Short name T15
Test name
Test status
Simulation time 49638850 ps
CPU time 0.62 seconds
Started Feb 07 01:41:25 PM PST 24
Finished Feb 07 01:41:27 PM PST 24
Peak memory 194428 kb
Host smart-6564a388-24bb-4cb6-8ccc-172e96c0eb5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156207113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4156207113
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2389514677
Short name T950
Test name
Test status
Simulation time 104835346 ps
CPU time 0.71 seconds
Started Feb 07 01:41:29 PM PST 24
Finished Feb 07 01:41:30 PM PST 24
Peak memory 195928 kb
Host smart-4a837ebd-325c-4055-b9d3-d02f97c896e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389514677 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2389514677
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3105112232
Short name T918
Test name
Test status
Simulation time 535064477 ps
CPU time 2.95 seconds
Started Feb 07 01:41:28 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 197748 kb
Host smart-fbc97660-5c12-448d-ae9f-b63dabae2f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105112232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3105112232
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2653484950
Short name T953
Test name
Test status
Simulation time 102355100 ps
CPU time 1.46 seconds
Started Feb 07 01:41:26 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 197828 kb
Host smart-8eff84d0-95ca-4445-b7ce-2337552739d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653484950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2653484950
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1188155861
Short name T4
Test name
Test status
Simulation time 15044851 ps
CPU time 0.6 seconds
Started Feb 07 01:41:28 PM PST 24
Finished Feb 07 01:41:29 PM PST 24
Peak memory 195572 kb
Host smart-a3ef375a-d096-4cc0-8d29-5af1b0d4f30d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188155861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1188155861
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.564682053
Short name T912
Test name
Test status
Simulation time 14672902 ps
CPU time 0.63 seconds
Started Feb 07 01:41:28 PM PST 24
Finished Feb 07 01:41:29 PM PST 24
Peak memory 194248 kb
Host smart-f4a9b793-8eda-4ab8-a711-fe423f22df32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564682053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.564682053
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3423704865
Short name T920
Test name
Test status
Simulation time 27977152 ps
CPU time 0.72 seconds
Started Feb 07 01:41:27 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 195084 kb
Host smart-09163e79-a3ca-4a40-ad37-35a08258cd53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423704865 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3423704865
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1286652941
Short name T928
Test name
Test status
Simulation time 31825829 ps
CPU time 1.65 seconds
Started Feb 07 01:41:24 PM PST 24
Finished Feb 07 01:41:26 PM PST 24
Peak memory 197936 kb
Host smart-a77147ea-35d3-4fe7-9912-63a017b6d801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286652941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1286652941
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2206899291
Short name T970
Test name
Test status
Simulation time 116214293 ps
CPU time 1.48 seconds
Started Feb 07 01:41:26 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 197944 kb
Host smart-3eca660b-6f3a-4884-9113-efbcb84f89db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206899291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2206899291
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1454387234
Short name T120
Test name
Test status
Simulation time 68214850 ps
CPU time 0.86 seconds
Started Feb 07 01:41:30 PM PST 24
Finished Feb 07 01:41:32 PM PST 24
Peak memory 197868 kb
Host smart-4163087e-95e6-445f-8c17-a514893819a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454387234 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1454387234
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2691071729
Short name T886
Test name
Test status
Simulation time 40981805 ps
CPU time 0.62 seconds
Started Feb 07 01:41:26 PM PST 24
Finished Feb 07 01:41:27 PM PST 24
Peak memory 194672 kb
Host smart-9bcb6457-b51c-4e0e-9f77-651bab9a415c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691071729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2691071729
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3124182277
Short name T115
Test name
Test status
Simulation time 37613090 ps
CPU time 0.6 seconds
Started Feb 07 01:41:26 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 194320 kb
Host smart-a54444a0-5af4-4bf4-bbd2-9b7e74bb4aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124182277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3124182277
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3715946626
Short name T899
Test name
Test status
Simulation time 17234136 ps
CPU time 0.7 seconds
Started Feb 07 01:41:26 PM PST 24
Finished Feb 07 01:41:27 PM PST 24
Peak memory 195880 kb
Host smart-fee0b9c2-17d8-4f68-b8f5-0885cf6f1e3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715946626 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3715946626
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1726611704
Short name T910
Test name
Test status
Simulation time 161078897 ps
CPU time 2.24 seconds
Started Feb 07 01:41:28 PM PST 24
Finished Feb 07 01:41:31 PM PST 24
Peak memory 197912 kb
Host smart-84fa9e48-10af-46e2-b3c3-86cb95879299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726611704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1726611704
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3157100166
Short name T20
Test name
Test status
Simulation time 131281585 ps
CPU time 1.06 seconds
Started Feb 07 01:41:23 PM PST 24
Finished Feb 07 01:41:25 PM PST 24
Peak memory 197852 kb
Host smart-d55d3848-e1d4-4e14-94a3-357472f620da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157100166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3157100166
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3359398683
Short name T937
Test name
Test status
Simulation time 116580265 ps
CPU time 0.61 seconds
Started Feb 07 01:41:27 PM PST 24
Finished Feb 07 01:41:29 PM PST 24
Peak memory 196236 kb
Host smart-bcf1b44f-0ac6-4a16-ac30-8b21318cdd9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359398683 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3359398683
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1796980331
Short name T3
Test name
Test status
Simulation time 24882424 ps
CPU time 0.59 seconds
Started Feb 07 01:41:25 PM PST 24
Finished Feb 07 01:41:26 PM PST 24
Peak memory 194568 kb
Host smart-8543671d-9f97-4fe8-ab80-64b5b2598509
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796980331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1796980331
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1707740130
Short name T126
Test name
Test status
Simulation time 40601936 ps
CPU time 0.59 seconds
Started Feb 07 01:41:32 PM PST 24
Finished Feb 07 01:41:33 PM PST 24
Peak memory 194316 kb
Host smart-125a764f-69b4-47b1-94db-56f4246aaf3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707740130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1707740130
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3542316269
Short name T88
Test name
Test status
Simulation time 97264589 ps
CPU time 0.78 seconds
Started Feb 07 01:41:28 PM PST 24
Finished Feb 07 01:41:29 PM PST 24
Peak memory 196284 kb
Host smart-f2210865-0c9d-4a46-a058-0067ecf05c85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542316269 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3542316269
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3877121162
Short name T888
Test name
Test status
Simulation time 72688209 ps
CPU time 1.84 seconds
Started Feb 07 01:41:25 PM PST 24
Finished Feb 07 01:41:28 PM PST 24
Peak memory 197864 kb
Host smart-a8baa8b0-c916-40d4-8140-ee96357384f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877121162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3877121162
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.860279212
Short name T962
Test name
Test status
Simulation time 174331755 ps
CPU time 0.88 seconds
Started Feb 07 01:41:24 PM PST 24
Finished Feb 07 01:41:25 PM PST 24
Peak memory 197248 kb
Host smart-45fde097-a742-4031-bd1a-029d571ce92d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860279212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.860279212
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3434160616
Short name T955
Test name
Test status
Simulation time 218818623 ps
CPU time 0.95 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:36 PM PST 24
Peak memory 197816 kb
Host smart-b9848aeb-a2d1-4ea5-a22b-cbcdefbd5110
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434160616 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3434160616
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3842690164
Short name T960
Test name
Test status
Simulation time 35782882 ps
CPU time 0.56 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193368 kb
Host smart-0a689502-8a12-4013-8a11-f1953700bff3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842690164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3842690164
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3857415619
Short name T116
Test name
Test status
Simulation time 11488330 ps
CPU time 0.59 seconds
Started Feb 07 01:41:35 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193704 kb
Host smart-33ac18a5-3ce4-4bb7-8a65-15b288f79979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857415619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3857415619
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3372543525
Short name T921
Test name
Test status
Simulation time 35772651 ps
CPU time 0.97 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 196072 kb
Host smart-fda063c4-fd78-4f44-bf0d-a40cec4afeea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372543525 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3372543525
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2265873887
Short name T956
Test name
Test status
Simulation time 169202649 ps
CPU time 1.67 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:40 PM PST 24
Peak memory 197900 kb
Host smart-b8c17b50-26f6-4fc3-be38-447a9e9bf93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265873887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2265873887
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2756071055
Short name T94
Test name
Test status
Simulation time 150665115 ps
CPU time 1.38 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 197936 kb
Host smart-9d49237b-5650-49fb-80a6-c203253231e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756071055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2756071055
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.535849230
Short name T105
Test name
Test status
Simulation time 23887945 ps
CPU time 0.81 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:36 PM PST 24
Peak memory 197864 kb
Host smart-5fa3988a-cce1-427f-bf7b-3acc037c88ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535849230 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.535849230
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2091357119
Short name T80
Test name
Test status
Simulation time 13343336 ps
CPU time 0.65 seconds
Started Feb 07 01:41:41 PM PST 24
Finished Feb 07 01:41:43 PM PST 24
Peak memory 194872 kb
Host smart-a79fabe2-aa95-4001-80f3-8543b00d1524
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091357119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2091357119
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1320499025
Short name T941
Test name
Test status
Simulation time 102889137 ps
CPU time 0.58 seconds
Started Feb 07 01:41:33 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193668 kb
Host smart-c61adc83-1aa1-48fb-aa15-24f9f7046b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320499025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1320499025
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2401629382
Short name T90
Test name
Test status
Simulation time 76527947 ps
CPU time 0.84 seconds
Started Feb 07 01:41:38 PM PST 24
Finished Feb 07 01:41:40 PM PST 24
Peak memory 196960 kb
Host smart-96d91a58-3e4f-4105-b448-ba94fe922105
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401629382 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2401629382
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.372549264
Short name T122
Test name
Test status
Simulation time 101862574 ps
CPU time 1.84 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 197912 kb
Host smart-8fe41f6d-a711-481d-9aa3-037865e082cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372549264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.372549264
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.205304125
Short name T929
Test name
Test status
Simulation time 288896503 ps
CPU time 1.19 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 197908 kb
Host smart-a9080ed7-a3ea-45ea-8608-8a5dc6e675b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205304125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.205304125
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1961833584
Short name T77
Test name
Test status
Simulation time 56796761 ps
CPU time 0.75 seconds
Started Feb 07 01:40:44 PM PST 24
Finished Feb 07 01:40:55 PM PST 24
Peak memory 196020 kb
Host smart-94f95a80-128b-4abd-b703-669ab7dfa116
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961833584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1961833584
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4062962960
Short name T896
Test name
Test status
Simulation time 3327343122 ps
CPU time 3.46 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 196624 kb
Host smart-783f0143-fcd1-463d-9e32-0b1cdc7cc456
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062962960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4062962960
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3401325955
Short name T76
Test name
Test status
Simulation time 32688901 ps
CPU time 0.69 seconds
Started Feb 07 01:40:40 PM PST 24
Finished Feb 07 01:40:46 PM PST 24
Peak memory 194992 kb
Host smart-0ff7facb-a782-4884-80e1-51dbbfefa25c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401325955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3401325955
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2069019348
Short name T898
Test name
Test status
Simulation time 27001114 ps
CPU time 0.64 seconds
Started Feb 07 01:40:54 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 196356 kb
Host smart-1bcf89bc-20fd-439f-be8c-642b0e5bd6ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069019348 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2069019348
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1149541365
Short name T100
Test name
Test status
Simulation time 222413616 ps
CPU time 0.6 seconds
Started Feb 07 01:40:44 PM PST 24
Finished Feb 07 01:40:55 PM PST 24
Peak memory 194748 kb
Host smart-e352d5a7-434b-4cfd-be30-0207af298412
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149541365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1149541365
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2282153441
Short name T112
Test name
Test status
Simulation time 15028969 ps
CPU time 0.68 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 193732 kb
Host smart-7c9d02ff-636b-462e-acb4-025ccd4b5f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282153441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2282153441
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3560620887
Short name T86
Test name
Test status
Simulation time 33843728 ps
CPU time 0.66 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 195228 kb
Host smart-c3d80c54-9380-4541-bb40-107522e994df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560620887 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3560620887
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.387606543
Short name T925
Test name
Test status
Simulation time 558864799 ps
CPU time 2.47 seconds
Started Feb 07 01:40:43 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 197896 kb
Host smart-7c211a2d-6943-4eae-8bd7-c8153f18b183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387606543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.387606543
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.559216380
Short name T911
Test name
Test status
Simulation time 177360528 ps
CPU time 0.87 seconds
Started Feb 07 01:40:42 PM PST 24
Finished Feb 07 01:40:50 PM PST 24
Peak memory 196948 kb
Host smart-4dac3306-2b02-40cf-aa34-9978cb8e03dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559216380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.559216380
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.820032664
Short name T905
Test name
Test status
Simulation time 12454617 ps
CPU time 0.58 seconds
Started Feb 07 01:41:35 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193672 kb
Host smart-4bca9041-704c-4454-8148-b75d111be043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820032664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.820032664
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.583934444
Short name T908
Test name
Test status
Simulation time 11878957 ps
CPU time 0.57 seconds
Started Feb 07 01:41:35 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193668 kb
Host smart-a4c44cf4-5abd-4627-ae41-54d04b44e4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583934444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.583934444
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4267161522
Short name T110
Test name
Test status
Simulation time 166672064 ps
CPU time 0.59 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 194344 kb
Host smart-699741fe-bf2b-4e1b-b11d-bf33a06d9875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267161522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4267161522
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1233686260
Short name T903
Test name
Test status
Simulation time 31051147 ps
CPU time 0.59 seconds
Started Feb 07 01:41:32 PM PST 24
Finished Feb 07 01:41:34 PM PST 24
Peak memory 194356 kb
Host smart-7f40990f-45eb-4598-a44a-457185199987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233686260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1233686260
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1268026754
Short name T934
Test name
Test status
Simulation time 27115882 ps
CPU time 0.64 seconds
Started Feb 07 01:41:33 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193636 kb
Host smart-6e8ff425-26ff-4ba5-818e-202b49397d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268026754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1268026754
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.361633013
Short name T942
Test name
Test status
Simulation time 11244173 ps
CPU time 0.59 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193776 kb
Host smart-1b683b57-99d2-4113-a174-4f6bbbcd939a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361633013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.361633013
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2864523186
Short name T930
Test name
Test status
Simulation time 13892340 ps
CPU time 0.59 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 193620 kb
Host smart-617cf5b4-ef87-4b37-90a9-47d27a52694a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864523186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2864523186
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.466095197
Short name T113
Test name
Test status
Simulation time 24683003 ps
CPU time 0.58 seconds
Started Feb 07 01:41:32 PM PST 24
Finished Feb 07 01:41:34 PM PST 24
Peak memory 194304 kb
Host smart-1a6a91b1-53f3-4495-abaa-762c0ee5acef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466095197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.466095197
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1164136932
Short name T119
Test name
Test status
Simulation time 39251075 ps
CPU time 0.57 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 193488 kb
Host smart-0ac358b3-3099-42d1-b338-9e4388f0bc24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164136932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1164136932
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2035901849
Short name T114
Test name
Test status
Simulation time 258017929 ps
CPU time 2.41 seconds
Started Feb 07 01:40:47 PM PST 24
Finished Feb 07 01:40:58 PM PST 24
Peak memory 196996 kb
Host smart-950b451c-a186-404b-aa37-44b2bb1206d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035901849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2035901849
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.914024469
Short name T79
Test name
Test status
Simulation time 44726283 ps
CPU time 0.58 seconds
Started Feb 07 01:40:51 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 194208 kb
Host smart-0847493c-42e6-4891-b96b-f8a0450bc511
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914024469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.914024469
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2993205973
Short name T904
Test name
Test status
Simulation time 26361016 ps
CPU time 0.84 seconds
Started Feb 07 01:40:54 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 197672 kb
Host smart-9d90c42a-d75e-4f2f-aa0f-8b783c6a7de7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993205973 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2993205973
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2601338143
Short name T101
Test name
Test status
Simulation time 24628170 ps
CPU time 0.6 seconds
Started Feb 07 01:40:44 PM PST 24
Finished Feb 07 01:40:54 PM PST 24
Peak memory 194732 kb
Host smart-ec176209-acaf-42b7-bf4e-52f50dff4280
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601338143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2601338143
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.211663133
Short name T946
Test name
Test status
Simulation time 15634973 ps
CPU time 0.58 seconds
Started Feb 07 01:40:51 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 193940 kb
Host smart-7595f2b4-b36a-4c9e-88bc-069944a5e759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211663133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.211663133
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3996701538
Short name T932
Test name
Test status
Simulation time 24680125 ps
CPU time 0.72 seconds
Started Feb 07 01:40:42 PM PST 24
Finished Feb 07 01:40:50 PM PST 24
Peak memory 195812 kb
Host smart-786ce9fc-a716-487b-b34b-baa9ecf9df1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996701538 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3996701538
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2813953036
Short name T948
Test name
Test status
Simulation time 145566786 ps
CPU time 2.97 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:58 PM PST 24
Peak memory 197912 kb
Host smart-4c12961f-d659-4602-9d7b-2c46f4b53919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813953036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2813953036
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1229631033
Short name T947
Test name
Test status
Simulation time 15115368 ps
CPU time 0.61 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 194284 kb
Host smart-1101fe05-ead4-432e-875a-1d5c0f7b91e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229631033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1229631033
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2751156152
Short name T945
Test name
Test status
Simulation time 74649612 ps
CPU time 0.59 seconds
Started Feb 07 01:41:33 PM PST 24
Finished Feb 07 01:41:34 PM PST 24
Peak memory 194412 kb
Host smart-6c4f8539-2e31-4c8a-a22f-a1ad23f23f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751156152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2751156152
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2747829852
Short name T936
Test name
Test status
Simulation time 71328157 ps
CPU time 0.57 seconds
Started Feb 07 01:41:32 PM PST 24
Finished Feb 07 01:41:34 PM PST 24
Peak memory 193624 kb
Host smart-3df70bfd-381d-44b9-a1c3-5cd01117ff41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747829852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2747829852
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3647587638
Short name T895
Test name
Test status
Simulation time 23407925 ps
CPU time 0.56 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193664 kb
Host smart-f6aeee2d-b2c1-46e9-b1bb-75665f290f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647587638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3647587638
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3892260271
Short name T951
Test name
Test status
Simulation time 13883828 ps
CPU time 0.6 seconds
Started Feb 07 01:41:38 PM PST 24
Finished Feb 07 01:41:40 PM PST 24
Peak memory 193684 kb
Host smart-5796fb5e-b673-4b0d-be7e-8221b8c6ad33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892260271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3892260271
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2426493488
Short name T900
Test name
Test status
Simulation time 36675936 ps
CPU time 0.59 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:36 PM PST 24
Peak memory 193648 kb
Host smart-e9ba036e-c2ff-4c15-b791-356d5534f813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426493488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2426493488
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3374470717
Short name T919
Test name
Test status
Simulation time 23161027 ps
CPU time 0.58 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:36 PM PST 24
Peak memory 193680 kb
Host smart-cd3b4a2b-639d-4f19-b21b-119355bdd227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374470717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3374470717
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2755214376
Short name T957
Test name
Test status
Simulation time 13541220 ps
CPU time 0.58 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 193664 kb
Host smart-5bf5d89c-8f85-4555-a16f-b8e5a3b49699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755214376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2755214376
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2757252810
Short name T965
Test name
Test status
Simulation time 21545531 ps
CPU time 0.61 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193732 kb
Host smart-464348f8-810f-410d-91d5-c7beec727f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757252810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2757252810
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3792577546
Short name T923
Test name
Test status
Simulation time 20295437 ps
CPU time 0.58 seconds
Started Feb 07 01:41:38 PM PST 24
Finished Feb 07 01:41:40 PM PST 24
Peak memory 193644 kb
Host smart-804348dc-9392-4b73-97bd-9d23d8d62d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792577546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3792577546
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.645514650
Short name T916
Test name
Test status
Simulation time 25824697 ps
CPU time 0.74 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 195540 kb
Host smart-771b872a-6d1c-4ed2-9d8f-03a45eda2d5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645514650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.645514650
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3625707053
Short name T915
Test name
Test status
Simulation time 93003036 ps
CPU time 1.45 seconds
Started Feb 07 01:40:48 PM PST 24
Finished Feb 07 01:40:57 PM PST 24
Peak memory 196752 kb
Host smart-630db2b5-fcb7-4ecc-b747-3330ff445bce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625707053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3625707053
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3191560214
Short name T958
Test name
Test status
Simulation time 26018148 ps
CPU time 0.64 seconds
Started Feb 07 01:40:56 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 194660 kb
Host smart-31f103ca-fb52-405d-abe7-dfb1a41ec19f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191560214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3191560214
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3437119578
Short name T83
Test name
Test status
Simulation time 69766582 ps
CPU time 0.93 seconds
Started Feb 07 01:40:56 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 197672 kb
Host smart-9fa7796c-dc69-4e87-80a3-1aed7285767c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437119578 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3437119578
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1766531275
Short name T72
Test name
Test status
Simulation time 53648639 ps
CPU time 0.59 seconds
Started Feb 07 01:40:51 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 194628 kb
Host smart-0a3f4797-dae6-4bf3-9068-481976a7caa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766531275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1766531275
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.172129284
Short name T118
Test name
Test status
Simulation time 33254830 ps
CPU time 0.57 seconds
Started Feb 07 01:40:51 PM PST 24
Finished Feb 07 01:40:56 PM PST 24
Peak memory 193312 kb
Host smart-3cdd5957-fc22-406b-8360-99db837c939d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172129284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.172129284
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1457760526
Short name T968
Test name
Test status
Simulation time 18887683 ps
CPU time 0.86 seconds
Started Feb 07 01:42:35 PM PST 24
Finished Feb 07 01:42:37 PM PST 24
Peak memory 194948 kb
Host smart-5c874783-a669-496a-a259-3b89adea55df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457760526 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1457760526
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2129311530
Short name T954
Test name
Test status
Simulation time 176559989 ps
CPU time 2.96 seconds
Started Feb 07 01:40:46 PM PST 24
Finished Feb 07 01:40:58 PM PST 24
Peak memory 197924 kb
Host smart-6839339a-b14a-426b-ab53-0946f2138fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129311530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2129311530
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1141291428
Short name T902
Test name
Test status
Simulation time 18237829 ps
CPU time 0.66 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193720 kb
Host smart-68318319-d065-4700-a50f-9b27aad62ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141291428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1141291428
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1118286684
Short name T967
Test name
Test status
Simulation time 42239812 ps
CPU time 0.65 seconds
Started Feb 07 01:41:35 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 194320 kb
Host smart-6febf833-6ea9-4e04-a908-34cd923b932f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118286684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1118286684
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3177969610
Short name T892
Test name
Test status
Simulation time 37729312 ps
CPU time 0.61 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193700 kb
Host smart-ebdaa9c1-aa09-4e0f-b344-480dc62bc244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177969610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3177969610
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3233851634
Short name T901
Test name
Test status
Simulation time 277638804 ps
CPU time 0.66 seconds
Started Feb 07 01:41:33 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193692 kb
Host smart-e4a19fd1-493f-4ea0-b7d0-7c916e45292f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233851634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3233851634
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.442536946
Short name T82
Test name
Test status
Simulation time 53289605 ps
CPU time 0.6 seconds
Started Feb 07 01:41:35 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193632 kb
Host smart-fadd07ef-2192-4851-8449-e40cbef08b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442536946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.442536946
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.588568142
Short name T964
Test name
Test status
Simulation time 66570641 ps
CPU time 0.55 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:38 PM PST 24
Peak memory 194060 kb
Host smart-31cf85f4-9dc5-4374-a6d2-3c6d12fa4011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588568142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.588568142
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.480380141
Short name T907
Test name
Test status
Simulation time 31785002 ps
CPU time 0.57 seconds
Started Feb 07 01:41:35 PM PST 24
Finished Feb 07 01:41:36 PM PST 24
Peak memory 193660 kb
Host smart-c269e830-63d2-4d7f-87df-8cc55a682f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480380141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.480380141
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2770764077
Short name T935
Test name
Test status
Simulation time 23842025 ps
CPU time 0.58 seconds
Started Feb 07 01:41:36 PM PST 24
Finished Feb 07 01:41:37 PM PST 24
Peak memory 193628 kb
Host smart-fc3e38e1-dd9c-4265-85fe-3a46c4a6401f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770764077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2770764077
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1646655752
Short name T123
Test name
Test status
Simulation time 39155816 ps
CPU time 0.57 seconds
Started Feb 07 01:41:34 PM PST 24
Finished Feb 07 01:41:35 PM PST 24
Peak memory 193688 kb
Host smart-a2580c35-4a19-4342-8355-3bbd62603bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646655752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1646655752
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3466942882
Short name T124
Test name
Test status
Simulation time 30561956 ps
CPU time 0.59 seconds
Started Feb 07 01:41:37 PM PST 24
Finished Feb 07 01:41:39 PM PST 24
Peak memory 193728 kb
Host smart-e62bd1e1-bb51-47b3-9080-db00548a273c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466942882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3466942882
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2040544665
Short name T966
Test name
Test status
Simulation time 101920792 ps
CPU time 0.65 seconds
Started Feb 07 01:41:01 PM PST 24
Finished Feb 07 01:41:03 PM PST 24
Peak memory 197072 kb
Host smart-f32f15f4-c8e1-4f36-94e0-eb99befca323
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040544665 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2040544665
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2712160027
Short name T85
Test name
Test status
Simulation time 14155910 ps
CPU time 0.59 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 194956 kb
Host smart-9103ecdb-ee28-4332-bc36-dc7d00638cf9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712160027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2712160027
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.100312363
Short name T14
Test name
Test status
Simulation time 18579639 ps
CPU time 0.59 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 193628 kb
Host smart-88c754a5-32da-482f-9d67-9dce08285b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100312363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.100312363
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.794672050
Short name T969
Test name
Test status
Simulation time 111060706 ps
CPU time 0.75 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 195908 kb
Host smart-bf96e8cf-fd28-4524-933b-837da7554984
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794672050 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.794672050
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3430897071
Short name T894
Test name
Test status
Simulation time 420691127 ps
CPU time 2.44 seconds
Started Feb 07 01:40:56 PM PST 24
Finished Feb 07 01:41:02 PM PST 24
Peak memory 197916 kb
Host smart-100fa788-d368-41cf-9aa9-0cc73b5473c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430897071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3430897071
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1219456932
Short name T963
Test name
Test status
Simulation time 227557860 ps
CPU time 1.18 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 197572 kb
Host smart-b810c67c-f4f4-448b-98be-7d257c06afc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219456932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1219456932
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4257039212
Short name T102
Test name
Test status
Simulation time 130377588 ps
CPU time 1.01 seconds
Started Feb 07 01:40:57 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 197816 kb
Host smart-5782c190-463c-4fe9-b206-0bd52ab59473
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257039212 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4257039212
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1940076773
Short name T961
Test name
Test status
Simulation time 13379247 ps
CPU time 0.61 seconds
Started Feb 07 01:40:57 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 195532 kb
Host smart-382828f8-8939-43bd-b2f2-494d67a3f8db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940076773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1940076773
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1284979660
Short name T914
Test name
Test status
Simulation time 44894850 ps
CPU time 0.6 seconds
Started Feb 07 01:42:54 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 193428 kb
Host smart-0ab150f6-17a1-4898-bb98-d8a9210dc411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284979660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1284979660
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.905354323
Short name T87
Test name
Test status
Simulation time 31901906 ps
CPU time 0.83 seconds
Started Feb 07 01:41:00 PM PST 24
Finished Feb 07 01:41:02 PM PST 24
Peak memory 196000 kb
Host smart-8f4101e7-6767-4017-a4d1-001e9942aada
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905354323 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.905354323
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3421696146
Short name T66
Test name
Test status
Simulation time 38367967 ps
CPU time 1.84 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 197932 kb
Host smart-46be0f6d-db6d-4ba4-a2f8-082d71e5c534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421696146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3421696146
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.275544409
Short name T959
Test name
Test status
Simulation time 135787438 ps
CPU time 0.83 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 196984 kb
Host smart-f48c4d0e-76ae-4219-afb1-39f29b3c201d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275544409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.275544409
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.220091841
Short name T909
Test name
Test status
Simulation time 40203442 ps
CPU time 1.06 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:41:00 PM PST 24
Peak memory 197920 kb
Host smart-e973fa49-1681-4dee-8fb6-a8b49a8ab96d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220091841 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.220091841
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4273403619
Short name T940
Test name
Test status
Simulation time 23780833 ps
CPU time 0.6 seconds
Started Feb 07 01:40:55 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 195240 kb
Host smart-130eb534-9937-4b12-847e-f3c735f42482
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273403619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.4273403619
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.799567967
Short name T84
Test name
Test status
Simulation time 24540727 ps
CPU time 0.55 seconds
Started Feb 07 01:40:54 PM PST 24
Finished Feb 07 01:40:59 PM PST 24
Peak memory 194340 kb
Host smart-0aa3b16a-166a-428b-b9cd-4e82ede86d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799567967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.799567967
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2016418968
Short name T16
Test name
Test status
Simulation time 73284465 ps
CPU time 0.7 seconds
Started Feb 07 01:42:55 PM PST 24
Finished Feb 07 01:43:04 PM PST 24
Peak memory 195464 kb
Host smart-c3cb3385-65cd-4807-a4b0-01dc44b92168
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016418968 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2016418968
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3454919362
Short name T31
Test name
Test status
Simulation time 102325356 ps
CPU time 2.2 seconds
Started Feb 07 01:42:35 PM PST 24
Finished Feb 07 01:42:38 PM PST 24
Peak memory 196568 kb
Host smart-7242aa06-6b0d-4b0d-9632-c3d3388a643b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454919362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3454919362
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3966956502
Short name T939
Test name
Test status
Simulation time 246409681 ps
CPU time 1.09 seconds
Started Feb 07 01:42:55 PM PST 24
Finished Feb 07 01:43:05 PM PST 24
Peak memory 197488 kb
Host smart-62404600-fa1e-4c05-a65b-32125bde05ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966956502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3966956502
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3528495520
Short name T26
Test name
Test status
Simulation time 76102233 ps
CPU time 0.76 seconds
Started Feb 07 01:42:53 PM PST 24
Finished Feb 07 01:42:59 PM PST 24
Peak memory 197604 kb
Host smart-25f0f289-f96a-49de-ac16-ab43f99e9a28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528495520 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3528495520
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.328157179
Short name T74
Test name
Test status
Simulation time 37925612 ps
CPU time 0.6 seconds
Started Feb 07 01:40:58 PM PST 24
Finished Feb 07 01:41:01 PM PST 24
Peak memory 195368 kb
Host smart-ce17ae90-bed0-4cfa-9523-5832ad6ee942
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328157179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.328157179
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.477905780
Short name T111
Test name
Test status
Simulation time 15377842 ps
CPU time 0.59 seconds
Started Feb 07 01:41:12 PM PST 24
Finished Feb 07 01:41:13 PM PST 24
Peak memory 193416 kb
Host smart-de1a8261-f609-47e7-be13-8cab04ac9a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477905780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.477905780
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4047995549
Short name T917
Test name
Test status
Simulation time 30678240 ps
CPU time 0.74 seconds
Started Feb 07 01:41:11 PM PST 24
Finished Feb 07 01:41:13 PM PST 24
Peak memory 195736 kb
Host smart-5ab5432b-8a40-49fc-aabe-9d089637d0d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047995549 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4047995549
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2607008635
Short name T117
Test name
Test status
Simulation time 118234529 ps
CPU time 1.56 seconds
Started Feb 07 01:41:05 PM PST 24
Finished Feb 07 01:41:08 PM PST 24
Peak memory 197924 kb
Host smart-bb30c063-e480-409f-a3ec-1b4091a98630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607008635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2607008635
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.176798686
Short name T29
Test name
Test status
Simulation time 54361237 ps
CPU time 0.84 seconds
Started Feb 07 01:41:04 PM PST 24
Finished Feb 07 01:41:06 PM PST 24
Peak memory 197012 kb
Host smart-faed5e8a-1b4a-44e0-91b3-5aa9dbf6ac18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176798686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.176798686
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.198504059
Short name T890
Test name
Test status
Simulation time 48366472 ps
CPU time 0.96 seconds
Started Feb 07 01:41:08 PM PST 24
Finished Feb 07 01:41:10 PM PST 24
Peak memory 197864 kb
Host smart-491aa737-445e-4ea0-aa9f-a4f6f8f3c187
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198504059 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.198504059
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3700108018
Short name T891
Test name
Test status
Simulation time 35910221 ps
CPU time 0.55 seconds
Started Feb 07 01:41:04 PM PST 24
Finished Feb 07 01:41:05 PM PST 24
Peak memory 195352 kb
Host smart-fc3d0970-3213-49c9-a09c-639ab49ece17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700108018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3700108018
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3629592710
Short name T9
Test name
Test status
Simulation time 59648855 ps
CPU time 0.76 seconds
Started Feb 07 01:41:06 PM PST 24
Finished Feb 07 01:41:08 PM PST 24
Peak memory 196076 kb
Host smart-683f48cd-8543-4035-a93f-b4cec487663a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629592710 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3629592710
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.640314660
Short name T8
Test name
Test status
Simulation time 140105788 ps
CPU time 2.2 seconds
Started Feb 07 01:42:55 PM PST 24
Finished Feb 07 01:43:06 PM PST 24
Peak memory 197608 kb
Host smart-8a3e64dc-e2d9-4eff-a999-223006bac6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640314660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.640314660
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.51599519
Short name T944
Test name
Test status
Simulation time 289086824 ps
CPU time 1.14 seconds
Started Feb 07 01:41:04 PM PST 24
Finished Feb 07 01:41:06 PM PST 24
Peak memory 197984 kb
Host smart-b24b34e7-f123-4daa-a49f-e7ac6119164b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51599519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.gpio_tl_intg_err.51599519
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3574316090
Short name T751
Test name
Test status
Simulation time 34977152 ps
CPU time 0.58 seconds
Started Feb 07 05:03:57 PM PST 24
Finished Feb 07 05:03:58 PM PST 24
Peak memory 193296 kb
Host smart-ba119743-6931-481c-b6bd-722d2a9fa57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574316090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3574316090
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1737148375
Short name T429
Test name
Test status
Simulation time 45845566 ps
CPU time 0.75 seconds
Started Feb 07 05:03:53 PM PST 24
Finished Feb 07 05:03:54 PM PST 24
Peak memory 193996 kb
Host smart-8d0692f7-ea3b-4e32-a9ef-4cd173502d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737148375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1737148375
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2104720637
Short name T277
Test name
Test status
Simulation time 607725286 ps
CPU time 8.33 seconds
Started Feb 07 05:03:46 PM PST 24
Finished Feb 07 05:03:55 PM PST 24
Peak memory 195328 kb
Host smart-1623a3a8-02c4-4fcd-9844-964ae1d655b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104720637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2104720637
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.402196668
Short name T476
Test name
Test status
Simulation time 45598141 ps
CPU time 0.86 seconds
Started Feb 07 05:03:47 PM PST 24
Finished Feb 07 05:03:48 PM PST 24
Peak memory 195864 kb
Host smart-7dde04cc-87b8-4227-97eb-c244f0f13029
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402196668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.402196668
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.9074013
Short name T297
Test name
Test status
Simulation time 202871684 ps
CPU time 0.99 seconds
Started Feb 07 05:03:53 PM PST 24
Finished Feb 07 05:03:55 PM PST 24
Peak memory 196260 kb
Host smart-cd95de1e-6d78-48d7-9369-31349382e4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9074013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.9074013
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.647690789
Short name T426
Test name
Test status
Simulation time 113925204 ps
CPU time 1.27 seconds
Started Feb 07 05:03:51 PM PST 24
Finished Feb 07 05:03:53 PM PST 24
Peak memory 196644 kb
Host smart-cbf73b13-b1f5-4e5b-b4f7-8a057cdb4233
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647690789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.647690789
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1287969093
Short name T761
Test name
Test status
Simulation time 372114607 ps
CPU time 3.19 seconds
Started Feb 07 05:03:46 PM PST 24
Finished Feb 07 05:03:49 PM PST 24
Peak memory 196812 kb
Host smart-24fede0c-1868-40eb-ba2c-c9fc44a6f0fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287969093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1287969093
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2391857384
Short name T489
Test name
Test status
Simulation time 24373891 ps
CPU time 1.05 seconds
Started Feb 07 05:03:54 PM PST 24
Finished Feb 07 05:03:57 PM PST 24
Peak memory 195724 kb
Host smart-f58c0f61-76ae-4d31-953d-6c8bc4ecf62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391857384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2391857384
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1899285319
Short name T422
Test name
Test status
Simulation time 43023552 ps
CPU time 0.95 seconds
Started Feb 07 05:03:48 PM PST 24
Finished Feb 07 05:03:49 PM PST 24
Peak memory 197132 kb
Host smart-cec4fda8-d641-4a25-b23c-8ebd28bb5de9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899285319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1899285319
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2797045300
Short name T432
Test name
Test status
Simulation time 93693706 ps
CPU time 1.6 seconds
Started Feb 07 05:03:49 PM PST 24
Finished Feb 07 05:03:52 PM PST 24
Peak memory 197768 kb
Host smart-e9469da7-8a99-40db-b5a3-d2b3b5da10f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797045300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2797045300
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3924601218
Short name T52
Test name
Test status
Simulation time 65724841 ps
CPU time 0.9 seconds
Started Feb 07 05:03:55 PM PST 24
Finished Feb 07 05:03:57 PM PST 24
Peak memory 213296 kb
Host smart-c3504246-b3e0-4f4d-a35d-8a4d245e4191
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924601218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3924601218
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1017975314
Short name T256
Test name
Test status
Simulation time 195900147 ps
CPU time 1.09 seconds
Started Feb 07 05:03:48 PM PST 24
Finished Feb 07 05:03:50 PM PST 24
Peak memory 196120 kb
Host smart-beb441a5-0f47-4a4a-b550-b611e8b6c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017975314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1017975314
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.534750973
Short name T300
Test name
Test status
Simulation time 109753426 ps
CPU time 0.97 seconds
Started Feb 07 05:03:49 PM PST 24
Finished Feb 07 05:03:51 PM PST 24
Peak memory 196056 kb
Host smart-6e640e76-1b92-4b31-a891-f144e9d6abc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534750973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.534750973
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2385045363
Short name T91
Test name
Test status
Simulation time 70004296629 ps
CPU time 197.96 seconds
Started Feb 07 05:03:44 PM PST 24
Finished Feb 07 05:07:03 PM PST 24
Peak memory 197924 kb
Host smart-03304191-b193-4fc7-8641-cef984a6f2c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385045363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2385045363
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1831822234
Short name T350
Test name
Test status
Simulation time 364427652123 ps
CPU time 1248.37 seconds
Started Feb 07 05:03:55 PM PST 24
Finished Feb 07 05:24:45 PM PST 24
Peak memory 198080 kb
Host smart-b9a6ea98-6f7d-49aa-a868-c29f7988fac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1831822234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1831822234
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.223888238
Short name T814
Test name
Test status
Simulation time 31019667 ps
CPU time 0.63 seconds
Started Feb 07 05:04:14 PM PST 24
Finished Feb 07 05:04:15 PM PST 24
Peak memory 193716 kb
Host smart-6d9ca98e-b198-4cdd-a7e3-68112a453a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223888238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.223888238
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2709858572
Short name T582
Test name
Test status
Simulation time 16197515 ps
CPU time 0.66 seconds
Started Feb 07 05:03:55 PM PST 24
Finished Feb 07 05:03:56 PM PST 24
Peak memory 193748 kb
Host smart-388db2dc-039c-4f2c-ac85-bc1c06807637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709858572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2709858572
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.748211105
Short name T574
Test name
Test status
Simulation time 264038818 ps
CPU time 14.74 seconds
Started Feb 07 05:03:59 PM PST 24
Finished Feb 07 05:04:14 PM PST 24
Peak memory 197724 kb
Host smart-06590b6d-c6f1-42ec-97cb-44004f332085
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748211105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.748211105
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1522353978
Short name T603
Test name
Test status
Simulation time 1381336297 ps
CPU time 1.04 seconds
Started Feb 07 05:03:55 PM PST 24
Finished Feb 07 05:03:58 PM PST 24
Peak memory 196888 kb
Host smart-2101d29f-89e7-472a-ad87-c568ed68b441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522353978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1522353978
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1430470296
Short name T235
Test name
Test status
Simulation time 130820324 ps
CPU time 1.08 seconds
Started Feb 07 05:03:58 PM PST 24
Finished Feb 07 05:04:00 PM PST 24
Peak memory 195780 kb
Host smart-a17fc628-3622-45f9-8176-4908a72f9162
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430470296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1430470296
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2217017532
Short name T548
Test name
Test status
Simulation time 742034742 ps
CPU time 2.99 seconds
Started Feb 07 05:03:54 PM PST 24
Finished Feb 07 05:03:59 PM PST 24
Peak memory 197736 kb
Host smart-cb9e378e-5ead-436a-89c6-0a7f59c7a1bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217017532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2217017532
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3015754485
Short name T583
Test name
Test status
Simulation time 116156327 ps
CPU time 2.89 seconds
Started Feb 07 05:03:56 PM PST 24
Finished Feb 07 05:04:00 PM PST 24
Peak memory 196688 kb
Host smart-60a7ae67-4c05-41ef-a14f-909c46847b9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015754485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3015754485
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.175612979
Short name T791
Test name
Test status
Simulation time 92920454 ps
CPU time 0.89 seconds
Started Feb 07 05:03:54 PM PST 24
Finished Feb 07 05:03:56 PM PST 24
Peak memory 196108 kb
Host smart-d5bfb86f-bffb-44c6-a76c-cd7ecf57e7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175612979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.175612979
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.747165592
Short name T609
Test name
Test status
Simulation time 518871695 ps
CPU time 1.03 seconds
Started Feb 07 05:03:55 PM PST 24
Finished Feb 07 05:03:57 PM PST 24
Peak memory 195728 kb
Host smart-534fec0f-373b-4527-932d-98478c9df57a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747165592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.747165592
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2646045613
Short name T423
Test name
Test status
Simulation time 298019938 ps
CPU time 2.94 seconds
Started Feb 07 05:03:58 PM PST 24
Finished Feb 07 05:04:01 PM PST 24
Peak memory 197700 kb
Host smart-0cea27ac-66dc-4db9-adcc-f951ec46137b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646045613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2646045613
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4254176013
Short name T22
Test name
Test status
Simulation time 59883952 ps
CPU time 0.93 seconds
Started Feb 07 05:04:09 PM PST 24
Finished Feb 07 05:04:10 PM PST 24
Peak memory 213356 kb
Host smart-f80b742b-a5ff-4fd6-becb-cd0d805520da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254176013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4254176013
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.632413624
Short name T377
Test name
Test status
Simulation time 36558567 ps
CPU time 0.9 seconds
Started Feb 07 05:03:54 PM PST 24
Finished Feb 07 05:03:56 PM PST 24
Peak memory 195124 kb
Host smart-dbaeb525-e741-40a9-b24c-083ad9d1f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632413624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.632413624
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2352303238
Short name T365
Test name
Test status
Simulation time 268203155 ps
CPU time 1.23 seconds
Started Feb 07 05:04:00 PM PST 24
Finished Feb 07 05:04:02 PM PST 24
Peak memory 195444 kb
Host smart-24296c68-121f-4846-a016-d33bef2e549e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352303238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2352303238
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.494051018
Short name T459
Test name
Test status
Simulation time 66897452105 ps
CPU time 210.51 seconds
Started Feb 07 05:04:02 PM PST 24
Finished Feb 07 05:07:32 PM PST 24
Peak memory 197916 kb
Host smart-29ed79cc-7697-4d6f-b005-8aaca61e2acc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494051018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.494051018
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.4240028145
Short name T621
Test name
Test status
Simulation time 260599937072 ps
CPU time 1898.46 seconds
Started Feb 07 05:03:59 PM PST 24
Finished Feb 07 05:35:38 PM PST 24
Peak memory 198052 kb
Host smart-92a856c3-5cad-4b6e-bc94-670d4753f33b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4240028145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.4240028145
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3625917688
Short name T652
Test name
Test status
Simulation time 15984738 ps
CPU time 0.59 seconds
Started Feb 07 05:04:56 PM PST 24
Finished Feb 07 05:04:58 PM PST 24
Peak memory 193992 kb
Host smart-d6785440-62cd-4f17-980c-df72c37f9d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625917688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3625917688
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2039090865
Short name T632
Test name
Test status
Simulation time 25789678 ps
CPU time 0.71 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 194280 kb
Host smart-0986661b-14fe-4cf9-8e29-8feec0e0cf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039090865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2039090865
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1732598696
Short name T562
Test name
Test status
Simulation time 3074789670 ps
CPU time 28.45 seconds
Started Feb 07 05:04:54 PM PST 24
Finished Feb 07 05:05:23 PM PST 24
Peak memory 196392 kb
Host smart-375c4fe0-7f06-430c-bea1-339f56b483d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732598696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1732598696
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.4178936134
Short name T634
Test name
Test status
Simulation time 69409492 ps
CPU time 0.8 seconds
Started Feb 07 05:04:56 PM PST 24
Finished Feb 07 05:04:57 PM PST 24
Peak memory 195292 kb
Host smart-8980be60-7048-4255-b96b-38cca16cb64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178936134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.4178936134
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1565999730
Short name T782
Test name
Test status
Simulation time 107025614 ps
CPU time 0.98 seconds
Started Feb 07 05:05:00 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 195828 kb
Host smart-aeb3de90-a5d2-4303-96fb-ceb18d184207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565999730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1565999730
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1315682128
Short name T447
Test name
Test status
Simulation time 107452620 ps
CPU time 2.34 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:05:03 PM PST 24
Peak memory 197872 kb
Host smart-6c20ce74-9b3d-414c-8063-d237e6730689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315682128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1315682128
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1397480886
Short name T567
Test name
Test status
Simulation time 33230721 ps
CPU time 0.74 seconds
Started Feb 07 05:04:58 PM PST 24
Finished Feb 07 05:04:59 PM PST 24
Peak memory 194088 kb
Host smart-1e446472-3612-41f2-8070-65d00da479bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397480886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1397480886
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2041533099
Short name T637
Test name
Test status
Simulation time 115565581 ps
CPU time 1.14 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 195664 kb
Host smart-3082cc7e-883f-440f-8118-959e540c9436
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041533099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2041533099
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3131966298
Short name T868
Test name
Test status
Simulation time 1820911722 ps
CPU time 2.36 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:05 PM PST 24
Peak memory 197788 kb
Host smart-3087b5f7-dc67-4689-b677-2ad37de5f3a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131966298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3131966298
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2069117235
Short name T407
Test name
Test status
Simulation time 173289180 ps
CPU time 1.68 seconds
Started Feb 07 05:05:20 PM PST 24
Finished Feb 07 05:05:23 PM PST 24
Peak memory 196408 kb
Host smart-f7721bf3-87a3-4c7c-8e0a-2b0fe6dd414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069117235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2069117235
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3310203879
Short name T278
Test name
Test status
Simulation time 45237197 ps
CPU time 1.25 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 196100 kb
Host smart-54643329-2176-4b72-a1d5-40f7bd6ce6fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310203879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3310203879
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.825886430
Short name T483
Test name
Test status
Simulation time 2958746855 ps
CPU time 37.56 seconds
Started Feb 07 05:04:57 PM PST 24
Finished Feb 07 05:05:36 PM PST 24
Peak memory 197920 kb
Host smart-4261ef90-c08e-44cf-9438-bdd4970ae32c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825886430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.825886430
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.608794164
Short name T330
Test name
Test status
Simulation time 57759896688 ps
CPU time 596.16 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:14:58 PM PST 24
Peak memory 197672 kb
Host smart-8e2a2fb5-ee21-4929-9a3a-3901ed83412f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=608794164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.608794164
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1413982087
Short name T552
Test name
Test status
Simulation time 47986998 ps
CPU time 0.61 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 193708 kb
Host smart-575e8bbb-9b2f-4598-bcf1-eb96d2ca23f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413982087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1413982087
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.253681477
Short name T58
Test name
Test status
Simulation time 446226013 ps
CPU time 0.82 seconds
Started Feb 07 05:05:04 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 195148 kb
Host smart-c37f16a9-4783-4798-9f3d-6f9da42c2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253681477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.253681477
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2313184548
Short name T615
Test name
Test status
Simulation time 1385145669 ps
CPU time 19.47 seconds
Started Feb 07 05:05:06 PM PST 24
Finished Feb 07 05:05:26 PM PST 24
Peak memory 196648 kb
Host smart-04106692-4837-40d9-a7bc-a5ffd7e153da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313184548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2313184548
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1945432087
Short name T601
Test name
Test status
Simulation time 22308470 ps
CPU time 0.65 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:05:01 PM PST 24
Peak memory 194200 kb
Host smart-39551819-bffd-44af-bd54-6049406dabba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945432087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1945432087
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3409110190
Short name T291
Test name
Test status
Simulation time 251960544 ps
CPU time 2.83 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 197672 kb
Host smart-41ba11a1-ab2e-41ab-bfe7-7f1cc4238fa8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409110190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3409110190
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1500271280
Short name T496
Test name
Test status
Simulation time 51580746 ps
CPU time 1.41 seconds
Started Feb 07 05:04:58 PM PST 24
Finished Feb 07 05:05:00 PM PST 24
Peak memory 197456 kb
Host smart-f969372a-2038-444e-b895-10e5bfddabfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500271280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1500271280
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4042325434
Short name T436
Test name
Test status
Simulation time 18949841 ps
CPU time 0.78 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:05:01 PM PST 24
Peak memory 195152 kb
Host smart-28a79383-ff19-4afc-9058-5f05d5400e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042325434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4042325434
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3514506041
Short name T409
Test name
Test status
Simulation time 31723609 ps
CPU time 0.75 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 194252 kb
Host smart-60132a65-cde1-4235-b244-ba9420004b4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514506041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3514506041
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1460237038
Short name T606
Test name
Test status
Simulation time 1228557328 ps
CPU time 5.11 seconds
Started Feb 07 05:04:58 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 197716 kb
Host smart-00188a59-6e5f-4ca8-afd7-fbd02d3ea040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460237038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1460237038
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1473070639
Short name T737
Test name
Test status
Simulation time 31912456 ps
CPU time 0.94 seconds
Started Feb 07 05:04:54 PM PST 24
Finished Feb 07 05:04:56 PM PST 24
Peak memory 195080 kb
Host smart-8028a1e0-c99a-4e20-b0e7-e28fabce611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473070639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1473070639
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.306780991
Short name T384
Test name
Test status
Simulation time 499013002 ps
CPU time 0.93 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:05:01 PM PST 24
Peak memory 196236 kb
Host smart-871b56f8-6a35-4a60-854c-eaa48a87027c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306780991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.306780991
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1838730745
Short name T689
Test name
Test status
Simulation time 56612233975 ps
CPU time 228.9 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:08:52 PM PST 24
Peak memory 197900 kb
Host smart-6835098e-cfb5-4ff2-b5e5-e52d21b21f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838730745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1838730745
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3159477433
Short name T744
Test name
Test status
Simulation time 168670496150 ps
CPU time 611.95 seconds
Started Feb 07 05:05:03 PM PST 24
Finished Feb 07 05:15:16 PM PST 24
Peak memory 197880 kb
Host smart-6ccadd2a-d4b3-4b6b-8b3a-d607e0fe9c3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3159477433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3159477433
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.777766300
Short name T564
Test name
Test status
Simulation time 13844780 ps
CPU time 0.62 seconds
Started Feb 07 05:05:04 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 194616 kb
Host smart-b0fecade-0084-46e9-a4ef-f90ffc09aa85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777766300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.777766300
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3886767514
Short name T551
Test name
Test status
Simulation time 88049660 ps
CPU time 0.79 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 194112 kb
Host smart-e337a779-f583-4ebd-9778-162f2954d015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886767514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3886767514
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3581541092
Short name T516
Test name
Test status
Simulation time 797987485 ps
CPU time 10.92 seconds
Started Feb 07 05:04:57 PM PST 24
Finished Feb 07 05:05:09 PM PST 24
Peak memory 196772 kb
Host smart-d3db02c6-0800-4791-b5e7-796e920d998b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581541092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3581541092
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2934956048
Short name T714
Test name
Test status
Simulation time 87166335 ps
CPU time 0.91 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 196628 kb
Host smart-8c3e760b-a074-490e-a056-205d99f32420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934956048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2934956048
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2879014266
Short name T619
Test name
Test status
Simulation time 107415898 ps
CPU time 1.18 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:03 PM PST 24
Peak memory 195712 kb
Host smart-ab5fb00c-3da5-4d43-8708-bba0c13d08de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879014266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2879014266
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2026326523
Short name T614
Test name
Test status
Simulation time 394335417 ps
CPU time 3.19 seconds
Started Feb 07 05:05:05 PM PST 24
Finished Feb 07 05:05:09 PM PST 24
Peak memory 196236 kb
Host smart-77d710f4-a864-437a-a262-3c706c57090f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026326523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2026326523
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1067394973
Short name T270
Test name
Test status
Simulation time 117959170 ps
CPU time 2.82 seconds
Started Feb 07 05:05:00 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 196628 kb
Host smart-210c44ff-6694-421a-b8ea-9c6c1ff75860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067394973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1067394973
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2729128961
Short name T464
Test name
Test status
Simulation time 81674346 ps
CPU time 1.08 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:03 PM PST 24
Peak memory 196552 kb
Host smart-df6ab2ad-9a51-471f-a0dc-e1ee704bc802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729128961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2729128961
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3519382928
Short name T757
Test name
Test status
Simulation time 357295477 ps
CPU time 1.39 seconds
Started Feb 07 05:05:04 PM PST 24
Finished Feb 07 05:05:07 PM PST 24
Peak memory 196736 kb
Host smart-ed53e053-ef8e-4e0a-84ec-6ef64ddcbfe3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519382928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3519382928
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2267240572
Short name T437
Test name
Test status
Simulation time 199775251 ps
CPU time 5.31 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:07 PM PST 24
Peak memory 197764 kb
Host smart-f1d3c8d0-dbfc-49a4-8677-ecf6c510491b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267240572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2267240572
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1141804669
Short name T532
Test name
Test status
Simulation time 45750382 ps
CPU time 0.99 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:03 PM PST 24
Peak memory 197016 kb
Host smart-f92e04fc-0d20-49d0-9730-bf3eb71fb907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141804669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1141804669
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2532843557
Short name T240
Test name
Test status
Simulation time 72043230 ps
CPU time 1.47 seconds
Started Feb 07 05:05:04 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 197796 kb
Host smart-f28a5fc6-7899-4400-86ee-9b6eb10d30ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532843557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2532843557
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4097417297
Short name T556
Test name
Test status
Simulation time 13361312976 ps
CPU time 189.91 seconds
Started Feb 07 05:05:04 PM PST 24
Finished Feb 07 05:08:15 PM PST 24
Peak memory 197912 kb
Host smart-94119a09-281f-441c-b597-f4ddff430e4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097417297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4097417297
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.555552505
Short name T484
Test name
Test status
Simulation time 983010667289 ps
CPU time 875.98 seconds
Started Feb 07 05:05:00 PM PST 24
Finished Feb 07 05:19:37 PM PST 24
Peak memory 206204 kb
Host smart-afb4f0e0-62ab-4b46-bc3e-a2e9c4a7e9c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=555552505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.555552505
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1910909842
Short name T525
Test name
Test status
Simulation time 25026090 ps
CPU time 0.61 seconds
Started Feb 07 05:05:04 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 193712 kb
Host smart-377e803e-d511-4926-9771-bda89984980a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910909842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1910909842
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.729422103
Short name T585
Test name
Test status
Simulation time 25480323 ps
CPU time 0.78 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:03 PM PST 24
Peak memory 193976 kb
Host smart-53dee72e-c5d0-4be0-8759-645308a3a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729422103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.729422103
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3502186249
Short name T667
Test name
Test status
Simulation time 95894657 ps
CPU time 4.61 seconds
Started Feb 07 05:04:58 PM PST 24
Finished Feb 07 05:05:03 PM PST 24
Peak memory 195728 kb
Host smart-6a7d340c-a6c0-40ce-9be3-911a53f75bc0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502186249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3502186249
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.326433599
Short name T375
Test name
Test status
Simulation time 177357093 ps
CPU time 0.86 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 195768 kb
Host smart-01b31f61-424a-4141-b5cd-9ce7673ba0a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326433599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.326433599
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4251375550
Short name T802
Test name
Test status
Simulation time 17561349 ps
CPU time 0.76 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 194888 kb
Host smart-650e07f3-11f4-4c17-a35e-e2ca5511e252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251375550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4251375550
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.4006451893
Short name T650
Test name
Test status
Simulation time 210420327 ps
CPU time 2.47 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 197788 kb
Host smart-e8e955cb-678e-4520-8610-fb4d373fdb39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006451893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.4006451893
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2810301562
Short name T529
Test name
Test status
Simulation time 157914569 ps
CPU time 2.86 seconds
Started Feb 07 05:05:03 PM PST 24
Finished Feb 07 05:05:08 PM PST 24
Peak memory 197816 kb
Host smart-fd315597-1092-485e-b4d5-8816868990bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810301562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2810301562
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1064357568
Short name T352
Test name
Test status
Simulation time 27234344 ps
CPU time 1.08 seconds
Started Feb 07 05:05:00 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 195692 kb
Host smart-35b3268b-0426-4844-a69f-3874aba19377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064357568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1064357568
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.927767128
Short name T725
Test name
Test status
Simulation time 71463699 ps
CPU time 0.9 seconds
Started Feb 07 05:05:05 PM PST 24
Finished Feb 07 05:05:07 PM PST 24
Peak memory 196460 kb
Host smart-52470902-d784-45a3-aab1-b37ebcec598f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927767128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.927767128
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1551492027
Short name T399
Test name
Test status
Simulation time 578553933 ps
CPU time 5.61 seconds
Started Feb 07 05:05:00 PM PST 24
Finished Feb 07 05:05:06 PM PST 24
Peak memory 197748 kb
Host smart-57fc9b48-76b4-4e51-bd1f-ff65dc1d6cbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551492027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1551492027
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1644100422
Short name T688
Test name
Test status
Simulation time 36172721 ps
CPU time 0.98 seconds
Started Feb 07 05:05:03 PM PST 24
Finished Feb 07 05:05:05 PM PST 24
Peak memory 196244 kb
Host smart-63fab21c-8c4d-49fd-86a1-aa05cde3b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644100422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1644100422
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3620028028
Short name T723
Test name
Test status
Simulation time 111852126 ps
CPU time 1.02 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 195128 kb
Host smart-1139f4df-74ad-4a33-94bd-4a02bdf859b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620028028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3620028028
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2834234144
Short name T870
Test name
Test status
Simulation time 7313605699 ps
CPU time 112.08 seconds
Started Feb 07 05:05:03 PM PST 24
Finished Feb 07 05:06:57 PM PST 24
Peak memory 197908 kb
Host smart-71427559-3202-4edd-b394-2d6c2ee9cc63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834234144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2834234144
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2789687412
Short name T753
Test name
Test status
Simulation time 27105630694 ps
CPU time 270.6 seconds
Started Feb 07 05:05:03 PM PST 24
Finished Feb 07 05:09:35 PM PST 24
Peak memory 198120 kb
Host smart-39e22641-df24-4c2d-8866-a1c1458b6e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2789687412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2789687412
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3797355307
Short name T834
Test name
Test status
Simulation time 12749120 ps
CPU time 0.59 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:13 PM PST 24
Peak memory 193668 kb
Host smart-4f02be43-0612-4f9f-97f0-675adbfafa58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797355307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3797355307
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3074890089
Short name T539
Test name
Test status
Simulation time 32162552 ps
CPU time 0.73 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 193960 kb
Host smart-8e751f40-093d-418e-821c-67f95f6ff9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074890089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3074890089
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1563493519
Short name T749
Test name
Test status
Simulation time 641303917 ps
CPU time 20.35 seconds
Started Feb 07 05:05:11 PM PST 24
Finished Feb 07 05:05:34 PM PST 24
Peak memory 197652 kb
Host smart-49ffc454-6fd1-44f7-a4e4-094f1c342cda
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563493519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1563493519
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1874510321
Short name T421
Test name
Test status
Simulation time 519295538 ps
CPU time 0.92 seconds
Started Feb 07 05:05:13 PM PST 24
Finished Feb 07 05:05:15 PM PST 24
Peak memory 196448 kb
Host smart-54d4e33b-af4b-4408-8bf5-254b1ecca553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874510321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1874510321
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1265560861
Short name T732
Test name
Test status
Simulation time 312544916 ps
CPU time 1.47 seconds
Started Feb 07 05:05:06 PM PST 24
Finished Feb 07 05:05:09 PM PST 24
Peak memory 197840 kb
Host smart-c9dd0729-9993-46d9-9304-7e114c43d730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265560861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1265560861
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.383310027
Short name T580
Test name
Test status
Simulation time 82297776 ps
CPU time 3.36 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:05:17 PM PST 24
Peak memory 197864 kb
Host smart-31436a53-89c9-4f21-a5ac-828a636ad72f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383310027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.383310027
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1572293603
Short name T510
Test name
Test status
Simulation time 1588309468 ps
CPU time 2.61 seconds
Started Feb 07 05:05:08 PM PST 24
Finished Feb 07 05:05:12 PM PST 24
Peak memory 196308 kb
Host smart-951c2cf9-4f09-442e-befa-dd816db89f8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572293603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1572293603
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3272139160
Short name T97
Test name
Test status
Simulation time 27515459 ps
CPU time 0.83 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 195324 kb
Host smart-ef2475c2-67e6-41ca-8a35-cc7839fe7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272139160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3272139160
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1920726280
Short name T613
Test name
Test status
Simulation time 96165097 ps
CPU time 1.18 seconds
Started Feb 07 05:05:12 PM PST 24
Finished Feb 07 05:05:15 PM PST 24
Peak memory 196876 kb
Host smart-71adccc6-8fe4-458c-a068-7864c6303c9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920726280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1920726280
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2144732227
Short name T502
Test name
Test status
Simulation time 343607026 ps
CPU time 6.21 seconds
Started Feb 07 05:05:08 PM PST 24
Finished Feb 07 05:05:18 PM PST 24
Peak memory 197788 kb
Host smart-12a83bdd-88f6-4f34-9d77-0bb3dcf3bd64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144732227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2144732227
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.133993391
Short name T249
Test name
Test status
Simulation time 136667128 ps
CPU time 1.23 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:05 PM PST 24
Peak memory 195456 kb
Host smart-b1dac9e6-e83c-4740-9c03-ea84661d5b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133993391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.133993391
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2453180395
Short name T260
Test name
Test status
Simulation time 211205052 ps
CPU time 1.05 seconds
Started Feb 07 05:05:02 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 196332 kb
Host smart-db3f9780-2152-4f0e-9ad2-64681e3eccbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453180395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2453180395
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1939814114
Short name T244
Test name
Test status
Simulation time 8222426566 ps
CPU time 92.46 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:06:45 PM PST 24
Peak memory 197788 kb
Host smart-c464bf5b-68af-46f5-a9a5-6d3843d29153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939814114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1939814114
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.603489414
Short name T568
Test name
Test status
Simulation time 64234273349 ps
CPU time 1604.73 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:31:58 PM PST 24
Peak memory 198060 kb
Host smart-240212c2-94c6-4e6c-9ffb-9ab9cdc61474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=603489414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.603489414
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1031203042
Short name T359
Test name
Test status
Simulation time 13425214 ps
CPU time 0.61 seconds
Started Feb 07 05:05:13 PM PST 24
Finished Feb 07 05:05:15 PM PST 24
Peak memory 194376 kb
Host smart-cd1f69d5-95f8-4b14-baac-f3747586aaea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031203042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1031203042
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1469024966
Short name T665
Test name
Test status
Simulation time 34424453 ps
CPU time 0.75 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 195072 kb
Host smart-6d5d57f4-3c6c-4280-ba8f-c9d81def1f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469024966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1469024966
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3426584058
Short name T586
Test name
Test status
Simulation time 535748869 ps
CPU time 17.29 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:31 PM PST 24
Peak memory 196968 kb
Host smart-91898ae8-e461-4ad0-935c-bec8d1ccbe8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426584058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3426584058
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.737638477
Short name T38
Test name
Test status
Simulation time 147900458 ps
CPU time 0.69 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 194440 kb
Host smart-376eb58d-bb34-4bfc-862a-871f68194b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737638477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.737638477
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.630612355
Short name T490
Test name
Test status
Simulation time 256196172 ps
CPU time 1.39 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:15 PM PST 24
Peak memory 196912 kb
Host smart-7f4f9c57-6429-4cd0-8ebd-b2747428e1f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630612355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.630612355
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3180217786
Short name T457
Test name
Test status
Simulation time 70587611 ps
CPU time 1.72 seconds
Started Feb 07 05:05:08 PM PST 24
Finished Feb 07 05:05:10 PM PST 24
Peak memory 196476 kb
Host smart-8133c3a4-3b97-40a8-b211-b7983d3e7df4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180217786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3180217786
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2564248066
Short name T498
Test name
Test status
Simulation time 479875205 ps
CPU time 1.94 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:05:15 PM PST 24
Peak memory 195800 kb
Host smart-a1dfa632-dd16-4005-8c49-9ae208edeeed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564248066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2564248066
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.99771314
Short name T387
Test name
Test status
Simulation time 97310695 ps
CPU time 1.25 seconds
Started Feb 07 05:05:15 PM PST 24
Finished Feb 07 05:05:18 PM PST 24
Peak memory 195892 kb
Host smart-3b901c49-b6c1-440f-b405-add05ee89eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99771314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.99771314
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3645306858
Short name T544
Test name
Test status
Simulation time 29650940 ps
CPU time 1.08 seconds
Started Feb 07 05:05:12 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 195552 kb
Host smart-5dcc8c82-75e9-4bb7-8435-c3405b4a04c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645306858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3645306858
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1133942888
Short name T503
Test name
Test status
Simulation time 101394260 ps
CPU time 4.97 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:18 PM PST 24
Peak memory 197704 kb
Host smart-f369a3f9-af42-4ae9-9336-3db5a3fa5102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133942888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1133942888
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2878630864
Short name T328
Test name
Test status
Simulation time 43272488 ps
CPU time 0.95 seconds
Started Feb 07 05:05:07 PM PST 24
Finished Feb 07 05:05:09 PM PST 24
Peak memory 195424 kb
Host smart-187329f7-640d-4414-85f7-a1884f10af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878630864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2878630864
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.866577154
Short name T801
Test name
Test status
Simulation time 442768422 ps
CPU time 1.16 seconds
Started Feb 07 05:05:07 PM PST 24
Finished Feb 07 05:05:09 PM PST 24
Peak memory 195596 kb
Host smart-1bef9046-ddc5-4fa2-9aea-70eb28bf6375
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866577154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.866577154
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3915712979
Short name T550
Test name
Test status
Simulation time 2467350362 ps
CPU time 72.76 seconds
Started Feb 07 05:05:13 PM PST 24
Finished Feb 07 05:06:27 PM PST 24
Peak memory 197964 kb
Host smart-c95d4e47-fc47-46cd-a8f1-512c5511e044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915712979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3915712979
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2390583137
Short name T374
Test name
Test status
Simulation time 94480576065 ps
CPU time 340.09 seconds
Started Feb 07 05:05:12 PM PST 24
Finished Feb 07 05:10:54 PM PST 24
Peak memory 198024 kb
Host smart-adcca86a-a79f-494e-8b6b-60c9b94b5c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2390583137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2390583137
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.244308138
Short name T446
Test name
Test status
Simulation time 12457547 ps
CPU time 0.57 seconds
Started Feb 07 05:05:19 PM PST 24
Finished Feb 07 05:05:20 PM PST 24
Peak memory 193724 kb
Host smart-799e2397-f868-4d8c-8e21-ad7ea23c8946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244308138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.244308138
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3979194985
Short name T807
Test name
Test status
Simulation time 20579279 ps
CPU time 0.67 seconds
Started Feb 07 05:05:15 PM PST 24
Finished Feb 07 05:05:17 PM PST 24
Peak memory 194592 kb
Host smart-027f2b33-65a2-4112-99d4-ef1ac62f24c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979194985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3979194985
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.169520621
Short name T764
Test name
Test status
Simulation time 298436974 ps
CPU time 13.08 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:26 PM PST 24
Peak memory 196860 kb
Host smart-cc2f1ec5-4f71-490f-89ab-582b3529d2eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169520621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.169520621
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2616238266
Short name T219
Test name
Test status
Simulation time 98276580 ps
CPU time 0.71 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 194188 kb
Host smart-9c16dd81-6217-4508-816b-7c69fd31947e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616238266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2616238266
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3424518268
Short name T724
Test name
Test status
Simulation time 201225990 ps
CPU time 1.16 seconds
Started Feb 07 05:05:09 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 195852 kb
Host smart-e8158494-449c-4cc7-ba2b-ad39007e2c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424518268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3424518268
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3448652987
Short name T641
Test name
Test status
Simulation time 26706797 ps
CPU time 1.2 seconds
Started Feb 07 05:05:07 PM PST 24
Finished Feb 07 05:05:09 PM PST 24
Peak memory 196152 kb
Host smart-48e6f856-042b-4722-b89b-eb15524fd5da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448652987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3448652987
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.750520063
Short name T358
Test name
Test status
Simulation time 85702574 ps
CPU time 2.01 seconds
Started Feb 07 05:05:07 PM PST 24
Finished Feb 07 05:05:10 PM PST 24
Peak memory 196720 kb
Host smart-24f91b17-946b-4c1e-b2c5-32b81de4a8d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750520063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
750520063
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2203852059
Short name T411
Test name
Test status
Simulation time 210303335 ps
CPU time 0.74 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 194720 kb
Host smart-12a563bc-cd7b-4e39-932d-70144e21b24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203852059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2203852059
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2782245741
Short name T28
Test name
Test status
Simulation time 33969695 ps
CPU time 0.99 seconds
Started Feb 07 05:05:15 PM PST 24
Finished Feb 07 05:05:17 PM PST 24
Peak memory 195712 kb
Host smart-cbf3f0d7-05b9-4c8a-939e-3454f0b82658
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782245741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2782245741
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2824473477
Short name T355
Test name
Test status
Simulation time 62858919 ps
CPU time 3.1 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:05:16 PM PST 24
Peak memory 197660 kb
Host smart-4bf9c53b-3c41-4cfe-a6c7-89903e3b2003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824473477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2824473477
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3466416861
Short name T805
Test name
Test status
Simulation time 35521329 ps
CPU time 0.92 seconds
Started Feb 07 05:05:10 PM PST 24
Finished Feb 07 05:05:14 PM PST 24
Peak memory 195244 kb
Host smart-5a389d64-669e-4fad-b2ba-5a68b7fa7f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466416861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3466416861
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3683714865
Short name T843
Test name
Test status
Simulation time 135209173 ps
CPU time 1.19 seconds
Started Feb 07 05:05:13 PM PST 24
Finished Feb 07 05:05:16 PM PST 24
Peak memory 195336 kb
Host smart-0f05fff4-c7e6-4970-b9de-e36ec6f3b1ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683714865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3683714865
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2939815654
Short name T311
Test name
Test status
Simulation time 6519565890 ps
CPU time 196.22 seconds
Started Feb 07 05:05:20 PM PST 24
Finished Feb 07 05:08:37 PM PST 24
Peak memory 197952 kb
Host smart-441ae51f-981e-4ab8-a650-c7b79ea6a32f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939815654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2939815654
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2763610891
Short name T660
Test name
Test status
Simulation time 223764580723 ps
CPU time 1653.35 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:33:01 PM PST 24
Peak memory 197988 kb
Host smart-92166355-b2c1-4620-b011-0ad71b88c554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2763610891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2763610891
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1999384199
Short name T743
Test name
Test status
Simulation time 20739788 ps
CPU time 0.59 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 193372 kb
Host smart-38b6bdf8-cf82-4443-a452-67c08da68108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999384199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1999384199
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3057349127
Short name T643
Test name
Test status
Simulation time 119070027 ps
CPU time 0.84 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 195060 kb
Host smart-f4251265-0bf3-4619-a31f-554084b72282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057349127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3057349127
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.489894130
Short name T845
Test name
Test status
Simulation time 2698020216 ps
CPU time 21.45 seconds
Started Feb 07 05:05:21 PM PST 24
Finished Feb 07 05:05:43 PM PST 24
Peak memory 197868 kb
Host smart-caf63902-dc24-4218-aee4-b9871ad1f462
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489894130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.489894130
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2512017439
Short name T228
Test name
Test status
Simulation time 46332601 ps
CPU time 0.87 seconds
Started Feb 07 05:05:22 PM PST 24
Finished Feb 07 05:05:23 PM PST 24
Peak memory 195816 kb
Host smart-f37a79fa-8f55-4ed2-8a83-937f26c17264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512017439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2512017439
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.874781466
Short name T747
Test name
Test status
Simulation time 360046394 ps
CPU time 1.6 seconds
Started Feb 07 05:05:21 PM PST 24
Finished Feb 07 05:05:24 PM PST 24
Peak memory 197040 kb
Host smart-1ebf961c-35a7-46ab-a2aa-359b8a9ba260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874781466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.874781466
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.866064069
Short name T477
Test name
Test status
Simulation time 295940359 ps
CPU time 3.34 seconds
Started Feb 07 05:05:21 PM PST 24
Finished Feb 07 05:05:25 PM PST 24
Peak memory 197812 kb
Host smart-6f7f893e-f4f5-44bf-912e-ecfaa79c407e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866064069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.866064069
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2742032276
Short name T321
Test name
Test status
Simulation time 715154548 ps
CPU time 2.89 seconds
Started Feb 07 05:05:25 PM PST 24
Finished Feb 07 05:05:30 PM PST 24
Peak memory 196672 kb
Host smart-c4efdbd8-eaec-4732-ae3d-3865ecf03dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742032276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2742032276
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.640128506
Short name T786
Test name
Test status
Simulation time 30979441 ps
CPU time 0.94 seconds
Started Feb 07 05:05:26 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 196112 kb
Host smart-3951011e-e82f-4261-95fa-4a5d4b19f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640128506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.640128506
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3870602169
Short name T702
Test name
Test status
Simulation time 27917762 ps
CPU time 0.88 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 195924 kb
Host smart-61cc1173-b831-46eb-84a1-a24d8811bea3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870602169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3870602169
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3193419798
Short name T308
Test name
Test status
Simulation time 774713370 ps
CPU time 5.21 seconds
Started Feb 07 05:05:18 PM PST 24
Finished Feb 07 05:05:24 PM PST 24
Peak memory 197584 kb
Host smart-6fc0f684-17ce-4fdf-9846-2236ae65f601
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193419798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3193419798
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1498258000
Short name T630
Test name
Test status
Simulation time 245878006 ps
CPU time 1.33 seconds
Started Feb 07 05:05:37 PM PST 24
Finished Feb 07 05:05:39 PM PST 24
Peak memory 196148 kb
Host smart-177fb098-8a6f-4d71-8a63-fe9b4f9d8f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498258000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1498258000
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1215747920
Short name T581
Test name
Test status
Simulation time 44549216 ps
CPU time 1.23 seconds
Started Feb 07 05:05:20 PM PST 24
Finished Feb 07 05:05:23 PM PST 24
Peak memory 196160 kb
Host smart-58b1d96d-4430-4bd7-9193-e6208ccf57b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215747920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1215747920
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1025651204
Short name T520
Test name
Test status
Simulation time 19359935748 ps
CPU time 233.14 seconds
Started Feb 07 05:05:20 PM PST 24
Finished Feb 07 05:09:14 PM PST 24
Peak memory 197904 kb
Host smart-72d89c95-3e24-4f1b-9fb5-4df17edb386d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025651204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1025651204
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1661605208
Short name T809
Test name
Test status
Simulation time 178519585403 ps
CPU time 912.4 seconds
Started Feb 07 05:05:19 PM PST 24
Finished Feb 07 05:20:32 PM PST 24
Peak memory 198032 kb
Host smart-004d6002-1ed6-4bbb-8916-de03bc4d6882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1661605208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1661605208
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3786934177
Short name T785
Test name
Test status
Simulation time 43852295 ps
CPU time 0.61 seconds
Started Feb 07 05:05:28 PM PST 24
Finished Feb 07 05:05:32 PM PST 24
Peak memory 193688 kb
Host smart-2b96ffe1-e8eb-4a0d-8961-06f123ddaa88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786934177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3786934177
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3790870584
Short name T883
Test name
Test status
Simulation time 19863943 ps
CPU time 0.74 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 193724 kb
Host smart-2d45e9e6-93f8-4d59-8d43-7d79c77ccbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790870584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3790870584
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2120533823
Short name T847
Test name
Test status
Simulation time 420760412 ps
CPU time 23.96 seconds
Started Feb 07 05:05:27 PM PST 24
Finished Feb 07 05:05:54 PM PST 24
Peak memory 196464 kb
Host smart-be1a773e-a15d-4157-96d3-78b288f7914d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120533823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2120533823
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1225242602
Short name T39
Test name
Test status
Simulation time 200806359 ps
CPU time 0.92 seconds
Started Feb 07 05:05:30 PM PST 24
Finished Feb 07 05:05:32 PM PST 24
Peak memory 197068 kb
Host smart-69aa3995-72c6-4a82-9fdb-5dff9049656e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225242602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1225242602
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1520117644
Short name T605
Test name
Test status
Simulation time 55186675 ps
CPU time 0.67 seconds
Started Feb 07 05:05:42 PM PST 24
Finished Feb 07 05:05:43 PM PST 24
Peak memory 194044 kb
Host smart-43440ef1-b20d-4236-9bef-050882ed6a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520117644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1520117644
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.815155344
Short name T563
Test name
Test status
Simulation time 90920179 ps
CPU time 3.92 seconds
Started Feb 07 05:05:25 PM PST 24
Finished Feb 07 05:05:31 PM PST 24
Peak memory 197760 kb
Host smart-3876a9a0-411d-4d55-bd13-5f1acbe29c9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815155344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.815155344
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3904721972
Short name T865
Test name
Test status
Simulation time 422715839 ps
CPU time 3.74 seconds
Started Feb 07 05:05:27 PM PST 24
Finished Feb 07 05:05:32 PM PST 24
Peak memory 197840 kb
Host smart-d017327b-5bda-47cc-a12d-a13f177ac875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904721972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3904721972
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.203932101
Short name T628
Test name
Test status
Simulation time 132935423 ps
CPU time 0.88 seconds
Started Feb 07 05:05:21 PM PST 24
Finished Feb 07 05:05:22 PM PST 24
Peak memory 195260 kb
Host smart-a6ade4b9-42fb-4eeb-88ce-49601697c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203932101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.203932101
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.426683058
Short name T861
Test name
Test status
Simulation time 91957552 ps
CPU time 1.12 seconds
Started Feb 07 05:05:20 PM PST 24
Finished Feb 07 05:05:22 PM PST 24
Peak memory 196296 kb
Host smart-7f03ea17-fa30-4730-9d61-185074a4a76e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426683058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.426683058
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.817487857
Short name T740
Test name
Test status
Simulation time 159033075 ps
CPU time 6.05 seconds
Started Feb 07 05:05:26 PM PST 24
Finished Feb 07 05:05:33 PM PST 24
Peak memory 197748 kb
Host smart-adb72d62-fd5c-4ce8-80e4-24e38f8cce51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817487857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.817487857
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.495380118
Short name T771
Test name
Test status
Simulation time 41222303 ps
CPU time 1.3 seconds
Started Feb 07 05:05:21 PM PST 24
Finished Feb 07 05:05:23 PM PST 24
Peak memory 195444 kb
Host smart-a0151ae2-356b-445a-b246-08cbb7620738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495380118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.495380118
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3460988647
Short name T792
Test name
Test status
Simulation time 49426829 ps
CPU time 1.45 seconds
Started Feb 07 05:05:24 PM PST 24
Finished Feb 07 05:05:29 PM PST 24
Peak memory 195224 kb
Host smart-a01f3c02-a516-4d7d-b775-5ac4ebf1159a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460988647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3460988647
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2888473489
Short name T779
Test name
Test status
Simulation time 4739417021 ps
CPU time 135.25 seconds
Started Feb 07 05:05:26 PM PST 24
Finished Feb 07 05:07:43 PM PST 24
Peak memory 197956 kb
Host smart-2f69f462-cb25-4d48-9ed0-beef55a35522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888473489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2888473489
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3114830634
Short name T797
Test name
Test status
Simulation time 223664799722 ps
CPU time 1674.57 seconds
Started Feb 07 05:05:26 PM PST 24
Finished Feb 07 05:33:22 PM PST 24
Peak memory 198096 kb
Host smart-ba091f36-5547-4b91-bbc3-ebc205ac85d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3114830634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3114830634
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1596141522
Short name T698
Test name
Test status
Simulation time 69918647 ps
CPU time 0.61 seconds
Started Feb 07 05:05:39 PM PST 24
Finished Feb 07 05:05:41 PM PST 24
Peak memory 193880 kb
Host smart-cf51df87-0230-41b5-af12-1a7b364df169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596141522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1596141522
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3842286650
Short name T678
Test name
Test status
Simulation time 70700352 ps
CPU time 0.7 seconds
Started Feb 07 05:05:27 PM PST 24
Finished Feb 07 05:05:29 PM PST 24
Peak memory 194640 kb
Host smart-37b6aea7-380a-4203-aedd-5e54a924fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842286650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3842286650
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4099109495
Short name T576
Test name
Test status
Simulation time 72858013 ps
CPU time 4.27 seconds
Started Feb 07 05:05:41 PM PST 24
Finished Feb 07 05:05:46 PM PST 24
Peak memory 195576 kb
Host smart-d7577397-b0cc-4d77-8b0a-6e0a88be391e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099109495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4099109495
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.614065982
Short name T508
Test name
Test status
Simulation time 102817375 ps
CPU time 1.11 seconds
Started Feb 07 05:05:40 PM PST 24
Finished Feb 07 05:05:42 PM PST 24
Peak memory 196216 kb
Host smart-eea9f6b3-f69d-45d5-8e6a-4b57f8f48986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614065982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.614065982
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3963480107
Short name T850
Test name
Test status
Simulation time 28567865 ps
CPU time 0.75 seconds
Started Feb 07 05:05:36 PM PST 24
Finished Feb 07 05:05:37 PM PST 24
Peak memory 194960 kb
Host smart-73e0ddea-223b-4ddb-936e-e612b405ebc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963480107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3963480107
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1845859913
Short name T412
Test name
Test status
Simulation time 54307801 ps
CPU time 2.46 seconds
Started Feb 07 05:05:41 PM PST 24
Finished Feb 07 05:05:44 PM PST 24
Peak memory 196044 kb
Host smart-c8bdf586-95c3-4679-9507-c09c00fe7eab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845859913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1845859913
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3993468145
Short name T587
Test name
Test status
Simulation time 598190208 ps
CPU time 3.03 seconds
Started Feb 07 05:05:36 PM PST 24
Finished Feb 07 05:05:40 PM PST 24
Peak memory 195592 kb
Host smart-e4aeae5e-609f-41b0-9532-667f338c1407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993468145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3993468145
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3148725677
Short name T318
Test name
Test status
Simulation time 328679654 ps
CPU time 1.44 seconds
Started Feb 07 05:05:27 PM PST 24
Finished Feb 07 05:05:30 PM PST 24
Peak memory 196376 kb
Host smart-284a3b61-96c9-4bde-9801-8de2e772c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148725677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3148725677
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2597313799
Short name T298
Test name
Test status
Simulation time 125320209 ps
CPU time 0.67 seconds
Started Feb 07 05:05:31 PM PST 24
Finished Feb 07 05:05:33 PM PST 24
Peak memory 194960 kb
Host smart-896e2646-a152-4023-a2db-d6ed0307f1db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597313799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2597313799
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4160947005
Short name T54
Test name
Test status
Simulation time 114500345 ps
CPU time 1.95 seconds
Started Feb 07 05:05:38 PM PST 24
Finished Feb 07 05:05:41 PM PST 24
Peak memory 197836 kb
Host smart-7010023d-dd8b-42a5-abf4-d8a2eb3999cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160947005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4160947005
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.387846693
Short name T467
Test name
Test status
Simulation time 169160309 ps
CPU time 0.86 seconds
Started Feb 07 05:05:26 PM PST 24
Finished Feb 07 05:05:28 PM PST 24
Peak memory 194996 kb
Host smart-df243993-da35-4175-af9b-acb68c3a9ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387846693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.387846693
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4100798347
Short name T854
Test name
Test status
Simulation time 222448849 ps
CPU time 1.18 seconds
Started Feb 07 05:05:28 PM PST 24
Finished Feb 07 05:05:32 PM PST 24
Peak memory 195340 kb
Host smart-74e2a904-5cc5-494c-a3fd-daacbe8d1109
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100798347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4100798347
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3220035318
Short name T848
Test name
Test status
Simulation time 7399210169 ps
CPU time 117.91 seconds
Started Feb 07 05:05:36 PM PST 24
Finished Feb 07 05:07:35 PM PST 24
Peak memory 197944 kb
Host smart-8506667e-8e5d-4668-8cbf-ba79826de7d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220035318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3220035318
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1695930951
Short name T577
Test name
Test status
Simulation time 135063430684 ps
CPU time 1720.2 seconds
Started Feb 07 05:05:40 PM PST 24
Finished Feb 07 05:34:21 PM PST 24
Peak memory 198076 kb
Host smart-b70e78d8-b41d-492b-9639-d6cb5118fee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1695930951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1695930951
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.590520019
Short name T390
Test name
Test status
Simulation time 30873861 ps
CPU time 0.63 seconds
Started Feb 07 05:04:12 PM PST 24
Finished Feb 07 05:04:13 PM PST 24
Peak memory 193924 kb
Host smart-d4ea5761-3c4a-49e3-bdfe-587568339336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590520019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.590520019
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3072214663
Short name T376
Test name
Test status
Simulation time 105380636 ps
CPU time 0.85 seconds
Started Feb 07 05:04:18 PM PST 24
Finished Feb 07 05:04:20 PM PST 24
Peak memory 195768 kb
Host smart-f14bafe1-5072-40a3-afb2-ca63351c79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072214663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3072214663
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3780173109
Short name T645
Test name
Test status
Simulation time 1974777865 ps
CPU time 16.45 seconds
Started Feb 07 05:04:11 PM PST 24
Finished Feb 07 05:04:28 PM PST 24
Peak memory 196964 kb
Host smart-d954cfd5-a62a-4517-a613-88bbc44c412f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780173109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3780173109
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4244694954
Short name T788
Test name
Test status
Simulation time 136139138 ps
CPU time 0.79 seconds
Started Feb 07 05:04:12 PM PST 24
Finished Feb 07 05:04:13 PM PST 24
Peak memory 195680 kb
Host smart-ab588b11-880d-40ad-b311-fa526168a3dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244694954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4244694954
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1701801537
Short name T420
Test name
Test status
Simulation time 263575737 ps
CPU time 1.3 seconds
Started Feb 07 05:04:13 PM PST 24
Finished Feb 07 05:04:14 PM PST 24
Peak memory 195612 kb
Host smart-e2480fb0-c143-4dc6-b6fa-964bf1da8c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701801537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1701801537
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.82456036
Short name T884
Test name
Test status
Simulation time 147468594 ps
CPU time 1.89 seconds
Started Feb 07 05:04:18 PM PST 24
Finished Feb 07 05:04:22 PM PST 24
Peak memory 197708 kb
Host smart-4498585d-e32b-40be-b58c-e16562b06195
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82456036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.gpio_intr_with_filter_rand_intr_event.82456036
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1281871803
Short name T397
Test name
Test status
Simulation time 225745947 ps
CPU time 1.36 seconds
Started Feb 07 05:04:13 PM PST 24
Finished Feb 07 05:04:15 PM PST 24
Peak memory 195584 kb
Host smart-120c6313-8c74-4917-9f96-b315ecdb4b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281871803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1281871803
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1413756262
Short name T857
Test name
Test status
Simulation time 63225598 ps
CPU time 1.42 seconds
Started Feb 07 05:04:12 PM PST 24
Finished Feb 07 05:04:14 PM PST 24
Peak memory 196856 kb
Host smart-75323c5f-cb7c-4805-9b63-04ae0b15d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413756262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1413756262
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2721556220
Short name T579
Test name
Test status
Simulation time 87947749 ps
CPU time 1.07 seconds
Started Feb 07 05:04:11 PM PST 24
Finished Feb 07 05:04:12 PM PST 24
Peak memory 195544 kb
Host smart-acfd1f69-e269-42d4-92d7-c23a5e6a524c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721556220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2721556220
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3405857711
Short name T482
Test name
Test status
Simulation time 782067671 ps
CPU time 5.48 seconds
Started Feb 07 05:04:13 PM PST 24
Finished Feb 07 05:04:19 PM PST 24
Peak memory 197784 kb
Host smart-e86ddd07-4b66-4ecd-8683-557086665245
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405857711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3405857711
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1168955780
Short name T23
Test name
Test status
Simulation time 76183522 ps
CPU time 0.87 seconds
Started Feb 07 05:04:13 PM PST 24
Finished Feb 07 05:04:14 PM PST 24
Peak memory 213376 kb
Host smart-fcab5bd3-0023-4454-8b3a-f60e43577a07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168955780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1168955780
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.623559990
Short name T242
Test name
Test status
Simulation time 38700480 ps
CPU time 1.2 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:04:18 PM PST 24
Peak memory 195620 kb
Host smart-3f12cd81-af17-4c53-89e3-85069766181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623559990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.623559990
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4141402228
Short name T494
Test name
Test status
Simulation time 112811136 ps
CPU time 1.19 seconds
Started Feb 07 05:04:22 PM PST 24
Finished Feb 07 05:04:26 PM PST 24
Peak memory 195516 kb
Host smart-41f4de22-3c14-41dd-9284-d6e9c8b24071
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141402228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4141402228
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1318079876
Short name T519
Test name
Test status
Simulation time 32208306882 ps
CPU time 208.31 seconds
Started Feb 07 05:04:21 PM PST 24
Finished Feb 07 05:07:53 PM PST 24
Peak memory 197924 kb
Host smart-609ef972-9c7e-4349-9a3a-88100b6c6cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318079876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1318079876
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1053257074
Short name T514
Test name
Test status
Simulation time 175831874503 ps
CPU time 349.67 seconds
Started Feb 07 05:04:09 PM PST 24
Finished Feb 07 05:09:59 PM PST 24
Peak memory 198008 kb
Host smart-257e983c-b46f-4432-a9a7-1e8a3039ae3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1053257074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1053257074
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4117818448
Short name T480
Test name
Test status
Simulation time 37002099 ps
CPU time 0.91 seconds
Started Feb 07 05:05:36 PM PST 24
Finished Feb 07 05:05:38 PM PST 24
Peak memory 195664 kb
Host smart-3630fa62-d80a-4343-b58a-fa7f1e25c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117818448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4117818448
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1983209582
Short name T254
Test name
Test status
Simulation time 279601147 ps
CPU time 14.57 seconds
Started Feb 07 05:05:36 PM PST 24
Finished Feb 07 05:05:52 PM PST 24
Peak memory 196776 kb
Host smart-133df3fc-23ca-4e1f-a916-ec616506b829
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983209582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1983209582
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1660302087
Short name T542
Test name
Test status
Simulation time 192370423 ps
CPU time 0.86 seconds
Started Feb 07 05:05:35 PM PST 24
Finished Feb 07 05:05:36 PM PST 24
Peak memory 195744 kb
Host smart-8b8f387a-3089-488a-8dae-2e250ba21740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660302087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1660302087
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1782035676
Short name T541
Test name
Test status
Simulation time 32843160 ps
CPU time 1.11 seconds
Started Feb 07 05:05:39 PM PST 24
Finished Feb 07 05:05:41 PM PST 24
Peak memory 196384 kb
Host smart-2870ac75-fa6a-49a2-9afa-a033aa371e00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782035676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1782035676
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3907769411
Short name T682
Test name
Test status
Simulation time 236234680 ps
CPU time 1.92 seconds
Started Feb 07 05:05:37 PM PST 24
Finished Feb 07 05:05:40 PM PST 24
Peak memory 197836 kb
Host smart-af26cdab-801a-4eb3-a6cd-cf408e7d90ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907769411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3907769411
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4006631079
Short name T518
Test name
Test status
Simulation time 64709090 ps
CPU time 0.98 seconds
Started Feb 07 05:05:38 PM PST 24
Finished Feb 07 05:05:40 PM PST 24
Peak memory 195380 kb
Host smart-2ac5b8ee-1f20-4bb2-9c00-5f433dfe53f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006631079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4006631079
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2740519815
Short name T647
Test name
Test status
Simulation time 153857504 ps
CPU time 1.12 seconds
Started Feb 07 05:05:35 PM PST 24
Finished Feb 07 05:05:37 PM PST 24
Peak memory 195660 kb
Host smart-43c05a84-c5ff-4a75-b9c9-c9cfb1cc69bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740519815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2740519815
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3938910476
Short name T241
Test name
Test status
Simulation time 56080532 ps
CPU time 1.26 seconds
Started Feb 07 05:05:37 PM PST 24
Finished Feb 07 05:05:39 PM PST 24
Peak memory 195836 kb
Host smart-9d4520e9-8d49-42f2-ba9c-29ea3b304235
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938910476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3938910476
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2360567132
Short name T284
Test name
Test status
Simulation time 137013360 ps
CPU time 1.8 seconds
Started Feb 07 05:05:37 PM PST 24
Finished Feb 07 05:05:39 PM PST 24
Peak memory 197708 kb
Host smart-802e6d50-4513-4ce4-be30-02bef398d66c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360567132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2360567132
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1220919040
Short name T662
Test name
Test status
Simulation time 89693724 ps
CPU time 1.45 seconds
Started Feb 07 05:05:35 PM PST 24
Finished Feb 07 05:05:37 PM PST 24
Peak memory 197784 kb
Host smart-4121225a-e68d-43bf-aa20-5e883dfc48e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220919040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1220919040
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3071548905
Short name T293
Test name
Test status
Simulation time 718262788 ps
CPU time 0.97 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:45 PM PST 24
Peak memory 196176 kb
Host smart-83622b11-c049-4ba3-99f7-3f023cf78b9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071548905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3071548905
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3927408883
Short name T403
Test name
Test status
Simulation time 1157311479 ps
CPU time 27.83 seconds
Started Feb 07 05:05:39 PM PST 24
Finished Feb 07 05:06:07 PM PST 24
Peak memory 197764 kb
Host smart-1829b39e-0aaf-4fcc-86ed-76e8be76153c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927408883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3927408883
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2403504934
Short name T672
Test name
Test status
Simulation time 229052702630 ps
CPU time 912.25 seconds
Started Feb 07 05:05:38 PM PST 24
Finished Feb 07 05:20:51 PM PST 24
Peak memory 206188 kb
Host smart-9f121fa3-65a9-4990-8b9f-2f6208f1adf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2403504934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2403504934
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.4124691259
Short name T804
Test name
Test status
Simulation time 12649001 ps
CPU time 0.61 seconds
Started Feb 07 05:05:46 PM PST 24
Finished Feb 07 05:05:48 PM PST 24
Peak memory 194412 kb
Host smart-721f5c10-47e2-4df8-bc12-27bcd063a97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124691259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.4124691259
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2565242914
Short name T454
Test name
Test status
Simulation time 26023696 ps
CPU time 0.64 seconds
Started Feb 07 05:05:35 PM PST 24
Finished Feb 07 05:05:36 PM PST 24
Peak memory 194532 kb
Host smart-68dabe6c-1995-4e67-a106-c2b4bccb4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565242914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2565242914
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3705220675
Short name T342
Test name
Test status
Simulation time 380671681 ps
CPU time 21.17 seconds
Started Feb 07 05:05:38 PM PST 24
Finished Feb 07 05:06:00 PM PST 24
Peak memory 197744 kb
Host smart-d3371b70-e94f-41e3-89dc-0cd7f131a7cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705220675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3705220675
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1681369506
Short name T875
Test name
Test status
Simulation time 207083404 ps
CPU time 1.07 seconds
Started Feb 07 05:05:53 PM PST 24
Finished Feb 07 05:05:54 PM PST 24
Peak memory 197504 kb
Host smart-0b18a969-588a-4c61-9281-9abd2a4e19a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681369506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1681369506
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2602315516
Short name T569
Test name
Test status
Simulation time 31202744 ps
CPU time 0.73 seconds
Started Feb 07 05:05:35 PM PST 24
Finished Feb 07 05:05:36 PM PST 24
Peak memory 194964 kb
Host smart-1715dfd2-4b82-4deb-bdce-be76103a484f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602315516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2602315516
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2687084799
Short name T558
Test name
Test status
Simulation time 51815445 ps
CPU time 2.19 seconds
Started Feb 07 05:05:39 PM PST 24
Finished Feb 07 05:05:42 PM PST 24
Peak memory 197824 kb
Host smart-e3203d6e-9512-4018-b1ea-5e8650dec3ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687084799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2687084799
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.715584655
Short name T419
Test name
Test status
Simulation time 63023951 ps
CPU time 1.54 seconds
Started Feb 07 05:05:36 PM PST 24
Finished Feb 07 05:05:38 PM PST 24
Peak memory 195652 kb
Host smart-005b75d0-fb35-4bf5-9e06-101698175690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715584655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
715584655
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1221550652
Short name T649
Test name
Test status
Simulation time 243107493 ps
CPU time 0.9 seconds
Started Feb 07 05:05:41 PM PST 24
Finished Feb 07 05:05:42 PM PST 24
Peak memory 196324 kb
Host smart-915a022f-19c5-4135-9e25-c98def0fad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221550652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1221550652
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.695473414
Short name T431
Test name
Test status
Simulation time 170036546 ps
CPU time 0.89 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:45 PM PST 24
Peak memory 197164 kb
Host smart-5c053c2d-b763-4bb3-815a-66f8bcb41a71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695473414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.695473414
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3471950739
Short name T224
Test name
Test status
Simulation time 611846434 ps
CPU time 4.32 seconds
Started Feb 07 05:05:47 PM PST 24
Finished Feb 07 05:05:51 PM PST 24
Peak memory 197740 kb
Host smart-19b37e5d-fe62-4e3b-b342-d0b9b98efb93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471950739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3471950739
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1218921664
Short name T846
Test name
Test status
Simulation time 33331092 ps
CPU time 1.07 seconds
Started Feb 07 05:05:42 PM PST 24
Finished Feb 07 05:05:44 PM PST 24
Peak memory 195480 kb
Host smart-4ca89049-22c4-492b-a1da-c48a313f05a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218921664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1218921664
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3480375757
Short name T237
Test name
Test status
Simulation time 205561752 ps
CPU time 1.02 seconds
Started Feb 07 05:05:39 PM PST 24
Finished Feb 07 05:05:41 PM PST 24
Peak memory 196100 kb
Host smart-ec0e7a93-0398-4f0d-9e41-8e814fbeb2ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480375757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3480375757
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3854712543
Short name T810
Test name
Test status
Simulation time 116734669660 ps
CPU time 160.75 seconds
Started Feb 07 05:05:44 PM PST 24
Finished Feb 07 05:08:26 PM PST 24
Peak memory 197996 kb
Host smart-51220cde-fe70-4276-afb3-8b96e23067ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854712543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3854712543
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2151525951
Short name T406
Test name
Test status
Simulation time 82134987541 ps
CPU time 655.33 seconds
Started Feb 07 05:05:51 PM PST 24
Finished Feb 07 05:16:47 PM PST 24
Peak memory 197984 kb
Host smart-3a7131d1-cf53-4e72-a346-26f36451cd6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2151525951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2151525951
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2147402347
Short name T279
Test name
Test status
Simulation time 13358939 ps
CPU time 0.58 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:44 PM PST 24
Peak memory 193744 kb
Host smart-b5e7b85d-2f31-4173-8dd5-aa43712e1e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147402347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2147402347
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3682310156
Short name T326
Test name
Test status
Simulation time 70146667 ps
CPU time 0.73 seconds
Started Feb 07 05:05:42 PM PST 24
Finished Feb 07 05:05:44 PM PST 24
Peak memory 195796 kb
Host smart-fb77c9db-de4c-42a3-a16d-cb982cc63202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682310156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3682310156
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2386722058
Short name T257
Test name
Test status
Simulation time 418665297 ps
CPU time 10.47 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:06:00 PM PST 24
Peak memory 195304 kb
Host smart-9d98decd-09cc-457c-a1b6-52372381debf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386722058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2386722058
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2998291297
Short name T372
Test name
Test status
Simulation time 326775406 ps
CPU time 1.15 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:45 PM PST 24
Peak memory 197648 kb
Host smart-83e48107-8f14-4d17-846a-bb485dfddba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998291297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2998291297
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1253772852
Short name T96
Test name
Test status
Simulation time 63567484 ps
CPU time 0.76 seconds
Started Feb 07 05:05:51 PM PST 24
Finished Feb 07 05:05:53 PM PST 24
Peak memory 194208 kb
Host smart-725d92aa-ae14-417b-baef-8ae6168272e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253772852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1253772852
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.256782750
Short name T686
Test name
Test status
Simulation time 135724821 ps
CPU time 3.1 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:47 PM PST 24
Peak memory 197880 kb
Host smart-1ad1951b-c26e-4c47-856d-af4711ac7468
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256782750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.256782750
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.265511621
Short name T855
Test name
Test status
Simulation time 510243893 ps
CPU time 3.06 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:05:52 PM PST 24
Peak memory 197048 kb
Host smart-af44844c-4328-402d-bd69-9b71a2a2e54e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265511621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
265511621
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.377497913
Short name T642
Test name
Test status
Simulation time 151946391 ps
CPU time 1.05 seconds
Started Feb 07 05:05:42 PM PST 24
Finished Feb 07 05:05:44 PM PST 24
Peak memory 195784 kb
Host smart-873bef87-5931-4e2d-8a8d-9a772b8c46ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377497913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.377497913
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3699037177
Short name T549
Test name
Test status
Simulation time 47773586 ps
CPU time 1.01 seconds
Started Feb 07 05:05:47 PM PST 24
Finished Feb 07 05:05:49 PM PST 24
Peak memory 195856 kb
Host smart-66e1e9bf-46e1-4ec3-958b-a1c513a25d01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699037177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3699037177
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2654467324
Short name T666
Test name
Test status
Simulation time 171206893 ps
CPU time 3.31 seconds
Started Feb 07 05:05:47 PM PST 24
Finished Feb 07 05:05:51 PM PST 24
Peak memory 197712 kb
Host smart-bb99482c-6723-40da-a38e-4eb439971e82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654467324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2654467324
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1362447339
Short name T264
Test name
Test status
Simulation time 60931330 ps
CPU time 0.67 seconds
Started Feb 07 05:05:50 PM PST 24
Finished Feb 07 05:05:52 PM PST 24
Peak memory 193844 kb
Host smart-370d0a4d-6a87-425b-8095-96af09d57b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362447339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1362447339
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3796000261
Short name T458
Test name
Test status
Simulation time 108978627 ps
CPU time 0.95 seconds
Started Feb 07 05:05:45 PM PST 24
Finished Feb 07 05:05:46 PM PST 24
Peak memory 195272 kb
Host smart-f77e776b-ffd9-4bd3-9af7-c6c44cd7eebf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796000261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3796000261
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.197299181
Short name T497
Test name
Test status
Simulation time 2056178585 ps
CPU time 27.15 seconds
Started Feb 07 05:05:49 PM PST 24
Finished Feb 07 05:06:17 PM PST 24
Peak memory 197844 kb
Host smart-6de1723e-8c92-43fe-8b0f-e80edda231f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197299181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.197299181
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.503021909
Short name T825
Test name
Test status
Simulation time 85426842621 ps
CPU time 1613.94 seconds
Started Feb 07 05:05:45 PM PST 24
Finished Feb 07 05:32:39 PM PST 24
Peak memory 198052 kb
Host smart-d4d82ad5-debc-4b44-8f98-ed5f35d38715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=503021909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.503021909
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3293577133
Short name T43
Test name
Test status
Simulation time 114500316 ps
CPU time 0.61 seconds
Started Feb 07 05:05:49 PM PST 24
Finished Feb 07 05:05:50 PM PST 24
Peak memory 194372 kb
Host smart-95f26646-8b89-403c-a9f2-77b2bc7da460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293577133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3293577133
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1497958763
Short name T427
Test name
Test status
Simulation time 107427609 ps
CPU time 0.84 seconds
Started Feb 07 05:05:49 PM PST 24
Finished Feb 07 05:05:50 PM PST 24
Peak memory 195192 kb
Host smart-f470d69d-0598-4bd5-8390-6053c50bb3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497958763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1497958763
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4145956479
Short name T842
Test name
Test status
Simulation time 562180550 ps
CPU time 19.95 seconds
Started Feb 07 05:05:49 PM PST 24
Finished Feb 07 05:06:09 PM PST 24
Peak memory 197768 kb
Host smart-8efe24d5-3831-4fbe-a95b-794f1774625e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145956479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4145956479
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2603555215
Short name T416
Test name
Test status
Simulation time 66436648 ps
CPU time 0.79 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:45 PM PST 24
Peak memory 195388 kb
Host smart-7ea3c43c-be82-4081-b7a7-ad996f6cb92a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603555215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2603555215
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3418234318
Short name T592
Test name
Test status
Simulation time 28690031 ps
CPU time 0.8 seconds
Started Feb 07 05:05:45 PM PST 24
Finished Feb 07 05:05:46 PM PST 24
Peak memory 194908 kb
Host smart-2088ec3f-9fc5-4d32-8843-a5e202687d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418234318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3418234318
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2507053343
Short name T319
Test name
Test status
Simulation time 177014549 ps
CPU time 2.44 seconds
Started Feb 07 05:05:44 PM PST 24
Finished Feb 07 05:05:47 PM PST 24
Peak memory 197872 kb
Host smart-03acf799-b7f7-46e9-8948-4f277a948b34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507053343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2507053343
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4049353117
Short name T430
Test name
Test status
Simulation time 32778782 ps
CPU time 0.99 seconds
Started Feb 07 05:05:44 PM PST 24
Finished Feb 07 05:05:45 PM PST 24
Peak memory 194780 kb
Host smart-b0689639-7a4a-41a6-88fe-610a6f9fd556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049353117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4049353117
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3674320065
Short name T44
Test name
Test status
Simulation time 122229969 ps
CPU time 1.45 seconds
Started Feb 07 05:05:49 PM PST 24
Finished Feb 07 05:05:51 PM PST 24
Peak memory 197780 kb
Host smart-452233dd-ca40-4d4f-a9b0-142b89733404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674320065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3674320065
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1632205864
Short name T232
Test name
Test status
Simulation time 29560544 ps
CPU time 1.07 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:05:50 PM PST 24
Peak memory 195716 kb
Host smart-39110ebe-75d9-42cc-a8a3-96a645feffe0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632205864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1632205864
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3790683329
Short name T664
Test name
Test status
Simulation time 1352960578 ps
CPU time 4.23 seconds
Started Feb 07 05:05:50 PM PST 24
Finished Feb 07 05:05:55 PM PST 24
Peak memory 197744 kb
Host smart-dd17c72e-7ab2-4f36-ae32-e07206f8cc86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790683329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3790683329
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2685058694
Short name T385
Test name
Test status
Simulation time 32296946 ps
CPU time 0.98 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:05:49 PM PST 24
Peak memory 196132 kb
Host smart-81d5da89-10c7-4c95-b37b-af7e1a239d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685058694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2685058694
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.704765089
Short name T640
Test name
Test status
Simulation time 118772097 ps
CPU time 1.22 seconds
Started Feb 07 05:05:46 PM PST 24
Finished Feb 07 05:05:48 PM PST 24
Peak memory 196964 kb
Host smart-ac7a7f54-1c60-4747-a520-5ad84f340354
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704765089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.704765089
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.601597025
Short name T512
Test name
Test status
Simulation time 6388685650 ps
CPU time 203.98 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:09:12 PM PST 24
Peak memory 197736 kb
Host smart-566c7ae2-12b8-432b-acc1-0030a54643b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601597025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.601597025
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1562270700
Short name T812
Test name
Test status
Simulation time 65699548690 ps
CPU time 92.97 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:07:21 PM PST 24
Peak memory 206320 kb
Host smart-27551fe1-fe5f-4e6d-a2ad-5350c7b9d0c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1562270700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1562270700
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3557438822
Short name T570
Test name
Test status
Simulation time 14904340 ps
CPU time 0.64 seconds
Started Feb 07 05:05:56 PM PST 24
Finished Feb 07 05:05:58 PM PST 24
Peak memory 193880 kb
Host smart-152c21ff-5e51-4b12-8041-51d3f8032e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557438822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3557438822
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.254192341
Short name T478
Test name
Test status
Simulation time 102415074 ps
CPU time 0.8 seconds
Started Feb 07 05:05:50 PM PST 24
Finished Feb 07 05:05:52 PM PST 24
Peak memory 195096 kb
Host smart-d38521a7-5592-493b-9ef9-a293eb4d14a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254192341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.254192341
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.419869358
Short name T789
Test name
Test status
Simulation time 439933058 ps
CPU time 23.82 seconds
Started Feb 07 05:05:53 PM PST 24
Finished Feb 07 05:06:17 PM PST 24
Peak memory 196776 kb
Host smart-1eb533fd-907c-4ab6-81c3-7b2e46a00335
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419869358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.419869358
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4110283568
Short name T775
Test name
Test status
Simulation time 62846990 ps
CPU time 1.11 seconds
Started Feb 07 05:05:53 PM PST 24
Finished Feb 07 05:05:55 PM PST 24
Peak memory 196432 kb
Host smart-f46c3c87-ca7f-4bf9-be8e-5f4af0455e69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110283568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4110283568
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3114090972
Short name T347
Test name
Test status
Simulation time 110190443 ps
CPU time 1.68 seconds
Started Feb 07 05:05:45 PM PST 24
Finished Feb 07 05:05:48 PM PST 24
Peak memory 196840 kb
Host smart-f5eb9911-ec5f-41f2-ae1f-6fc82ffd1752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114090972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3114090972
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2094071263
Short name T817
Test name
Test status
Simulation time 45916460 ps
CPU time 2.16 seconds
Started Feb 07 05:05:46 PM PST 24
Finished Feb 07 05:05:48 PM PST 24
Peak memory 196220 kb
Host smart-4a431043-f334-4c02-b98b-016bccf58043
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094071263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2094071263
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.413401319
Short name T595
Test name
Test status
Simulation time 489550969 ps
CPU time 2.62 seconds
Started Feb 07 05:05:43 PM PST 24
Finished Feb 07 05:05:46 PM PST 24
Peak memory 196776 kb
Host smart-8963f9e4-17c9-4b3e-9948-3b2e9dc1f2bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413401319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
413401319
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3379319154
Short name T722
Test name
Test status
Simulation time 58502061 ps
CPU time 1.33 seconds
Started Feb 07 05:05:50 PM PST 24
Finished Feb 07 05:05:52 PM PST 24
Peak memory 195528 kb
Host smart-405229e8-6c33-4f45-9413-c9770f60be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379319154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3379319154
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.206691915
Short name T831
Test name
Test status
Simulation time 227749934 ps
CPU time 1.28 seconds
Started Feb 07 05:05:47 PM PST 24
Finished Feb 07 05:05:49 PM PST 24
Peak memory 195608 kb
Host smart-22d5fb0b-a6e5-434f-a3e5-20aad332ebb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206691915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.206691915
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.14956585
Short name T309
Test name
Test status
Simulation time 120064803 ps
CPU time 5.92 seconds
Started Feb 07 05:05:54 PM PST 24
Finished Feb 07 05:06:01 PM PST 24
Peak memory 197812 kb
Host smart-dec6c65d-88fd-4921-9de4-f6922debe324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14956585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand
om_long_reg_writes_reg_reads.14956585
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1084727689
Short name T325
Test name
Test status
Simulation time 131657203 ps
CPU time 1.1 seconds
Started Feb 07 05:05:48 PM PST 24
Finished Feb 07 05:05:50 PM PST 24
Peak memory 195548 kb
Host smart-160c56f6-2aeb-43d6-ac94-a4b2cf951e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084727689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1084727689
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3199791472
Short name T517
Test name
Test status
Simulation time 142360998 ps
CPU time 1.33 seconds
Started Feb 07 05:05:47 PM PST 24
Finished Feb 07 05:05:50 PM PST 24
Peak memory 196344 kb
Host smart-fda705e8-553d-4680-847c-96d2e326d8d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199791472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3199791472
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.183953698
Short name T511
Test name
Test status
Simulation time 12246320822 ps
CPU time 134.43 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:08:13 PM PST 24
Peak memory 197896 kb
Host smart-e5e8f28c-a30b-418f-86f3-12c485c54b21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183953698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.183953698
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2007653534
Short name T393
Test name
Test status
Simulation time 14963117 ps
CPU time 0.59 seconds
Started Feb 07 05:05:53 PM PST 24
Finished Feb 07 05:05:54 PM PST 24
Peak memory 193724 kb
Host smart-03d85dac-6742-486d-8c91-d926bc94ad06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007653534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2007653534
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3262386076
Short name T363
Test name
Test status
Simulation time 45154346 ps
CPU time 0.78 seconds
Started Feb 07 05:05:51 PM PST 24
Finished Feb 07 05:05:53 PM PST 24
Peak memory 195840 kb
Host smart-111475da-f8a7-463f-a650-f0996dc1d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262386076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3262386076
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3422876376
Short name T835
Test name
Test status
Simulation time 1325878448 ps
CPU time 9.92 seconds
Started Feb 07 05:05:57 PM PST 24
Finished Feb 07 05:06:08 PM PST 24
Peak memory 195280 kb
Host smart-bbfc1375-31f9-4689-b0ef-b8c66ce38a1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422876376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3422876376
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1841394212
Short name T479
Test name
Test status
Simulation time 116217517 ps
CPU time 0.67 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:05:59 PM PST 24
Peak memory 194244 kb
Host smart-569481d7-ff83-40bf-9665-7301e18ad5ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841394212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1841394212
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2906601543
Short name T320
Test name
Test status
Simulation time 349869586 ps
CPU time 1.01 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:06:00 PM PST 24
Peak memory 197348 kb
Host smart-8bc35db1-4426-4d68-9f6d-b735bbd68f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906601543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2906601543
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.174690691
Short name T245
Test name
Test status
Simulation time 126029612 ps
CPU time 3.08 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:06:02 PM PST 24
Peak memory 197840 kb
Host smart-bd38214e-22e4-499d-a533-0a093a29166b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174690691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.174690691
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.13838464
Short name T878
Test name
Test status
Simulation time 120021019 ps
CPU time 1.86 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:06:03 PM PST 24
Peak memory 196432 kb
Host smart-61f236de-e439-43fc-b4ee-15af4af2c40f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13838464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.13838464
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1093743368
Short name T392
Test name
Test status
Simulation time 112970058 ps
CPU time 1.18 seconds
Started Feb 07 05:05:55 PM PST 24
Finished Feb 07 05:05:56 PM PST 24
Peak memory 196848 kb
Host smart-0dfd8eb4-42d0-4a8d-8024-050dfe28a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093743368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1093743368
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3003080765
Short name T774
Test name
Test status
Simulation time 28927789 ps
CPU time 0.76 seconds
Started Feb 07 05:05:59 PM PST 24
Finished Feb 07 05:06:01 PM PST 24
Peak memory 195188 kb
Host smart-1d016f34-6593-43bf-b551-2bb9c99c9421
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003080765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3003080765
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.89708165
Short name T557
Test name
Test status
Simulation time 690647906 ps
CPU time 6.48 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:06:08 PM PST 24
Peak memory 197784 kb
Host smart-fddcbcdd-d2ba-4cc1-a8e4-5f398a75d989
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89708165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand
om_long_reg_writes_reg_reads.89708165
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3116852867
Short name T862
Test name
Test status
Simulation time 87427394 ps
CPU time 1.31 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:06:00 PM PST 24
Peak memory 195564 kb
Host smart-fc639041-8e02-4746-8ced-c74b27b6a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116852867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3116852867
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2452246706
Short name T670
Test name
Test status
Simulation time 97329816 ps
CPU time 1.06 seconds
Started Feb 07 05:05:53 PM PST 24
Finished Feb 07 05:05:54 PM PST 24
Peak memory 196996 kb
Host smart-eff400bf-4cde-4778-8f8d-ff309efe22df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452246706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2452246706
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.4178024175
Short name T699
Test name
Test status
Simulation time 9177749709 ps
CPU time 71.79 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:07:13 PM PST 24
Peak memory 198012 kb
Host smart-86b6d69b-7022-40e1-b41a-1a421eac5de3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178024175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.4178024175
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1174727930
Short name T286
Test name
Test status
Simulation time 129795391451 ps
CPU time 1116.75 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:24:38 PM PST 24
Peak memory 198084 kb
Host smart-8e472f4c-aa77-4e8d-82a7-169946e87c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1174727930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1174727930
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.188069228
Short name T584
Test name
Test status
Simulation time 17087602 ps
CPU time 0.65 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:06:02 PM PST 24
Peak memory 193780 kb
Host smart-19908ee8-45a4-463b-a7b0-a978f473caa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188069228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.188069228
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1001520186
Short name T331
Test name
Test status
Simulation time 24157269 ps
CPU time 0.87 seconds
Started Feb 07 05:05:51 PM PST 24
Finished Feb 07 05:05:52 PM PST 24
Peak memory 195076 kb
Host smart-3f971821-e600-4495-902c-ad1d0348a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001520186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1001520186
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.897430801
Short name T381
Test name
Test status
Simulation time 3681382410 ps
CPU time 15.25 seconds
Started Feb 07 05:05:57 PM PST 24
Finished Feb 07 05:06:13 PM PST 24
Peak memory 196732 kb
Host smart-c9b36677-c702-43f2-b9c2-36e084611c0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897430801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.897430801
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.350443610
Short name T307
Test name
Test status
Simulation time 117196703 ps
CPU time 0.75 seconds
Started Feb 07 05:05:57 PM PST 24
Finished Feb 07 05:05:59 PM PST 24
Peak memory 194680 kb
Host smart-b012bf39-ba81-4610-9871-d335195dd1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350443610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.350443610
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3427657959
Short name T251
Test name
Test status
Simulation time 31123537 ps
CPU time 1.11 seconds
Started Feb 07 05:05:56 PM PST 24
Finished Feb 07 05:05:58 PM PST 24
Peak memory 196552 kb
Host smart-ae25f71a-56ca-46ba-b5dd-58fc9ea46e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427657959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3427657959
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2324349963
Short name T820
Test name
Test status
Simulation time 323966007 ps
CPU time 3.75 seconds
Started Feb 07 05:05:57 PM PST 24
Finished Feb 07 05:06:01 PM PST 24
Peak memory 197864 kb
Host smart-670fd208-477f-4fdc-8e0f-7aa9ee710248
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324349963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2324349963
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.424558574
Short name T755
Test name
Test status
Simulation time 167184976 ps
CPU time 3.13 seconds
Started Feb 07 05:05:57 PM PST 24
Finished Feb 07 05:06:01 PM PST 24
Peak memory 197100 kb
Host smart-8228af97-b0ee-4010-90b0-364fff8d0ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424558574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
424558574
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3903663961
Short name T681
Test name
Test status
Simulation time 33861362 ps
CPU time 1 seconds
Started Feb 07 05:05:59 PM PST 24
Finished Feb 07 05:06:00 PM PST 24
Peak memory 195728 kb
Host smart-42b633b2-2678-4340-a442-d8071ffab9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903663961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3903663961
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1295796620
Short name T324
Test name
Test status
Simulation time 22568304 ps
CPU time 0.85 seconds
Started Feb 07 05:05:56 PM PST 24
Finished Feb 07 05:05:57 PM PST 24
Peak memory 196404 kb
Host smart-9633c60b-f0e3-44e2-8f1d-6bc6ca1e2ae7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295796620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1295796620
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1172997101
Short name T830
Test name
Test status
Simulation time 226242953 ps
CPU time 3.41 seconds
Started Feb 07 05:05:53 PM PST 24
Finished Feb 07 05:05:56 PM PST 24
Peak memory 197788 kb
Host smart-10163bd9-bda9-4eea-a08c-e2c934f338e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172997101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1172997101
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1968293604
Short name T434
Test name
Test status
Simulation time 183097357 ps
CPU time 1.2 seconds
Started Feb 07 05:05:59 PM PST 24
Finished Feb 07 05:06:02 PM PST 24
Peak memory 195512 kb
Host smart-6907762e-7d69-4aa4-807e-49b165a91ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968293604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1968293604
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1100785997
Short name T572
Test name
Test status
Simulation time 28606437 ps
CPU time 0.9 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:05:59 PM PST 24
Peak memory 195108 kb
Host smart-0c9b6887-9589-4e94-8b1d-271d1776ed08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100785997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1100785997
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3867509409
Short name T730
Test name
Test status
Simulation time 3115578050 ps
CPU time 41.56 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:06:43 PM PST 24
Peak memory 197908 kb
Host smart-b628961f-faf8-4022-91ee-62952245cddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867509409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3867509409
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.565703324
Short name T294
Test name
Test status
Simulation time 63286364960 ps
CPU time 1695.89 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:34:17 PM PST 24
Peak memory 197920 kb
Host smart-8eb2d7c9-bdd6-44d3-ab52-9031175b0157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=565703324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.565703324
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3350592980
Short name T633
Test name
Test status
Simulation time 54489387 ps
CPU time 0.59 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:10 PM PST 24
Peak memory 194388 kb
Host smart-174c3eee-cd45-437f-a832-42ac9533f6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350592980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3350592980
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.772204239
Short name T268
Test name
Test status
Simulation time 41630843 ps
CPU time 0.74 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:10 PM PST 24
Peak memory 193940 kb
Host smart-c676fcef-f9e1-41de-bcd7-c16a605c62c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772204239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.772204239
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2239692273
Short name T463
Test name
Test status
Simulation time 414476120 ps
CPU time 12.13 seconds
Started Feb 07 05:05:59 PM PST 24
Finished Feb 07 05:06:12 PM PST 24
Peak memory 197804 kb
Host smart-b6da1d16-d0ff-445e-a3a4-90d09b4d96dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239692273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2239692273
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3196750072
Short name T553
Test name
Test status
Simulation time 125570994 ps
CPU time 1.03 seconds
Started Feb 07 05:06:08 PM PST 24
Finished Feb 07 05:06:10 PM PST 24
Peak memory 196956 kb
Host smart-a9e066c4-f050-4480-898d-444a8c29d878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196750072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3196750072
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2909988653
Short name T492
Test name
Test status
Simulation time 77889571 ps
CPU time 0.91 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:06:02 PM PST 24
Peak memory 196596 kb
Host smart-161863f2-ad50-4416-87ec-65cf938ed284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909988653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2909988653
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2726737660
Short name T354
Test name
Test status
Simulation time 21633368 ps
CPU time 1.09 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 195744 kb
Host smart-0f8910b0-0715-4f26-9d43-913e8577582a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726737660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2726737660
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1104560650
Short name T391
Test name
Test status
Simulation time 508703191 ps
CPU time 4.15 seconds
Started Feb 07 05:06:01 PM PST 24
Finished Feb 07 05:06:06 PM PST 24
Peak memory 196904 kb
Host smart-5e56c2f1-ba61-40b2-a6ba-14fd287fa9c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104560650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1104560650
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4291763139
Short name T312
Test name
Test status
Simulation time 82109597 ps
CPU time 1.46 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:12 PM PST 24
Peak memory 196728 kb
Host smart-ea54aaa4-a29d-4b32-a3bc-45f59cfef56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291763139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4291763139
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2872773430
Short name T231
Test name
Test status
Simulation time 183697559 ps
CPU time 1.39 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:12 PM PST 24
Peak memory 196912 kb
Host smart-8b2bbbff-4b16-4085-b25c-4815cfc9c3c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872773430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2872773430
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1395632746
Short name T301
Test name
Test status
Simulation time 1520090452 ps
CPU time 4.35 seconds
Started Feb 07 05:06:04 PM PST 24
Finished Feb 07 05:06:09 PM PST 24
Peak memory 197720 kb
Host smart-1ad94197-09d4-4860-8071-120fa294e0df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395632746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1395632746
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.476218963
Short name T543
Test name
Test status
Simulation time 60293571 ps
CPU time 1.29 seconds
Started Feb 07 05:05:58 PM PST 24
Finished Feb 07 05:06:00 PM PST 24
Peak memory 197840 kb
Host smart-26f88f26-3f71-466c-9b1b-c81b6ccac340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476218963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.476218963
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3092983558
Short name T272
Test name
Test status
Simulation time 107402517 ps
CPU time 1.11 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 195328 kb
Host smart-42486505-80a3-45ee-935b-16364c8787e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092983558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3092983558
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3740695447
Short name T711
Test name
Test status
Simulation time 31617387483 ps
CPU time 86.06 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 197868 kb
Host smart-f4fc0f3c-746e-4da3-8c1c-311116843920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740695447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3740695447
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1687597928
Short name T473
Test name
Test status
Simulation time 393418173365 ps
CPU time 1123.11 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:24:54 PM PST 24
Peak memory 198012 kb
Host smart-b329ea10-f7af-4279-94bc-1fc74735cefd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1687597928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1687597928
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1679754419
Short name T832
Test name
Test status
Simulation time 20770697 ps
CPU time 0.56 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 193752 kb
Host smart-8b1403a1-5bce-484b-9f74-f7149cd68360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679754419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1679754419
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1958144947
Short name T692
Test name
Test status
Simulation time 207101413 ps
CPU time 0.96 seconds
Started Feb 07 05:06:11 PM PST 24
Finished Feb 07 05:06:13 PM PST 24
Peak memory 196348 kb
Host smart-e34d4f80-35ef-4039-a477-0d8f095ecd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958144947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1958144947
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3933846273
Short name T608
Test name
Test status
Simulation time 3387683592 ps
CPU time 30.96 seconds
Started Feb 07 05:06:11 PM PST 24
Finished Feb 07 05:06:43 PM PST 24
Peak memory 196388 kb
Host smart-9f9c0584-4721-4710-a371-f0a7c4f6cbb3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933846273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3933846273
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.327189057
Short name T280
Test name
Test status
Simulation time 72915804 ps
CPU time 1.08 seconds
Started Feb 07 05:06:05 PM PST 24
Finished Feb 07 05:06:06 PM PST 24
Peak memory 197732 kb
Host smart-bed91732-0c88-4c0d-a4e1-00be2ae1a1a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327189057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.327189057
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1434410397
Short name T773
Test name
Test status
Simulation time 39141807 ps
CPU time 1.08 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 195628 kb
Host smart-78ffcb7e-bf0c-4506-bad4-ce905d7e5bb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434410397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1434410397
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4162739908
Short name T784
Test name
Test status
Simulation time 195514760 ps
CPU time 2.31 seconds
Started Feb 07 05:06:03 PM PST 24
Finished Feb 07 05:06:06 PM PST 24
Peak memory 197880 kb
Host smart-726999e6-b12c-47f1-b36e-327abba8559e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162739908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.4162739908
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2577953265
Short name T816
Test name
Test status
Simulation time 109715822 ps
CPU time 1.24 seconds
Started Feb 07 05:06:14 PM PST 24
Finished Feb 07 05:06:16 PM PST 24
Peak memory 196228 kb
Host smart-a169e64c-0225-4bee-8ba8-445b0d401ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577953265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2577953265
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3374741252
Short name T545
Test name
Test status
Simulation time 201631699 ps
CPU time 1.31 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:13 PM PST 24
Peak memory 196828 kb
Host smart-ac650725-22ad-4ee2-b890-0b13aa9985ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374741252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3374741252
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4048120213
Short name T867
Test name
Test status
Simulation time 27606163 ps
CPU time 0.83 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 195380 kb
Host smart-a5a2c484-f40b-4ebc-85b5-1e5d608ed951
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048120213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4048120213
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1989861726
Short name T310
Test name
Test status
Simulation time 300053140 ps
CPU time 5.44 seconds
Started Feb 07 05:06:08 PM PST 24
Finished Feb 07 05:06:15 PM PST 24
Peak memory 197704 kb
Host smart-3dff3eeb-a38f-413f-b0bd-34c090ecec0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989861726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1989861726
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1021711598
Short name T565
Test name
Test status
Simulation time 26706985 ps
CPU time 0.86 seconds
Started Feb 07 05:06:00 PM PST 24
Finished Feb 07 05:06:02 PM PST 24
Peak memory 195820 kb
Host smart-7651e256-ac72-420a-bd43-129eecbf055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021711598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1021711598
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2561213115
Short name T345
Test name
Test status
Simulation time 125274452 ps
CPU time 1.35 seconds
Started Feb 07 05:06:01 PM PST 24
Finished Feb 07 05:06:03 PM PST 24
Peak memory 196472 kb
Host smart-fc17e897-089e-4532-9be8-dcd9715926a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561213115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2561213115
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2486246525
Short name T367
Test name
Test status
Simulation time 16854465302 ps
CPU time 195.06 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:09:29 PM PST 24
Peak memory 197936 kb
Host smart-69ef391f-c4c9-4ccd-a7e9-094bb7dd644d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486246525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2486246525
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2482806903
Short name T371
Test name
Test status
Simulation time 81410167946 ps
CPU time 1973.55 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:39:08 PM PST 24
Peak memory 198040 kb
Host smart-3d8c815d-5e83-456c-99a8-dbb9bd7e5d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2482806903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2482806903
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1904399380
Short name T872
Test name
Test status
Simulation time 54249015 ps
CPU time 0.6 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 193928 kb
Host smart-9fddee89-6de9-4fbd-8b03-1727a62afcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904399380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1904399380
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1487835348
Short name T803
Test name
Test status
Simulation time 111741192 ps
CPU time 1.05 seconds
Started Feb 07 05:06:14 PM PST 24
Finished Feb 07 05:06:16 PM PST 24
Peak memory 195604 kb
Host smart-8b5ca208-5c06-4708-818a-0f10eee3b6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487835348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1487835348
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2286254585
Short name T607
Test name
Test status
Simulation time 552336352 ps
CPU time 17.99 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:29 PM PST 24
Peak memory 196112 kb
Host smart-32383706-2d9f-4e18-abb4-8a362bbfc8d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286254585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2286254585
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4106189506
Short name T349
Test name
Test status
Simulation time 267605720 ps
CPU time 1.14 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 196408 kb
Host smart-a6a1555f-eac3-45e0-8bec-fa935f4068a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106189506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4106189506
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1555464982
Short name T487
Test name
Test status
Simulation time 487788037 ps
CPU time 1.47 seconds
Started Feb 07 05:06:17 PM PST 24
Finished Feb 07 05:06:19 PM PST 24
Peak memory 196536 kb
Host smart-12077428-0abc-4843-876c-5069ac105d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555464982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1555464982
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3016139388
Short name T765
Test name
Test status
Simulation time 185939118 ps
CPU time 4.22 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:13 PM PST 24
Peak memory 197840 kb
Host smart-ebb2ee3c-eff6-43a2-9458-e09d89ccd06b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016139388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3016139388
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.318932747
Short name T221
Test name
Test status
Simulation time 204865577 ps
CPU time 1.84 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:13 PM PST 24
Peak memory 196328 kb
Host smart-df6e5dc6-4515-436a-b49e-737abda24a71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318932747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
318932747
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3646697257
Short name T495
Test name
Test status
Simulation time 68425588 ps
CPU time 1.31 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 196680 kb
Host smart-020c5a45-2c76-400d-ac93-94778be1ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646697257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3646697257
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.889186234
Short name T849
Test name
Test status
Simulation time 60167395 ps
CPU time 0.69 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:13 PM PST 24
Peak memory 194128 kb
Host smart-72bae498-f82d-4ff8-9dca-91d9ade39111
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889186234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.889186234
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2541674822
Short name T627
Test name
Test status
Simulation time 110048973 ps
CPU time 5.91 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:19 PM PST 24
Peak memory 197772 kb
Host smart-d0af53b0-55a0-46e2-9694-e1050df1a0e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541674822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2541674822
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.939407455
Short name T766
Test name
Test status
Simulation time 82427287 ps
CPU time 1.03 seconds
Started Feb 07 05:06:17 PM PST 24
Finished Feb 07 05:06:18 PM PST 24
Peak memory 195476 kb
Host smart-0baa099e-009b-4669-b6fa-b06b529b7642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939407455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.939407455
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2657937037
Short name T625
Test name
Test status
Simulation time 50467881 ps
CPU time 0.85 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:12 PM PST 24
Peak memory 194968 kb
Host smart-82b9a243-dbd1-4e08-ab60-02ea719ed4c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657937037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2657937037
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.299051839
Short name T252
Test name
Test status
Simulation time 5189506628 ps
CPU time 82.51 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:07:33 PM PST 24
Peak memory 197920 kb
Host smart-cb1f2683-ede7-4e15-8ef0-0e1b2d249c32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299051839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.299051839
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.4210809904
Short name T59
Test name
Test status
Simulation time 30350762626 ps
CPU time 555.64 seconds
Started Feb 07 05:06:17 PM PST 24
Finished Feb 07 05:15:33 PM PST 24
Peak memory 197976 kb
Host smart-7cbc0976-4581-4991-8311-8e2a3d2c70ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4210809904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.4210809904
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1946803376
Short name T285
Test name
Test status
Simulation time 140435203 ps
CPU time 0.64 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:04:17 PM PST 24
Peak memory 194348 kb
Host smart-01d2d618-c5a8-4318-90fd-05f0384229a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946803376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1946803376
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1754140582
Short name T781
Test name
Test status
Simulation time 25220944 ps
CPU time 0.65 seconds
Started Feb 07 05:04:08 PM PST 24
Finished Feb 07 05:04:09 PM PST 24
Peak memory 194568 kb
Host smart-bd2a9486-511b-4cdd-8ff9-86ba2eba67c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754140582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1754140582
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.596001484
Short name T239
Test name
Test status
Simulation time 91927441 ps
CPU time 4.87 seconds
Started Feb 07 05:04:10 PM PST 24
Finished Feb 07 05:04:15 PM PST 24
Peak memory 195916 kb
Host smart-461e4f23-412a-4479-b0a8-444030b1a293
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596001484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.596001484
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3601798922
Short name T258
Test name
Test status
Simulation time 36323929 ps
CPU time 0.81 seconds
Started Feb 07 05:04:25 PM PST 24
Finished Feb 07 05:04:27 PM PST 24
Peak memory 195440 kb
Host smart-c15da267-6601-4923-938e-c60882f5c142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601798922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3601798922
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.544937447
Short name T481
Test name
Test status
Simulation time 55503743 ps
CPU time 1.38 seconds
Started Feb 07 05:04:12 PM PST 24
Finished Feb 07 05:04:14 PM PST 24
Peak memory 196716 kb
Host smart-8602ace2-9d23-4549-b323-4a6f24190ae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544937447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.544937447
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2759844796
Short name T752
Test name
Test status
Simulation time 46986927 ps
CPU time 1.91 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:04:18 PM PST 24
Peak memory 197844 kb
Host smart-7668aa1d-3fd3-4fc3-9778-f0f7874e8874
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759844796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2759844796
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2135901792
Short name T864
Test name
Test status
Simulation time 104922145 ps
CPU time 2.79 seconds
Started Feb 07 05:04:14 PM PST 24
Finished Feb 07 05:04:18 PM PST 24
Peak memory 197840 kb
Host smart-a3cad432-9f69-4c5e-a854-b18d388f4c30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135901792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2135901792
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.192848816
Short name T351
Test name
Test status
Simulation time 232966602 ps
CPU time 1.25 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:04:17 PM PST 24
Peak memory 195544 kb
Host smart-9b63bd94-a6eb-42a2-9cef-351616de0be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192848816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.192848816
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.529644588
Short name T451
Test name
Test status
Simulation time 22442444 ps
CPU time 0.95 seconds
Started Feb 07 05:04:11 PM PST 24
Finished Feb 07 05:04:12 PM PST 24
Peak memory 195612 kb
Host smart-1eac7a84-dcfd-4196-a21d-0a379cd3e84f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529644588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.529644588
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3459089143
Short name T515
Test name
Test status
Simulation time 192753326 ps
CPU time 5 seconds
Started Feb 07 05:04:18 PM PST 24
Finished Feb 07 05:04:25 PM PST 24
Peak memory 197700 kb
Host smart-d49c9dc7-7caa-438b-b51d-44f80590acf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459089143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3459089143
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2207001579
Short name T53
Test name
Test status
Simulation time 215287623 ps
CPU time 0.85 seconds
Started Feb 07 05:04:25 PM PST 24
Finished Feb 07 05:04:27 PM PST 24
Peak memory 213180 kb
Host smart-a25df076-c84d-4267-8569-8f245c75b518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207001579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2207001579
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2396181204
Short name T526
Test name
Test status
Simulation time 140135466 ps
CPU time 1.37 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:04:19 PM PST 24
Peak memory 195264 kb
Host smart-cbc2af4e-f9f5-476e-8c64-979e856fcf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396181204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2396181204
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3313880275
Short name T276
Test name
Test status
Simulation time 140694167 ps
CPU time 0.99 seconds
Started Feb 07 05:04:09 PM PST 24
Finished Feb 07 05:04:11 PM PST 24
Peak memory 195940 kb
Host smart-79460253-51aa-4522-afed-e4cb8c3ee081
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313880275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3313880275
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2880983234
Short name T441
Test name
Test status
Simulation time 59047804255 ps
CPU time 166.01 seconds
Started Feb 07 05:04:15 PM PST 24
Finished Feb 07 05:07:02 PM PST 24
Peak memory 197808 kb
Host smart-689613bc-34ce-4855-8510-1e95b15b6627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880983234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2880983234
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2853699980
Short name T736
Test name
Test status
Simulation time 52761551817 ps
CPU time 782.58 seconds
Started Feb 07 05:04:21 PM PST 24
Finished Feb 07 05:17:27 PM PST 24
Peak memory 198060 kb
Host smart-ac8a2d58-0f1b-482e-b626-a5c21faab432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2853699980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2853699980
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2344322543
Short name T701
Test name
Test status
Simulation time 47418406 ps
CPU time 0.6 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 193676 kb
Host smart-3a8c25af-ed0e-4bf1-aabb-a8664acc0a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344322543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2344322543
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2111196139
Short name T216
Test name
Test status
Simulation time 51632899 ps
CPU time 0.76 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:12 PM PST 24
Peak memory 194036 kb
Host smart-f04ecf8a-7c26-4eb8-8791-2230a5cdfb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111196139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2111196139
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2509766631
Short name T522
Test name
Test status
Simulation time 480781904 ps
CPU time 13.6 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:06:27 PM PST 24
Peak memory 196820 kb
Host smart-14a3bab8-d82b-4427-bad4-c6eb456c9d59
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509766631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2509766631
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.280623420
Short name T383
Test name
Test status
Simulation time 224133120 ps
CPU time 0.98 seconds
Started Feb 07 05:06:14 PM PST 24
Finished Feb 07 05:06:16 PM PST 24
Peak memory 195836 kb
Host smart-3eca74f0-52bb-4c76-9f12-67f9e9515f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280623420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.280623420
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2811181796
Short name T618
Test name
Test status
Simulation time 213975362 ps
CPU time 1.09 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:12 PM PST 24
Peak memory 195740 kb
Host smart-36fc641e-0836-4519-b296-0714191079f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811181796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2811181796
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2081606560
Short name T836
Test name
Test status
Simulation time 75853657 ps
CPU time 3.22 seconds
Started Feb 07 05:06:10 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 197028 kb
Host smart-8863b8d8-ae4d-4883-8142-7aaa5b616a12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081606560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2081606560
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2791166358
Short name T507
Test name
Test status
Simulation time 120114330 ps
CPU time 0.96 seconds
Started Feb 07 05:06:09 PM PST 24
Finished Feb 07 05:06:11 PM PST 24
Peak memory 194236 kb
Host smart-13c04e30-dd47-4ba1-a761-9a225a93633e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791166358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2791166358
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2861259390
Short name T767
Test name
Test status
Simulation time 59356416 ps
CPU time 1.15 seconds
Started Feb 07 05:06:14 PM PST 24
Finished Feb 07 05:06:16 PM PST 24
Peak memory 195728 kb
Host smart-55ab0d67-91be-477e-9e3b-2fffef34e90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861259390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2861259390
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2746036558
Short name T274
Test name
Test status
Simulation time 30715368 ps
CPU time 1.2 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 195768 kb
Host smart-bd4cab7c-5724-4468-9d24-054424f94579
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746036558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2746036558
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.295609781
Short name T292
Test name
Test status
Simulation time 274859076 ps
CPU time 3.26 seconds
Started Feb 07 05:06:14 PM PST 24
Finished Feb 07 05:06:18 PM PST 24
Peak memory 197672 kb
Host smart-f60c0910-4720-405e-831f-56fae35498c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295609781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.295609781
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2301646874
Short name T450
Test name
Test status
Simulation time 167689580 ps
CPU time 1.1 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 196136 kb
Host smart-3c24b089-aa82-4676-9aca-39c33b3c00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301646874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2301646874
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1589543202
Short name T440
Test name
Test status
Simulation time 109563900 ps
CPU time 0.96 seconds
Started Feb 07 05:06:17 PM PST 24
Finished Feb 07 05:06:18 PM PST 24
Peak memory 196008 kb
Host smart-38c0be0d-80e9-4ea3-8f27-60f068595c34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589543202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1589543202
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2888403895
Short name T602
Test name
Test status
Simulation time 18787864968 ps
CPU time 211.79 seconds
Started Feb 07 05:06:11 PM PST 24
Finished Feb 07 05:09:44 PM PST 24
Peak memory 197864 kb
Host smart-03f22314-036d-4b79-9243-39b30e504247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888403895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2888403895
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1529530451
Short name T366
Test name
Test status
Simulation time 333170201883 ps
CPU time 1962.73 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:38:57 PM PST 24
Peak memory 198024 kb
Host smart-fcc81a57-de4e-4448-9062-98daa66e5a03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1529530451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1529530451
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3931844286
Short name T523
Test name
Test status
Simulation time 46598122 ps
CPU time 0.6 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:29 PM PST 24
Peak memory 193704 kb
Host smart-112f9d9f-9ae1-42c7-87e8-4bd37f6fd152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931844286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3931844286
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.523768925
Short name T827
Test name
Test status
Simulation time 59332874 ps
CPU time 0.77 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 195884 kb
Host smart-9b0a0cc1-cc4b-41b2-8865-acc6b0dacfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523768925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.523768925
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2703173978
Short name T651
Test name
Test status
Simulation time 643957086 ps
CPU time 4.89 seconds
Started Feb 07 05:06:20 PM PST 24
Finished Feb 07 05:06:26 PM PST 24
Peak memory 195692 kb
Host smart-360574bc-32c2-48a5-b01c-3e3226b433af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703173978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2703173978
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2011028461
Short name T452
Test name
Test status
Simulation time 48833863 ps
CPU time 0.76 seconds
Started Feb 07 05:06:21 PM PST 24
Finished Feb 07 05:06:23 PM PST 24
Peak memory 195576 kb
Host smart-11c2e300-caa3-4424-972f-9f69b36b94dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011028461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2011028461
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4189651501
Short name T748
Test name
Test status
Simulation time 100502118 ps
CPU time 1.44 seconds
Started Feb 07 05:06:26 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 196800 kb
Host smart-c79cc816-4283-434f-9b08-6d41e9de79a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189651501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4189651501
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3853468581
Short name T287
Test name
Test status
Simulation time 264579888 ps
CPU time 2.96 seconds
Started Feb 07 05:06:19 PM PST 24
Finished Feb 07 05:06:23 PM PST 24
Peak memory 197876 kb
Host smart-dc8099f6-c232-41d0-a2ce-b14ab17f01ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853468581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3853468581
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3442456272
Short name T694
Test name
Test status
Simulation time 222955802 ps
CPU time 1.92 seconds
Started Feb 07 05:06:21 PM PST 24
Finished Feb 07 05:06:24 PM PST 24
Peak memory 196252 kb
Host smart-44a09871-ac25-492d-8b7c-d4f3bba1a07f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442456272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3442456272
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4007277250
Short name T438
Test name
Test status
Simulation time 20807675 ps
CPU time 0.87 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:06:15 PM PST 24
Peak memory 196456 kb
Host smart-46c92289-5b88-4880-bdc0-5944d1d3adf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007277250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4007277250
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3524608675
Short name T659
Test name
Test status
Simulation time 62009295 ps
CPU time 1.27 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 195644 kb
Host smart-17720346-a703-4b0b-9a4a-c6b5402002f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524608675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3524608675
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2055849082
Short name T594
Test name
Test status
Simulation time 194002164 ps
CPU time 5.01 seconds
Started Feb 07 05:06:23 PM PST 24
Finished Feb 07 05:06:33 PM PST 24
Peak memory 197768 kb
Host smart-6c06c318-7756-4781-b992-d9957c9a0d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055849082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2055849082
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4200133865
Short name T671
Test name
Test status
Simulation time 51742049 ps
CPU time 1.59 seconds
Started Feb 07 05:06:13 PM PST 24
Finished Feb 07 05:06:15 PM PST 24
Peak memory 196576 kb
Host smart-7056038b-4215-4b9f-8e48-8a75d9d02bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200133865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4200133865
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2781714138
Short name T386
Test name
Test status
Simulation time 103110182 ps
CPU time 1.45 seconds
Started Feb 07 05:06:12 PM PST 24
Finished Feb 07 05:06:14 PM PST 24
Peak memory 196608 kb
Host smart-939b366a-cdbb-479d-8180-9ceffa4fb193
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781714138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2781714138
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.4134070959
Short name T504
Test name
Test status
Simulation time 10125628442 ps
CPU time 139.66 seconds
Started Feb 07 05:06:20 PM PST 24
Finished Feb 07 05:08:40 PM PST 24
Peak memory 197940 kb
Host smart-282d0429-d25a-4d22-9fb2-8631ff29786f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134070959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.4134070959
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.864039799
Short name T881
Test name
Test status
Simulation time 86220193321 ps
CPU time 591.61 seconds
Started Feb 07 05:06:25 PM PST 24
Finished Feb 07 05:16:20 PM PST 24
Peak memory 198072 kb
Host smart-8a747483-fdec-4ed7-8521-e97974c14b69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=864039799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.864039799
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1614897221
Short name T394
Test name
Test status
Simulation time 20940737 ps
CPU time 0.58 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 194360 kb
Host smart-adbbdd4b-0bf6-4a77-86d8-1095ae5fcd7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614897221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1614897221
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2337997746
Short name T344
Test name
Test status
Simulation time 29276961 ps
CPU time 0.89 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195080 kb
Host smart-cde0333a-9976-460c-967a-8bcc2299ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337997746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2337997746
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2225698345
Short name T882
Test name
Test status
Simulation time 1723074239 ps
CPU time 13.31 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:42 PM PST 24
Peak memory 197740 kb
Host smart-24955859-2c75-470c-bcf9-489ce399e90a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225698345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2225698345
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3145071248
Short name T388
Test name
Test status
Simulation time 36472612 ps
CPU time 0.81 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 195628 kb
Host smart-ca077e5a-801e-403e-83f6-64160fe556b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145071248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3145071248
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.451970953
Short name T93
Test name
Test status
Simulation time 80571677 ps
CPU time 1.3 seconds
Started Feb 07 05:06:23 PM PST 24
Finished Feb 07 05:06:29 PM PST 24
Peak memory 195520 kb
Host smart-0a7ad209-2d7b-47cb-8ff5-8291eadc29ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451970953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.451970953
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.904672056
Short name T879
Test name
Test status
Simulation time 224740345 ps
CPU time 2.77 seconds
Started Feb 07 05:06:25 PM PST 24
Finished Feb 07 05:06:31 PM PST 24
Peak memory 197804 kb
Host smart-3a60f688-23a9-42a9-8ac0-4ff922ebd2cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904672056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.904672056
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3353923366
Short name T707
Test name
Test status
Simulation time 406190705 ps
CPU time 3.34 seconds
Started Feb 07 05:06:19 PM PST 24
Finished Feb 07 05:06:23 PM PST 24
Peak memory 196752 kb
Host smart-38f104cb-4d3e-464b-b19f-1afe3d916009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353923366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3353923366
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3168282934
Short name T315
Test name
Test status
Simulation time 48994016 ps
CPU time 1.14 seconds
Started Feb 07 05:06:26 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 196448 kb
Host smart-1ee481b5-bfa1-485f-82e6-f3a980e76acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168282934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3168282934
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4057533111
Short name T364
Test name
Test status
Simulation time 72067763 ps
CPU time 0.97 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195756 kb
Host smart-1a124332-9194-472d-928c-feb759cfb182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057533111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4057533111
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1531102561
Short name T361
Test name
Test status
Simulation time 236611880 ps
CPU time 1.95 seconds
Started Feb 07 05:06:24 PM PST 24
Finished Feb 07 05:06:31 PM PST 24
Peak memory 197704 kb
Host smart-6342e649-0ff8-48f1-815c-4fd4788a7ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531102561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1531102561
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2281812488
Short name T783
Test name
Test status
Simulation time 41438525 ps
CPU time 1.18 seconds
Started Feb 07 05:06:20 PM PST 24
Finished Feb 07 05:06:22 PM PST 24
Peak memory 195260 kb
Host smart-13310ac5-70ec-4641-a07c-d2f552028c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281812488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2281812488
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1595967685
Short name T418
Test name
Test status
Simulation time 266452852 ps
CPU time 1.25 seconds
Started Feb 07 05:06:18 PM PST 24
Finished Feb 07 05:06:20 PM PST 24
Peak memory 195676 kb
Host smart-b5b0a2a6-4c79-4fe5-92d8-f94c64bddc1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595967685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1595967685
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4240152067
Short name T338
Test name
Test status
Simulation time 9891984992 ps
CPU time 80.13 seconds
Started Feb 07 05:06:31 PM PST 24
Finished Feb 07 05:07:54 PM PST 24
Peak memory 197824 kb
Host smart-5222cc6e-65d7-495c-a594-1d60e626c684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240152067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4240152067
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2098637317
Short name T533
Test name
Test status
Simulation time 748257055834 ps
CPU time 2138.57 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:42:07 PM PST 24
Peak memory 206256 kb
Host smart-7466802b-1ee6-4618-b42a-3912654d40c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2098637317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2098637317
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3132684609
Short name T680
Test name
Test status
Simulation time 13821807 ps
CPU time 0.66 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:29 PM PST 24
Peak memory 193708 kb
Host smart-4587c81f-dc31-419e-91b4-cc3636359e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132684609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3132684609
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4218734101
Short name T369
Test name
Test status
Simulation time 22819018 ps
CPU time 0.67 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:29 PM PST 24
Peak memory 194520 kb
Host smart-50175f5c-4ed0-4d00-b77a-243dd7cce42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218734101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4218734101
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3388247435
Short name T62
Test name
Test status
Simulation time 2362745792 ps
CPU time 19.09 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:52 PM PST 24
Peak memory 195336 kb
Host smart-ab2834cd-be08-43e1-bcec-28223cda2009
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388247435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3388247435
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3750766581
Short name T269
Test name
Test status
Simulation time 108023755 ps
CPU time 1.09 seconds
Started Feb 07 05:06:28 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195784 kb
Host smart-3c7980c2-c9df-467b-bf8a-1c5791615227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750766581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3750766581
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2270815731
Short name T653
Test name
Test status
Simulation time 937347325 ps
CPU time 3.43 seconds
Started Feb 07 05:06:28 PM PST 24
Finished Feb 07 05:06:36 PM PST 24
Peak memory 197844 kb
Host smart-9894c186-954c-46cf-9d41-09845aac0d2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270815731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2270815731
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2588744915
Short name T234
Test name
Test status
Simulation time 195399166 ps
CPU time 1.7 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:06:35 PM PST 24
Peak memory 195856 kb
Host smart-e20f30b1-09a9-4d30-b2b4-606a613a62e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588744915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2588744915
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3464915406
Short name T713
Test name
Test status
Simulation time 16798916 ps
CPU time 0.83 seconds
Started Feb 07 05:06:31 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195208 kb
Host smart-3d6cc790-8812-4a91-8f2a-08dd5eae7368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464915406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3464915406
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3819005858
Short name T236
Test name
Test status
Simulation time 70840186 ps
CPU time 0.89 seconds
Started Feb 07 05:06:31 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195336 kb
Host smart-fc3d8bc3-0db2-42a6-b5a4-cadceac417e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819005858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3819005858
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3676789105
Short name T530
Test name
Test status
Simulation time 846416818 ps
CPU time 4.51 seconds
Started Feb 07 05:06:26 PM PST 24
Finished Feb 07 05:06:33 PM PST 24
Peak memory 197836 kb
Host smart-1a92091f-bf92-4d3b-9e40-632f628bdd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676789105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3676789105
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.797496161
Short name T356
Test name
Test status
Simulation time 115156809 ps
CPU time 1.39 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 196724 kb
Host smart-b28944dd-d592-450b-a4e5-c2dd1914f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797496161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.797496161
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.504950103
Short name T243
Test name
Test status
Simulation time 49533112 ps
CPU time 1.38 seconds
Started Feb 07 05:06:28 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 197724 kb
Host smart-a91974d4-ab5d-4eb9-a223-7f603f348669
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504950103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.504950103
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.397062586
Short name T616
Test name
Test status
Simulation time 10726100611 ps
CPU time 141.48 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:08:50 PM PST 24
Peak memory 197908 kb
Host smart-3d1e1f7c-fb9d-49c3-a3bd-1a59f3b575bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397062586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.397062586
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1950951660
Short name T695
Test name
Test status
Simulation time 45458403225 ps
CPU time 977.92 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:22:51 PM PST 24
Peak memory 198064 kb
Host smart-2a849b3a-cd9c-43f3-8232-c641ba844438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1950951660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1950951660
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.698958094
Short name T42
Test name
Test status
Simulation time 23452285 ps
CPU time 0.59 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:29 PM PST 24
Peak memory 194376 kb
Host smart-1168990c-f478-4a88-a910-6f9bb175bc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698958094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.698958094
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.664596726
Short name T266
Test name
Test status
Simulation time 23115286 ps
CPU time 0.83 seconds
Started Feb 07 05:06:28 PM PST 24
Finished Feb 07 05:06:31 PM PST 24
Peak memory 195208 kb
Host smart-fc9c61b9-469f-49c5-8e8c-b5901d1d4ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664596726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.664596726
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2662555023
Short name T506
Test name
Test status
Simulation time 361043777 ps
CPU time 13.36 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 196084 kb
Host smart-17ae7998-0f49-4bbc-b199-c011fa6aba68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662555023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2662555023
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2987567402
Short name T738
Test name
Test status
Simulation time 31035661 ps
CPU time 0.74 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:33 PM PST 24
Peak memory 194456 kb
Host smart-899e5df4-80e1-47f3-a772-d1945b57696b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987567402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2987567402
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1305691111
Short name T218
Test name
Test status
Simulation time 63890407 ps
CPU time 1.26 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195584 kb
Host smart-194bc253-870c-42a1-9ad4-aea198bfb191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305691111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1305691111
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1675254960
Short name T760
Test name
Test status
Simulation time 60898132 ps
CPU time 2.31 seconds
Started Feb 07 05:06:28 PM PST 24
Finished Feb 07 05:06:33 PM PST 24
Peak memory 196032 kb
Host smart-a6f75c86-6fa5-4607-a075-1921dc21a9a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675254960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1675254960
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3384470638
Short name T754
Test name
Test status
Simulation time 122912597 ps
CPU time 2.92 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:06:36 PM PST 24
Peak memory 196872 kb
Host smart-f5e4b3e5-aa8c-4151-92e2-b8031f08d6d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384470638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3384470638
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1644468190
Short name T697
Test name
Test status
Simulation time 99420404 ps
CPU time 1.35 seconds
Started Feb 07 05:06:25 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 196396 kb
Host smart-722fbcdc-aa2c-40a8-9a4f-235e7b1507bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644468190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1644468190
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1988060178
Short name T719
Test name
Test status
Simulation time 31623719 ps
CPU time 1.18 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 196604 kb
Host smart-5e22ecab-4b6a-4c3e-b04b-941744ede534
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988060178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1988060178
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2584075334
Short name T413
Test name
Test status
Simulation time 1351906445 ps
CPU time 6.12 seconds
Started Feb 07 05:06:35 PM PST 24
Finished Feb 07 05:06:42 PM PST 24
Peak memory 197732 kb
Host smart-36335264-518e-4c25-97c0-bd8f3478e356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584075334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2584075334
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2866930203
Short name T395
Test name
Test status
Simulation time 213735906 ps
CPU time 1.06 seconds
Started Feb 07 05:06:30 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195308 kb
Host smart-ef896037-ad4b-4add-b253-a0469f824597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866930203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2866930203
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3079847392
Short name T513
Test name
Test status
Simulation time 42713071 ps
CPU time 1.23 seconds
Started Feb 07 05:06:35 PM PST 24
Finished Feb 07 05:06:37 PM PST 24
Peak memory 196300 kb
Host smart-2abab8c0-2283-49b9-83a7-74249412e7ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079847392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3079847392
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1249611231
Short name T822
Test name
Test status
Simulation time 18215540880 ps
CPU time 217.95 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:10:07 PM PST 24
Peak memory 197896 kb
Host smart-ea9d9120-3d89-41fe-ba99-706b6a4fd001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249611231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1249611231
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2544886202
Short name T465
Test name
Test status
Simulation time 207219128750 ps
CPU time 1391.99 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:29:45 PM PST 24
Peak memory 198004 kb
Host smart-ae3c5d14-6222-47c3-a07d-0f3c094f2eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2544886202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2544886202
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.4242769152
Short name T704
Test name
Test status
Simulation time 131306755 ps
CPU time 0.62 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 193896 kb
Host smart-55eae8a8-db0b-486c-b546-2fcbcfe7797e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242769152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.4242769152
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1678626545
Short name T675
Test name
Test status
Simulation time 36829378 ps
CPU time 0.76 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:06:45 PM PST 24
Peak memory 193904 kb
Host smart-925583f7-6a76-4be2-be1d-19deaa805fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678626545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1678626545
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4102549246
Short name T289
Test name
Test status
Simulation time 440048509 ps
CPU time 24.8 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:07:08 PM PST 24
Peak memory 196072 kb
Host smart-8bc7da19-038b-426a-a5f7-3491decf6bc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102549246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4102549246
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3140963800
Short name T705
Test name
Test status
Simulation time 354590119 ps
CPU time 0.98 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:06:45 PM PST 24
Peak memory 196776 kb
Host smart-a9bfcf2a-a1f8-4d34-814e-27aa8418b5aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140963800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3140963800
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2707583715
Short name T638
Test name
Test status
Simulation time 404833981 ps
CPU time 1.38 seconds
Started Feb 07 05:06:41 PM PST 24
Finished Feb 07 05:06:43 PM PST 24
Peak memory 196884 kb
Host smart-7faa25b7-465a-40e9-bdc2-fa5a6d953b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707583715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2707583715
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1347733988
Short name T600
Test name
Test status
Simulation time 126518739 ps
CPU time 1.31 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:06:44 PM PST 24
Peak memory 197508 kb
Host smart-ce9eb1ff-d920-4590-a6ed-bbdbbfe5d8be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347733988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1347733988
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2661928032
Short name T599
Test name
Test status
Simulation time 423735367 ps
CPU time 2.46 seconds
Started Feb 07 05:06:45 PM PST 24
Finished Feb 07 05:06:49 PM PST 24
Peak memory 197804 kb
Host smart-60c080e3-e4ae-4bf5-8523-9f928dbda723
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661928032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2661928032
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.261430891
Short name T435
Test name
Test status
Simulation time 105106898 ps
CPU time 0.88 seconds
Started Feb 07 05:06:31 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195420 kb
Host smart-a42ff20b-dca6-4e7e-af05-7bd9dbb2ecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261430891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.261430891
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1923865058
Short name T217
Test name
Test status
Simulation time 50734347 ps
CPU time 0.84 seconds
Started Feb 07 05:06:29 PM PST 24
Finished Feb 07 05:06:34 PM PST 24
Peak memory 195992 kb
Host smart-764c7a03-bd64-4734-a7b8-e75d451eda6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923865058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1923865058
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3786374513
Short name T863
Test name
Test status
Simulation time 59944982 ps
CPU time 2.93 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:06:47 PM PST 24
Peak memory 197764 kb
Host smart-4ac0c009-4e36-4caa-a4bf-4d92a47d0713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786374513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3786374513
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.308281499
Short name T826
Test name
Test status
Simulation time 85245626 ps
CPU time 1.43 seconds
Started Feb 07 05:06:23 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 196308 kb
Host smart-8bd3ed2b-97fd-44bf-86c2-01e187646f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308281499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.308281499
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.124261314
Short name T644
Test name
Test status
Simulation time 162869390 ps
CPU time 1.37 seconds
Started Feb 07 05:06:27 PM PST 24
Finished Feb 07 05:06:30 PM PST 24
Peak memory 195528 kb
Host smart-0d1bb798-8a7b-4a6b-8de9-554ab88248f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124261314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.124261314
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1961402853
Short name T493
Test name
Test status
Simulation time 3463127314 ps
CPU time 53.96 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 198012 kb
Host smart-c1b5caee-a186-4e1c-8cf0-c75946a9c3e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961402853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1961402853
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.86333323
Short name T55
Test name
Test status
Simulation time 330553060043 ps
CPU time 1124.58 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:25:30 PM PST 24
Peak memory 198052 kb
Host smart-15014eea-48ae-4547-bfed-2814f66d78fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=86333323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.86333323
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3638726815
Short name T657
Test name
Test status
Simulation time 14692863 ps
CPU time 0.57 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:06:43 PM PST 24
Peak memory 193704 kb
Host smart-669eadd6-ff37-44ba-9b50-b2895d4a3156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638726815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3638726815
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4087585296
Short name T636
Test name
Test status
Simulation time 173086520 ps
CPU time 0.79 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:06:45 PM PST 24
Peak memory 195176 kb
Host smart-68706344-c34d-48d1-9a68-0c327be2049f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087585296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4087585296
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1951519945
Short name T56
Test name
Test status
Simulation time 6156638273 ps
CPU time 20.29 seconds
Started Feb 07 05:06:39 PM PST 24
Finished Feb 07 05:06:59 PM PST 24
Peak memory 196732 kb
Host smart-fbb2ce9c-ec54-4664-83c7-5dbd1c744b21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951519945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1951519945
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.610901135
Short name T370
Test name
Test status
Simulation time 98487261 ps
CPU time 0.71 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:06:44 PM PST 24
Peak memory 194504 kb
Host smart-0280c258-3340-4683-80ce-2cd9454014ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610901135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.610901135
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2143922840
Short name T844
Test name
Test status
Simulation time 62307609 ps
CPU time 0.76 seconds
Started Feb 07 05:06:49 PM PST 24
Finished Feb 07 05:06:51 PM PST 24
Peak memory 195824 kb
Host smart-9ce80329-01d7-41d8-8206-e0900dc90526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143922840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2143922840
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3851279605
Short name T818
Test name
Test status
Simulation time 156599349 ps
CPU time 1.87 seconds
Started Feb 07 05:06:49 PM PST 24
Finished Feb 07 05:06:51 PM PST 24
Peak memory 197692 kb
Host smart-3258a4ac-d47f-4b38-a29d-36320ea4e3e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851279605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3851279605
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.629691637
Short name T591
Test name
Test status
Simulation time 215187277 ps
CPU time 1.93 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 196528 kb
Host smart-28bdd091-18b2-47f6-afcd-b14d571b4d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629691637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
629691637
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.395027150
Short name T726
Test name
Test status
Simulation time 25265981 ps
CPU time 1.18 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:06:44 PM PST 24
Peak memory 195644 kb
Host smart-5f38c2ca-4414-4a06-b694-1a1eeb8d7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395027150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.395027150
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.143784910
Short name T415
Test name
Test status
Simulation time 45283759 ps
CPU time 0.84 seconds
Started Feb 07 05:06:41 PM PST 24
Finished Feb 07 05:06:43 PM PST 24
Peak memory 195356 kb
Host smart-4f7823bc-b26b-4b8d-997a-20b3f0288723
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143784910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.143784910
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.492519674
Short name T559
Test name
Test status
Simulation time 107263476 ps
CPU time 5.64 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:06:49 PM PST 24
Peak memory 197780 kb
Host smart-98d2455c-4490-4221-a454-e8b3f889bf8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492519674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.492519674
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3060972369
Short name T314
Test name
Test status
Simulation time 156576944 ps
CPU time 1.17 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 196160 kb
Host smart-41b2bce7-fdc7-490b-a079-14fdfa7d0ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060972369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3060972369
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.888912205
Short name T456
Test name
Test status
Simulation time 1631525082 ps
CPU time 1.48 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 196536 kb
Host smart-fa5100e4-6336-44cc-8262-9d7b77a65054
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888912205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.888912205
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2945335272
Short name T348
Test name
Test status
Simulation time 34822666002 ps
CPU time 100.52 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:08:25 PM PST 24
Peak memory 197880 kb
Host smart-f9eee51d-cb1e-4683-9e7a-e537d9e49643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945335272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2945335272
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.299802791
Short name T402
Test name
Test status
Simulation time 159256632128 ps
CPU time 574.34 seconds
Started Feb 07 05:06:46 PM PST 24
Finished Feb 07 05:16:21 PM PST 24
Peak memory 198000 kb
Host smart-0ed90596-2a5a-441a-bba2-c34802d04af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=299802791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.299802791
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3054390153
Short name T787
Test name
Test status
Simulation time 22935957 ps
CPU time 0.57 seconds
Started Feb 07 05:06:45 PM PST 24
Finished Feb 07 05:06:47 PM PST 24
Peak memory 194380 kb
Host smart-99cd4196-6543-47d1-8f22-67bf5b76aaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054390153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3054390153
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1791066659
Short name T332
Test name
Test status
Simulation time 72508807 ps
CPU time 0.95 seconds
Started Feb 07 05:06:43 PM PST 24
Finished Feb 07 05:06:45 PM PST 24
Peak memory 195964 kb
Host smart-cac5af23-e95b-4156-a67e-e1f32b1c22c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791066659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1791066659
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3126015012
Short name T538
Test name
Test status
Simulation time 215255491 ps
CPU time 11.64 seconds
Started Feb 07 05:06:46 PM PST 24
Finished Feb 07 05:06:58 PM PST 24
Peak memory 196520 kb
Host smart-39bcd41d-9deb-4b32-8847-91a3c5e23de2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126015012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3126015012
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1485734728
Short name T460
Test name
Test status
Simulation time 308663728 ps
CPU time 0.83 seconds
Started Feb 07 05:06:46 PM PST 24
Finished Feb 07 05:06:48 PM PST 24
Peak memory 195740 kb
Host smart-bebdfc9e-dba0-475a-b8b9-c761df544a31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485734728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1485734728
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2741940279
Short name T735
Test name
Test status
Simulation time 119547566 ps
CPU time 0.88 seconds
Started Feb 07 05:06:49 PM PST 24
Finished Feb 07 05:06:51 PM PST 24
Peak memory 195332 kb
Host smart-aa4eb521-be68-496e-a63c-ce565ca3e24f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741940279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2741940279
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2926024006
Short name T656
Test name
Test status
Simulation time 178327525 ps
CPU time 2.05 seconds
Started Feb 07 05:06:47 PM PST 24
Finished Feb 07 05:06:50 PM PST 24
Peak memory 197704 kb
Host smart-435b9121-efae-47fe-ae4b-eb6a289b4129
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926024006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2926024006
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4057962050
Short name T573
Test name
Test status
Simulation time 223674080 ps
CPU time 3.67 seconds
Started Feb 07 05:06:49 PM PST 24
Finished Feb 07 05:06:54 PM PST 24
Peak memory 197832 kb
Host smart-c3a3a1e0-a0e3-4d38-99e8-9eb7db3b04ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057962050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4057962050
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3956811856
Short name T469
Test name
Test status
Simulation time 65705768 ps
CPU time 0.97 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 195732 kb
Host smart-39a9e663-af2b-48da-94dc-d24ec02e583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956811856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3956811856
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1224734401
Short name T646
Test name
Test status
Simulation time 39491888 ps
CPU time 0.96 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:06:46 PM PST 24
Peak memory 195708 kb
Host smart-4e12d3dd-922d-41f4-b66b-8d66fc6048c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224734401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1224734401
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.832840830
Short name T535
Test name
Test status
Simulation time 3965518938 ps
CPU time 5.15 seconds
Started Feb 07 05:06:56 PM PST 24
Finished Feb 07 05:07:03 PM PST 24
Peak memory 197864 kb
Host smart-933dc02d-5f19-44aa-878c-08b2865fd609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832840830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.832840830
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1097472241
Short name T684
Test name
Test status
Simulation time 214487706 ps
CPU time 1.11 seconds
Started Feb 07 05:06:45 PM PST 24
Finished Feb 07 05:06:47 PM PST 24
Peak memory 195508 kb
Host smart-595ceb6f-c88c-44ff-9373-b617c5d3ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097472241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1097472241
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.858514117
Short name T823
Test name
Test status
Simulation time 70889059 ps
CPU time 1.19 seconds
Started Feb 07 05:06:42 PM PST 24
Finished Feb 07 05:06:44 PM PST 24
Peak memory 195480 kb
Host smart-bc8d1213-c5a5-49b7-b39c-413df955f7ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858514117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.858514117
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1219503325
Short name T414
Test name
Test status
Simulation time 68981977877 ps
CPU time 203.23 seconds
Started Feb 07 05:06:48 PM PST 24
Finished Feb 07 05:10:13 PM PST 24
Peak memory 197864 kb
Host smart-4ecace97-406c-4509-8e52-277a302c1f14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219503325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1219503325
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.94951462
Short name T379
Test name
Test status
Simulation time 58008692063 ps
CPU time 756.8 seconds
Started Feb 07 05:06:44 PM PST 24
Finished Feb 07 05:19:21 PM PST 24
Peak memory 198108 kb
Host smart-5569bba8-dec4-452a-97bb-9b34b30a118d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=94951462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.94951462
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3234832350
Short name T700
Test name
Test status
Simulation time 49183098 ps
CPU time 0.57 seconds
Started Feb 07 05:06:53 PM PST 24
Finished Feb 07 05:06:55 PM PST 24
Peak memory 193728 kb
Host smart-4e2b50a9-eeaf-49f4-bcc7-b819f877f1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234832350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3234832350
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.547572446
Short name T635
Test name
Test status
Simulation time 63545139 ps
CPU time 0.65 seconds
Started Feb 07 05:06:57 PM PST 24
Finished Feb 07 05:07:00 PM PST 24
Peak memory 193884 kb
Host smart-51024703-a5ba-4c7f-962e-1ec0f0ff35bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547572446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.547572446
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3995416601
Short name T295
Test name
Test status
Simulation time 419220388 ps
CPU time 16.14 seconds
Started Feb 07 05:06:56 PM PST 24
Finished Feb 07 05:07:14 PM PST 24
Peak memory 196508 kb
Host smart-eb75cfd9-aae1-4ce1-add0-ba7f26cb48ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995416601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3995416601
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2046966756
Short name T629
Test name
Test status
Simulation time 304599805 ps
CPU time 1.19 seconds
Started Feb 07 05:06:58 PM PST 24
Finished Feb 07 05:07:01 PM PST 24
Peak memory 197892 kb
Host smart-5a3c3721-1d74-4374-97ba-ebb7264f7b02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046966756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2046966756
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1207266227
Short name T304
Test name
Test status
Simulation time 33269839 ps
CPU time 0.85 seconds
Started Feb 07 05:06:51 PM PST 24
Finished Feb 07 05:06:52 PM PST 24
Peak memory 195936 kb
Host smart-8bd9540a-f535-4a65-87d2-87eac63c6fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207266227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1207266227
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1623310194
Short name T721
Test name
Test status
Simulation time 59858831 ps
CPU time 2.44 seconds
Started Feb 07 05:06:51 PM PST 24
Finished Feb 07 05:06:55 PM PST 24
Peak memory 197736 kb
Host smart-cf2e3d05-192c-46a8-810f-7e4ff93144b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623310194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1623310194
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2932077663
Short name T858
Test name
Test status
Simulation time 185284888 ps
CPU time 3.3 seconds
Started Feb 07 05:06:51 PM PST 24
Finished Feb 07 05:06:55 PM PST 24
Peak memory 196944 kb
Host smart-438d61be-cbbd-4f4c-a0b6-8f6ed08caade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932077663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2932077663
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.943356861
Short name T763
Test name
Test status
Simulation time 402220580 ps
CPU time 1.26 seconds
Started Feb 07 05:06:49 PM PST 24
Finished Feb 07 05:06:51 PM PST 24
Peak memory 196288 kb
Host smart-68664022-1512-4c32-ac06-6eb8d08eaeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943356861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.943356861
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.887580397
Short name T663
Test name
Test status
Simulation time 152773712 ps
CPU time 1.28 seconds
Started Feb 07 05:06:51 PM PST 24
Finished Feb 07 05:06:53 PM PST 24
Peak memory 195864 kb
Host smart-06846375-5a9f-46bf-bf2c-acea6db8a28e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887580397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.887580397
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.303597974
Short name T449
Test name
Test status
Simulation time 127539181 ps
CPU time 2.15 seconds
Started Feb 07 05:06:52 PM PST 24
Finished Feb 07 05:06:56 PM PST 24
Peak memory 197752 kb
Host smart-96f6c2d9-7caf-4765-984e-6eb1f31e4466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303597974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.303597974
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3325510645
Short name T811
Test name
Test status
Simulation time 100605507 ps
CPU time 1.15 seconds
Started Feb 07 05:06:51 PM PST 24
Finished Feb 07 05:06:52 PM PST 24
Peak memory 196204 kb
Host smart-ee5b4be7-ef70-4395-9930-dc6a66dfcbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325510645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3325510645
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3537652969
Short name T808
Test name
Test status
Simulation time 34579615 ps
CPU time 0.97 seconds
Started Feb 07 05:06:47 PM PST 24
Finished Feb 07 05:06:49 PM PST 24
Peak memory 195828 kb
Host smart-def858cd-f750-4ba1-aa37-4fc0c9cc3031
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537652969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3537652969
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1848470555
Short name T790
Test name
Test status
Simulation time 5787011241 ps
CPU time 68.56 seconds
Started Feb 07 05:06:52 PM PST 24
Finished Feb 07 05:08:02 PM PST 24
Peak memory 197852 kb
Host smart-7e83bd8f-2c9b-43e8-806f-80324311a39d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848470555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1848470555
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3977899269
Short name T776
Test name
Test status
Simulation time 185917035770 ps
CPU time 1209.8 seconds
Started Feb 07 05:06:56 PM PST 24
Finished Feb 07 05:27:08 PM PST 24
Peak memory 198036 kb
Host smart-185e9de1-894a-46dc-8083-b9a7da72802d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3977899269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3977899269
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.354324140
Short name T261
Test name
Test status
Simulation time 11761606 ps
CPU time 0.59 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 193472 kb
Host smart-400f503e-df58-4894-aee5-932d22b80f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354324140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.354324140
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3811164941
Short name T109
Test name
Test status
Simulation time 101835850 ps
CPU time 0.94 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 195236 kb
Host smart-f350359e-a8b8-4fdc-b7be-ae9b14412737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811164941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3811164941
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3609385201
Short name T417
Test name
Test status
Simulation time 546773171 ps
CPU time 29.89 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:40 PM PST 24
Peak memory 196532 kb
Host smart-40ac6c35-9a25-4b29-89ca-67a405627d47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609385201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3609385201
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2041768215
Short name T648
Test name
Test status
Simulation time 208896902 ps
CPU time 1.07 seconds
Started Feb 07 05:07:01 PM PST 24
Finished Feb 07 05:07:04 PM PST 24
Peak memory 197828 kb
Host smart-ac0d1249-aaf4-48c9-bf6d-9be0831dc501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041768215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2041768215
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2139408752
Short name T833
Test name
Test status
Simulation time 196460635 ps
CPU time 1.19 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195760 kb
Host smart-a1a8e3e4-0daf-4e50-b619-eeb8dc424c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139408752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2139408752
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.4158849721
Short name T566
Test name
Test status
Simulation time 58760482 ps
CPU time 2.87 seconds
Started Feb 07 05:06:54 PM PST 24
Finished Feb 07 05:06:59 PM PST 24
Peak memory 197756 kb
Host smart-a474507a-efb1-435f-8690-29657a9d224e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158849721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.4158849721
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3452839428
Short name T720
Test name
Test status
Simulation time 113793966 ps
CPU time 3.12 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:13 PM PST 24
Peak memory 196988 kb
Host smart-d861ebbe-5c05-4ed8-958f-eacd05822542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452839428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3452839428
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1894683770
Short name T746
Test name
Test status
Simulation time 296257098 ps
CPU time 1.51 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 196544 kb
Host smart-426e674b-ca91-42d4-b3e8-3b2a39489d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894683770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1894683770
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.38129088
Short name T444
Test name
Test status
Simulation time 329048982 ps
CPU time 1.2 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:12 PM PST 24
Peak memory 195536 kb
Host smart-3f20afea-b4da-4287-868d-c31bb4e64ce8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38129088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_
pulldown.38129088
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1761439881
Short name T527
Test name
Test status
Simulation time 80812098 ps
CPU time 3.91 seconds
Started Feb 07 05:06:52 PM PST 24
Finished Feb 07 05:06:58 PM PST 24
Peak memory 197796 kb
Host smart-60c20cc9-c66f-42b0-ba9e-e9a6998a19ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761439881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1761439881
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2564202757
Short name T466
Test name
Test status
Simulation time 57937974 ps
CPU time 1.04 seconds
Started Feb 07 05:07:00 PM PST 24
Finished Feb 07 05:07:02 PM PST 24
Peak memory 196872 kb
Host smart-7b28db78-f3cf-4cee-a6af-5fd4a80a69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564202757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2564202757
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1932661608
Short name T674
Test name
Test status
Simulation time 235029592 ps
CPU time 0.92 seconds
Started Feb 07 05:06:57 PM PST 24
Finished Feb 07 05:07:00 PM PST 24
Peak memory 195168 kb
Host smart-28c79f29-4077-44f9-b6fb-fdcdbde3e16b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932661608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1932661608
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3879257212
Short name T229
Test name
Test status
Simulation time 28240073387 ps
CPU time 62.14 seconds
Started Feb 07 05:06:54 PM PST 24
Finished Feb 07 05:07:59 PM PST 24
Peak memory 197924 kb
Host smart-4704a470-2714-428b-a927-3294aad1c357
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879257212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3879257212
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1167078485
Short name T729
Test name
Test status
Simulation time 82880369235 ps
CPU time 1815.89 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:37:26 PM PST 24
Peak memory 198064 kb
Host smart-39f7f255-f714-4966-99fc-3966add1e562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1167078485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1167078485
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3205700447
Short name T283
Test name
Test status
Simulation time 18492572 ps
CPU time 0.6 seconds
Started Feb 07 05:04:26 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 193768 kb
Host smart-8d7b437d-30ae-444d-9b99-5bf90f49d41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205700447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3205700447
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.973503515
Short name T639
Test name
Test status
Simulation time 195708127 ps
CPU time 0.96 seconds
Started Feb 07 05:04:27 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 195528 kb
Host smart-975a53ae-ae29-4854-916c-0c6ab9080e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973503515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.973503515
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2758040911
Short name T756
Test name
Test status
Simulation time 250333038 ps
CPU time 7.14 seconds
Started Feb 07 05:04:22 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 197744 kb
Host smart-ae0cfb2d-13ef-4571-a7ee-c1ce540aabef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758040911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2758040911
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.686880175
Short name T453
Test name
Test status
Simulation time 146781257 ps
CPU time 0.97 seconds
Started Feb 07 05:04:22 PM PST 24
Finished Feb 07 05:04:25 PM PST 24
Peak memory 195924 kb
Host smart-af6de27b-a50b-466e-805e-bbfdab7c1a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686880175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.686880175
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4192253614
Short name T313
Test name
Test status
Simulation time 46106827 ps
CPU time 1.38 seconds
Started Feb 07 05:04:29 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 196636 kb
Host smart-8f4f2e03-42a9-4eaf-8079-c5e81c46d0e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192253614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4192253614
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1198076824
Short name T306
Test name
Test status
Simulation time 323716290 ps
CPU time 3.72 seconds
Started Feb 07 05:04:24 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 197892 kb
Host smart-3987b827-44cb-45f0-994f-dca559aaabc1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198076824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1198076824
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.339558981
Short name T813
Test name
Test status
Simulation time 564206462 ps
CPU time 2.88 seconds
Started Feb 07 05:04:14 PM PST 24
Finished Feb 07 05:04:18 PM PST 24
Peak memory 197808 kb
Host smart-238304fa-d7da-451d-9460-872d13416ff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339558981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.339558981
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3779393061
Short name T60
Test name
Test status
Simulation time 387449085 ps
CPU time 1.34 seconds
Started Feb 07 05:04:15 PM PST 24
Finished Feb 07 05:04:17 PM PST 24
Peak memory 196716 kb
Host smart-d5153a67-93f5-4644-b397-16650bc4d867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779393061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3779393061
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.538889827
Short name T540
Test name
Test status
Simulation time 34697577 ps
CPU time 0.79 seconds
Started Feb 07 05:04:15 PM PST 24
Finished Feb 07 05:04:16 PM PST 24
Peak memory 195900 kb
Host smart-339465d3-2856-4ddb-9196-bee5d2d81c2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538889827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.538889827
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1038989091
Short name T668
Test name
Test status
Simulation time 162352739 ps
CPU time 2.85 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:04:19 PM PST 24
Peak memory 197812 kb
Host smart-dcace085-a9ff-4b19-a65e-774b63af8202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038989091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1038989091
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.4000402245
Short name T762
Test name
Test status
Simulation time 526559908 ps
CPU time 1.38 seconds
Started Feb 07 05:04:29 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 195312 kb
Host smart-b57b8ad9-aee7-49a6-99c2-e93037eb9628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000402245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4000402245
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1223995455
Short name T796
Test name
Test status
Simulation time 123634988 ps
CPU time 1.21 seconds
Started Feb 07 05:04:15 PM PST 24
Finished Feb 07 05:04:17 PM PST 24
Peak memory 195300 kb
Host smart-36b3c87f-247b-45d3-9bad-a363ea26b012
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223995455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1223995455
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1433234117
Short name T282
Test name
Test status
Simulation time 16789614002 ps
CPU time 199.94 seconds
Started Feb 07 05:04:28 PM PST 24
Finished Feb 07 05:07:49 PM PST 24
Peak memory 197924 kb
Host smart-d4a3d2de-1caa-48cf-87d9-531f41fb295d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433234117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1433234117
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3463482506
Short name T877
Test name
Test status
Simulation time 67017679201 ps
CPU time 674.14 seconds
Started Feb 07 05:04:16 PM PST 24
Finished Feb 07 05:15:30 PM PST 24
Peak memory 197980 kb
Host smart-0b76f417-a6f3-4c7f-8a98-2ee002ee9b83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3463482506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3463482506
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1039248323
Short name T547
Test name
Test status
Simulation time 22364297 ps
CPU time 0.63 seconds
Started Feb 07 05:06:53 PM PST 24
Finished Feb 07 05:06:55 PM PST 24
Peak memory 193912 kb
Host smart-ea557c78-b2fc-4a09-abe5-34d08a87dcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039248323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1039248323
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.546502483
Short name T61
Test name
Test status
Simulation time 52490009 ps
CPU time 0.88 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 196128 kb
Host smart-fda903e5-4eb9-493a-809f-457a65a22117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546502483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.546502483
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.434700529
Short name T225
Test name
Test status
Simulation time 1868782784 ps
CPU time 24.82 seconds
Started Feb 07 05:06:52 PM PST 24
Finished Feb 07 05:07:19 PM PST 24
Peak memory 196508 kb
Host smart-c017101a-dcf9-4863-9bce-200ce1d05fd2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434700529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.434700529
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.810132121
Short name T40
Test name
Test status
Simulation time 71000368 ps
CPU time 1.07 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:12 PM PST 24
Peak memory 197104 kb
Host smart-b38d247f-69a4-42b4-b825-dfad4cab02a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810132121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.810132121
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1316763948
Short name T741
Test name
Test status
Simulation time 94582306 ps
CPU time 1.43 seconds
Started Feb 07 05:07:03 PM PST 24
Finished Feb 07 05:07:10 PM PST 24
Peak memory 195860 kb
Host smart-0354adff-c318-42cd-9a10-3f1b01e2d6fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316763948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1316763948
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1877070716
Short name T851
Test name
Test status
Simulation time 281289802 ps
CPU time 3 seconds
Started Feb 07 05:07:02 PM PST 24
Finished Feb 07 05:07:06 PM PST 24
Peak memory 197816 kb
Host smart-091f0930-3cfe-473d-a46f-322bb863a951
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877070716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1877070716
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2816313030
Short name T612
Test name
Test status
Simulation time 233803948 ps
CPU time 2.13 seconds
Started Feb 07 05:06:53 PM PST 24
Finished Feb 07 05:06:57 PM PST 24
Peak memory 197064 kb
Host smart-966308c0-ad31-4e68-a44f-d4675a23e645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816313030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2816313030
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2353595539
Short name T534
Test name
Test status
Simulation time 236075204 ps
CPU time 1.45 seconds
Started Feb 07 05:06:58 PM PST 24
Finished Feb 07 05:07:01 PM PST 24
Peak memory 195616 kb
Host smart-0c1e1de0-36b8-4f9a-be97-81f1336391bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353595539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2353595539
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1275984815
Short name T555
Test name
Test status
Simulation time 48913663 ps
CPU time 0.84 seconds
Started Feb 07 05:06:51 PM PST 24
Finished Feb 07 05:06:53 PM PST 24
Peak memory 195216 kb
Host smart-67fef827-d481-4512-96e4-a4472d618dac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275984815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1275984815
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4010215460
Short name T687
Test name
Test status
Simulation time 182775991 ps
CPU time 3.41 seconds
Started Feb 07 05:06:54 PM PST 24
Finished Feb 07 05:07:00 PM PST 24
Peak memory 197752 kb
Host smart-6cd891f5-a4fb-4770-9c0f-20bd976d1200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010215460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4010215460
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3409640964
Short name T346
Test name
Test status
Simulation time 308415222 ps
CPU time 1.51 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:12 PM PST 24
Peak memory 195312 kb
Host smart-127d7624-a9f5-4eec-b9ac-87fe903be462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409640964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3409640964
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1097458399
Short name T778
Test name
Test status
Simulation time 140839866 ps
CPU time 1.01 seconds
Started Feb 07 05:07:02 PM PST 24
Finished Feb 07 05:07:04 PM PST 24
Peak memory 195628 kb
Host smart-942fc655-33b5-453a-8664-e7170dba43c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097458399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1097458399
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1061733287
Short name T223
Test name
Test status
Simulation time 5221231889 ps
CPU time 60.62 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:08:11 PM PST 24
Peak memory 197768 kb
Host smart-9b2728f4-5d31-4447-855b-0c75329d442e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061733287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1061733287
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3614613926
Short name T334
Test name
Test status
Simulation time 25844047789 ps
CPU time 400.75 seconds
Started Feb 07 05:07:02 PM PST 24
Finished Feb 07 05:13:44 PM PST 24
Peak memory 198072 kb
Host smart-0a22d6b1-28c2-471d-bb4e-608dcac67e7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3614613926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3614613926
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1944208563
Short name T335
Test name
Test status
Simulation time 25116903 ps
CPU time 0.61 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:16 PM PST 24
Peak memory 194420 kb
Host smart-8b2a59eb-dba1-4746-809f-88098a36dcbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944208563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1944208563
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.588202353
Short name T597
Test name
Test status
Simulation time 196462820 ps
CPU time 1.05 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195488 kb
Host smart-596973c3-ea12-4935-a42f-e96860780c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588202353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.588202353
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.984129939
Short name T716
Test name
Test status
Simulation time 2625114011 ps
CPU time 21.59 seconds
Started Feb 07 05:07:09 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 197240 kb
Host smart-0d6e16cd-1c2a-41e0-b46a-3330520f6046
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984129939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.984129939
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1011655038
Short name T461
Test name
Test status
Simulation time 84243359 ps
CPU time 1.07 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 197520 kb
Host smart-2a090c2d-7a0f-4e6c-9eb1-7302aea87163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011655038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1011655038
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.13313110
Short name T733
Test name
Test status
Simulation time 45085748 ps
CPU time 1.31 seconds
Started Feb 07 05:07:01 PM PST 24
Finished Feb 07 05:07:04 PM PST 24
Peak memory 195784 kb
Host smart-e1f4a7a8-1635-4f6d-a1eb-9bee7f66e6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13313110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.13313110
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2743996125
Short name T593
Test name
Test status
Simulation time 165678906 ps
CPU time 2 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:13 PM PST 24
Peak memory 197728 kb
Host smart-f632532a-dc12-4ea8-b759-f26bb7f8e2a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743996125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2743996125
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.669751116
Short name T622
Test name
Test status
Simulation time 118881438 ps
CPU time 2.22 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:18 PM PST 24
Peak memory 195832 kb
Host smart-a2e48604-7402-40a5-b84a-a4e6a4c4972e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669751116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
669751116
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2805897041
Short name T474
Test name
Test status
Simulation time 29726107 ps
CPU time 1.23 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195944 kb
Host smart-e7a33364-f836-498f-a476-2263d4f6bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805897041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2805897041
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.194581794
Short name T339
Test name
Test status
Simulation time 1371375325 ps
CPU time 1.31 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195600 kb
Host smart-e60683d4-4824-4933-a309-cbe022ce12f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194581794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.194581794
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2377411369
Short name T828
Test name
Test status
Simulation time 968728797 ps
CPU time 5.21 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:15 PM PST 24
Peak memory 197656 kb
Host smart-cc7f8165-af1d-4579-b648-f7447a443bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377411369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2377411369
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.4279214631
Short name T259
Test name
Test status
Simulation time 125583398 ps
CPU time 0.95 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 196204 kb
Host smart-e07a8a37-cd06-409a-9fe9-db88654cbef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279214631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.4279214631
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2902989970
Short name T693
Test name
Test status
Simulation time 254124358 ps
CPU time 1.08 seconds
Started Feb 07 05:06:57 PM PST 24
Finished Feb 07 05:07:00 PM PST 24
Peak memory 196832 kb
Host smart-09dd3196-8428-4a5c-94ff-1c80af025ff2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902989970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2902989970
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3378729091
Short name T703
Test name
Test status
Simulation time 12951449504 ps
CPU time 80.86 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:08:31 PM PST 24
Peak memory 197968 kb
Host smart-e57eb9fa-bbfb-436e-ab90-a19b9f335b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378729091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3378729091
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3678980856
Short name T408
Test name
Test status
Simulation time 51650681978 ps
CPU time 1386.2 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:30:16 PM PST 24
Peak memory 198072 kb
Host smart-f727d42e-a208-41bd-b922-587d12bc8953
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3678980856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3678980856
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2501698823
Short name T712
Test name
Test status
Simulation time 74027616 ps
CPU time 0.63 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 194480 kb
Host smart-768d6186-2338-4ce3-916a-49f2c22f5101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501698823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2501698823
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3544084668
Short name T222
Test name
Test status
Simulation time 54239719 ps
CPU time 0.63 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 193872 kb
Host smart-ffd0a62d-b22b-41a7-843c-73e010f3a1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544084668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3544084668
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3500491718
Short name T696
Test name
Test status
Simulation time 1136348374 ps
CPU time 16.55 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:07:32 PM PST 24
Peak memory 196656 kb
Host smart-7f043529-5fd1-461b-abb7-5b42c0353262
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500491718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3500491718
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3302514041
Short name T488
Test name
Test status
Simulation time 153799478 ps
CPU time 0.87 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 195748 kb
Host smart-7540a20a-e5b8-40f0-b5a2-a6d07da0fb00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302514041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3302514041
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.881852016
Short name T468
Test name
Test status
Simulation time 43550422 ps
CPU time 1.01 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 196428 kb
Host smart-6c98e1e7-0655-49ad-aa0a-fd9b8928a2b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881852016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.881852016
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3935060794
Short name T869
Test name
Test status
Simulation time 274479598 ps
CPU time 2.99 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:07:19 PM PST 24
Peak memory 197740 kb
Host smart-5f0cf97d-2f32-4849-aca7-fb923a40b0f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935060794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3935060794
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.172340761
Short name T524
Test name
Test status
Simulation time 1963496873 ps
CPU time 3.79 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:07:20 PM PST 24
Peak memory 196276 kb
Host smart-86ece072-324e-4852-aef5-76230eb2448e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172340761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
172340761
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2927855421
Short name T560
Test name
Test status
Simulation time 76557233 ps
CPU time 1 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 196580 kb
Host smart-db54da17-560a-42de-945b-1c85391f48a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927855421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2927855421
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1706931767
Short name T655
Test name
Test status
Simulation time 56994897 ps
CPU time 0.78 seconds
Started Feb 07 05:07:05 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195372 kb
Host smart-7812a57e-6eca-47cd-9471-6fb280f42e46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706931767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1706931767
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.749842707
Short name T281
Test name
Test status
Simulation time 192071214 ps
CPU time 3.46 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:14 PM PST 24
Peak memory 197664 kb
Host smart-62de5141-ca18-4c90-8bad-838717d71d12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749842707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.749842707
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2227566024
Short name T521
Test name
Test status
Simulation time 124529999 ps
CPU time 1.94 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:18 PM PST 24
Peak memory 197764 kb
Host smart-2336ca41-4005-435c-8d35-47f52ec07ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227566024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2227566024
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3942810512
Short name T425
Test name
Test status
Simulation time 51362996 ps
CPU time 0.89 seconds
Started Feb 07 05:07:07 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 196184 kb
Host smart-fee56783-ba46-43e1-ae10-ed7351fd090c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942810512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3942810512
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1898261673
Short name T404
Test name
Test status
Simulation time 3772388001 ps
CPU time 109.06 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:09:05 PM PST 24
Peak memory 197928 kb
Host smart-267d4ff4-9287-4238-a6ae-111498cf8271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898261673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1898261673
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3254872467
Short name T840
Test name
Test status
Simulation time 72913498231 ps
CPU time 517.39 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:15:53 PM PST 24
Peak memory 197940 kb
Host smart-027af067-d54e-4356-affb-5e31dbdc721b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3254872467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3254872467
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.4068455937
Short name T255
Test name
Test status
Simulation time 15339365 ps
CPU time 0.6 seconds
Started Feb 07 05:07:09 PM PST 24
Finished Feb 07 05:07:15 PM PST 24
Peak memory 193716 kb
Host smart-00c6a922-8c4c-418d-a19d-003b9b9f988e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068455937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4068455937
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2052253837
Short name T798
Test name
Test status
Simulation time 30137232 ps
CPU time 0.9 seconds
Started Feb 07 05:07:07 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 196092 kb
Host smart-dd179101-a3c2-4e4d-9d31-cf2a89f10c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052253837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2052253837
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1946707858
Short name T676
Test name
Test status
Simulation time 420617320 ps
CPU time 22.74 seconds
Started Feb 07 05:07:07 PM PST 24
Finished Feb 07 05:07:33 PM PST 24
Peak memory 196544 kb
Host smart-de4dab88-89e6-493b-8631-da78c338fbaa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946707858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1946707858
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4292912270
Short name T329
Test name
Test status
Simulation time 494429840 ps
CPU time 0.76 seconds
Started Feb 07 05:07:11 PM PST 24
Finished Feb 07 05:07:16 PM PST 24
Peak memory 194280 kb
Host smart-30e64f23-b076-4de2-8554-1611e27b7dcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292912270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4292912270
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.874410622
Short name T303
Test name
Test status
Simulation time 51289634 ps
CPU time 1.1 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195528 kb
Host smart-e12c05d9-39c1-434b-b73c-c1c2dc96f813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874410622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.874410622
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1626542642
Short name T360
Test name
Test status
Simulation time 46068949 ps
CPU time 1.98 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:13 PM PST 24
Peak memory 197728 kb
Host smart-e3f99d4f-7bd0-478f-bedb-59587d56a7fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626542642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1626542642
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1060780321
Short name T819
Test name
Test status
Simulation time 212434738 ps
CPU time 3.45 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:07:14 PM PST 24
Peak memory 196744 kb
Host smart-090d614d-7b22-4f63-9369-43414c2c29c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060780321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1060780321
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3027941437
Short name T745
Test name
Test status
Simulation time 16513065 ps
CPU time 0.73 seconds
Started Feb 07 05:07:06 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195816 kb
Host smart-dec88474-af55-4e3e-a389-5906f59fb7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027941437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3027941437
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.53141921
Short name T806
Test name
Test status
Simulation time 21173568 ps
CPU time 0.9 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:12 PM PST 24
Peak memory 195320 kb
Host smart-034103d8-3cd7-4398-99b2-e32426879aa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53141921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup_
pulldown.53141921
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4243794020
Short name T389
Test name
Test status
Simulation time 416487005 ps
CPU time 1.68 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:12 PM PST 24
Peak memory 197692 kb
Host smart-1f5e933a-8a1c-48a1-b727-d82c5254c0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243794020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4243794020
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1196896477
Short name T290
Test name
Test status
Simulation time 137757202 ps
CPU time 1 seconds
Started Feb 07 05:07:04 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 197056 kb
Host smart-b3609496-2ef4-486b-a745-61e2203d7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196896477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1196896477
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.147433925
Short name T856
Test name
Test status
Simulation time 337831673 ps
CPU time 1.18 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:13 PM PST 24
Peak memory 195228 kb
Host smart-6d0e9fdb-3946-40d6-a73a-a8d36eb8501e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147433925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.147433925
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1208912674
Short name T873
Test name
Test status
Simulation time 30200743453 ps
CPU time 167.39 seconds
Started Feb 07 05:07:21 PM PST 24
Finished Feb 07 05:10:15 PM PST 24
Peak memory 197824 kb
Host smart-db79e6c0-14da-4a79-8469-b8b088549ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208912674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1208912674
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3528955875
Short name T357
Test name
Test status
Simulation time 121032585003 ps
CPU time 394.03 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:13:50 PM PST 24
Peak memory 198036 kb
Host smart-80249307-1c0b-461b-b4c6-9887bad7acb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3528955875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3528955875
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.467390034
Short name T734
Test name
Test status
Simulation time 15966834 ps
CPU time 0.62 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:16 PM PST 24
Peak memory 193744 kb
Host smart-982c056c-9dff-4e54-9bea-055132529f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467390034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.467390034
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1178630778
Short name T343
Test name
Test status
Simulation time 46709349 ps
CPU time 1.05 seconds
Started Feb 07 05:07:09 PM PST 24
Finished Feb 07 05:07:16 PM PST 24
Peak memory 197112 kb
Host smart-b6ef0180-3cab-457d-9d48-7e9377451ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178630778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1178630778
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1617935686
Short name T265
Test name
Test status
Simulation time 7108264498 ps
CPU time 27.27 seconds
Started Feb 07 05:07:09 PM PST 24
Finished Feb 07 05:07:42 PM PST 24
Peak memory 196760 kb
Host smart-88f2d1b4-8ef6-4dc4-a98e-e8579c945a82
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617935686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1617935686
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1577731869
Short name T780
Test name
Test status
Simulation time 292283087 ps
CPU time 1 seconds
Started Feb 07 05:07:21 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 197120 kb
Host smart-ee252f3b-bf30-4f57-92d1-7c9bd2143d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577731869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1577731869
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2451089827
Short name T658
Test name
Test status
Simulation time 36495685 ps
CPU time 0.88 seconds
Started Feb 07 05:07:14 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 195256 kb
Host smart-7d4af364-3e6f-42f5-9d66-a5f45bee92f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451089827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2451089827
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2068486308
Short name T793
Test name
Test status
Simulation time 65008726 ps
CPU time 1.58 seconds
Started Feb 07 05:07:21 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 197824 kb
Host smart-6d5bc8e6-e6cf-4153-a58f-08c15f5ebc59
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068486308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2068486308
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1804502941
Short name T829
Test name
Test status
Simulation time 191915724 ps
CPU time 1.68 seconds
Started Feb 07 05:07:10 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 196332 kb
Host smart-bb091465-4eac-4d08-8565-04211178ced0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804502941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1804502941
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.18220021
Short name T673
Test name
Test status
Simulation time 23739853 ps
CPU time 1.07 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195824 kb
Host smart-3dff9ec4-46b7-4a98-8c5a-666fa2bafdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18220021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.18220021
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2890333187
Short name T617
Test name
Test status
Simulation time 204047646 ps
CPU time 1.41 seconds
Started Feb 07 05:07:11 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 197852 kb
Host smart-5467b16b-e11b-469a-8350-fdb888676a3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890333187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2890333187
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3712444727
Short name T839
Test name
Test status
Simulation time 1017216196 ps
CPU time 4.92 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:21 PM PST 24
Peak memory 197532 kb
Host smart-389651cb-b612-4163-b8bf-21d1867062d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712444727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3712444727
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1410778345
Short name T220
Test name
Test status
Simulation time 56163995 ps
CPU time 1.05 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:12 PM PST 24
Peak memory 195588 kb
Host smart-4453caa6-9214-43c3-be25-ee9e6ba6bcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410778345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1410778345
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.881670548
Short name T709
Test name
Test status
Simulation time 129476894 ps
CPU time 1 seconds
Started Feb 07 05:07:08 PM PST 24
Finished Feb 07 05:07:11 PM PST 24
Peak memory 195144 kb
Host smart-274307e9-f823-41db-a6b4-d77124763970
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881670548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.881670548
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.311461079
Short name T718
Test name
Test status
Simulation time 32169809461 ps
CPU time 192.11 seconds
Started Feb 07 05:07:13 PM PST 24
Finished Feb 07 05:10:28 PM PST 24
Peak memory 197860 kb
Host smart-b50db8f1-1ed2-4be9-bcc9-b1934c696b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311461079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.311461079
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2383046802
Short name T677
Test name
Test status
Simulation time 65973707339 ps
CPU time 771.81 seconds
Started Feb 07 05:07:20 PM PST 24
Finished Feb 07 05:20:20 PM PST 24
Peak memory 198060 kb
Host smart-6a430c21-350f-4af5-97a0-ef4580267093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2383046802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2383046802
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.4199357978
Short name T575
Test name
Test status
Simulation time 78474043 ps
CPU time 0.61 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:34 PM PST 24
Peak memory 194448 kb
Host smart-a8b0649f-dc17-4bed-a43b-fa49cb80f3ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199357978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.4199357978
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2908045171
Short name T571
Test name
Test status
Simulation time 53399043 ps
CPU time 0.69 seconds
Started Feb 07 05:07:25 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 193904 kb
Host smart-e1c1594e-d834-4bc1-a402-5f031a75d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908045171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2908045171
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2557760677
Short name T400
Test name
Test status
Simulation time 183466441 ps
CPU time 5.24 seconds
Started Feb 07 05:07:22 PM PST 24
Finished Feb 07 05:07:33 PM PST 24
Peak memory 196864 kb
Host smart-adb92802-6e09-4eaa-93cf-74693e106948
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557760677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2557760677
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1378997391
Short name T715
Test name
Test status
Simulation time 180050982 ps
CPU time 1.19 seconds
Started Feb 07 05:07:22 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196396 kb
Host smart-d451e47e-f336-4914-90b5-8dc5d319581b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378997391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1378997391
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2569250934
Short name T772
Test name
Test status
Simulation time 95703022 ps
CPU time 1.11 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:35 PM PST 24
Peak memory 195608 kb
Host smart-08a20f63-a8ab-45c5-bc17-21b350eef88d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569250934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2569250934
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3531081956
Short name T108
Test name
Test status
Simulation time 312134429 ps
CPU time 3.57 seconds
Started Feb 07 05:07:25 PM PST 24
Finished Feb 07 05:07:32 PM PST 24
Peak memory 197752 kb
Host smart-629f5b53-06f2-4c07-a2de-8f8e4beb2fe2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531081956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3531081956
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1479859207
Short name T398
Test name
Test status
Simulation time 149506587 ps
CPU time 3.12 seconds
Started Feb 07 05:07:22 PM PST 24
Finished Feb 07 05:07:31 PM PST 24
Peak memory 197816 kb
Host smart-4ea7ce8d-ffb9-465e-a962-558df17d6739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479859207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1479859207
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1958137938
Short name T373
Test name
Test status
Simulation time 63848147 ps
CPU time 1.27 seconds
Started Feb 07 05:07:20 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 195768 kb
Host smart-707e41f8-2888-4bb2-ad36-a4e93ef443c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958137938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1958137938
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1615923616
Short name T611
Test name
Test status
Simulation time 157831701 ps
CPU time 1.1 seconds
Started Feb 07 05:07:21 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 195620 kb
Host smart-22883015-a957-4dcd-a317-9d4882b4e9a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615923616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1615923616
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1562404081
Short name T880
Test name
Test status
Simulation time 340213524 ps
CPU time 2.46 seconds
Started Feb 07 05:07:23 PM PST 24
Finished Feb 07 05:07:30 PM PST 24
Peak memory 197716 kb
Host smart-6226299e-9dcf-4352-a7d3-7bbdfb4a14f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562404081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1562404081
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.305775868
Short name T690
Test name
Test status
Simulation time 69539038 ps
CPU time 1.56 seconds
Started Feb 07 05:07:12 PM PST 24
Finished Feb 07 05:07:17 PM PST 24
Peak memory 196452 kb
Host smart-f38201ad-1b24-4826-8364-ae9462cebd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305775868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.305775868
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3786287031
Short name T57
Test name
Test status
Simulation time 259123846 ps
CPU time 1.46 seconds
Started Feb 07 05:07:09 PM PST 24
Finished Feb 07 05:07:16 PM PST 24
Peak memory 197720 kb
Host smart-f8edfcdb-a0e3-4fba-9536-0d0a3ebad999
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786287031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3786287031
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2122643118
Short name T685
Test name
Test status
Simulation time 5141617133 ps
CPU time 104.3 seconds
Started Feb 07 05:07:24 PM PST 24
Finished Feb 07 05:09:13 PM PST 24
Peak memory 197816 kb
Host smart-6eb6923a-4771-48ff-93d5-0f8ee1854074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122643118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2122643118
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2865415002
Short name T445
Test name
Test status
Simulation time 264982091340 ps
CPU time 1612.19 seconds
Started Feb 07 05:07:25 PM PST 24
Finished Feb 07 05:34:21 PM PST 24
Peak memory 198104 kb
Host smart-da8d279f-cd94-4df3-aaa4-198512bdd25b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2865415002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2865415002
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1920069442
Short name T768
Test name
Test status
Simulation time 29436825 ps
CPU time 0.55 seconds
Started Feb 07 05:07:22 PM PST 24
Finished Feb 07 05:07:28 PM PST 24
Peak memory 194436 kb
Host smart-713f45bf-ec6f-4a17-9e86-cde71ec83954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920069442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1920069442
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2847941160
Short name T448
Test name
Test status
Simulation time 31235964 ps
CPU time 1.01 seconds
Started Feb 07 05:07:21 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196556 kb
Host smart-b555a163-b388-4426-b211-2bbb235272cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847941160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2847941160
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3663150099
Short name T821
Test name
Test status
Simulation time 1173568938 ps
CPU time 8.04 seconds
Started Feb 07 05:07:22 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 196880 kb
Host smart-daceaaab-f1a9-48b8-a7aa-24703986a991
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663150099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3663150099
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.244582307
Short name T462
Test name
Test status
Simulation time 199170197 ps
CPU time 0.74 seconds
Started Feb 07 05:07:25 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 194584 kb
Host smart-e1babf7c-b6b5-404b-95ff-c85768eb7ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244582307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.244582307
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3776240403
Short name T424
Test name
Test status
Simulation time 13506199 ps
CPU time 0.66 seconds
Started Feb 07 05:07:22 PM PST 24
Finished Feb 07 05:07:28 PM PST 24
Peak memory 194052 kb
Host smart-8c306500-0fbd-45af-926a-5877c82d90c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776240403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3776240403
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2614173911
Short name T106
Test name
Test status
Simulation time 71538148 ps
CPU time 1.66 seconds
Started Feb 07 05:07:25 PM PST 24
Finished Feb 07 05:07:30 PM PST 24
Peak memory 196600 kb
Host smart-327902db-31be-4845-afca-f4792ba96a9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614173911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2614173911
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2354905165
Short name T759
Test name
Test status
Simulation time 131224018 ps
CPU time 1.29 seconds
Started Feb 07 05:07:21 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196544 kb
Host smart-5e5bdcdb-620e-42bc-a4db-de9101e37399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354905165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2354905165
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1845000196
Short name T590
Test name
Test status
Simulation time 496992678 ps
CPU time 1.27 seconds
Started Feb 07 05:07:25 PM PST 24
Finished Feb 07 05:07:30 PM PST 24
Peak memory 195636 kb
Host smart-8b127757-8bac-4a89-a661-7b0a3b7cb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845000196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1845000196
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.277508870
Short name T439
Test name
Test status
Simulation time 21350521 ps
CPU time 0.91 seconds
Started Feb 07 05:07:23 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196268 kb
Host smart-81161b0c-589f-4fe4-8ef3-e5581e040386
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277508870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.277508870
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3664755917
Short name T860
Test name
Test status
Simulation time 370522202 ps
CPU time 4.81 seconds
Started Feb 07 05:07:23 PM PST 24
Finished Feb 07 05:07:33 PM PST 24
Peak memory 197804 kb
Host smart-27fd959b-2107-4ca3-ab72-eb50b20db261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664755917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3664755917
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3908920026
Short name T316
Test name
Test status
Simulation time 83152192 ps
CPU time 1.5 seconds
Started Feb 07 05:07:26 PM PST 24
Finished Feb 07 05:07:30 PM PST 24
Peak memory 197788 kb
Host smart-70fcc130-9535-4d63-8822-0d4f2ffe8f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908920026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3908920026
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2223380316
Short name T323
Test name
Test status
Simulation time 68166662 ps
CPU time 1.53 seconds
Started Feb 07 05:07:23 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196032 kb
Host smart-239f7543-2ea8-4d9a-8492-575e5356698c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223380316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2223380316
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1182283226
Short name T874
Test name
Test status
Simulation time 14376711291 ps
CPU time 41.44 seconds
Started Feb 07 05:07:24 PM PST 24
Finished Feb 07 05:08:10 PM PST 24
Peak memory 197824 kb
Host smart-b8b392ff-ee25-4cfa-880f-28d19b5df724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182283226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1182283226
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3432054755
Short name T327
Test name
Test status
Simulation time 133090221073 ps
CPU time 1336.15 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:29:49 PM PST 24
Peak memory 206352 kb
Host smart-2e5be3af-7890-48d5-99e1-4f07f24710f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3432054755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3432054755
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.540614976
Short name T710
Test name
Test status
Simulation time 22991295 ps
CPU time 0.6 seconds
Started Feb 07 05:07:31 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 193500 kb
Host smart-f326f487-0a2a-432b-a082-b402c4f6a523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540614976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.540614976
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4062036075
Short name T433
Test name
Test status
Simulation time 33263246 ps
CPU time 0.8 seconds
Started Feb 07 05:07:26 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 195868 kb
Host smart-08ed7c47-ef4c-4f35-ad55-ab889d9fdee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062036075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4062036075
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3293047551
Short name T589
Test name
Test status
Simulation time 824898938 ps
CPU time 22.48 seconds
Started Feb 07 05:07:31 PM PST 24
Finished Feb 07 05:07:58 PM PST 24
Peak memory 194960 kb
Host smart-d92d6af4-4159-4423-ba21-a098aac85f8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293047551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3293047551
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1869590476
Short name T362
Test name
Test status
Simulation time 61788894 ps
CPU time 1.14 seconds
Started Feb 07 05:07:29 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 196324 kb
Host smart-c6d2baab-e5f8-4193-a3f2-89b2cb42e489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869590476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1869590476
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2814204701
Short name T382
Test name
Test status
Simulation time 35453228 ps
CPU time 0.81 seconds
Started Feb 07 05:07:28 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 195316 kb
Host smart-8f89a8db-079e-4416-b375-cbdac94c0ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814204701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2814204701
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3968205707
Short name T253
Test name
Test status
Simulation time 70090207 ps
CPU time 2.96 seconds
Started Feb 07 05:07:31 PM PST 24
Finished Feb 07 05:07:39 PM PST 24
Peak memory 196244 kb
Host smart-f52ae2dd-0bc8-4787-8e24-c76fa3243bc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968205707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3968205707
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1089449119
Short name T317
Test name
Test status
Simulation time 318090702 ps
CPU time 2.49 seconds
Started Feb 07 05:07:26 PM PST 24
Finished Feb 07 05:07:31 PM PST 24
Peak memory 195592 kb
Host smart-34984e34-6068-442b-9060-ba96764d65ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089449119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1089449119
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2066631013
Short name T546
Test name
Test status
Simulation time 38272450 ps
CPU time 0.94 seconds
Started Feb 07 05:07:24 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196556 kb
Host smart-d3d7ab4e-444a-4286-b494-805fa2598fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066631013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2066631013
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3498692729
Short name T273
Test name
Test status
Simulation time 533203832 ps
CPU time 1.13 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:35 PM PST 24
Peak memory 195884 kb
Host smart-0c75c606-8e77-4f68-962a-7e57f268a08d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498692729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3498692729
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3373466420
Short name T537
Test name
Test status
Simulation time 356285977 ps
CPU time 1.56 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 197796 kb
Host smart-178fd266-97dc-4100-aed4-38247d4fc09f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373466420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3373466420
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2288358077
Short name T717
Test name
Test status
Simulation time 605642277 ps
CPU time 1.07 seconds
Started Feb 07 05:07:24 PM PST 24
Finished Feb 07 05:07:29 PM PST 24
Peak memory 196304 kb
Host smart-735411ce-b45c-41a9-b7df-1d0fcad8f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288358077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2288358077
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2391192601
Short name T837
Test name
Test status
Simulation time 59722490 ps
CPU time 1.19 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:35 PM PST 24
Peak memory 195316 kb
Host smart-c18afc07-7841-411c-a2ce-ca51870a69ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391192601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2391192601
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4150430598
Short name T536
Test name
Test status
Simulation time 19409412944 ps
CPU time 265.35 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:11:59 PM PST 24
Peak memory 198000 kb
Host smart-fab39818-3e79-4b62-bcbf-ead4475efe40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150430598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4150430598
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1026342428
Short name T75
Test name
Test status
Simulation time 282913033753 ps
CPU time 1167.06 seconds
Started Feb 07 05:07:26 PM PST 24
Finished Feb 07 05:26:56 PM PST 24
Peak memory 198004 kb
Host smart-feb5b302-9877-4427-9db8-8411d91feed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1026342428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1026342428
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2057761958
Short name T401
Test name
Test status
Simulation time 33484186 ps
CPU time 0.61 seconds
Started Feb 07 05:07:30 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 193828 kb
Host smart-3827496d-ee7c-4d21-bfad-852d10f89ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057761958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2057761958
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.176506376
Short name T322
Test name
Test status
Simulation time 25791001 ps
CPU time 0.76 seconds
Started Feb 07 05:07:31 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 193804 kb
Host smart-484a38d7-a51f-4243-b239-cd97a612e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176506376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.176506376
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.518071603
Short name T505
Test name
Test status
Simulation time 630022092 ps
CPU time 21.46 seconds
Started Feb 07 05:07:28 PM PST 24
Finished Feb 07 05:07:56 PM PST 24
Peak memory 196684 kb
Host smart-6aa7e6c3-a106-4349-ac18-af67cc14e8c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518071603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.518071603
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2826653127
Short name T626
Test name
Test status
Simulation time 83169428 ps
CPU time 1.04 seconds
Started Feb 07 05:07:29 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 196972 kb
Host smart-f7a00d5d-6e51-4339-92d7-fa8b2b12fe56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826653127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2826653127
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.8171412
Short name T679
Test name
Test status
Simulation time 22552084 ps
CPU time 0.77 seconds
Started Feb 07 05:07:29 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 195332 kb
Host smart-4af09e2b-5534-4ac3-b9e0-140544881fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8171412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.8171412
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2349412541
Short name T554
Test name
Test status
Simulation time 181928596 ps
CPU time 2.62 seconds
Started Feb 07 05:07:28 PM PST 24
Finished Feb 07 05:07:38 PM PST 24
Peak memory 197892 kb
Host smart-62ed1d65-4485-4761-a22d-46372c4688e7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349412541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2349412541
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3849459888
Short name T247
Test name
Test status
Simulation time 297886457 ps
CPU time 3.12 seconds
Started Feb 07 05:07:38 PM PST 24
Finished Feb 07 05:07:48 PM PST 24
Peak memory 197048 kb
Host smart-fb990baf-076b-443c-8650-b5db022ab129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849459888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3849459888
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1852884130
Short name T728
Test name
Test status
Simulation time 298295881 ps
CPU time 1.45 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:36 PM PST 24
Peak memory 196752 kb
Host smart-19b3d44c-6400-471c-9c0b-b969a24c3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852884130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1852884130
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.652798210
Short name T610
Test name
Test status
Simulation time 35067576 ps
CPU time 0.87 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:34 PM PST 24
Peak memory 196476 kb
Host smart-f51078c3-8a80-4d4e-b766-91cba48e5b05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652798210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.652798210
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.775232623
Short name T442
Test name
Test status
Simulation time 1622285964 ps
CPU time 4.56 seconds
Started Feb 07 05:07:36 PM PST 24
Finished Feb 07 05:07:47 PM PST 24
Peak memory 197728 kb
Host smart-cc7df735-a9fc-4968-a701-643e5894ee50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775232623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.775232623
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3290001822
Short name T405
Test name
Test status
Simulation time 256934382 ps
CPU time 1.05 seconds
Started Feb 07 05:07:27 PM PST 24
Finished Feb 07 05:07:35 PM PST 24
Peak memory 197116 kb
Host smart-7b1b3860-dd92-4a00-bf22-61d42266e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290001822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3290001822
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4256582703
Short name T578
Test name
Test status
Simulation time 158044600 ps
CPU time 1.36 seconds
Started Feb 07 05:07:30 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 195320 kb
Host smart-9ec5e171-f19f-47ac-8edd-c69dd0aec9f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256582703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4256582703
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.974770945
Short name T866
Test name
Test status
Simulation time 18232613331 ps
CPU time 123.64 seconds
Started Feb 07 05:07:31 PM PST 24
Finished Feb 07 05:09:39 PM PST 24
Peak memory 197756 kb
Host smart-56f6b821-0644-4143-a1a4-4ef7102a2230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974770945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.974770945
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3574036245
Short name T654
Test name
Test status
Simulation time 3505308919 ps
CPU time 124.61 seconds
Started Feb 07 05:07:26 PM PST 24
Finished Feb 07 05:09:36 PM PST 24
Peak memory 198016 kb
Host smart-021b99ac-1103-416f-85a2-8e73aab43242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3574036245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3574036245
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1871690567
Short name T443
Test name
Test status
Simulation time 11957871 ps
CPU time 0.58 seconds
Started Feb 07 05:07:42 PM PST 24
Finished Feb 07 05:07:48 PM PST 24
Peak memory 193724 kb
Host smart-4f0ec883-6eaf-4495-91fd-2427cd1283af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871690567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1871690567
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1916824107
Short name T509
Test name
Test status
Simulation time 18720899 ps
CPU time 0.65 seconds
Started Feb 07 05:07:38 PM PST 24
Finished Feb 07 05:07:46 PM PST 24
Peak memory 194596 kb
Host smart-ea83ba27-233d-4fb7-bf40-00266d0250fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916824107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1916824107
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2585212085
Short name T588
Test name
Test status
Simulation time 1389151046 ps
CPU time 12.88 seconds
Started Feb 07 05:07:39 PM PST 24
Finished Feb 07 05:07:58 PM PST 24
Peak memory 195368 kb
Host smart-695ac63a-e048-4cf9-8e19-3a4eac9b64a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585212085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2585212085
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.851914437
Short name T596
Test name
Test status
Simulation time 119306335 ps
CPU time 0.96 seconds
Started Feb 07 05:07:37 PM PST 24
Finished Feb 07 05:07:44 PM PST 24
Peak memory 196556 kb
Host smart-5722319a-bcea-4651-aa3e-7f9745b00c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851914437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.851914437
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3814788885
Short name T528
Test name
Test status
Simulation time 55505277 ps
CPU time 1.12 seconds
Started Feb 07 05:07:30 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 195188 kb
Host smart-6987b068-093f-4861-95a9-c0753fce0181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814788885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3814788885
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.840179569
Short name T815
Test name
Test status
Simulation time 479093218 ps
CPU time 2.93 seconds
Started Feb 07 05:07:37 PM PST 24
Finished Feb 07 05:07:46 PM PST 24
Peak memory 197796 kb
Host smart-fd7e7f52-0897-4b5f-aa90-341b9efc670d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840179569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.840179569
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.567691124
Short name T396
Test name
Test status
Simulation time 391209091 ps
CPU time 3.34 seconds
Started Feb 07 05:07:33 PM PST 24
Finished Feb 07 05:07:40 PM PST 24
Peak memory 196792 kb
Host smart-55876cf9-97ae-4a04-ab4a-bc418a526e5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567691124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
567691124
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2276691027
Short name T455
Test name
Test status
Simulation time 89525468 ps
CPU time 1.22 seconds
Started Feb 07 05:07:33 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 195784 kb
Host smart-9725921d-c1fe-4dea-b18d-3c5ff943dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276691027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2276691027
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2019945792
Short name T305
Test name
Test status
Simulation time 119013466 ps
CPU time 0.9 seconds
Started Feb 07 05:07:30 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 195900 kb
Host smart-ed002fd3-558f-424a-9d28-e918864d13f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019945792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2019945792
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3360858472
Short name T472
Test name
Test status
Simulation time 901938246 ps
CPU time 8.72 seconds
Started Feb 07 05:07:35 PM PST 24
Finished Feb 07 05:07:49 PM PST 24
Peak memory 197800 kb
Host smart-3986db47-bb41-4f65-a155-238b30f063d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360858472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3360858472
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3779382274
Short name T500
Test name
Test status
Simulation time 95677827 ps
CPU time 1.13 seconds
Started Feb 07 05:07:30 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 195356 kb
Host smart-ce66622d-dcab-48a7-a876-021487180ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779382274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3779382274
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1596337639
Short name T227
Test name
Test status
Simulation time 1347200381 ps
CPU time 1.41 seconds
Started Feb 07 05:07:30 PM PST 24
Finished Feb 07 05:07:37 PM PST 24
Peak memory 196172 kb
Host smart-06353f94-5ae1-423b-8784-24a8516da04b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596337639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1596337639
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1193862913
Short name T380
Test name
Test status
Simulation time 55391855602 ps
CPU time 151.09 seconds
Started Feb 07 05:07:40 PM PST 24
Finished Feb 07 05:10:17 PM PST 24
Peak memory 197924 kb
Host smart-3c86c0b0-19d1-4042-83ba-4dac40d545e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193862913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1193862913
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1426786302
Short name T333
Test name
Test status
Simulation time 152564042253 ps
CPU time 1293.62 seconds
Started Feb 07 05:07:41 PM PST 24
Finished Feb 07 05:29:20 PM PST 24
Peak memory 198032 kb
Host smart-236cb996-accb-4c99-8dda-8acaefe1029c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1426786302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1426786302
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.117994465
Short name T336
Test name
Test status
Simulation time 25152141 ps
CPU time 0.59 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:44 PM PST 24
Peak memory 193756 kb
Host smart-81800916-b76c-4f0c-a2d1-80c05ab29875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117994465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.117994465
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3822414765
Short name T852
Test name
Test status
Simulation time 183271420 ps
CPU time 1.07 seconds
Started Feb 07 05:04:27 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 196268 kb
Host smart-281e8da7-ffb6-4e6c-b547-c657016598a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822414765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3822414765
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.864326706
Short name T604
Test name
Test status
Simulation time 510371379 ps
CPU time 29.24 seconds
Started Feb 07 05:04:29 PM PST 24
Finished Feb 07 05:05:00 PM PST 24
Peak memory 197804 kb
Host smart-38584156-d453-4784-a919-4b035931246f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864326706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.864326706
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.821268984
Short name T859
Test name
Test status
Simulation time 68114694 ps
CPU time 1.1 seconds
Started Feb 07 05:04:29 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 196220 kb
Host smart-a5574a26-6d19-42dd-a87d-dc6d44bb0c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821268984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.821268984
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1187220623
Short name T337
Test name
Test status
Simulation time 167725077 ps
CPU time 0.98 seconds
Started Feb 07 05:04:27 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 196220 kb
Host smart-f39e7c49-d35b-4f7f-af5a-50c587a3399d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187220623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1187220623
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2457788083
Short name T824
Test name
Test status
Simulation time 135432844 ps
CPU time 3.07 seconds
Started Feb 07 05:04:26 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 197900 kb
Host smart-d6c0d1cb-1998-447a-89f8-d6ba88f49212
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457788083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2457788083
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.833154499
Short name T250
Test name
Test status
Simulation time 645698879 ps
CPU time 3.2 seconds
Started Feb 07 05:04:27 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 197892 kb
Host smart-62553e04-7033-4f82-9ab2-4c9157131365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833154499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.833154499
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.538166238
Short name T230
Test name
Test status
Simulation time 60244447 ps
CPU time 1.22 seconds
Started Feb 07 05:04:29 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 195752 kb
Host smart-8ac83513-9780-486c-b96e-21e89d4a3dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538166238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.538166238
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.465036257
Short name T708
Test name
Test status
Simulation time 49399499 ps
CPU time 1.1 seconds
Started Feb 07 05:04:25 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 195764 kb
Host smart-bffcdfde-9553-4d16-9d08-129893d593b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465036257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.465036257
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3579717627
Short name T215
Test name
Test status
Simulation time 250431640 ps
CPU time 3.15 seconds
Started Feb 07 05:04:34 PM PST 24
Finished Feb 07 05:04:37 PM PST 24
Peak memory 197640 kb
Host smart-3e3a126a-3518-4137-8881-26e2a0112dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579717627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3579717627
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.179659490
Short name T683
Test name
Test status
Simulation time 50373934 ps
CPU time 1.58 seconds
Started Feb 07 05:04:30 PM PST 24
Finished Feb 07 05:04:32 PM PST 24
Peak memory 195264 kb
Host smart-6f7157d5-9138-4661-a8a5-1e4e8436b250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179659490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.179659490
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1791608320
Short name T470
Test name
Test status
Simulation time 157435540 ps
CPU time 0.98 seconds
Started Feb 07 05:04:27 PM PST 24
Finished Feb 07 05:04:29 PM PST 24
Peak memory 195932 kb
Host smart-5ffe58df-494f-4163-847a-d3a72ed248cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791608320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1791608320
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.111193231
Short name T428
Test name
Test status
Simulation time 19433034482 ps
CPU time 146.29 seconds
Started Feb 07 05:04:25 PM PST 24
Finished Feb 07 05:06:54 PM PST 24
Peak memory 197900 kb
Host smart-d0f6260a-d6fb-45f9-96cf-b1bead2d1985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111193231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.111193231
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.500322194
Short name T742
Test name
Test status
Simulation time 126677325376 ps
CPU time 2021.9 seconds
Started Feb 07 05:04:33 PM PST 24
Finished Feb 07 05:38:16 PM PST 24
Peak memory 198048 kb
Host smart-4d64c68c-e162-4c67-b934-d81cceb30b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=500322194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.500322194
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3131606183
Short name T750
Test name
Test status
Simulation time 62459848 ps
CPU time 0.61 seconds
Started Feb 07 05:04:35 PM PST 24
Finished Feb 07 05:04:36 PM PST 24
Peak memory 193864 kb
Host smart-a7c55d9d-0a9f-486a-8cea-8f3e81ab4b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131606183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3131606183
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1639123263
Short name T246
Test name
Test status
Simulation time 31416215 ps
CPU time 0.78 seconds
Started Feb 07 05:04:47 PM PST 24
Finished Feb 07 05:04:48 PM PST 24
Peak memory 194672 kb
Host smart-47c0fdd3-3070-4710-8049-0f71b97740ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639123263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1639123263
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4128240299
Short name T410
Test name
Test status
Simulation time 176830875 ps
CPU time 6.25 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:50 PM PST 24
Peak memory 196564 kb
Host smart-c1e85272-cdf6-48b1-9983-2422a293a3c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128240299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4128240299
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3918648076
Short name T871
Test name
Test status
Simulation time 51455609 ps
CPU time 0.88 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:44 PM PST 24
Peak memory 196452 kb
Host smart-5061d8eb-4adf-4cfb-ac75-dd3f450828ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918648076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3918648076
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2429862002
Short name T499
Test name
Test status
Simulation time 132158345 ps
CPU time 0.97 seconds
Started Feb 07 05:04:36 PM PST 24
Finished Feb 07 05:04:38 PM PST 24
Peak memory 195504 kb
Host smart-bd6eccee-3c41-421d-b54f-df5a21774f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429862002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2429862002
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4081646134
Short name T795
Test name
Test status
Simulation time 246644347 ps
CPU time 3.09 seconds
Started Feb 07 05:04:34 PM PST 24
Finished Feb 07 05:04:38 PM PST 24
Peak memory 197808 kb
Host smart-c8cb6ff4-c227-4ae8-b1e3-4d53362e7e97
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081646134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4081646134
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1957695541
Short name T661
Test name
Test status
Simulation time 129717618 ps
CPU time 2.69 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 197816 kb
Host smart-58c714e3-8e7e-4a02-8429-357cae1ec6f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957695541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1957695541
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.687665848
Short name T620
Test name
Test status
Simulation time 35508243 ps
CPU time 1.57 seconds
Started Feb 07 05:04:44 PM PST 24
Finished Feb 07 05:04:46 PM PST 24
Peak memory 197876 kb
Host smart-413cbfd0-fc83-497f-bbb6-c91990af40da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687665848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.687665848
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3726306086
Short name T841
Test name
Test status
Simulation time 21864769 ps
CPU time 0.82 seconds
Started Feb 07 05:04:38 PM PST 24
Finished Feb 07 05:04:39 PM PST 24
Peak memory 195956 kb
Host smart-c1425589-616a-49af-9a33-a33a941c4d50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726306086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3726306086
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1121286
Short name T531
Test name
Test status
Simulation time 409650425 ps
CPU time 5.48 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:49 PM PST 24
Peak memory 197788 kb
Host smart-172457d3-8a67-49c9-9620-2d02e7c5c4db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random
_long_reg_writes_reg_reads.1121286
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2229937690
Short name T838
Test name
Test status
Simulation time 124862176 ps
CPU time 1.13 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:45 PM PST 24
Peak memory 196148 kb
Host smart-26a7acef-3258-4399-898b-6c0735b54aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229937690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2229937690
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1812195604
Short name T302
Test name
Test status
Simulation time 36895910 ps
CPU time 0.87 seconds
Started Feb 07 05:04:38 PM PST 24
Finished Feb 07 05:04:40 PM PST 24
Peak memory 196264 kb
Host smart-f46a9c4c-bb41-4faa-a9ad-0d2a44e06eb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812195604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1812195604
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2484691730
Short name T485
Test name
Test status
Simulation time 2071536572 ps
CPU time 25.87 seconds
Started Feb 07 05:04:42 PM PST 24
Finished Feb 07 05:05:08 PM PST 24
Peak memory 197892 kb
Host smart-6bd0813d-7fe0-44b8-9155-56f56be819a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484691730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2484691730
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1068467477
Short name T262
Test name
Test status
Simulation time 29856853788 ps
CPU time 889.38 seconds
Started Feb 07 05:04:32 PM PST 24
Finished Feb 07 05:19:23 PM PST 24
Peak memory 198032 kb
Host smart-83d71e1d-6fb7-46aa-ae9f-cf752506b231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1068467477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1068467477
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3808788073
Short name T471
Test name
Test status
Simulation time 14538115 ps
CPU time 0.63 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:49 PM PST 24
Peak memory 193704 kb
Host smart-bc3be2dc-c130-446f-83f8-af1631521d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808788073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3808788073
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2236407527
Short name T353
Test name
Test status
Simulation time 136609885 ps
CPU time 0.92 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:46 PM PST 24
Peak memory 195112 kb
Host smart-4f50fe7f-2428-428a-9086-2d54f610e529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236407527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2236407527
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2701062486
Short name T623
Test name
Test status
Simulation time 873981537 ps
CPU time 14.37 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 197744 kb
Host smart-44e481c6-fb01-4391-bf18-2ee2a86c9c7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701062486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2701062486
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2624217746
Short name T758
Test name
Test status
Simulation time 83376949 ps
CPU time 1.14 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 196324 kb
Host smart-46766aae-94bf-4f79-9ea7-aaf117388051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624217746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2624217746
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.382515242
Short name T271
Test name
Test status
Simulation time 91844611 ps
CPU time 1.54 seconds
Started Feb 07 05:04:49 PM PST 24
Finished Feb 07 05:04:51 PM PST 24
Peak memory 197872 kb
Host smart-72c86e6a-c7ca-499e-a61b-a7e062eca759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382515242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.382515242
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1600427644
Short name T368
Test name
Test status
Simulation time 106312446 ps
CPU time 2.53 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:51 PM PST 24
Peak memory 197712 kb
Host smart-eda89c27-4321-4df6-8d9e-45ec7d53154d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600427644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1600427644
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.825429460
Short name T248
Test name
Test status
Simulation time 29534307 ps
CPU time 0.89 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:45 PM PST 24
Peak memory 194944 kb
Host smart-03eef781-64c9-4f32-b8d3-3b89dbd73bcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825429460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.825429460
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1068772579
Short name T226
Test name
Test status
Simulation time 105831901 ps
CPU time 1.05 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 195780 kb
Host smart-7b4b07a3-8f30-41a2-86a9-86e36fadfbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068772579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1068772579
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1027690722
Short name T691
Test name
Test status
Simulation time 176846368 ps
CPU time 0.71 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:46 PM PST 24
Peak memory 194924 kb
Host smart-4a0c8566-dfc1-493f-8ff1-5cdf277dca4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027690722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1027690722
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4016250846
Short name T501
Test name
Test status
Simulation time 255039413 ps
CPU time 4.8 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:50 PM PST 24
Peak memory 197736 kb
Host smart-deed1b56-dfd3-4bdd-97f0-b4a29702e6ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016250846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4016250846
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3479703076
Short name T739
Test name
Test status
Simulation time 81629456 ps
CPU time 0.85 seconds
Started Feb 07 05:04:30 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 196068 kb
Host smart-58d7180f-4392-4898-88a8-1c57d3d96c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479703076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3479703076
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1038742281
Short name T727
Test name
Test status
Simulation time 57908000 ps
CPU time 1.2 seconds
Started Feb 07 05:04:38 PM PST 24
Finished Feb 07 05:04:40 PM PST 24
Peak memory 195304 kb
Host smart-ab1a3d47-c5a9-43b4-87c7-021b93182bad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038742281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1038742281
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2642539559
Short name T669
Test name
Test status
Simulation time 52844343473 ps
CPU time 50.19 seconds
Started Feb 07 05:04:44 PM PST 24
Finished Feb 07 05:05:34 PM PST 24
Peak memory 197948 kb
Host smart-0f7841ac-e0f2-4728-a7a5-844408cab449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642539559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2642539559
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2997634108
Short name T233
Test name
Test status
Simulation time 57604525926 ps
CPU time 400.41 seconds
Started Feb 07 05:04:47 PM PST 24
Finished Feb 07 05:11:29 PM PST 24
Peak memory 198100 kb
Host smart-a3a98b55-47e1-41a6-83f4-c7bd033a7370
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2997634108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2997634108
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2106838380
Short name T794
Test name
Test status
Simulation time 16907774 ps
CPU time 0.59 seconds
Started Feb 07 05:04:46 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 193768 kb
Host smart-43392644-aade-4ea5-8f4e-64c0e08b5210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106838380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2106838380
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1058020334
Short name T288
Test name
Test status
Simulation time 14520515 ps
CPU time 0.69 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:49 PM PST 24
Peak memory 193692 kb
Host smart-8d0d2126-7ee6-4baa-9cdb-a36e579afa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058020334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1058020334
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1021155411
Short name T598
Test name
Test status
Simulation time 2520121513 ps
CPU time 18.4 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:05:04 PM PST 24
Peak memory 195548 kb
Host smart-3d3ccde9-e88a-46d7-876a-fd8584194928
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021155411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1021155411
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4006059111
Short name T769
Test name
Test status
Simulation time 33746467 ps
CPU time 0.75 seconds
Started Feb 07 05:04:44 PM PST 24
Finished Feb 07 05:04:45 PM PST 24
Peak memory 195628 kb
Host smart-c73e2d55-e80c-4c96-8f29-e577584e0aac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006059111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4006059111
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1760975220
Short name T770
Test name
Test status
Simulation time 54520245 ps
CPU time 0.78 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 194240 kb
Host smart-5410a7ce-670b-45bc-b318-1b1a90e0d7af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760975220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1760975220
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3040030503
Short name T296
Test name
Test status
Simulation time 75454703 ps
CPU time 1.78 seconds
Started Feb 07 05:04:47 PM PST 24
Finished Feb 07 05:04:49 PM PST 24
Peak memory 196420 kb
Host smart-853e9bd0-5c8a-4ac5-a51f-ef8718925a14
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040030503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3040030503
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2641255117
Short name T267
Test name
Test status
Simulation time 467275722 ps
CPU time 3.44 seconds
Started Feb 07 05:04:49 PM PST 24
Finished Feb 07 05:04:54 PM PST 24
Peak memory 196816 kb
Host smart-01a58124-a1e7-4631-b37c-da7fb9fdac8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641255117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2641255117
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4000070424
Short name T486
Test name
Test status
Simulation time 117464321 ps
CPU time 1.26 seconds
Started Feb 07 05:04:46 PM PST 24
Finished Feb 07 05:04:48 PM PST 24
Peak memory 196864 kb
Host smart-653e3fb6-ad83-4ce1-958f-f53fa664db5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000070424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4000070424
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2359637789
Short name T777
Test name
Test status
Simulation time 97022789 ps
CPU time 1.18 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 196636 kb
Host smart-a24921b2-36ae-4b73-97e7-9d940761cf11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359637789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2359637789
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3726064912
Short name T624
Test name
Test status
Simulation time 349931149 ps
CPU time 4.15 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:52 PM PST 24
Peak memory 197792 kb
Host smart-3e4a8b83-9768-41ab-a83a-e4f13244c752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726064912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3726064912
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3267248945
Short name T853
Test name
Test status
Simulation time 85646568 ps
CPU time 1.52 seconds
Started Feb 07 05:04:49 PM PST 24
Finished Feb 07 05:04:52 PM PST 24
Peak memory 196612 kb
Host smart-8044cb58-36a0-4652-92a9-370553a1218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267248945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3267248945
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1665426881
Short name T631
Test name
Test status
Simulation time 64074495 ps
CPU time 1.1 seconds
Started Feb 07 05:04:45 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 196064 kb
Host smart-60a99f58-bcea-4cda-acd0-775fe31ab17b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665426881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1665426881
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3290844727
Short name T561
Test name
Test status
Simulation time 45761222994 ps
CPU time 61.74 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:05:50 PM PST 24
Peak memory 197940 kb
Host smart-a2c59196-49a2-4e7d-9e18-8b81a975d700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290844727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3290844727
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1583921440
Short name T341
Test name
Test status
Simulation time 67784643655 ps
CPU time 496.45 seconds
Started Feb 07 05:04:44 PM PST 24
Finished Feb 07 05:13:01 PM PST 24
Peak memory 198068 kb
Host smart-0bccef7b-3340-4203-873f-bc5344a837a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1583921440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1583921440
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2295731546
Short name T876
Test name
Test status
Simulation time 12789521 ps
CPU time 0.63 seconds
Started Feb 07 05:05:01 PM PST 24
Finished Feb 07 05:05:02 PM PST 24
Peak memory 193816 kb
Host smart-858ab104-72f1-425d-b53c-fb2b990a49c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295731546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2295731546
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3598018806
Short name T275
Test name
Test status
Simulation time 29607819 ps
CPU time 0.69 seconds
Started Feb 07 05:04:49 PM PST 24
Finished Feb 07 05:04:50 PM PST 24
Peak memory 193884 kb
Host smart-25cd25d9-b715-404f-8b0b-ac9152d81111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598018806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3598018806
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1737798382
Short name T491
Test name
Test status
Simulation time 641529246 ps
CPU time 26.71 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:05:16 PM PST 24
Peak memory 197588 kb
Host smart-c9bd9fc5-c950-4769-80a0-b351ee98adb3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737798382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1737798382
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2755127559
Short name T731
Test name
Test status
Simulation time 135406243 ps
CPU time 0.79 seconds
Started Feb 07 05:05:00 PM PST 24
Finished Feb 07 05:05:01 PM PST 24
Peak memory 194472 kb
Host smart-358b4630-6311-4b0c-854d-13789bc53d6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755127559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2755127559
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1297199669
Short name T706
Test name
Test status
Simulation time 54306178 ps
CPU time 1.07 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:50 PM PST 24
Peak memory 196568 kb
Host smart-56bdaa1b-b98b-48d0-aead-3cb0663613e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297199669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1297199669
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2852203501
Short name T799
Test name
Test status
Simulation time 69991640 ps
CPU time 3.18 seconds
Started Feb 07 05:04:43 PM PST 24
Finished Feb 07 05:04:47 PM PST 24
Peak memory 197884 kb
Host smart-cce78920-fdac-45be-a714-e94b6add9d81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852203501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2852203501
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2209963876
Short name T263
Test name
Test status
Simulation time 1004843571 ps
CPU time 3.96 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:53 PM PST 24
Peak memory 197648 kb
Host smart-6d1dd89b-b746-46d0-84f8-54ecdf07cc94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209963876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2209963876
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2748379014
Short name T238
Test name
Test status
Simulation time 70834168 ps
CPU time 0.7 seconds
Started Feb 07 05:04:46 PM PST 24
Finished Feb 07 05:04:48 PM PST 24
Peak memory 194096 kb
Host smart-68c62ae5-03e1-4311-84ff-7e2ce202c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748379014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2748379014
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3436490238
Short name T800
Test name
Test status
Simulation time 229824937 ps
CPU time 1.4 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:50 PM PST 24
Peak memory 196848 kb
Host smart-93eee29c-6c8b-49fc-9f23-a1e9dd21f745
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436490238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3436490238
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.259454546
Short name T378
Test name
Test status
Simulation time 94197562 ps
CPU time 4.66 seconds
Started Feb 07 05:04:49 PM PST 24
Finished Feb 07 05:04:54 PM PST 24
Peak memory 197712 kb
Host smart-43703158-2206-4479-90da-80dcb0969428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259454546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.259454546
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1374964552
Short name T885
Test name
Test status
Simulation time 182351366 ps
CPU time 1.11 seconds
Started Feb 07 05:04:46 PM PST 24
Finished Feb 07 05:04:48 PM PST 24
Peak memory 195372 kb
Host smart-f52b3113-bb4c-485a-93ad-281de2369048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374964552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1374964552
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2034693966
Short name T299
Test name
Test status
Simulation time 275252983 ps
CPU time 1.38 seconds
Started Feb 07 05:04:48 PM PST 24
Finished Feb 07 05:04:50 PM PST 24
Peak memory 197784 kb
Host smart-8cd6abbc-b882-4e42-afb3-bbeb838dd1c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034693966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2034693966
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3341623060
Short name T475
Test name
Test status
Simulation time 3365706166 ps
CPU time 78.85 seconds
Started Feb 07 05:04:59 PM PST 24
Finished Feb 07 05:06:19 PM PST 24
Peak memory 197880 kb
Host smart-dda5b807-80a7-4f20-a800-8b90d26add91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341623060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3341623060
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3130504050
Short name T340
Test name
Test status
Simulation time 7815692799 ps
CPU time 122.25 seconds
Started Feb 07 05:04:55 PM PST 24
Finished Feb 07 05:06:58 PM PST 24
Peak memory 198104 kb
Host smart-23f9f3f4-0634-445a-8582-3107b94c43ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3130504050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3130504050
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.137886907
Short name T151
Test name
Test status
Simulation time 32726669 ps
CPU time 0.97 seconds
Started Feb 07 01:46:29 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 195840 kb
Host smart-3fba2a6c-839d-4559-8fe3-2948a3b69186
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=137886907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.137886907
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.414418087
Short name T206
Test name
Test status
Simulation time 66222819 ps
CPU time 1.26 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:32 PM PST 24
Peak memory 195744 kb
Host smart-7e9de888-80ef-4a37-a336-9390cc4dbaf7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414418087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.414418087
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4212212668
Short name T134
Test name
Test status
Simulation time 90099991 ps
CPU time 0.83 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:32 PM PST 24
Peak memory 196508 kb
Host smart-d95f0b29-c34c-4ca4-bb43-699691827440
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4212212668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4212212668
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2657506818
Short name T46
Test name
Test status
Simulation time 36862785 ps
CPU time 1 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:37 PM PST 24
Peak memory 196772 kb
Host smart-0eac3289-381f-4b92-a7e5-11a9ac815ca9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657506818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2657506818
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3693258074
Short name T149
Test name
Test status
Simulation time 46689388 ps
CPU time 1.22 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196808 kb
Host smart-df047903-022d-45d8-8f77-f56b35333bca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3693258074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3693258074
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2438802533
Short name T194
Test name
Test status
Simulation time 73484769 ps
CPU time 1.28 seconds
Started Feb 07 01:46:51 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 196900 kb
Host smart-6864a349-5cad-4b10-b356-133a4511fe09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438802533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2438802533
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1196259660
Short name T130
Test name
Test status
Simulation time 75962072 ps
CPU time 1.24 seconds
Started Feb 07 01:46:36 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 197940 kb
Host smart-1ebc2c64-fb2f-4bf0-92d0-fde5a26d1db5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1196259660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1196259660
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3519059882
Short name T167
Test name
Test status
Simulation time 46305210 ps
CPU time 1.31 seconds
Started Feb 07 01:46:51 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 198140 kb
Host smart-8f08b29f-7bdc-4ce6-a9cf-2bb8c4a8170f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519059882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3519059882
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.963867851
Short name T207
Test name
Test status
Simulation time 67139406 ps
CPU time 0.96 seconds
Started Feb 07 01:46:44 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196312 kb
Host smart-2381960f-97c3-4230-85bf-8182df236bec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=963867851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.963867851
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.259995385
Short name T138
Test name
Test status
Simulation time 289401855 ps
CPU time 1.46 seconds
Started Feb 07 01:46:41 PM PST 24
Finished Feb 07 01:46:43 PM PST 24
Peak memory 196872 kb
Host smart-ecb6bfff-5284-416f-8a97-e272656d673e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259995385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.259995385
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3833496366
Short name T45
Test name
Test status
Simulation time 50688043 ps
CPU time 1 seconds
Started Feb 07 01:46:34 PM PST 24
Finished Feb 07 01:46:36 PM PST 24
Peak memory 195612 kb
Host smart-bf4eefc9-dae0-439b-a705-d6533bf66933
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3833496366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3833496366
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1277966174
Short name T158
Test name
Test status
Simulation time 51944109 ps
CPU time 0.97 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 195472 kb
Host smart-2426acd3-9f94-4a64-aeda-765ed3973556
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277966174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1277966174
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2319470716
Short name T140
Test name
Test status
Simulation time 227247979 ps
CPU time 1.28 seconds
Started Feb 07 01:46:51 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 197116 kb
Host smart-bbdf72f7-adcf-4c1c-9bff-432f1437e9e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2319470716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2319470716
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2408440563
Short name T150
Test name
Test status
Simulation time 103808364 ps
CPU time 1.05 seconds
Started Feb 07 01:46:41 PM PST 24
Finished Feb 07 01:46:43 PM PST 24
Peak memory 198108 kb
Host smart-7fdf0a0c-84b5-4d25-b03f-d35d3e09682c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408440563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2408440563
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3176255392
Short name T182
Test name
Test status
Simulation time 115173475 ps
CPU time 0.89 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 195300 kb
Host smart-ce002f48-9e7a-46a2-aedd-313fb582ff91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3176255392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3176255392
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.242630858
Short name T165
Test name
Test status
Simulation time 20727252 ps
CPU time 0.72 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 194380 kb
Host smart-d543af97-4780-468b-8319-3f7c577fc340
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242630858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.242630858
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.709343243
Short name T145
Test name
Test status
Simulation time 99579661 ps
CPU time 0.95 seconds
Started Feb 07 01:46:40 PM PST 24
Finished Feb 07 01:46:42 PM PST 24
Peak memory 197228 kb
Host smart-fadb1221-c441-4341-959f-3a07b4afa4ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=709343243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.709343243
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.493693441
Short name T187
Test name
Test status
Simulation time 50277326 ps
CPU time 0.85 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 195548 kb
Host smart-795b99e2-df5f-4546-bda4-060ed853fee5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493693441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.493693441
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.729558812
Short name T185
Test name
Test status
Simulation time 460825570 ps
CPU time 1.08 seconds
Started Feb 07 01:46:52 PM PST 24
Finished Feb 07 01:46:54 PM PST 24
Peak memory 195992 kb
Host smart-f94e9cf7-a085-4dc0-a8c4-3b2d1570082e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=729558812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.729558812
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2344404787
Short name T164
Test name
Test status
Simulation time 144256236 ps
CPU time 1.31 seconds
Started Feb 07 01:46:51 PM PST 24
Finished Feb 07 01:46:53 PM PST 24
Peak memory 196056 kb
Host smart-52747f12-2cc8-4503-8677-7285f449be52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344404787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2344404787
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2853008039
Short name T155
Test name
Test status
Simulation time 108532968 ps
CPU time 0.8 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196132 kb
Host smart-29f7c6b4-d49e-474e-a8a6-15b87c285097
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2853008039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2853008039
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274525959
Short name T162
Test name
Test status
Simulation time 38567263 ps
CPU time 0.82 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 195384 kb
Host smart-53478b0e-5031-493e-9cff-cd8a5c4f3b05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274525959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2274525959
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1948411406
Short name T139
Test name
Test status
Simulation time 180474141 ps
CPU time 0.98 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196628 kb
Host smart-3ec7b011-6cba-4029-84d4-6a288182db75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1948411406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1948411406
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3004100741
Short name T183
Test name
Test status
Simulation time 38926217 ps
CPU time 0.92 seconds
Started Feb 07 01:46:40 PM PST 24
Finished Feb 07 01:46:42 PM PST 24
Peak memory 195552 kb
Host smart-767cd6e4-9fd3-4fc7-a599-34538cd00220
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004100741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3004100741
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2357119976
Short name T153
Test name
Test status
Simulation time 66544455 ps
CPU time 1.12 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 195820 kb
Host smart-cacd8d8b-06fe-47f8-9cf2-41d7b723a973
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2357119976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2357119976
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2239621825
Short name T47
Test name
Test status
Simulation time 85091155 ps
CPU time 1.33 seconds
Started Feb 07 01:46:36 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 196480 kb
Host smart-e9e0826e-3ac1-47c1-837d-691b7a4e5782
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239621825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2239621825
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.45312088
Short name T154
Test name
Test status
Simulation time 157907880 ps
CPU time 0.93 seconds
Started Feb 07 01:46:41 PM PST 24
Finished Feb 07 01:46:43 PM PST 24
Peak memory 195504 kb
Host smart-e937db74-9c67-43dd-a153-97ac50cdc29f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=45312088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.45312088
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2651179950
Short name T191
Test name
Test status
Simulation time 113047273 ps
CPU time 0.92 seconds
Started Feb 07 01:46:36 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 196216 kb
Host smart-b6a1ef85-6cea-4119-a70e-e5ab2528684d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651179950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2651179950
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.339354781
Short name T36
Test name
Test status
Simulation time 72746059 ps
CPU time 1.16 seconds
Started Feb 07 01:46:44 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196868 kb
Host smart-cd06f57f-b082-4d24-8771-9b2490ab640f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=339354781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.339354781
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.211316635
Short name T157
Test name
Test status
Simulation time 40051804 ps
CPU time 1.17 seconds
Started Feb 07 01:46:50 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 196452 kb
Host smart-360aeb62-7481-40e5-b3c8-03807fce0cd1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211316635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.211316635
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2690345712
Short name T190
Test name
Test status
Simulation time 358486339 ps
CPU time 1.25 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 197076 kb
Host smart-c9fa5e1c-73dd-49e6-90dc-825a21343293
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2690345712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2690345712
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.444938292
Short name T129
Test name
Test status
Simulation time 72921317 ps
CPU time 0.72 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 01:47:01 PM PST 24
Peak memory 195072 kb
Host smart-59158601-849b-4583-889d-f6459b930591
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444938292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.444938292
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3577528279
Short name T175
Test name
Test status
Simulation time 289879563 ps
CPU time 1.18 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 196544 kb
Host smart-30452b22-e004-4993-94d4-164d942e723c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3577528279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3577528279
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2544368765
Short name T51
Test name
Test status
Simulation time 147482034 ps
CPU time 1.01 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 01:47:01 PM PST 24
Peak memory 195768 kb
Host smart-a94f6546-854d-4517-8797-95d123126160
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544368765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2544368765
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.168530879
Short name T48
Test name
Test status
Simulation time 42842947 ps
CPU time 1.13 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 195952 kb
Host smart-d97ca7c8-2e4d-48de-8d9e-a23b60377a5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=168530879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.168530879
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1582725017
Short name T132
Test name
Test status
Simulation time 375726454 ps
CPU time 1.27 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 196872 kb
Host smart-764733e1-8bcd-4016-8890-6a5d003992b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582725017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1582725017
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2191502456
Short name T127
Test name
Test status
Simulation time 142945148 ps
CPU time 1.45 seconds
Started Feb 07 01:46:44 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 198068 kb
Host smart-a3894ad8-31a2-4c65-9606-d19068606687
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2191502456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2191502456
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3057716082
Short name T201
Test name
Test status
Simulation time 66024002 ps
CPU time 1.01 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 198064 kb
Host smart-269d6289-7335-4a80-ad90-8f0977ed5aa6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057716082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3057716082
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2926376656
Short name T199
Test name
Test status
Simulation time 112542394 ps
CPU time 1.49 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 196644 kb
Host smart-b7d00b87-3ae5-4dba-badf-3d71e403c9bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2926376656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2926376656
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.475078487
Short name T174
Test name
Test status
Simulation time 181115546 ps
CPU time 0.94 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196624 kb
Host smart-7fce0919-39c9-47c3-bfc2-14065e924807
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475078487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.475078487
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3110039643
Short name T188
Test name
Test status
Simulation time 102874325 ps
CPU time 0.93 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196516 kb
Host smart-ec3b8eec-1924-45a6-9993-2d1b227c5ab6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3110039643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3110039643
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463514430
Short name T133
Test name
Test status
Simulation time 145419641 ps
CPU time 0.93 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196256 kb
Host smart-d84eb3b7-fa69-4acb-b09b-f9cc76f1e491
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463514430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3463514430
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3514782024
Short name T202
Test name
Test status
Simulation time 59915904 ps
CPU time 1.09 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 01:47:01 PM PST 24
Peak memory 196528 kb
Host smart-d8f802e4-b326-447c-ba89-9b5c024b507e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3514782024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3514782024
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3220755397
Short name T213
Test name
Test status
Simulation time 142679946 ps
CPU time 0.87 seconds
Started Feb 07 01:46:50 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 195524 kb
Host smart-ee9839da-9391-4869-b881-abb5d0051ced
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220755397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3220755397
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2218660309
Short name T209
Test name
Test status
Simulation time 48959336 ps
CPU time 1.34 seconds
Started Feb 07 01:46:47 PM PST 24
Finished Feb 07 01:46:50 PM PST 24
Peak memory 195552 kb
Host smart-f36150a0-82e5-4cf9-a88a-c2129ee09023
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2218660309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2218660309
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1711091610
Short name T214
Test name
Test status
Simulation time 146901246 ps
CPU time 0.87 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:47:02 PM PST 24
Peak memory 195408 kb
Host smart-abc8e272-0b05-498e-ab95-7d2185ef2e38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711091610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1711091610
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1602874781
Short name T137
Test name
Test status
Simulation time 19382214 ps
CPU time 0.72 seconds
Started Feb 07 01:46:40 PM PST 24
Finished Feb 07 01:46:41 PM PST 24
Peak memory 194264 kb
Host smart-2ac7402b-0063-4316-bb85-5da042b0839f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1602874781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1602874781
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3898338931
Short name T176
Test name
Test status
Simulation time 466893863 ps
CPU time 1.32 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 198100 kb
Host smart-c860e9e5-ece5-46ee-8adc-ca056af770f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898338931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3898338931
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3706218904
Short name T156
Test name
Test status
Simulation time 144219024 ps
CPU time 1.04 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196612 kb
Host smart-0fae7fef-3c15-4b88-8787-db9ee99c6c7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3706218904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3706218904
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2981147662
Short name T198
Test name
Test status
Simulation time 53363299 ps
CPU time 1.4 seconds
Started Feb 07 01:46:48 PM PST 24
Finished Feb 07 01:46:51 PM PST 24
Peak memory 196700 kb
Host smart-ef56cfb0-6d35-4faa-bc8a-2acfe8270d78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981147662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2981147662
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3153868814
Short name T171
Test name
Test status
Simulation time 47794436 ps
CPU time 1.28 seconds
Started Feb 07 01:46:44 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196636 kb
Host smart-790c2f51-8a02-4ed0-9d04-9ed87b8519f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3153868814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3153868814
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4122199360
Short name T50
Test name
Test status
Simulation time 542565417 ps
CPU time 1.24 seconds
Started Feb 07 01:46:45 PM PST 24
Finished Feb 07 01:46:47 PM PST 24
Peak memory 198036 kb
Host smart-6721f755-ffdc-4761-af9b-1394c314139d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122199360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4122199360
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3403685719
Short name T35
Test name
Test status
Simulation time 223740187 ps
CPU time 0.85 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:43 PM PST 24
Peak memory 195400 kb
Host smart-bb8a7b68-97db-4b82-84a3-331c38fa7a01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3403685719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3403685719
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114899841
Short name T131
Test name
Test status
Simulation time 275632486 ps
CPU time 1.26 seconds
Started Feb 07 01:46:41 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 198048 kb
Host smart-abab8a4b-2f3f-4c1a-b934-80d2f3dd19be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114899841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3114899841
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3308228553
Short name T170
Test name
Test status
Simulation time 186220505 ps
CPU time 1 seconds
Started Feb 07 01:46:53 PM PST 24
Finished Feb 07 01:46:55 PM PST 24
Peak memory 195980 kb
Host smart-0434b04e-83fc-48a9-b186-264ea5fec86d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3308228553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3308228553
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.783471322
Short name T147
Test name
Test status
Simulation time 52889722 ps
CPU time 0.8 seconds
Started Feb 07 01:46:47 PM PST 24
Finished Feb 07 01:46:50 PM PST 24
Peak memory 194936 kb
Host smart-3eff93af-e7a5-4cd4-a2ae-aadc6ad3891f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783471322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.783471322
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4246336926
Short name T204
Test name
Test status
Simulation time 216099899 ps
CPU time 1.47 seconds
Started Feb 07 01:46:45 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 197372 kb
Host smart-f3e1047a-d671-4dd5-bafc-e5d3d8ccef59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4246336926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4246336926
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.400690669
Short name T146
Test name
Test status
Simulation time 27415488 ps
CPU time 0.93 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 196564 kb
Host smart-54ebd7c6-d301-40c9-8925-fe9bf1f4489c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400690669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.400690669
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3047565885
Short name T179
Test name
Test status
Simulation time 80216643 ps
CPU time 1.11 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 196588 kb
Host smart-d861fa6c-830a-4111-a726-017bf20bc637
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3047565885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3047565885
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.165981182
Short name T166
Test name
Test status
Simulation time 59574992 ps
CPU time 1.01 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 195912 kb
Host smart-151c47b6-9c8a-4f05-bd64-4306f17b071c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165981182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.165981182
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.121863481
Short name T163
Test name
Test status
Simulation time 283249354 ps
CPU time 1.31 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196864 kb
Host smart-aded38ed-ac40-4940-88e0-327e00698349
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=121863481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.121863481
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2372465663
Short name T173
Test name
Test status
Simulation time 131764004 ps
CPU time 1.09 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 196808 kb
Host smart-6c95f38d-40cb-4195-98ef-eb91537ffe98
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372465663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2372465663
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1807923599
Short name T142
Test name
Test status
Simulation time 541850098 ps
CPU time 1.16 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 195744 kb
Host smart-f11c308e-6254-48e2-a3a7-09405a0dfa02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1807923599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1807923599
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3266460145
Short name T184
Test name
Test status
Simulation time 33043727 ps
CPU time 1.02 seconds
Started Feb 07 01:46:47 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 198044 kb
Host smart-76d15c24-7c91-4067-9990-48234c268259
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3266460145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3266460145
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3869041462
Short name T196
Test name
Test status
Simulation time 213205773 ps
CPU time 1.16 seconds
Started Feb 07 01:46:41 PM PST 24
Finished Feb 07 01:46:43 PM PST 24
Peak memory 196760 kb
Host smart-b682437f-332e-4208-a75a-bc43b864a869
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869041462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3869041462
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.914005013
Short name T141
Test name
Test status
Simulation time 318701046 ps
CPU time 1.27 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:47:03 PM PST 24
Peak memory 195712 kb
Host smart-85018c07-3b59-427d-a2a1-94d7d7a1d25f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=914005013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.914005013
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539130923
Short name T169
Test name
Test status
Simulation time 344831347 ps
CPU time 1.31 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 197120 kb
Host smart-f1de113d-632a-4421-96f8-42ab5125474a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539130923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2539130923
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.618372224
Short name T99
Test name
Test status
Simulation time 24783038 ps
CPU time 0.8 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196172 kb
Host smart-afb86903-d7f0-414a-9611-3d6c135cc36c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=618372224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.618372224
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3058020008
Short name T180
Test name
Test status
Simulation time 161119866 ps
CPU time 1.2 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 195840 kb
Host smart-23601622-398d-48ed-9eaa-1b1a0ebe88e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058020008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3058020008
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.322145016
Short name T135
Test name
Test status
Simulation time 178538441 ps
CPU time 1.11 seconds
Started Feb 07 01:46:47 PM PST 24
Finished Feb 07 01:46:49 PM PST 24
Peak memory 198088 kb
Host smart-192d7172-a687-42ce-9bce-5680f7e51c04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=322145016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.322145016
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98098375
Short name T159
Test name
Test status
Simulation time 160838516 ps
CPU time 0.81 seconds
Started Feb 07 01:46:50 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 195348 kb
Host smart-9f1964d1-80d8-4999-b0c5-bb1aa4b92122
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98098375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.98098375
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1949468116
Short name T186
Test name
Test status
Simulation time 67240027 ps
CPU time 1.09 seconds
Started Feb 07 01:46:43 PM PST 24
Finished Feb 07 01:46:45 PM PST 24
Peak memory 195680 kb
Host smart-13e134f8-e914-445f-9e9e-33fe3a9dfea0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1949468116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1949468116
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3050512927
Short name T152
Test name
Test status
Simulation time 240504710 ps
CPU time 1.23 seconds
Started Feb 07 01:46:44 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196004 kb
Host smart-2bc01894-7c9a-482d-8b1f-0f9a77516fb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050512927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3050512927
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1116902923
Short name T172
Test name
Test status
Simulation time 257103872 ps
CPU time 1.14 seconds
Started Feb 07 01:46:45 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 196444 kb
Host smart-36632f57-4d6e-4725-b75c-2d137299a032
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1116902923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1116902923
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525547316
Short name T193
Test name
Test status
Simulation time 84535751 ps
CPU time 1.43 seconds
Started Feb 07 01:46:45 PM PST 24
Finished Feb 07 01:46:47 PM PST 24
Peak memory 196704 kb
Host smart-3155283a-ce6e-4fb6-ae7b-e6522b318ca4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525547316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3525547316
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3270777699
Short name T143
Test name
Test status
Simulation time 52290666 ps
CPU time 0.96 seconds
Started Feb 07 01:46:50 PM PST 24
Finished Feb 07 01:46:52 PM PST 24
Peak memory 196508 kb
Host smart-fcaa1314-2292-4e92-960a-8e05ecafd616
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3270777699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3270777699
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1660585989
Short name T192
Test name
Test status
Simulation time 201905044 ps
CPU time 1.01 seconds
Started Feb 07 01:46:44 PM PST 24
Finished Feb 07 01:46:46 PM PST 24
Peak memory 196728 kb
Host smart-c85a0bf5-51fd-4ec3-be4d-f0e8e276f0fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660585989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1660585989
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1332032942
Short name T178
Test name
Test status
Simulation time 48227741 ps
CPU time 1.04 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 195516 kb
Host smart-76681be0-8066-4bcc-ba6c-d40a3b235030
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1332032942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1332032942
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.530745417
Short name T211
Test name
Test status
Simulation time 82412646 ps
CPU time 1.06 seconds
Started Feb 07 01:46:59 PM PST 24
Finished Feb 07 01:47:02 PM PST 24
Peak memory 195876 kb
Host smart-5093bcc0-ad30-471b-93bd-3feb69e76979
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530745417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.530745417
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2113909663
Short name T148
Test name
Test status
Simulation time 700195656 ps
CPU time 1.51 seconds
Started Feb 07 01:46:48 PM PST 24
Finished Feb 07 01:46:51 PM PST 24
Peak memory 196396 kb
Host smart-9b87646d-e8b7-4e20-9f8b-8377c13c5674
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2113909663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2113909663
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1027824550
Short name T49
Test name
Test status
Simulation time 134111861 ps
CPU time 1.09 seconds
Started Feb 07 01:46:53 PM PST 24
Finished Feb 07 01:46:54 PM PST 24
Peak memory 196044 kb
Host smart-c1f110e0-eaab-47b1-9b37-d72611df5250
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027824550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1027824550
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1560769077
Short name T136
Test name
Test status
Simulation time 41926111 ps
CPU time 0.72 seconds
Started Feb 07 01:46:46 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 194356 kb
Host smart-c1eb5d6e-ab13-4b78-9dd1-636338174e8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1560769077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1560769077
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4039189879
Short name T160
Test name
Test status
Simulation time 160047970 ps
CPU time 1.03 seconds
Started Feb 07 01:46:58 PM PST 24
Finished Feb 07 01:46:59 PM PST 24
Peak memory 198052 kb
Host smart-fa231eb6-def6-47df-b016-0095be2d485d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039189879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4039189879
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1670295486
Short name T168
Test name
Test status
Simulation time 40138686 ps
CPU time 1.33 seconds
Started Feb 07 01:46:56 PM PST 24
Finished Feb 07 01:46:58 PM PST 24
Peak memory 197068 kb
Host smart-a010e78f-7c21-4df5-824e-26725ff7131a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1670295486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1670295486
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1752859056
Short name T189
Test name
Test status
Simulation time 183926798 ps
CPU time 1.01 seconds
Started Feb 07 01:46:52 PM PST 24
Finished Feb 07 01:46:54 PM PST 24
Peak memory 197852 kb
Host smart-86045a10-cd93-45d4-a7d2-a462938810d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752859056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1752859056
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2720992074
Short name T212
Test name
Test status
Simulation time 101039262 ps
CPU time 0.73 seconds
Started Feb 07 01:46:54 PM PST 24
Finished Feb 07 01:46:56 PM PST 24
Peak memory 194316 kb
Host smart-3f6ff49d-8607-49fd-9259-bc45c925aec8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720992074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2720992074
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3197497794
Short name T161
Test name
Test status
Simulation time 125886364 ps
CPU time 0.82 seconds
Started Feb 07 01:46:53 PM PST 24
Finished Feb 07 01:46:55 PM PST 24
Peak memory 195480 kb
Host smart-b57a7c87-ac73-4190-9b61-7ccafc145007
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197497794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3197497794
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1893704652
Short name T195
Test name
Test status
Simulation time 43724220 ps
CPU time 0.78 seconds
Started Feb 07 01:46:57 PM PST 24
Finished Feb 07 01:46:59 PM PST 24
Peak memory 196164 kb
Host smart-bdaf4b00-035c-4ea5-99de-94edf8ab2235
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893704652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1893704652
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.503725070
Short name T208
Test name
Test status
Simulation time 106127888 ps
CPU time 1.13 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:40 PM PST 24
Peak memory 198060 kb
Host smart-f1198854-4149-46ae-b798-91545eab256a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=503725070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.503725070
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1877461250
Short name T128
Test name
Test status
Simulation time 85536349 ps
CPU time 0.97 seconds
Started Feb 07 01:46:45 PM PST 24
Finished Feb 07 01:46:48 PM PST 24
Peak memory 196736 kb
Host smart-048c7c82-b2f9-47d7-b907-12b00ee85b57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877461250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1877461250
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2934491652
Short name T203
Test name
Test status
Simulation time 174005898 ps
CPU time 1.36 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:37 PM PST 24
Peak memory 196920 kb
Host smart-1c42a477-cd11-44db-8179-b653bbf9cbf3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2934491652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2934491652
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3207222444
Short name T197
Test name
Test status
Simulation time 54289083 ps
CPU time 0.93 seconds
Started Feb 07 01:46:42 PM PST 24
Finished Feb 07 01:46:44 PM PST 24
Peak memory 196704 kb
Host smart-f30b77de-89e5-405b-967c-74bc8dd9d18e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207222444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3207222444
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.617040232
Short name T205
Test name
Test status
Simulation time 30608559 ps
CPU time 1 seconds
Started Feb 07 01:46:36 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 196604 kb
Host smart-0927a6c9-21be-4f82-9040-a7a1afe62a49
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=617040232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.617040232
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1931419774
Short name T177
Test name
Test status
Simulation time 289850274 ps
CPU time 1.26 seconds
Started Feb 07 01:46:34 PM PST 24
Finished Feb 07 01:46:36 PM PST 24
Peak memory 196744 kb
Host smart-75933c67-4492-4446-a214-ec06de482b49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931419774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1931419774
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1688966679
Short name T200
Test name
Test status
Simulation time 697456506 ps
CPU time 0.83 seconds
Started Feb 07 01:46:40 PM PST 24
Finished Feb 07 01:46:41 PM PST 24
Peak memory 195332 kb
Host smart-0b11d526-f2eb-47bb-8d06-95bc31d4183f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1688966679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1688966679
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.243923125
Short name T181
Test name
Test status
Simulation time 44027818 ps
CPU time 1.12 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 196708 kb
Host smart-f1d8733a-d76b-4269-aa55-4c39bdb49635
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243923125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.243923125
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3133007067
Short name T210
Test name
Test status
Simulation time 316738390 ps
CPU time 1.32 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:37 PM PST 24
Peak memory 197992 kb
Host smart-945d0fbe-6973-4188-bb6b-7574067ec278
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3133007067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3133007067
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249240509
Short name T144
Test name
Test status
Simulation time 150410550 ps
CPU time 1.48 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 198104 kb
Host smart-43c4eb71-73a7-48c3-8bad-910042d3001d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249240509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.249240509
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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