Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3942518	1			T30	87102		T31	1		T32	1
all_pins[1]	3942518	1			T30	87102		T31	1		T32	1
all_pins[2]	3942518	1			T30	87102		T31	1		T32	1
all_pins[3]	3942518	1			T30	87102		T31	1		T32	1
all_pins[4]	3942518	1			T30	87102		T31	1		T32	1
all_pins[5]	3942518	1			T30	87102		T31	1		T32	1
all_pins[6]	3942518	1			T30	87102		T31	1		T32	1
all_pins[7]	3942518	1			T30	87102		T31	1		T32	1
all_pins[8]	3942518	1			T30	87102		T31	1		T32	1
all_pins[9]	3942518	1			T30	87102		T31	1		T32	1
all_pins[10]	3942518	1			T30	87102		T31	1		T32	1
all_pins[11]	3942518	1			T30	87102		T31	1		T32	1
all_pins[12]	3942518	1			T30	87102		T31	1		T32	1
all_pins[13]	3942518	1			T30	87102		T31	1		T32	1
all_pins[14]	3942518	1			T30	87102		T31	1		T32	1
all_pins[15]	3942518	1			T30	87102		T31	1		T32	1
all_pins[16]	3942518	1			T30	87102		T31	1		T32	1
all_pins[17]	3942518	1			T30	87102		T31	1		T32	1
all_pins[18]	3942518	1			T30	87102		T31	1		T32	1
all_pins[19]	3942518	1			T30	87102		T31	1		T32	1
all_pins[20]	3942518	1			T30	87102		T31	1		T32	1
all_pins[21]	3942518	1			T30	87102		T31	1		T32	1
all_pins[22]	3942518	1			T30	87102		T31	1		T32	1
all_pins[23]	3942518	1			T30	87102		T31	1		T32	1
all_pins[24]	3942518	1			T30	87102		T31	1		T32	1
all_pins[25]	3942518	1			T30	87102		T31	1		T32	1
all_pins[26]	3942518	1			T30	87102		T31	1		T32	1
all_pins[27]	3942518	1			T30	87102		T31	1		T32	1
all_pins[28]	3942518	1			T30	87102		T31	1		T32	1
all_pins[29]	3942518	1			T30	87102		T31	1		T32	1
all_pins[30]	3942518	1			T30	87102		T31	1		T32	1
all_pins[31]	3942518	1			T30	87102		T31	1		T32	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78253055	1			T30	172864		T31	32		T32	32
values[0x1]	47907521	1			T30	105861		T33	10053		T20	117
transitions[0x0=>0x1]	28676167	1			T30	634638		T33	6065		T20	95
transitions[0x1=>0x0]	28676010	1			T30	634637		T33	6064		T20	95

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2446563	1			T30	53618		T31	1		T32	1
all_pins[0]	values[0x1]	1495955	1			T30	33484		T33	337		T20	7
all_pins[0]	transitions[0x0=>0x1]	923948	1			T30	20383		T33	209		T20	6
all_pins[0]	transitions[0x1=>0x0]	927408	1			T30	20540		T33	205		T24	2
all_pins[1]	values[0x0]	2447116	1			T30	54507		T31	1		T32	1
all_pins[1]	values[0x1]	1495402	1			T30	32595		T33	317		T20	3
all_pins[1]	transitions[0x0=>0x1]	894682	1			T30	19379		T33	195		T20	1
all_pins[1]	transitions[0x1=>0x0]	895235	1			T30	20268		T33	215		T20	5
all_pins[2]	values[0x0]	2448968	1			T30	54551		T31	1		T32	1
all_pins[2]	values[0x1]	1493550	1			T30	32551		T33	304		T20	5
all_pins[2]	transitions[0x0=>0x1]	893294	1			T30	19467		T33	186		T20	5
all_pins[2]	transitions[0x1=>0x0]	895146	1			T30	19511		T33	199		T20	3
all_pins[3]	values[0x0]	2447345	1			T30	53359		T31	1		T32	1
all_pins[3]	values[0x1]	1495173	1			T30	33743		T33	299		T20	1
all_pins[3]	transitions[0x0=>0x1]	894341	1			T30	20430		T33	207		T24	4
all_pins[3]	transitions[0x1=>0x0]	892718	1			T30	19238		T33	212		T20	4
all_pins[4]	values[0x0]	2442869	1			T30	53809		T31	1		T32	1
all_pins[4]	values[0x1]	1499649	1			T30	33293		T33	274		T20	5
all_pins[4]	transitions[0x0=>0x1]	895831	1			T30	19304		T33	157		T20	4
all_pins[4]	transitions[0x1=>0x0]	891355	1			T30	19754		T33	182		T24	1
all_pins[5]	values[0x0]	2441836	1			T30	53872		T31	1		T32	1
all_pins[5]	values[0x1]	1500682	1			T30	33230		T33	361		T20	1
all_pins[5]	transitions[0x0=>0x1]	897309	1			T30	19662		T33	226		T24	5
all_pins[5]	transitions[0x1=>0x0]	896276	1			T30	19725		T33	139		T20	4
all_pins[6]	values[0x0]	2443012	1			T30	53540		T31	1		T32	1
all_pins[6]	values[0x1]	1499506	1			T30	33562		T33	363		T20	4
all_pins[6]	transitions[0x0=>0x1]	895390	1			T30	20220		T33	204		T20	4
all_pins[6]	transitions[0x1=>0x0]	896566	1			T30	19888		T33	202		T20	1
all_pins[7]	values[0x0]	2444943	1			T30	54478		T31	1		T32	1
all_pins[7]	values[0x1]	1497575	1			T30	32624		T33	335		T20	7
all_pins[7]	transitions[0x0=>0x1]	893204	1			T30	19833		T33	181		T20	7
all_pins[7]	transitions[0x1=>0x0]	895135	1			T30	20771		T33	209		T20	4
all_pins[8]	values[0x0]	2445789	1			T30	54746		T31	1		T32	1
all_pins[8]	values[0x1]	1496729	1			T30	32356		T33	333		T20	2
all_pins[8]	transitions[0x0=>0x1]	892076	1			T30	19451		T33	213		T20	1
all_pins[8]	transitions[0x1=>0x0]	892922	1			T30	19719		T33	215		T20	6
all_pins[9]	values[0x0]	2449848	1			T30	54304		T31	1		T32	1
all_pins[9]	values[0x1]	1492670	1			T30	32798		T33	354		T20	5
all_pins[9]	transitions[0x0=>0x1]	892692	1			T30	19934		T33	154		T20	5
all_pins[9]	transitions[0x1=>0x0]	896751	1			T30	19492		T33	133		T20	2
all_pins[10]	values[0x0]	2440858	1			T30	53644		T31	1		T32	1
all_pins[10]	values[0x1]	1501660	1			T30	33458		T33	421		T24	13
all_pins[10]	transitions[0x0=>0x1]	898011	1			T30	20029		T33	242		T25	92
all_pins[10]	transitions[0x1=>0x0]	889021	1			T30	19369		T33	175		T20	5
all_pins[11]	values[0x0]	2442548	1			T30	54547		T31	1		T32	1
all_pins[11]	values[0x1]	1499970	1			T30	32555		T33	218		T20	8
all_pins[11]	transitions[0x0=>0x1]	896384	1			T30	19418		T33	113		T20	8
all_pins[11]	transitions[0x1=>0x0]	898074	1			T30	20321		T33	316		T24	5
all_pins[12]	values[0x0]	2444676	1			T30	53752		T31	1		T32	1
all_pins[12]	values[0x1]	1497842	1			T30	33350		T33	348		T20	3
all_pins[12]	transitions[0x0=>0x1]	894395	1			T30	20186		T33	237		T24	5
all_pins[12]	transitions[0x1=>0x0]	896523	1			T30	19391		T33	107		T20	5
all_pins[13]	values[0x0]	2446157	1			T30	53306		T31	1		T32	1
all_pins[13]	values[0x1]	1496361	1			T30	33796		T33	390		T20	6
all_pins[13]	transitions[0x0=>0x1]	895083	1			T30	20406		T33	234		T20	3
all_pins[13]	transitions[0x1=>0x0]	896564	1			T30	19960		T33	192		T24	6
all_pins[14]	values[0x0]	2448126	1			T30	54886		T31	1		T32	1
all_pins[14]	values[0x1]	1494392	1			T30	32216		T33	320		T20	2
all_pins[14]	transitions[0x0=>0x1]	893108	1			T30	19316		T33	148		T24	3
all_pins[14]	transitions[0x1=>0x0]	895077	1			T30	20896		T33	218		T20	4
all_pins[15]	values[0x0]	2443796	1			T30	52954		T31	1		T32	1
all_pins[15]	values[0x1]	1498722	1			T30	34148		T33	333		T20	6
all_pins[15]	transitions[0x0=>0x1]	899376	1			T30	20605		T33	136		T20	5
all_pins[15]	transitions[0x1=>0x0]	895046	1			T30	18673		T33	123		T20	1
all_pins[16]	values[0x0]	2447224	1			T30	54048		T31	1		T32	1
all_pins[16]	values[0x1]	1495294	1			T30	33054		T33	307		T20	1
all_pins[16]	transitions[0x0=>0x1]	895606	1			T30	19672		T33	157		T20	1
all_pins[16]	transitions[0x1=>0x0]	899034	1			T30	20766		T33	183		T20	6
all_pins[17]	values[0x0]	2447092	1			T30	53680		T31	1		T32	1
all_pins[17]	values[0x1]	1495426	1			T30	33422		T33	290		T24	13
all_pins[17]	transitions[0x0=>0x1]	892928	1			T30	20236		T33	205		T24	11
all_pins[17]	transitions[0x1=>0x0]	892796	1			T30	19868		T33	222		T20	1
all_pins[18]	values[0x0]	2439783	1			T30	54060		T31	1		T32	1
all_pins[18]	values[0x1]	1502735	1			T30	33042		T33	331		T24	12
all_pins[18]	transitions[0x0=>0x1]	899230	1			T30	19455		T33	237		T24	6
all_pins[18]	transitions[0x1=>0x0]	891921	1			T30	19835		T33	196		T24	7
all_pins[19]	values[0x0]	2447316	1			T30	53553		T31	1		T32	1
all_pins[19]	values[0x1]	1495202	1			T30	33549		T33	313		T20	1
all_pins[19]	transitions[0x0=>0x1]	892715	1			T30	20216		T33	179		T20	1
all_pins[19]	transitions[0x1=>0x0]	900248	1			T30	19709		T33	197		T24	6
all_pins[20]	values[0x0]	2447231	1			T30	54003		T31	1		T32	1
all_pins[20]	values[0x1]	1495287	1			T30	33099		T33	273		T20	9
all_pins[20]	transitions[0x0=>0x1]	894155	1			T30	19683		T33	156		T20	9
all_pins[20]	transitions[0x1=>0x0]	894070	1			T30	20133		T33	196		T20	1
all_pins[21]	values[0x0]	2445816	1			T30	54951		T31	1		T32	1
all_pins[21]	values[0x1]	1496702	1			T30	32151		T33	261		T20	1
all_pins[21]	transitions[0x0=>0x1]	895687	1			T30	19736		T33	175		T24	8
all_pins[21]	transitions[0x1=>0x0]	894272	1			T30	20684		T33	187		T20	8
all_pins[22]	values[0x0]	2444326	1			T30	53791		T31	1		T32	1
all_pins[22]	values[0x1]	1498192	1			T30	33311		T33	248		T20	9
all_pins[22]	transitions[0x0=>0x1]	894337	1			T30	19959		T33	166		T20	8
all_pins[22]	transitions[0x1=>0x0]	892847	1			T30	18799		T33	179		T24	11
all_pins[23]	values[0x0]	2442369	1			T30	54215		T31	1		T32	1
all_pins[23]	values[0x1]	1500149	1			T30	32887		T33	321		T20	1
all_pins[23]	transitions[0x0=>0x1]	896584	1			T30	19242		T33	239		T24	7
all_pins[23]	transitions[0x1=>0x0]	894627	1			T30	19666		T33	166		T20	8
all_pins[24]	values[0x0]	2446722	1			T30	53862		T31	1		T32	1
all_pins[24]	values[0x1]	1495796	1			T30	33240		T33	252		T24	8
all_pins[24]	transitions[0x0=>0x1]	893656	1			T30	20306		T33	136		T24	4
all_pins[24]	transitions[0x1=>0x0]	898009	1			T30	19953		T33	205		T20	1
all_pins[25]	values[0x0]	2447100	1			T30	54441		T31	1		T32	1
all_pins[25]	values[0x1]	1495418	1			T30	32661		T33	248		T20	9
all_pins[25]	transitions[0x0=>0x1]	896643	1			T30	19429		T33	189		T20	9
all_pins[25]	transitions[0x1=>0x0]	897021	1			T30	20008		T33	193		T24	6
all_pins[26]	values[0x0]	2448678	1			T30	54366		T31	1		T32	1
all_pins[26]	values[0x1]	1493840	1			T30	32736		T33	324		T20	2
all_pins[26]	transitions[0x0=>0x1]	895562	1			T30	20074		T33	193		T20	1
all_pins[26]	transitions[0x1=>0x0]	897140	1			T30	19999		T33	117		T20	8
all_pins[27]	values[0x0]	2449015	1			T30	53641		T31	1		T32	1
all_pins[27]	values[0x1]	1493503	1			T30	33461		T33	301		T20	9
all_pins[27]	transitions[0x0=>0x1]	891901	1			T30	20291		T33	189		T20	7
all_pins[27]	transitions[0x1=>0x0]	892238	1			T30	19566		T33	212		T24	6
all_pins[28]	values[0x0]	2444320	1			T30	54505		T31	1		T32	1
all_pins[28]	values[0x1]	1498198	1			T30	32597		T33	430		T24	15
all_pins[28]	transitions[0x0=>0x1]	896712	1			T30	19095		T33	269		T24	11
all_pins[28]	transitions[0x1=>0x0]	892017	1			T30	19959		T33	140		T20	9
all_pins[29]	values[0x0]	2442559	1			T30	54173		T31	1		T32	1
all_pins[29]	values[0x1]	1499959	1			T30	32929		T33	291		T20	8
all_pins[29]	transitions[0x0=>0x1]	896547	1			T30	19837		T33	141		T20	8
all_pins[29]	transitions[0x1=>0x0]	894786	1			T30	19505		T33	280		T24	5
all_pins[30]	values[0x0]	2446108	1			T30	54025		T31	1		T32	1
all_pins[30]	values[0x1]	1496410	1			T30	33077		T33	222		T20	1
all_pins[30]	transitions[0x0=>0x1]	895414	1			T30	19608		T33	149		T20	1
all_pins[30]	transitions[0x1=>0x0]	898963	1			T30	19460		T33	218		T20	8
all_pins[31]	values[0x0]	2442946	1			T30	53460		T31	1		T32	1
all_pins[31]	values[0x1]	1499572	1			T30	33642		T33	334		T20	1
all_pins[31]	transitions[0x0=>0x1]	899366	1			T30	19776		T33	243		T20	1
all_pins[31]	transitions[0x1=>0x0]	896204	1			T30	19211		T33	131		T20	1