Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13744523	1			T30	246821		T31	276		T32	268
all_values[1]	13744523	1			T30	246821		T31	276		T32	268
all_values[2]	13744523	1			T30	246821		T31	276		T32	268
all_values[3]	13744523	1			T30	246821		T31	276		T32	268
all_values[4]	13744523	1			T30	246821		T31	276		T32	268
all_values[5]	13744523	1			T30	246821		T31	276		T32	268
all_values[6]	13744523	1			T30	246821		T31	276		T32	268
all_values[7]	13744523	1			T30	246821		T31	276		T32	268
all_values[8]	13744523	1			T30	246821		T31	276		T32	268
all_values[9]	13744523	1			T30	246821		T31	276		T32	268
all_values[10]	13744523	1			T30	246821		T31	276		T32	268
all_values[11]	13744523	1			T30	246821		T31	276		T32	268
all_values[12]	13744523	1			T30	246821		T31	276		T32	268
all_values[13]	13744523	1			T30	246821		T31	276		T32	268
all_values[14]	13744523	1			T30	246821		T31	276		T32	268
all_values[15]	13744523	1			T30	246821		T31	276		T32	268
all_values[16]	13744523	1			T30	246821		T31	276		T32	268
all_values[17]	13744523	1			T30	246821		T31	276		T32	268
all_values[18]	13744523	1			T30	246821		T31	276		T32	268
all_values[19]	13744523	1			T30	246821		T31	276		T32	268
all_values[20]	13744523	1			T30	246821		T31	276		T32	268
all_values[21]	13744523	1			T30	246821		T31	276		T32	268
all_values[22]	13744523	1			T30	246821		T31	276		T32	268
all_values[23]	13744523	1			T30	246821		T31	276		T32	268
all_values[24]	13744523	1			T30	246821		T31	276		T32	268
all_values[25]	13744523	1			T30	246821		T31	276		T32	268
all_values[26]	13744523	1			T30	246821		T31	276		T32	268
all_values[27]	13744523	1			T30	246821		T31	276		T32	268
all_values[28]	13744523	1			T30	246821		T31	276		T32	268
all_values[29]	13744523	1			T30	246821		T31	276		T32	268
all_values[30]	13744523	1			T30	246821		T31	276		T32	268
all_values[31]	13744523	1			T30	246821		T31	276		T32	268

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253024751

1

T30

395648

T31

8832

T32

8576

auto[1]

186799985

1

T30

394179

T33

38224

T20

309

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101052760

1

T30

767022

T31

8832

T32

8576

auto[1]

338771976

1

T30

713125

T33

71700

T20

794

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

434924230

1

T30

780115

T31

8832

T32

8576

auto[1]

4900506

1

T30

97118

T20

108

T29

116

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2615647	1			T30	11657		T31	276		T32	268
all_values[0]	auto[0]	auto[0]	auto[1]	5232734	1			T30	102400		T33	1065		T20	14
all_values[0]	auto[0]	auto[1]	auto[0]	543461	1			T30	11173		T33	100		T20	5
all_values[0]	auto[0]	auto[1]	auto[1]	5199312	1			T30	118523		T33	1191		T20	4
all_values[0]	auto[1]	auto[0]	auto[1]	76841	1			T30	1535		T20	2		T29	4
all_values[0]	auto[1]	auto[1]	auto[1]	76528	1			T30	1533		T20	2		T29	1
all_values[1]	auto[0]	auto[0]	auto[0]	2604325	1			T30	11189		T31	276		T32	268
all_values[1]	auto[0]	auto[0]	auto[1]	5246634	1			T30	111799		T33	1092		T20	24
all_values[1]	auto[0]	auto[1]	auto[0]	549745	1			T30	11479		T33	108		T20	5
all_values[1]	auto[0]	auto[1]	auto[1]	5190587	1			T30	109297		T33	1121		T20	3
all_values[1]	auto[1]	auto[0]	auto[1]	76987	1			T30	1557		T20	3		T29	4
all_values[1]	auto[1]	auto[1]	auto[1]	76245	1			T30	1500		T29	1		T35	1247
all_values[2]	auto[0]	auto[0]	auto[0]	2613774	1			T30	12666		T31	276		T32	268
all_values[2]	auto[0]	auto[0]	auto[1]	5210858	1			T30	108786		T33	1095		T20	14
all_values[2]	auto[0]	auto[1]	auto[0]	558988	1			T30	13318		T33	136		T20	4
all_values[2]	auto[0]	auto[1]	auto[1]	5207952	1			T30	109064		T33	1070		T20	3
all_values[2]	auto[1]	auto[0]	auto[1]	76696	1			T30	1556		T20	3		T29	2
all_values[2]	auto[1]	auto[1]	auto[1]	76255	1			T30	1431		T20	2		T29	1
all_values[3]	auto[0]	auto[0]	auto[0]	2609870	1			T30	11172		T31	276		T32	268
all_values[3]	auto[0]	auto[0]	auto[1]	5263147	1			T30	111653		T33	1195		T20	22
all_values[3]	auto[0]	auto[1]	auto[0]	545194	1			T30	12425		T33	62		T20	7
all_values[3]	auto[0]	auto[1]	auto[1]	5173467	1			T30	108456		T33	1073		T25	392
all_values[3]	auto[1]	auto[0]	auto[1]	76983	1			T30	1585		T20	3		T35	1287
all_values[3]	auto[1]	auto[1]	auto[1]	75862	1			T30	1530		T20	1		T29	1
all_values[4]	auto[0]	auto[0]	auto[0]	2608784	1			T30	12180		T31	276		T32	268
all_values[4]	auto[0]	auto[0]	auto[1]	5211163	1			T30	108163		T33	1311		T20	20
all_values[4]	auto[0]	auto[1]	auto[0]	546784	1			T30	12253		T33	76		T20	4
all_values[4]	auto[0]	auto[1]	auto[1]	5224560	1			T30	111161		T33	906		T20	2
all_values[4]	auto[1]	auto[0]	auto[1]	76902	1			T30	1545		T20	2		T29	3
all_values[4]	auto[1]	auto[1]	auto[1]	76330	1			T30	1519		T20	2		T29	2
all_values[5]	auto[0]	auto[0]	auto[0]	2614868	1			T30	12177		T31	276		T32	268
all_values[5]	auto[0]	auto[0]	auto[1]	5214163	1			T30	113198		T33	1163		T20	24
all_values[5]	auto[0]	auto[1]	auto[0]	550058	1			T30	11533		T33	83		T20	2
all_values[5]	auto[0]	auto[1]	auto[1]	5212487	1			T30	106894		T33	1156		T25	449
all_values[5]	auto[1]	auto[0]	auto[1]	76795	1			T30	1530		T20	3		T29	2
all_values[5]	auto[1]	auto[1]	auto[1]	76152	1			T30	1489		T20	1		T35	1257
all_values[6]	auto[0]	auto[0]	auto[0]	2602801	1			T30	13464		T31	276		T32	268
all_values[6]	auto[0]	auto[0]	auto[1]	5200973	1			T30	108665		T33	1082		T20	26
all_values[6]	auto[0]	auto[1]	auto[0]	542833	1			T30	11243		T33	77		T20	4
all_values[6]	auto[0]	auto[1]	auto[1]	5244529	1			T30	110419		T33	1207		T20	3
all_values[6]	auto[1]	auto[0]	auto[1]	76557	1			T30	1452		T20	4		T29	4
all_values[6]	auto[1]	auto[1]	auto[1]	76830	1			T30	1578		T20	1		T29	4
all_values[7]	auto[0]	auto[0]	auto[0]	2604566	1			T30	13118		T31	276		T32	268
all_values[7]	auto[0]	auto[0]	auto[1]	5210146	1			T30	112400		T33	1063		T20	12
all_values[7]	auto[0]	auto[1]	auto[0]	541780	1			T30	11407		T33	88		T20	15
all_values[7]	auto[0]	auto[1]	auto[1]	5234745	1			T30	106959		T33	1145		T20	7
all_values[7]	auto[1]	auto[0]	auto[1]	76804	1			T30	1536		T20	1		T29	2
all_values[7]	auto[1]	auto[1]	auto[1]	76482	1			T30	1401		T20	1		T29	3
all_values[8]	auto[0]	auto[0]	auto[0]	2606170	1			T30	11801		T31	276		T32	268
all_values[8]	auto[0]	auto[0]	auto[1]	5224765	1			T30	115589		T33	1112		T20	10
all_values[8]	auto[0]	auto[1]	auto[0]	550030	1			T30	11448		T33	112		T20	15
all_values[8]	auto[0]	auto[1]	auto[1]	5210768	1			T30	104895		T33	1150		T25	341
all_values[8]	auto[1]	auto[0]	auto[1]	76830	1			T30	1576		T20	3		T29	1
all_values[8]	auto[1]	auto[1]	auto[1]	75960	1			T30	1512		T20	2		T35	1202
all_values[9]	auto[0]	auto[0]	auto[0]	2622655	1			T30	11161		T31	276		T32	268
all_values[9]	auto[0]	auto[0]	auto[1]	5239391	1			T30	112797		T33	1110		T20	19
all_values[9]	auto[0]	auto[1]	auto[0]	551943	1			T30	11165		T33	46		T20	8
all_values[9]	auto[0]	auto[1]	auto[1]	5177030	1			T30	108670		T33	1244		T20	4
all_values[9]	auto[1]	auto[0]	auto[1]	77233	1			T30	1543		T20	2		T29	5
all_values[9]	auto[1]	auto[1]	auto[1]	76271	1			T30	1485		T20	2		T35	1269
all_values[10]	auto[0]	auto[0]	auto[0]	2601613	1			T30	12313		T31	276		T32	268
all_values[10]	auto[0]	auto[0]	auto[1]	5234076	1			T30	110338		T33	834		T20	30
all_values[10]	auto[0]	auto[1]	auto[0]	540527	1			T30	12208		T33	92		T20	6
all_values[10]	auto[0]	auto[1]	auto[1]	5215048	1			T30	108945		T33	1460		T25	485
all_values[10]	auto[1]	auto[0]	auto[1]	76395	1			T30	1475		T20	3		T29	2
all_values[10]	auto[1]	auto[1]	auto[1]	76864	1			T30	1542		T35	1233		T119	15
all_values[11]	auto[0]	auto[0]	auto[0]	2609419	1			T30	11792		T31	276		T32	268
all_values[11]	auto[0]	auto[0]	auto[1]	5248767	1			T30	114712		T33	1390		T20	23
all_values[11]	auto[0]	auto[1]	auto[0]	549656	1			T30	13409		T33	86		T20	5
all_values[11]	auto[0]	auto[1]	auto[1]	5183338	1			T30	103938		T33	815		T20	8
all_values[11]	auto[1]	auto[0]	auto[1]	76889	1			T30	1526		T20	3		T29	3
all_values[11]	auto[1]	auto[1]	auto[1]	76454	1			T30	1444		T20	1		T35	1237
all_values[12]	auto[0]	auto[0]	auto[0]	2607919	1			T30	12496		T31	276		T32	268
all_values[12]	auto[0]	auto[0]	auto[1]	5194415	1			T30	110379		T33	1107		T20	25
all_values[12]	auto[0]	auto[1]	auto[0]	547075	1			T30	11223		T33	68		T20	2
all_values[12]	auto[0]	auto[1]	auto[1]	5241595	1			T30	109722		T33	1221		T20	3
all_values[12]	auto[1]	auto[0]	auto[1]	76533	1			T30	1435		T20	2		T29	6
all_values[12]	auto[1]	auto[1]	auto[1]	76986	1			T30	1566		T29	1		T35	1204
all_values[13]	auto[0]	auto[0]	auto[0]	2610127	1			T30	11462		T31	276		T32	268
all_values[13]	auto[0]	auto[0]	auto[1]	5213311	1			T30	111369		T33	1021		T20	15
all_values[13]	auto[0]	auto[1]	auto[0]	552236	1			T30	11640		T33	117		T20	3
all_values[13]	auto[0]	auto[1]	auto[1]	5215853	1			T30	109308		T33	1219		T20	4
all_values[13]	auto[1]	auto[0]	auto[1]	76992	1			T30	1526		T20	2		T35	1188
all_values[13]	auto[1]	auto[1]	auto[1]	76004	1			T30	1516		T20	1		T29	2
all_values[14]	auto[0]	auto[0]	auto[0]	2606454	1			T30	12344		T31	276		T32	268
all_values[14]	auto[0]	auto[0]	auto[1]	5231682	1			T30	110758		T33	1125		T20	28
all_values[14]	auto[0]	auto[1]	auto[0]	544919	1			T30	12200		T33	118		T20	6
all_values[14]	auto[0]	auto[1]	auto[1]	5207811	1			T30	108433		T33	1120		T20	1
all_values[14]	auto[1]	auto[0]	auto[1]	76711	1			T30	1589		T20	2		T29	2
all_values[14]	auto[1]	auto[1]	auto[1]	76946	1			T30	1497		T20	1		T29	2
all_values[15]	auto[0]	auto[0]	auto[0]	2598736	1			T30	12400		T31	276		T32	268
all_values[15]	auto[0]	auto[0]	auto[1]	5236055	1			T30	103668		T33	1099		T20	26
all_values[15]	auto[0]	auto[1]	auto[0]	551838	1			T30	13016		T33	112		T20	3
all_values[15]	auto[0]	auto[1]	auto[1]	5204923	1			T30	114684		T33	1180		T20	5
all_values[15]	auto[1]	auto[0]	auto[1]	76627	1			T30	1378		T20	1		T29	5
all_values[15]	auto[1]	auto[1]	auto[1]	76344	1			T30	1675		T20	1		T29	1
all_values[16]	auto[0]	auto[0]	auto[0]	2602752	1			T30	12880		T31	276		T32	268
all_values[16]	auto[0]	auto[0]	auto[1]	5240700	1			T30	108792		T33	1240		T20	19
all_values[16]	auto[0]	auto[1]	auto[0]	552979	1			T30	11894		T33	93		T20	4
all_values[16]	auto[0]	auto[1]	auto[1]	5195029	1			T30	110174		T33	1000		T25	452
all_values[16]	auto[1]	auto[0]	auto[1]	77112	1			T30	1570		T20	1		T29	2
all_values[16]	auto[1]	auto[1]	auto[1]	75951	1			T30	1511		T20	1		T29	2
all_values[17]	auto[0]	auto[0]	auto[0]	2609043	1			T30	12576		T31	276		T32	268
all_values[17]	auto[0]	auto[0]	auto[1]	5214222	1			T30	108060		T33	1182		T20	19
all_values[17]	auto[0]	auto[1]	auto[0]	550040	1			T30	12700		T33	58		T20	3
all_values[17]	auto[0]	auto[1]	auto[1]	5218353	1			T30	110466		T33	1078		T25	305
all_values[17]	auto[1]	auto[0]	auto[1]	76840	1			T30	1448		T20	3		T29	2
all_values[17]	auto[1]	auto[1]	auto[1]	76025	1			T30	1571		T29	1		T35	1193
all_values[18]	auto[0]	auto[0]	auto[0]	2601987	1			T30	12414		T31	276		T32	268
all_values[18]	auto[0]	auto[0]	auto[1]	5222634	1			T30	111437		T33	1133		T20	29
all_values[18]	auto[0]	auto[1]	auto[0]	547205	1			T30	12297		T33	76		T25	13
all_values[18]	auto[0]	auto[1]	auto[1]	5219914	1			T30	107676		T33	1155		T25	419
all_values[18]	auto[1]	auto[0]	auto[1]	76493	1			T30	1458		T20	2		T29	1
all_values[18]	auto[1]	auto[1]	auto[1]	76290	1			T30	1539		T29	1		T35	1295
all_values[19]	auto[0]	auto[0]	auto[0]	2610319	1			T30	12303		T31	276		T32	268
all_values[19]	auto[0]	auto[0]	auto[1]	5245735	1			T30	110290		T33	979		T20	16
all_values[19]	auto[0]	auto[1]	auto[0]	550041	1			T30	11879		T33	143		T20	8
all_values[19]	auto[0]	auto[1]	auto[1]	5185085	1			T30	109340		T33	1151		T25	474
all_values[19]	auto[1]	auto[0]	auto[1]	76314	1			T30	1483		T20	2		T29	3
all_values[19]	auto[1]	auto[1]	auto[1]	77029	1			T30	1526		T20	1		T29	1
all_values[20]	auto[0]	auto[0]	auto[0]	2608237	1			T30	10712		T31	276		T32	268
all_values[20]	auto[0]	auto[0]	auto[1]	5197502	1			T30	113146		T33	1218		T20	18
all_values[20]	auto[0]	auto[1]	auto[0]	555723	1			T30	12279		T33	96		T20	2
all_values[20]	auto[0]	auto[1]	auto[1]	5229584	1			T30	107641		T33	1043		T20	12
all_values[20]	auto[1]	auto[0]	auto[1]	76551	1			T30	1559		T20	1		T29	4
all_values[20]	auto[1]	auto[1]	auto[1]	76926	1			T30	1484		T20	1		T35	1238
all_values[21]	auto[0]	auto[0]	auto[0]	2611133	1			T30	12325		T31	276		T32	268
all_values[21]	auto[0]	auto[0]	auto[1]	5209192	1			T30	108692		T33	1184		T20	22
all_values[21]	auto[0]	auto[1]	auto[0]	555313	1			T30	11873		T33	125		T20	5
all_values[21]	auto[0]	auto[1]	auto[1]	5215989	1			T30	110873		T33	923		T25	430
all_values[21]	auto[1]	auto[0]	auto[1]	76528	1			T30	1493		T20	3		T35	1261
all_values[21]	auto[1]	auto[1]	auto[1]	76368	1			T30	1565		T20	1		T29	2
all_values[22]	auto[0]	auto[0]	auto[0]	2604374	1			T30	11681		T31	276		T32	268
all_values[22]	auto[0]	auto[0]	auto[1]	5232082	1			T30	106785		T33	1308		T20	17
all_values[22]	auto[0]	auto[1]	auto[0]	553800	1			T30	11704		T33	49		T20	8
all_values[22]	auto[0]	auto[1]	auto[1]	5201225	1			T30	113614		T33	921		T20	8
all_values[22]	auto[1]	auto[0]	auto[1]	76877	1			T30	1526		T20	2		T29	3
all_values[22]	auto[1]	auto[1]	auto[1]	76165	1			T30	1511		T20	2		T29	1
all_values[23]	auto[0]	auto[0]	auto[0]	2607360	1			T30	12617		T31	276		T32	268
all_values[23]	auto[0]	auto[0]	auto[1]	5209555	1			T30	110531		T33	1077		T20	16
all_values[23]	auto[0]	auto[1]	auto[0]	555544	1			T30	12061		T33	127		T20	4
all_values[23]	auto[0]	auto[1]	auto[1]	5218765	1			T30	108569		T33	1133		T20	2
all_values[23]	auto[1]	auto[0]	auto[1]	76583	1			T30	1497		T20	5		T29	1
all_values[23]	auto[1]	auto[1]	auto[1]	76716	1			T30	1546		T29	1		T35	1220
all_values[24]	auto[0]	auto[0]	auto[0]	2609628	1			T30	11440		T31	276		T32	268
all_values[24]	auto[0]	auto[0]	auto[1]	5231860	1			T30	107717		T33	1172		T20	6
all_values[24]	auto[0]	auto[1]	auto[0]	538307	1			T30	11159		T33	64		T25	21
all_values[24]	auto[0]	auto[1]	auto[1]	5211702	1			T30	113498		T33	1043		T25	562
all_values[24]	auto[1]	auto[0]	auto[1]	76497	1			T30	1440		T20	5		T35	1327
all_values[24]	auto[1]	auto[1]	auto[1]	76529	1			T30	1567		T29	4		T35	1186
all_values[25]	auto[0]	auto[0]	auto[0]	2611561	1			T30	12014		T31	276		T32	268
all_values[25]	auto[0]	auto[0]	auto[1]	5203566	1			T30	111056		T33	1309		T20	19
all_values[25]	auto[0]	auto[1]	auto[0]	555985	1			T30	11645		T33	91		T20	13
all_values[25]	auto[0]	auto[1]	auto[1]	5219998	1			T30	109092		T33	867		T20	8
all_values[25]	auto[1]	auto[0]	auto[1]	76807	1			T30	1527		T20	1		T29	1
all_values[25]	auto[1]	auto[1]	auto[1]	76606	1			T30	1487		T20	2		T29	1
all_values[26]	auto[0]	auto[0]	auto[0]	2618107	1			T30	11435		T31	276		T32	268
all_values[26]	auto[0]	auto[0]	auto[1]	5222381	1			T30	112451		T33	1115		T20	19
all_values[26]	auto[0]	auto[1]	auto[0]	551570	1			T30	11017		T33	86		T20	7
all_values[26]	auto[0]	auto[1]	auto[1]	5199169	1			T30	108916		T33	1121		T20	1
all_values[26]	auto[1]	auto[0]	auto[1]	76933	1			T30	1495		T20	1		T29	2
all_values[26]	auto[1]	auto[1]	auto[1]	76363	1			T30	1507		T20	1		T29	2
all_values[27]	auto[0]	auto[0]	auto[0]	2615880	1			T30	12423		T31	276		T32	268
all_values[27]	auto[0]	auto[0]	auto[1]	5205854	1			T30	106888		T33	1163		T20	16
all_values[27]	auto[0]	auto[1]	auto[0]	543819	1			T30	11618		T33	51		T20	5
all_values[27]	auto[0]	auto[1]	auto[1]	5225743	1			T30	112896		T33	1102		T20	10
all_values[27]	auto[1]	auto[0]	auto[1]	77093	1			T30	1438		T20	3		T29	3
all_values[27]	auto[1]	auto[1]	auto[1]	76134	1			T30	1558		T20	2		T35	1118
all_values[28]	auto[0]	auto[0]	auto[0]	2604098	1			T30	12778		T31	276		T32	268
all_values[28]	auto[0]	auto[0]	auto[1]	5215678	1			T30	109567		T33	833		T20	11
all_values[28]	auto[0]	auto[1]	auto[0]	552078	1			T30	13093		T33	127		T20	11
all_values[28]	auto[0]	auto[1]	auto[1]	5219630	1			T30	108266		T33	1417		T25	512
all_values[28]	auto[1]	auto[0]	auto[1]	76826	1			T30	1483		T20	3		T29	1
all_values[28]	auto[1]	auto[1]	auto[1]	76213	1			T30	1634		T29	1		T35	1161
all_values[29]	auto[0]	auto[0]	auto[0]	2605623	1			T30	12129		T31	276		T32	268
all_values[29]	auto[0]	auto[0]	auto[1]	5210486	1			T30	113794		T33	1196		T20	11
all_values[29]	auto[0]	auto[1]	auto[0]	548608	1			T30	10651		T33	146		T20	3
all_values[29]	auto[0]	auto[1]	auto[1]	5227015	1			T30	107163		T33	997		T20	7
all_values[29]	auto[1]	auto[0]	auto[1]	76865	1			T30	1623		T29	2		T35	1194
all_values[29]	auto[1]	auto[1]	auto[1]	75926	1			T30	1461		T20	1		T29	3
all_values[30]	auto[0]	auto[0]	auto[0]	2610278	1			T30	11309		T31	276		T32	268
all_values[30]	auto[0]	auto[0]	auto[1]	5206392	1			T30	110179		T33	1374		T20	14
all_values[30]	auto[0]	auto[1]	auto[0]	553038	1			T30	11469		T33	84		T20	7
all_values[30]	auto[0]	auto[1]	auto[1]	5222128	1			T30	110894		T33	817		T25	445
all_values[30]	auto[1]	auto[0]	auto[1]	76368	1			T30	1499		T20	2		T29	2
all_values[30]	auto[1]	auto[1]	auto[1]	76319	1			T30	1471		T20	1		T29	2
all_values[31]	auto[0]	auto[0]	auto[0]	2603848	1			T30	11262		T31	276		T32	268
all_values[31]	auto[0]	auto[0]	auto[1]	5216402	1			T30	106292		T33	1105		T20	7
all_values[31]	auto[0]	auto[1]	auto[0]	549687	1			T30	12853		T33	79		T20	8
all_values[31]	auto[0]	auto[1]	auto[1]	5221615	1			T30	113335		T33	1202		T25	459
all_values[31]	auto[1]	auto[0]	auto[1]	76812	1			T30	1557		T20	3		T29	3
all_values[31]	auto[1]	auto[1]	auto[1]	76159	1			T30	1522		T20	1		T35	1297

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal