Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[1]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[2]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[3]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[4]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[5]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[6]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[7]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[8]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[9]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[10]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[11]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[12]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[13]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[14]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[15]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[16]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[17]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[18]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[19]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[20]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[21]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[22]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[23]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[24]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[25]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[26]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[27]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[28]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[29]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[30]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[31]	13571250	1			T30	241290		T31	535		T32	416

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

264501404

1

T30

507121

T31

13394

T32

9025

auto[1]

169778596

1

T30

265007

T31

3726

T32

4287

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

348152278

1

T30

604051

T31

13049

T32

8544

auto[1]

86127722

1

T30

168076

T31

4071

T32

4768

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322747723

1

T30

550055

T31

8653

T32

8563

auto[1]

111532277

1

T30

222072

T31

8467

T32

4749

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5120334	1			T30	92254		T31	189		T32	144
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3613504	1			T30	53686		T31	32		T32	51
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1356158	1			T30	26742		T31	53		T32	74
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1793227	1			T30	39928		T31	176		T32	61
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	344764	1			T30	2969		T31	25		T20	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1343263	1			T30	25711		T31	60		T32	86
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5105093	1			T30	92987		T31	153		T32	148
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3618053	1			T30	53423		T31	16		T32	59
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1353182	1			T30	26398		T31	57		T32	89
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1799796	1			T30	39402		T31	224		T32	60
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	347791	1			T30	3003		T31	29		T20	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1347335	1			T30	26077		T31	56		T32	60
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5117163	1			T30	91659		T31	206		T32	158
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3618847	1			T30	53712		T31	43		T32	57
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1353287	1			T30	25957		T31	58		T32	89
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1796529	1			T30	40488		T31	187		T32	60
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	345157	1			T30	2993		T31	19		T20	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1340267	1			T30	26481		T31	22		T32	52
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5121435	1			T30	92793		T31	170		T32	120
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3603906	1			T30	53616		T31	29		T32	61
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1353892	1			T30	27124		T31	55		T32	88
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1792935	1			T30	38596		T31	194		T32	58
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	348533	1			T30	3000		T31	32		T20	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1350549	1			T30	26161		T31	55		T32	89
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5112548	1			T30	91981		T31	157		T32	131
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3617469	1			T30	53583		T31	28		T32	58
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1350605	1			T30	26544		T31	50		T32	51
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1800888	1			T30	39765		T31	185		T32	86
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	348646	1			T30	2948		T31	24		T20	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1341094	1			T30	26469		T31	91		T32	90
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5104688	1			T30	91697		T31	212		T32	178
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3625413	1			T30	53567		T31	31		T32	50
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1355151	1			T30	26376		T31	93		T32	64
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1794825	1			T30	39720		T31	126		T32	68
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	346926	1			T30	2999		T31	25		T20	9
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1344247	1			T30	26931		T31	48		T32	56
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5115481	1			T30	91051		T31	121		T32	104
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3616980	1			T30	53400		T31	16		T32	57
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1354309	1			T30	26714		T31	96		T32	95
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1795591	1			T30	40904		T31	162		T32	66
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	346288	1			T30	3157		T31	39		T20	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1342601	1			T30	26064		T31	101		T32	94
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5108014	1			T30	92604		T31	166		T32	152
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3619355	1			T30	53417		T31	43		T32	49
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1351372	1			T30	26325		T31	109		T32	75
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1802167	1			T30	39983		T31	150		T32	62
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	345988	1			T30	3102		T31	21		T20	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1344354	1			T30	25859		T31	46		T32	78
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5108986	1			T30	91632		T31	125		T32	150
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3618234	1			T30	53524		T31	13		T32	53
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1353171	1			T30	26351		T31	29		T32	70
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1801916	1			T30	40299		T31	268		T32	60
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	345448	1			T30	3056		T31	41		T20	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1343495	1			T30	26428		T31	59		T32	83
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5102563	1			T30	91511		T31	252		T32	117
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3629421	1			T30	53609		T31	27		T32	68
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1350006	1			T30	26581		T31	49		T32	80
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1799083	1			T30	39965		T31	150		T32	74
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	346043	1			T30	2975		T31	26		T20	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1344134	1			T30	26649		T31	31		T32	77
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5113265	1			T30	91434		T31	218		T32	111
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3621664	1			T30	53475		T31	40		T32	59
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1348603	1			T30	26520		T31	66		T32	74
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1800398	1			T30	40481		T31	142		T32	94
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	347080	1			T30	3094		T31	17		T20	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1340240	1			T30	26286		T31	52		T32	78
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5109540	1			T30	92257		T31	159		T32	123
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3615530	1			T30	53484		T31	23		T32	64
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1352035	1			T30	25917		T31	76		T32	66
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1799934	1			T30	40337		T31	187		T32	89
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	349130	1			T30	3043		T31	29		T22	101
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1345081	1			T30	26252		T31	61		T32	74
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5119976	1			T30	92948		T31	135		T32	160
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3610728	1			T30	53632		T31	19		T32	57
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1355836	1			T30	26928		T31	62		T32	56
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1793089	1			T30	39012		T31	198		T32	86
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	345855	1			T30	2976		T31	27		T22	116
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1345766	1			T30	25794		T31	94		T32	57
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5109621	1			T30	92165		T31	205		T32	138
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3616814	1			T30	53351		T31	46		T32	60
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1354328	1			T30	27123		T31	69		T32	54
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1802246	1			T30	39329		T31	153		T32	94
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	346571	1			T30	2907		T31	17		T20	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1341670	1			T30	26415		T31	45		T32	70
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5112218	1			T30	91864		T31	152		T32	129
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3624682	1			T30	53703		T31	17		T32	54
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1352403	1			T30	25668		T31	50		T32	82
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1794623	1			T30	40909		T31	219		T32	73
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	344694	1			T30	3055		T31	34		T20	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1342630	1			T30	26091		T31	63		T32	78
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5109368	1			T30	91857		T31	144		T32	120
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3625862	1			T30	53525		T31	20		T32	63
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1358129	1			T30	26595		T31	50		T32	90
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1793550	1			T30	39883		T31	181		T32	69
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	346078	1			T30	3149		T31	28		T22	122
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1338263	1			T30	26281		T31	112		T32	74
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5124301	1			T30	91665		T31	138		T32	154
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3616756	1			T30	54002		T31	22		T32	57
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1349821	1			T30	26827		T31	80		T32	46
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1795413	1			T30	39934		T31	170		T32	96
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	347442	1			T30	3075		T31	27		T20	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1337517	1			T30	25787		T31	98		T32	63
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5103379	1			T30	91325		T31	178		T32	121
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3629253	1			T30	53816		T31	28		T32	61
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1352052	1			T30	26264		T31	81		T32	62
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1801973	1			T30	41033		T31	169		T32	94
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	346426	1			T30	3109		T31	25		T22	101
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1338167	1			T30	25743		T31	54		T32	78
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5108036	1			T30	90981		T31	195		T32	165
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3628812	1			T30	53900		T31	31		T32	54
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1349559	1			T30	26349		T31	26		T32	73
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1798996	1			T30	40012		T31	214		T32	68
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	345886	1			T30	3057		T31	25		T20	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1339961	1			T30	26991		T31	44		T32	56
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5113690	1			T30	91105		T31	241		T32	107
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3625979	1			T30	53350		T31	35		T32	58
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1342686	1			T30	25722		T31	78		T32	71
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1804534	1			T30	41448		T31	133		T32	66
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	346557	1			T30	3168		T31	10		T22	111
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1337804	1			T30	26497		T31	38		T32	114
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5114522	1			T30	92008		T31	162		T32	142
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3618047	1			T30	53763		T31	28		T32	60
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1345461	1			T30	25987		T31	42		T32	58
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1803494	1			T30	40397		T31	191		T32	82
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	347382	1			T30	3065		T31	25		T22	87
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1342344	1			T30	26070		T31	87		T32	74
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5121014	1			T30	91754		T31	110		T32	107
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3615180	1			T30	53781		T31	17		T32	62
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1350723	1			T30	26075		T31	56		T32	112
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1800446	1			T30	40291		T31	229		T32	55
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	347563	1			T30	2870		T31	36		T22	162
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1336324	1			T30	26519		T31	87		T32	80
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5129924	1			T30	93120		T31	173		T32	114
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3610210	1			T30	53637		T31	13		T32	63
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1350832	1			T30	26443		T31	28		T32	72
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1800322	1			T30	39292		T31	216		T32	83
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	345831	1			T30	2755		T31	31		T20	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1334131	1			T30	26043		T31	74		T32	84
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5126111	1			T30	92346		T31	201		T32	141
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3611385	1			T30	53265		T31	29		T32	54
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1347970	1			T30	26172		T31	72		T32	70
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1802207	1			T30	40634		T31	142		T32	64
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	347735	1			T30	3047		T31	22		T20	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1335842	1			T30	25826		T31	69		T32	87
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5120451	1			T30	92353		T31	192		T32	165
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3614271	1			T30	53747		T31	17		T32	54
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1346293	1			T30	26437		T31	68		T32	97
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1806259	1			T30	39850		T31	185		T32	48
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	344657	1			T30	3044		T31	22		T20	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1339319	1			T30	25859		T31	51		T32	52
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5124737	1			T30	91160		T31	180		T32	120
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3607799	1			T30	53475		T31	19		T32	55
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1348465	1			T30	26307		T31	34		T32	86
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1801542	1			T30	40676		T31	210		T32	52
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	348861	1			T30	3128		T31	24		T20	4
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1339846	1			T30	26544		T31	68		T32	103
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5125204	1			T30	92171		T31	193		T32	125
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3615937	1			T30	53628		T31	27		T32	64
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1353791	1			T30	25961		T31	59		T32	92
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1794509	1			T30	40759		T31	156		T32	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	346572	1			T30	3031		T31	24		T20	5
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1335237	1			T30	25740		T31	76		T32	81
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5115639	1			T30	91165		T31	183		T32	129
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3620700	1			T30	53796		T31	34		T32	62
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1348373	1			T30	25973		T31	92		T32	58
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1802716	1			T30	40833		T31	161		T32	101
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	345055	1			T30	3024		T31	23		T20	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1338767	1			T30	26499		T31	42		T32	66
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5126072	1			T30	92684		T31	188		T32	129
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3618955	1			T30	53821		T31	28		T32	62
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1347286	1			T30	26011		T31	85		T32	58
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1798900	1			T30	40282		T31	130		T32	104
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	347291	1			T30	2975		T31	29		T20	4
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1332746	1			T30	25517		T31	75		T32	63
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5126781	1			T30	91456		T31	183		T32	172
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3619789	1			T30	53655		T31	29		T32	71
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1347536	1			T30	26167		T31	111		T32	54
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1795827	1			T30	40586		T31	147		T32	60
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	345444	1			T30	3100		T31	27		T22	103
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1335873	1			T30	26326		T31	38		T32	59
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5120632	1			T30	92171		T31	259		T32	121
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3623413	1			T30	53391		T31	36		T32	56
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1352586	1			T30	25848		T31	42		T32	80
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1791376	1			T30	40919		T31	112		T32	74
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	346027	1			T30	3082		T31	16		T20	6
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1337216	1			T30	25879		T31	70		T32	85
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5122692	1			T30	92078		T31	215		T32	129
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3623283	1			T30	53650		T31	28		T32	66
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1352113	1			T30	26529		T31	58		T32	74
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1790601	1			T30	40092		T31	138		T32	80
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	348936	1			T30	2900		T31	26		T20	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1333625	1			T30	26041		T31	70		T32	67

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal