Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[1]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[2]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[3]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[4]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[5]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[6]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[7]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[8]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[9]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[10]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[11]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[12]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[13]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[14]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[15]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[16]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[17]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[18]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[19]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[20]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[21]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[22]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[23]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[24]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[25]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[26]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[27]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[28]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[29]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[30]	13571250	1			T30	241290		T31	535		T32	416
bins_for_gpio_bits[31]	13571250	1			T30	241290		T31	535		T32	416

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

264501404

1

T30

507121

T31

13394

T32

9025

auto[1]

169778596

1

T30

265007

T31

3726

T32

4287

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

264492290

1

T30

507119

T31

13392

T32

9013

auto[1]

169787710

1

T30

265008

T31

3728

T32

4299

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8029607	1			T30	154347		T31	408		T32	261
bins_for_gpio_bits[0]	auto[0]	auto[1]	239852	1			T30	4576		T31	10		T32	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	240112	1			T30	4577		T31	10		T32	18
bins_for_gpio_bits[0]	auto[1]	auto[1]	5061679	1			T30	77790		T31	107		T32	119
bins_for_gpio_bits[1]	auto[0]	auto[0]	8018216	1			T30	154183		T31	423		T32	283
bins_for_gpio_bits[1]	auto[0]	auto[1]	239579	1			T30	4604		T31	11		T32	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	239855	1			T30	4604		T31	11		T32	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	5073600	1			T30	77899		T31	90		T32	105
bins_for_gpio_bits[2]	auto[0]	auto[0]	8027362	1			T30	153433		T31	446		T32	294
bins_for_gpio_bits[2]	auto[0]	auto[1]	239331	1			T30	4671		T31	5		T32	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	239617	1			T30	4671		T31	5		T32	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	5064940	1			T30	78515		T31	79		T32	96
bins_for_gpio_bits[3]	auto[0]	auto[0]	8028019	1			T30	153980		T31	408		T32	245
bins_for_gpio_bits[3]	auto[0]	auto[1]	239957	1			T30	4533		T31	11		T32	20
bins_for_gpio_bits[3]	auto[1]	auto[0]	240243	1			T30	4533		T31	11		T32	21
bins_for_gpio_bits[3]	auto[1]	auto[1]	5063031	1			T30	78244		T31	105		T32	130
bins_for_gpio_bits[4]	auto[0]	auto[0]	8024328	1			T30	153662		T31	377		T32	251
bins_for_gpio_bits[4]	auto[0]	auto[1]	239439	1			T30	4628		T31	15		T32	17
bins_for_gpio_bits[4]	auto[1]	auto[0]	239713	1			T30	4628		T31	15		T32	17
bins_for_gpio_bits[4]	auto[1]	auto[1]	5067770	1			T30	78372		T31	128		T32	131
bins_for_gpio_bits[5]	auto[0]	auto[0]	8015423	1			T30	153144		T31	420		T32	297
bins_for_gpio_bits[5]	auto[0]	auto[1]	238983	1			T30	4648		T31	11		T32	13
bins_for_gpio_bits[5]	auto[1]	auto[0]	239241	1			T30	4649		T31	11		T32	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	5077603	1			T30	78849		T31	93		T32	93
bins_for_gpio_bits[6]	auto[0]	auto[0]	8025907	1			T30	153968		T31	357		T32	245
bins_for_gpio_bits[6]	auto[0]	auto[1]	239168	1			T30	4701		T31	22		T32	20
bins_for_gpio_bits[6]	auto[1]	auto[0]	239474	1			T30	4701		T31	22		T32	20
bins_for_gpio_bits[6]	auto[1]	auto[1]	5066701	1			T30	77920		T31	134		T32	131
bins_for_gpio_bits[7]	auto[0]	auto[0]	8021171	1			T30	154311		T31	416		T32	270
bins_for_gpio_bits[7]	auto[0]	auto[1]	240078	1			T30	4601		T31	9		T32	19
bins_for_gpio_bits[7]	auto[1]	auto[0]	240382	1			T30	4601		T31	9		T32	19
bins_for_gpio_bits[7]	auto[1]	auto[1]	5069619	1			T30	77777		T31	101		T32	108
bins_for_gpio_bits[8]	auto[0]	auto[0]	8024006	1			T30	153546		T31	409		T32	260
bins_for_gpio_bits[8]	auto[0]	auto[1]	239799	1			T30	4736		T31	13		T32	19
bins_for_gpio_bits[8]	auto[1]	auto[0]	240067	1			T30	4736		T31	13		T32	20
bins_for_gpio_bits[8]	auto[1]	auto[1]	5067378	1			T30	78272		T31	100		T32	117
bins_for_gpio_bits[9]	auto[0]	auto[0]	8011815	1			T30	153365		T31	445		T32	256
bins_for_gpio_bits[9]	auto[0]	auto[1]	239549	1			T30	4691		T31	6		T32	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	239837	1			T30	4692		T31	6		T32	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	5080049	1			T30	78542		T31	78		T32	131
bins_for_gpio_bits[10]	auto[0]	auto[0]	8022843	1			T30	153756		T31	418		T32	258
bins_for_gpio_bits[10]	auto[0]	auto[1]	239146	1			T30	4679		T31	8		T32	21
bins_for_gpio_bits[10]	auto[1]	auto[0]	239423	1			T30	4679		T31	8		T32	21
bins_for_gpio_bits[10]	auto[1]	auto[1]	5069838	1			T30	78176		T31	101		T32	116
bins_for_gpio_bits[11]	auto[0]	auto[0]	8021580	1			T30	153888		T31	410		T32	258
bins_for_gpio_bits[11]	auto[0]	auto[1]	239641	1			T30	4622		T31	12		T32	20
bins_for_gpio_bits[11]	auto[1]	auto[0]	239929	1			T30	4623		T31	12		T32	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	5070100	1			T30	78157		T31	101		T32	118
bins_for_gpio_bits[12]	auto[0]	auto[0]	8028809	1			T30	154287		T31	378		T32	287
bins_for_gpio_bits[12]	auto[0]	auto[1]	239803	1			T30	4601		T31	16		T32	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	240092	1			T30	4601		T31	17		T32	15
bins_for_gpio_bits[12]	auto[1]	auto[1]	5062546	1			T30	77801		T31	124		T32	100
bins_for_gpio_bits[13]	auto[0]	auto[0]	8025944	1			T30	154011		T31	416		T32	266
bins_for_gpio_bits[13]	auto[0]	auto[1]	239999	1			T30	4605		T31	11		T32	20
bins_for_gpio_bits[13]	auto[1]	auto[0]	240251	1			T30	4606		T31	11		T32	20
bins_for_gpio_bits[13]	auto[1]	auto[1]	5065056	1			T30	78068		T31	97		T32	110
bins_for_gpio_bits[14]	auto[0]	auto[0]	8019525	1			T30	153873		T31	408		T32	265
bins_for_gpio_bits[14]	auto[0]	auto[1]	239423	1			T30	4566		T31	13		T32	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	239719	1			T30	4568		T31	13		T32	19
bins_for_gpio_bits[14]	auto[1]	auto[1]	5072583	1			T30	78283		T31	101		T32	113
bins_for_gpio_bits[15]	auto[0]	auto[0]	8021632	1			T30	153687		T31	354		T32	260
bins_for_gpio_bits[15]	auto[0]	auto[1]	239113	1			T30	4647		T31	20		T32	19
bins_for_gpio_bits[15]	auto[1]	auto[0]	239415	1			T30	4648		T31	21		T32	19
bins_for_gpio_bits[15]	auto[1]	auto[1]	5071090	1			T30	78308		T31	140		T32	118
bins_for_gpio_bits[16]	auto[0]	auto[0]	8029731	1			T30	153808		T31	375		T32	278
bins_for_gpio_bits[16]	auto[0]	auto[1]	239503	1			T30	4618		T31	13		T32	17
bins_for_gpio_bits[16]	auto[1]	auto[0]	239804	1			T30	4618		T31	13		T32	18
bins_for_gpio_bits[16]	auto[1]	auto[1]	5062212	1			T30	78246		T31	134		T32	103
bins_for_gpio_bits[17]	auto[0]	auto[0]	8018536	1			T30	154037		T31	419		T32	258
bins_for_gpio_bits[17]	auto[0]	auto[1]	238630	1			T30	4585		T31	9		T32	19
bins_for_gpio_bits[17]	auto[1]	auto[0]	238868	1			T30	4585		T31	9		T32	19
bins_for_gpio_bits[17]	auto[1]	auto[1]	5075216	1			T30	78083		T31	98		T32	120
bins_for_gpio_bits[18]	auto[0]	auto[0]	8017204	1			T30	152730		T31	424		T32	292
bins_for_gpio_bits[18]	auto[0]	auto[1]	239078	1			T30	4612		T31	11		T32	14
bins_for_gpio_bits[18]	auto[1]	auto[0]	239387	1			T30	4612		T31	11		T32	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	5075581	1			T30	79336		T31	89		T32	96
bins_for_gpio_bits[19]	auto[0]	auto[0]	8021622	1			T30	153599		T31	444		T32	221
bins_for_gpio_bits[19]	auto[0]	auto[1]	239010	1			T30	4676		T31	8		T32	23
bins_for_gpio_bits[19]	auto[1]	auto[0]	239288	1			T30	4676		T31	8		T32	23
bins_for_gpio_bits[19]	auto[1]	auto[1]	5071330	1			T30	78339		T31	75		T32	149
bins_for_gpio_bits[20]	auto[0]	auto[0]	8023415	1			T30	153718		T31	378		T32	263
bins_for_gpio_bits[20]	auto[0]	auto[1]	239785	1			T30	4673		T31	17		T32	19
bins_for_gpio_bits[20]	auto[1]	auto[0]	240062	1			T30	4674		T31	17		T32	19
bins_for_gpio_bits[20]	auto[1]	auto[1]	5067988	1			T30	78225		T31	123		T32	115
bins_for_gpio_bits[21]	auto[0]	auto[0]	8032507	1			T30	153423		T31	381		T32	256
bins_for_gpio_bits[21]	auto[0]	auto[1]	239379	1			T30	4696		T31	14		T32	18
bins_for_gpio_bits[21]	auto[1]	auto[0]	239676	1			T30	4697		T31	14		T32	18
bins_for_gpio_bits[21]	auto[1]	auto[1]	5059688	1			T30	78474		T31	126		T32	124
bins_for_gpio_bits[22]	auto[0]	auto[0]	8042039	1			T30	154221		T31	405		T32	246
bins_for_gpio_bits[22]	auto[0]	auto[1]	238748	1			T30	4632		T31	12		T32	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	239039	1			T30	4634		T31	12		T32	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	5051424	1			T30	77803		T31	106		T32	124
bins_for_gpio_bits[23]	auto[0]	auto[0]	8037175	1			T30	154502		T31	403		T32	253
bins_for_gpio_bits[23]	auto[0]	auto[1]	238854	1			T30	4649		T31	12		T32	21
bins_for_gpio_bits[23]	auto[1]	auto[0]	239113	1			T30	4650		T31	12		T32	22
bins_for_gpio_bits[23]	auto[1]	auto[1]	5056108	1			T30	77489		T31	108		T32	120
bins_for_gpio_bits[24]	auto[0]	auto[0]	8032710	1			T30	154048		T31	436		T32	291
bins_for_gpio_bits[24]	auto[0]	auto[1]	240006	1			T30	4591		T31	9		T32	19
bins_for_gpio_bits[24]	auto[1]	auto[0]	240293	1			T30	4592		T31	9		T32	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	5058241	1			T30	78059		T31	81		T32	87
bins_for_gpio_bits[25]	auto[0]	auto[0]	8035027	1			T30	153493		T31	414		T32	234
bins_for_gpio_bits[25]	auto[0]	auto[1]	239398	1			T30	4648		T31	10		T32	23
bins_for_gpio_bits[25]	auto[1]	auto[0]	239717	1			T30	4650		T31	10		T32	24
bins_for_gpio_bits[25]	auto[1]	auto[1]	5057108	1			T30	78499		T31	101		T32	135
bins_for_gpio_bits[26]	auto[0]	auto[0]	8034190	1			T30	154312		T31	395		T32	251
bins_for_gpio_bits[26]	auto[0]	auto[1]	239011	1			T30	4579		T31	13		T32	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	239314	1			T30	4579		T31	13		T32	20
bins_for_gpio_bits[26]	auto[1]	auto[1]	5058735	1			T30	77820		T31	114		T32	126
bins_for_gpio_bits[27]	auto[0]	auto[0]	8027035	1			T30	153242		T31	428		T32	268
bins_for_gpio_bits[27]	auto[0]	auto[1]	239426	1			T30	4728		T31	8		T32	20
bins_for_gpio_bits[27]	auto[1]	auto[0]	239693	1			T30	4729		T31	8		T32	20
bins_for_gpio_bits[27]	auto[1]	auto[1]	5065096	1			T30	78591		T31	91		T32	108
bins_for_gpio_bits[28]	auto[0]	auto[0]	8033436	1			T30	154437		T31	393		T32	271
bins_for_gpio_bits[28]	auto[0]	auto[1]	238486	1			T30	4539		T31	10		T32	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	238822	1			T30	4540		T31	10		T32	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	5060506	1			T30	77774		T31	122		T32	106
bins_for_gpio_bits[29]	auto[0]	auto[0]	8030628	1			T30	153607		T31	431		T32	270
bins_for_gpio_bits[29]	auto[0]	auto[1]	239212	1			T30	4601		T31	10		T32	15
bins_for_gpio_bits[29]	auto[1]	auto[0]	239516	1			T30	4602		T31	10		T32	16
bins_for_gpio_bits[29]	auto[1]	auto[1]	5061894	1			T30	78480		T31	84		T32	115
bins_for_gpio_bits[30]	auto[0]	auto[0]	8025354	1			T30	154259		T31	401		T32	255
bins_for_gpio_bits[30]	auto[0]	auto[1]	238982	1			T30	4679		T31	12		T32	19
bins_for_gpio_bits[30]	auto[1]	auto[0]	239240	1			T30	4679		T31	12		T32	20
bins_for_gpio_bits[30]	auto[1]	auto[1]	5067674	1			T30	77673		T31	110		T32	122
bins_for_gpio_bits[31]	auto[0]	auto[0]	8026638	1			T30	153947		T31	400		T32	260
bins_for_gpio_bits[31]	auto[0]	auto[1]	238488	1			T30	4752		T31	11		T32	22
bins_for_gpio_bits[31]	auto[1]	auto[0]	238768	1			T30	4752		T31	11		T32	23
bins_for_gpio_bits[31]	auto[1]	auto[1]	5067356	1			T30	77839		T31	113		T32	111