Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925222 |
1 |
|
|
T30 |
115592 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5819301 |
1 |
|
|
T30 |
131229 |
|
T33 |
1291 |
|
T20 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12994273 |
1 |
|
|
T30 |
231412 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
750250 |
1 |
|
|
T30 |
15409 |
|
T33 |
283 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894292 |
1 |
|
|
T30 |
127469 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5850231 |
1 |
|
|
T30 |
119352 |
|
T33 |
1382 |
|
T20 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2560333 |
1 |
|
|
T30 |
49788 |
|
T33 |
520 |
|
T20 |
14 |
| auto[1] |
auto[0] |
auto[1] |
377485 |
1 |
|
|
T30 |
7314 |
|
T33 |
132 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2539648 |
1 |
|
|
T30 |
54155 |
|
T33 |
579 |
|
T25 |
172 |
| auto[1] |
auto[1] |
auto[1] |
372765 |
1 |
|
|
T30 |
8095 |
|
T33 |
151 |
|
T25 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7927946 |
1 |
|
|
T30 |
124545 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5816577 |
1 |
|
|
T30 |
122276 |
|
T33 |
1229 |
|
T20 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12993873 |
1 |
|
|
T30 |
230831 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
750650 |
1 |
|
|
T30 |
15990 |
|
T33 |
241 |
|
T25 |
131 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883792 |
1 |
|
|
T30 |
124248 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5860731 |
1 |
|
|
T30 |
122573 |
|
T33 |
1256 |
|
T20 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2570702 |
1 |
|
|
T30 |
54025 |
|
T33 |
502 |
|
T20 |
20 |
| auto[1] |
auto[0] |
auto[1] |
378662 |
1 |
|
|
T30 |
8114 |
|
T33 |
122 |
|
T25 |
88 |
| auto[1] |
auto[1] |
auto[0] |
2539379 |
1 |
|
|
T30 |
52558 |
|
T33 |
513 |
|
T25 |
169 |
| auto[1] |
auto[1] |
auto[1] |
371988 |
1 |
|
|
T30 |
7876 |
|
T33 |
119 |
|
T25 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912084 |
1 |
|
|
T30 |
124126 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5832439 |
1 |
|
|
T30 |
122695 |
|
T33 |
1552 |
|
T20 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12995389 |
1 |
|
|
T30 |
230610 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
749134 |
1 |
|
|
T30 |
16211 |
|
T33 |
233 |
|
T25 |
94 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895907 |
1 |
|
|
T30 |
121454 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5848616 |
1 |
|
|
T30 |
125367 |
|
T33 |
1210 |
|
T20 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2557913 |
1 |
|
|
T30 |
56553 |
|
T33 |
342 |
|
T20 |
18 |
| auto[1] |
auto[0] |
auto[1] |
375945 |
1 |
|
|
T30 |
8486 |
|
T33 |
79 |
|
T25 |
31 |
| auto[1] |
auto[1] |
auto[0] |
2541569 |
1 |
|
|
T30 |
52603 |
|
T33 |
635 |
|
T25 |
240 |
| auto[1] |
auto[1] |
auto[1] |
373189 |
1 |
|
|
T30 |
7725 |
|
T33 |
154 |
|
T25 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7935075 |
1 |
|
|
T30 |
128030 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5809448 |
1 |
|
|
T30 |
118791 |
|
T33 |
901 |
|
T20 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12992445 |
1 |
|
|
T30 |
231302 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
752078 |
1 |
|
|
T30 |
15519 |
|
T33 |
262 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878843 |
1 |
|
|
T30 |
125553 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5865680 |
1 |
|
|
T30 |
121268 |
|
T33 |
1391 |
|
T20 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2570588 |
1 |
|
|
T30 |
54873 |
|
T33 |
765 |
|
T20 |
15 |
| auto[1] |
auto[0] |
auto[1] |
377193 |
1 |
|
|
T30 |
8006 |
|
T33 |
175 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2543014 |
1 |
|
|
T30 |
50876 |
|
T33 |
364 |
|
T25 |
127 |
| auto[1] |
auto[1] |
auto[1] |
374885 |
1 |
|
|
T30 |
7513 |
|
T33 |
87 |
|
T25 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878867 |
1 |
|
|
T30 |
124310 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5865656 |
1 |
|
|
T30 |
122511 |
|
T33 |
1289 |
|
T20 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12995200 |
1 |
|
|
T30 |
230891 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
749323 |
1 |
|
|
T30 |
15930 |
|
T33 |
287 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902561 |
1 |
|
|
T30 |
124578 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5841962 |
1 |
|
|
T30 |
122243 |
|
T33 |
1431 |
|
T20 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2533298 |
1 |
|
|
T30 |
52294 |
|
T33 |
641 |
|
T20 |
14 |
| auto[1] |
auto[0] |
auto[1] |
372565 |
1 |
|
|
T30 |
7971 |
|
T33 |
159 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2559341 |
1 |
|
|
T30 |
54019 |
|
T33 |
503 |
|
T25 |
178 |
| auto[1] |
auto[1] |
auto[1] |
376758 |
1 |
|
|
T30 |
7959 |
|
T33 |
128 |
|
T25 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7900430 |
1 |
|
|
T30 |
124357 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5844093 |
1 |
|
|
T30 |
122464 |
|
T33 |
1336 |
|
T20 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12997547 |
1 |
|
|
T30 |
231163 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
746976 |
1 |
|
|
T30 |
15658 |
|
T33 |
268 |
|
T25 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909621 |
1 |
|
|
T30 |
125082 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5834902 |
1 |
|
|
T30 |
121739 |
|
T33 |
1373 |
|
T20 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2541873 |
1 |
|
|
T30 |
54851 |
|
T33 |
586 |
|
T20 |
22 |
| auto[1] |
auto[0] |
auto[1] |
372185 |
1 |
|
|
T30 |
8080 |
|
T33 |
137 |
|
T25 |
53 |
| auto[1] |
auto[1] |
auto[0] |
2546053 |
1 |
|
|
T30 |
51230 |
|
T33 |
519 |
|
T25 |
97 |
| auto[1] |
auto[1] |
auto[1] |
374791 |
1 |
|
|
T30 |
7578 |
|
T33 |
131 |
|
T25 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914847 |
1 |
|
|
T30 |
124691 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5829676 |
1 |
|
|
T30 |
122130 |
|
T33 |
1238 |
|
T20 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12994798 |
1 |
|
|
T30 |
231997 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
749725 |
1 |
|
|
T30 |
14824 |
|
T33 |
232 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895798 |
1 |
|
|
T30 |
130321 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5848725 |
1 |
|
|
T30 |
116500 |
|
T33 |
1283 |
|
T20 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2558384 |
1 |
|
|
T30 |
52852 |
|
T33 |
615 |
|
T20 |
20 |
| auto[1] |
auto[0] |
auto[1] |
376057 |
1 |
|
|
T30 |
7803 |
|
T33 |
137 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2540616 |
1 |
|
|
T30 |
48824 |
|
T33 |
436 |
|
T25 |
190 |
| auto[1] |
auto[1] |
auto[1] |
373668 |
1 |
|
|
T30 |
7021 |
|
T33 |
95 |
|
T25 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911418 |
1 |
|
|
T30 |
117446 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5833105 |
1 |
|
|
T30 |
129375 |
|
T33 |
1292 |
|
T20 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12991004 |
1 |
|
|
T30 |
231254 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
753519 |
1 |
|
|
T30 |
15567 |
|
T33 |
220 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863115 |
1 |
|
|
T30 |
125981 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5881408 |
1 |
|
|
T30 |
120840 |
|
T33 |
1160 |
|
T20 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2570789 |
1 |
|
|
T30 |
48502 |
|
T33 |
441 |
|
T20 |
33 |
| auto[1] |
auto[0] |
auto[1] |
378336 |
1 |
|
|
T30 |
7168 |
|
T33 |
102 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2557100 |
1 |
|
|
T30 |
56771 |
|
T33 |
499 |
|
T25 |
113 |
| auto[1] |
auto[1] |
auto[1] |
375183 |
1 |
|
|
T30 |
8399 |
|
T33 |
118 |
|
T25 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7920564 |
1 |
|
|
T30 |
123242 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5823959 |
1 |
|
|
T30 |
123579 |
|
T33 |
1093 |
|
T20 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12996288 |
1 |
|
|
T30 |
231072 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
748235 |
1 |
|
|
T30 |
15749 |
|
T33 |
195 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903643 |
1 |
|
|
T30 |
124829 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5840880 |
1 |
|
|
T30 |
121992 |
|
T33 |
1063 |
|
T20 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2553220 |
1 |
|
|
T30 |
52490 |
|
T33 |
541 |
|
T20 |
20 |
| auto[1] |
auto[0] |
auto[1] |
374856 |
1 |
|
|
T30 |
7830 |
|
T33 |
123 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2539425 |
1 |
|
|
T30 |
53753 |
|
T33 |
327 |
|
T25 |
167 |
| auto[1] |
auto[1] |
auto[1] |
373379 |
1 |
|
|
T30 |
7919 |
|
T33 |
72 |
|
T25 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7900105 |
1 |
|
|
T30 |
122084 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5844418 |
1 |
|
|
T30 |
124737 |
|
T33 |
1136 |
|
T20 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12998001 |
1 |
|
|
T30 |
231025 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
746522 |
1 |
|
|
T30 |
15796 |
|
T33 |
225 |
|
T25 |
90 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922140 |
1 |
|
|
T30 |
124735 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5822383 |
1 |
|
|
T30 |
122086 |
|
T33 |
1243 |
|
T20 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2535603 |
1 |
|
|
T30 |
51729 |
|
T33 |
571 |
|
T20 |
19 |
| auto[1] |
auto[0] |
auto[1] |
372496 |
1 |
|
|
T30 |
7680 |
|
T33 |
122 |
|
T25 |
59 |
| auto[1] |
auto[1] |
auto[0] |
2540258 |
1 |
|
|
T30 |
54561 |
|
T33 |
447 |
|
T25 |
130 |
| auto[1] |
auto[1] |
auto[1] |
374026 |
1 |
|
|
T30 |
8116 |
|
T33 |
103 |
|
T25 |
31 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7901114 |
1 |
|
|
T30 |
125309 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5843409 |
1 |
|
|
T30 |
121512 |
|
T33 |
1231 |
|
T25 |
432 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12993785 |
1 |
|
|
T30 |
230595 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
750738 |
1 |
|
|
T30 |
16226 |
|
T33 |
251 |
|
T25 |
105 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7886646 |
1 |
|
|
T30 |
121435 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5857877 |
1 |
|
|
T30 |
125386 |
|
T33 |
1390 |
|
T20 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2562507 |
1 |
|
|
T30 |
56054 |
|
T33 |
638 |
|
T20 |
18 |
| auto[1] |
auto[0] |
auto[1] |
376771 |
1 |
|
|
T30 |
8533 |
|
T33 |
136 |
|
T25 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2544632 |
1 |
|
|
T30 |
53106 |
|
T33 |
501 |
|
T25 |
219 |
| auto[1] |
auto[1] |
auto[1] |
373967 |
1 |
|
|
T30 |
7693 |
|
T33 |
115 |
|
T25 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7932368 |
1 |
|
|
T30 |
124076 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5812155 |
1 |
|
|
T30 |
122745 |
|
T33 |
1294 |
|
T20 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12991612 |
1 |
|
|
T30 |
229779 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
752911 |
1 |
|
|
T30 |
17042 |
|
T33 |
236 |
|
T25 |
103 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885352 |
1 |
|
|
T30 |
116905 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5859171 |
1 |
|
|
T30 |
129916 |
|
T33 |
1251 |
|
T20 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2561952 |
1 |
|
|
T30 |
57683 |
|
T33 |
446 |
|
T20 |
13 |
| auto[1] |
auto[0] |
auto[1] |
379019 |
1 |
|
|
T30 |
8811 |
|
T33 |
106 |
|
T25 |
33 |
| auto[1] |
auto[1] |
auto[0] |
2544308 |
1 |
|
|
T30 |
55191 |
|
T33 |
569 |
|
T25 |
247 |
| auto[1] |
auto[1] |
auto[1] |
373892 |
1 |
|
|
T30 |
8231 |
|
T33 |
130 |
|
T25 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7901328 |
1 |
|
|
T30 |
123008 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5843195 |
1 |
|
|
T30 |
123813 |
|
T33 |
1206 |
|
T20 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13000338 |
1 |
|
|
T30 |
231056 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
744185 |
1 |
|
|
T30 |
15765 |
|
T33 |
247 |
|
T25 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7928551 |
1 |
|
|
T30 |
124994 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5815972 |
1 |
|
|
T30 |
121827 |
|
T33 |
1241 |
|
T20 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540588 |
1 |
|
|
T30 |
51034 |
|
T33 |
452 |
|
T20 |
28 |
| auto[1] |
auto[0] |
auto[1] |
372681 |
1 |
|
|
T30 |
7563 |
|
T33 |
122 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2531199 |
1 |
|
|
T30 |
55028 |
|
T33 |
542 |
|
T25 |
150 |
| auto[1] |
auto[1] |
auto[1] |
371504 |
1 |
|
|
T30 |
8202 |
|
T33 |
125 |
|
T25 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882290 |
1 |
|
|
T30 |
125417 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5862233 |
1 |
|
|
T30 |
121404 |
|
T33 |
1139 |
|
T20 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13003633 |
1 |
|
|
T30 |
230967 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
740890 |
1 |
|
|
T30 |
15854 |
|
T33 |
251 |
|
T25 |
89 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7949284 |
1 |
|
|
T30 |
122966 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5795239 |
1 |
|
|
T30 |
123855 |
|
T33 |
1303 |
|
T20 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2523325 |
1 |
|
|
T30 |
57110 |
|
T33 |
610 |
|
T20 |
13 |
| auto[1] |
auto[0] |
auto[1] |
369815 |
1 |
|
|
T30 |
8526 |
|
T33 |
144 |
|
T25 |
37 |
| auto[1] |
auto[1] |
auto[0] |
2531024 |
1 |
|
|
T30 |
50891 |
|
T33 |
442 |
|
T20 |
3 |
| auto[1] |
auto[1] |
auto[1] |
371075 |
1 |
|
|
T30 |
7328 |
|
T33 |
107 |
|
T25 |
52 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7896853 |
1 |
|
|
T30 |
122510 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5847670 |
1 |
|
|
T30 |
124311 |
|
T33 |
1048 |
|
T20 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12997580 |
1 |
|
|
T30 |
230990 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
746943 |
1 |
|
|
T30 |
15831 |
|
T33 |
245 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919042 |
1 |
|
|
T30 |
123838 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5825481 |
1 |
|
|
T30 |
122983 |
|
T33 |
1269 |
|
T20 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538831 |
1 |
|
|
T30 |
53170 |
|
T33 |
549 |
|
T20 |
22 |
| auto[1] |
auto[0] |
auto[1] |
374087 |
1 |
|
|
T30 |
8032 |
|
T33 |
123 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2539707 |
1 |
|
|
T30 |
53982 |
|
T33 |
475 |
|
T25 |
152 |
| auto[1] |
auto[1] |
auto[1] |
372856 |
1 |
|
|
T30 |
7799 |
|
T33 |
122 |
|
T25 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7913333 |
1 |
|
|
T30 |
119992 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5831190 |
1 |
|
|
T30 |
126829 |
|
T33 |
970 |
|
T20 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12996564 |
1 |
|
|
T30 |
230154 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
747959 |
1 |
|
|
T30 |
16667 |
|
T33 |
234 |
|
T25 |
118 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7907481 |
1 |
|
|
T30 |
120658 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5837042 |
1 |
|
|
T30 |
126163 |
|
T33 |
1099 |
|
T20 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2550863 |
1 |
|
|
T30 |
51583 |
|
T33 |
477 |
|
T20 |
18 |
| auto[1] |
auto[0] |
auto[1] |
375508 |
1 |
|
|
T30 |
7670 |
|
T33 |
130 |
|
T25 |
69 |
| auto[1] |
auto[1] |
auto[0] |
2538220 |
1 |
|
|
T30 |
57913 |
|
T33 |
388 |
|
T20 |
5 |
| auto[1] |
auto[1] |
auto[1] |
372451 |
1 |
|
|
T30 |
8997 |
|
T33 |
104 |
|
T25 |
49 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7893498 |
1 |
|
|
T30 |
124645 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5851025 |
1 |
|
|
T30 |
122176 |
|
T33 |
1260 |
|
T20 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12994302 |
1 |
|
|
T30 |
230099 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
750221 |
1 |
|
|
T30 |
16722 |
|
T33 |
199 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7881985 |
1 |
|
|
T30 |
119405 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5862538 |
1 |
|
|
T30 |
127416 |
|
T33 |
1016 |
|
T20 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2550650 |
1 |
|
|
T30 |
56058 |
|
T33 |
299 |
|
T20 |
24 |
| auto[1] |
auto[0] |
auto[1] |
374023 |
1 |
|
|
T30 |
8527 |
|
T33 |
63 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2561667 |
1 |
|
|
T30 |
54636 |
|
T33 |
518 |
|
T25 |
225 |
| auto[1] |
auto[1] |
auto[1] |
376198 |
1 |
|
|
T30 |
8195 |
|
T33 |
136 |
|
T25 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7917985 |
1 |
|
|
T30 |
120597 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5826538 |
1 |
|
|
T30 |
126224 |
|
T33 |
1107 |
|
T25 |
583 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13001346 |
1 |
|
|
T30 |
230959 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
743177 |
1 |
|
|
T30 |
15862 |
|
T33 |
239 |
|
T25 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7940888 |
1 |
|
|
T30 |
124530 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5803635 |
1 |
|
|
T30 |
122291 |
|
T33 |
1332 |
|
T20 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538906 |
1 |
|
|
T30 |
52109 |
|
T33 |
584 |
|
T20 |
18 |
| auto[1] |
auto[0] |
auto[1] |
373207 |
1 |
|
|
T30 |
7765 |
|
T33 |
124 |
|
T25 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2521552 |
1 |
|
|
T30 |
54320 |
|
T33 |
509 |
|
T25 |
225 |
| auto[1] |
auto[1] |
auto[1] |
369970 |
1 |
|
|
T30 |
8097 |
|
T33 |
115 |
|
T25 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891934 |
1 |
|
|
T30 |
124597 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5852589 |
1 |
|
|
T30 |
122224 |
|
T33 |
958 |
|
T20 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12999646 |
1 |
|
|
T30 |
230056 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
744877 |
1 |
|
|
T30 |
16765 |
|
T33 |
176 |
|
T25 |
123 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922991 |
1 |
|
|
T30 |
117896 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5821532 |
1 |
|
|
T30 |
128925 |
|
T33 |
892 |
|
T20 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2524219 |
1 |
|
|
T30 |
56047 |
|
T33 |
458 |
|
T20 |
14 |
| auto[1] |
auto[0] |
auto[1] |
369698 |
1 |
|
|
T30 |
8478 |
|
T33 |
112 |
|
T25 |
59 |
| auto[1] |
auto[1] |
auto[0] |
2552436 |
1 |
|
|
T30 |
56113 |
|
T33 |
258 |
|
T20 |
3 |
| auto[1] |
auto[1] |
auto[1] |
375179 |
1 |
|
|
T30 |
8287 |
|
T33 |
64 |
|
T25 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |