Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905826 |
1 |
|
|
T30 |
126905 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5838697 |
1 |
|
|
T30 |
119916 |
|
T33 |
1239 |
|
T20 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12996590 |
1 |
|
|
T30 |
230384 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
747933 |
1 |
|
|
T30 |
16437 |
|
T33 |
279 |
|
T25 |
127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904680 |
1 |
|
|
T30 |
119757 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5839843 |
1 |
|
|
T30 |
127064 |
|
T33 |
1374 |
|
T20 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548376 |
1 |
|
|
T30 |
57468 |
|
T33 |
558 |
|
T20 |
21 |
| auto[1] |
auto[0] |
auto[1] |
373679 |
1 |
|
|
T30 |
8610 |
|
T33 |
139 |
|
T25 |
72 |
| auto[1] |
auto[1] |
auto[0] |
2543534 |
1 |
|
|
T30 |
53159 |
|
T33 |
537 |
|
T25 |
213 |
| auto[1] |
auto[1] |
auto[1] |
374254 |
1 |
|
|
T30 |
7827 |
|
T33 |
140 |
|
T25 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |