Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7939279 |
1 |
|
|
T30 |
125501 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5805244 |
1 |
|
|
T30 |
121320 |
|
T33 |
1290 |
|
T20 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12996449 |
1 |
|
|
T30 |
231329 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
748074 |
1 |
|
|
T30 |
15492 |
|
T33 |
274 |
|
T25 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906862 |
1 |
|
|
T30 |
127510 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5837661 |
1 |
|
|
T30 |
119311 |
|
T33 |
1479 |
|
T20 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2561576 |
1 |
|
|
T30 |
52344 |
|
T33 |
615 |
|
T20 |
20 |
| auto[1] |
auto[0] |
auto[1] |
376072 |
1 |
|
|
T30 |
7920 |
|
T33 |
135 |
|
T25 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2528011 |
1 |
|
|
T30 |
51475 |
|
T33 |
590 |
|
T25 |
123 |
| auto[1] |
auto[1] |
auto[1] |
372002 |
1 |
|
|
T30 |
7572 |
|
T33 |
139 |
|
T25 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |