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Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7901114 1 T30 125309 T31 276 T32 268
auto[1] 5843409 1 T30 121512 T33 1231 T25 432


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11394112 1 T30 199650 T31 276 T32 268
auto[1] 2350411 1 T30 47171 T33 615 T20 12


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7894240 1 T30 123754 T31 276 T32 268
auto[1] 5850283 1 T30 123067 T33 1243 T20 12


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1748678 1 T30 39149 T33 316 T25 149
auto[1] auto[0] auto[1] 1174363 1 T30 24278 T33 276 T20 12
auto[1] auto[1] auto[0] 1751194 1 T30 36747 T33 312 T25 154
auto[1] auto[1] auto[1] 1176048 1 T30 22893 T33 339 T25 169


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%