Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898827 |
1 |
|
|
T30 |
120749 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5845696 |
1 |
|
|
T30 |
126072 |
|
T33 |
1153 |
|
T20 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12999110 |
1 |
|
|
T30 |
231193 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
745413 |
1 |
|
|
T30 |
15628 |
|
T33 |
259 |
|
T25 |
67 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922271 |
1 |
|
|
T30 |
125064 |
|
T31 |
276 |
|
T32 |
268 |
| auto[1] |
5822252 |
1 |
|
|
T30 |
121757 |
|
T33 |
1286 |
|
T20 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2533405 |
1 |
|
|
T30 |
52511 |
|
T33 |
540 |
|
T20 |
15 |
| auto[1] |
auto[0] |
auto[1] |
371329 |
1 |
|
|
T30 |
7859 |
|
T33 |
139 |
|
T25 |
19 |
| auto[1] |
auto[1] |
auto[0] |
2543434 |
1 |
|
|
T30 |
53618 |
|
T33 |
487 |
|
T20 |
8 |
| auto[1] |
auto[1] |
auto[1] |
374084 |
1 |
|
|
T30 |
7769 |
|
T33 |
120 |
|
T25 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |