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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 948
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T764 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1357131828 Feb 18 12:31:39 PM PST 24 Feb 18 12:31:43 PM PST 24 50625348 ps
T765 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1168431219 Feb 18 12:32:05 PM PST 24 Feb 18 12:32:06 PM PST 24 95086394 ps
T766 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1898903126 Feb 18 12:31:29 PM PST 24 Feb 18 12:31:37 PM PST 24 194990761 ps
T767 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.519334060 Feb 18 12:31:24 PM PST 24 Feb 18 12:31:27 PM PST 24 43290196 ps
T768 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.740830034 Feb 18 12:35:14 PM PST 24 Feb 18 12:35:17 PM PST 24 35955003 ps
T102 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1664345304 Feb 18 12:31:48 PM PST 24 Feb 18 12:31:49 PM PST 24 26502476 ps
T769 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2861176753 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:37 PM PST 24 118914104 ps
T46 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3674241051 Feb 18 12:31:58 PM PST 24 Feb 18 12:32:01 PM PST 24 41397684 ps
T770 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2833016245 Feb 18 12:31:53 PM PST 24 Feb 18 12:31:56 PM PST 24 495673429 ps
T771 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1644651582 Feb 18 12:31:53 PM PST 24 Feb 18 12:31:56 PM PST 24 76398824 ps
T772 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1772259307 Feb 18 12:32:07 PM PST 24 Feb 18 12:32:09 PM PST 24 12510705 ps
T103 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1936958128 Feb 18 12:31:55 PM PST 24 Feb 18 12:31:57 PM PST 24 55927467 ps
T773 /workspace/coverage/cover_reg_top/43.gpio_intr_test.524394523 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:10 PM PST 24 13460800 ps
T774 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3060733829 Feb 18 12:31:37 PM PST 24 Feb 18 12:31:42 PM PST 24 14847829 ps
T775 /workspace/coverage/cover_reg_top/25.gpio_intr_test.4043297989 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:10 PM PST 24 15704294 ps
T776 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3206078262 Feb 18 12:32:05 PM PST 24 Feb 18 12:32:06 PM PST 24 14768876 ps
T777 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4201265821 Feb 18 12:31:26 PM PST 24 Feb 18 12:31:30 PM PST 24 15473925 ps
T778 /workspace/coverage/cover_reg_top/20.gpio_intr_test.4190024684 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:10 PM PST 24 17046725 ps
T779 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.42925102 Feb 18 12:31:26 PM PST 24 Feb 18 12:31:31 PM PST 24 122806301 ps
T50 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2801946105 Feb 18 12:31:27 PM PST 24 Feb 18 12:31:33 PM PST 24 98660294 ps
T780 /workspace/coverage/cover_reg_top/27.gpio_intr_test.216455455 Feb 18 12:32:13 PM PST 24 Feb 18 12:32:14 PM PST 24 24270599 ps
T781 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3629530414 Feb 18 12:31:30 PM PST 24 Feb 18 12:31:36 PM PST 24 72556257 ps
T92 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4181606873 Feb 18 12:31:34 PM PST 24 Feb 18 12:31:41 PM PST 24 39212067 ps
T782 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2393337785 Feb 18 12:31:35 PM PST 24 Feb 18 12:31:42 PM PST 24 514881808 ps
T783 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.144812332 Feb 18 12:31:53 PM PST 24 Feb 18 12:31:56 PM PST 24 502025463 ps
T784 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1140214167 Feb 18 12:31:33 PM PST 24 Feb 18 12:31:41 PM PST 24 135650562 ps
T104 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4178097834 Feb 18 12:31:32 PM PST 24 Feb 18 12:31:38 PM PST 24 20306898 ps
T785 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1834855059 Feb 18 12:31:36 PM PST 24 Feb 18 12:31:42 PM PST 24 48536668 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2312366055 Feb 18 12:31:22 PM PST 24 Feb 18 12:31:26 PM PST 24 32251624 ps
T787 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.796713719 Feb 18 12:31:50 PM PST 24 Feb 18 12:31:51 PM PST 24 42215133 ps
T788 /workspace/coverage/cover_reg_top/24.gpio_intr_test.4159455188 Feb 18 12:32:05 PM PST 24 Feb 18 12:32:07 PM PST 24 11032806 ps
T789 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.195513841 Feb 18 12:31:41 PM PST 24 Feb 18 12:31:45 PM PST 24 29722261 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.547731838 Feb 18 12:31:29 PM PST 24 Feb 18 12:31:35 PM PST 24 190908396 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1392179601 Feb 18 12:31:48 PM PST 24 Feb 18 12:31:49 PM PST 24 33261670 ps
T792 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2612582591 Feb 18 12:32:13 PM PST 24 Feb 18 12:32:15 PM PST 24 14292625 ps
T793 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4037546384 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:38 PM PST 24 172957930 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.973346741 Feb 18 12:31:37 PM PST 24 Feb 18 12:31:44 PM PST 24 258666550 ps
T795 /workspace/coverage/cover_reg_top/16.gpio_intr_test.55937934 Feb 18 12:31:52 PM PST 24 Feb 18 12:31:54 PM PST 24 19013192 ps
T796 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.189208790 Feb 18 12:31:36 PM PST 24 Feb 18 12:31:42 PM PST 24 180844506 ps
T797 /workspace/coverage/cover_reg_top/44.gpio_intr_test.4244485936 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:10 PM PST 24 14885443 ps
T48 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4227649089 Feb 18 12:31:26 PM PST 24 Feb 18 12:31:31 PM PST 24 71735143 ps
T798 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2197102705 Feb 18 12:32:09 PM PST 24 Feb 18 12:32:11 PM PST 24 17722150 ps
T799 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2942366779 Feb 18 12:31:47 PM PST 24 Feb 18 12:31:49 PM PST 24 20624114 ps
T93 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.119234328 Feb 18 12:31:46 PM PST 24 Feb 18 12:31:47 PM PST 24 48561370 ps
T800 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3812166772 Feb 18 12:31:50 PM PST 24 Feb 18 12:31:51 PM PST 24 15098019 ps
T801 /workspace/coverage/cover_reg_top/37.gpio_intr_test.841320661 Feb 18 12:32:05 PM PST 24 Feb 18 12:32:07 PM PST 24 34185454 ps
T802 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.534769210 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:40 PM PST 24 265088081 ps
T803 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3858440751 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:37 PM PST 24 14364299 ps
T94 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2117418901 Feb 18 12:31:28 PM PST 24 Feb 18 12:31:33 PM PST 24 27478711 ps
T804 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2668299544 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:12 PM PST 24 222834843 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4164928096 Feb 18 12:31:37 PM PST 24 Feb 18 12:31:43 PM PST 24 19033932 ps
T806 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4215135035 Feb 18 12:31:39 PM PST 24 Feb 18 12:31:44 PM PST 24 31101882 ps
T807 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.4076150340 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:38 PM PST 24 446425992 ps
T808 /workspace/coverage/cover_reg_top/35.gpio_intr_test.426663141 Feb 18 12:32:13 PM PST 24 Feb 18 12:32:14 PM PST 24 43264090 ps
T809 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2402119758 Feb 18 12:31:36 PM PST 24 Feb 18 12:31:43 PM PST 24 361410288 ps
T810 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2702967338 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:38 PM PST 24 197614109 ps
T811 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.251422761 Feb 18 12:31:40 PM PST 24 Feb 18 12:31:44 PM PST 24 798091359 ps
T812 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3673595106 Feb 18 12:31:22 PM PST 24 Feb 18 12:31:25 PM PST 24 36136681 ps
T813 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3416776432 Feb 18 12:31:29 PM PST 24 Feb 18 12:31:34 PM PST 24 116997932 ps
T814 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.720689903 Feb 18 12:31:35 PM PST 24 Feb 18 12:31:42 PM PST 24 45993221 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_intr_test.486180359 Feb 18 12:31:56 PM PST 24 Feb 18 12:31:58 PM PST 24 135912918 ps
T816 /workspace/coverage/cover_reg_top/23.gpio_intr_test.63170283 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:11 PM PST 24 71201025 ps
T817 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2616680656 Feb 18 12:31:46 PM PST 24 Feb 18 12:31:48 PM PST 24 55816296 ps
T818 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4007561692 Feb 18 12:32:17 PM PST 24 Feb 18 12:32:18 PM PST 24 39966180 ps
T819 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1658500487 Feb 18 12:31:41 PM PST 24 Feb 18 12:31:45 PM PST 24 100941661 ps
T95 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3555670122 Feb 18 12:31:24 PM PST 24 Feb 18 12:31:28 PM PST 24 12785906 ps
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2487211337 Feb 18 12:31:29 PM PST 24 Feb 18 12:31:33 PM PST 24 17896838 ps
T820 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4162727182 Feb 18 12:31:21 PM PST 24 Feb 18 12:31:26 PM PST 24 128009635 ps
T51 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3647321746 Feb 18 12:32:05 PM PST 24 Feb 18 12:32:06 PM PST 24 178412497 ps
T821 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2542504770 Feb 18 12:31:35 PM PST 24 Feb 18 12:31:42 PM PST 24 33544754 ps
T822 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1751526276 Feb 18 12:35:14 PM PST 24 Feb 18 12:35:17 PM PST 24 34208852 ps
T823 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4047539229 Feb 18 12:31:47 PM PST 24 Feb 18 12:31:49 PM PST 24 98378421 ps
T824 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3188395613 Feb 18 12:31:23 PM PST 24 Feb 18 12:31:27 PM PST 24 138683721 ps
T825 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1204169809 Feb 18 12:31:22 PM PST 24 Feb 18 12:31:26 PM PST 24 26596565 ps
T826 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3466795404 Feb 18 12:31:31 PM PST 24 Feb 18 12:31:37 PM PST 24 159683667 ps
T827 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.800437723 Feb 18 12:31:43 PM PST 24 Feb 18 12:31:46 PM PST 24 64204174 ps
T828 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4034161338 Feb 18 12:31:23 PM PST 24 Feb 18 12:31:27 PM PST 24 54104076 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2044821363 Feb 18 12:31:37 PM PST 24 Feb 18 12:31:43 PM PST 24 24012848 ps
T830 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.544891472 Feb 18 12:31:58 PM PST 24 Feb 18 12:32:00 PM PST 24 19180585 ps
T831 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1876605252 Feb 18 12:31:29 PM PST 24 Feb 18 12:31:34 PM PST 24 49281734 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.738581689 Feb 18 12:32:05 PM PST 24 Feb 18 12:32:06 PM PST 24 36832117 ps
T833 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1946247921 Feb 18 12:31:35 PM PST 24 Feb 18 12:31:42 PM PST 24 53841365 ps
T834 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2248221419 Feb 18 12:32:13 PM PST 24 Feb 18 12:32:14 PM PST 24 15022238 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4239634360 Feb 18 12:31:50 PM PST 24 Feb 18 12:31:52 PM PST 24 21760391 ps
T836 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3946629800 Feb 18 12:31:57 PM PST 24 Feb 18 12:32:02 PM PST 24 1056194569 ps
T837 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3669038025 Feb 18 12:31:53 PM PST 24 Feb 18 12:31:56 PM PST 24 136270864 ps
T838 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2598049825 Feb 18 12:31:57 PM PST 24 Feb 18 12:32:01 PM PST 24 52764269 ps
T839 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1242968828 Feb 18 12:32:15 PM PST 24 Feb 18 12:32:16 PM PST 24 14738142 ps
T840 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3720888638 Feb 18 12:31:46 PM PST 24 Feb 18 12:31:48 PM PST 24 32318829 ps
T841 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1436514765 Feb 18 12:32:08 PM PST 24 Feb 18 12:32:10 PM PST 24 40209234 ps
T842 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2854062716 Feb 18 12:31:37 PM PST 24 Feb 18 12:31:43 PM PST 24 15625376 ps
T843 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.205203671 Feb 18 12:31:30 PM PST 24 Feb 18 12:31:38 PM PST 24 424028446 ps
T844 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2420819944 Feb 18 12:31:46 PM PST 24 Feb 18 12:31:49 PM PST 24 725894021 ps
T845 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1815100329 Feb 18 12:31:50 PM PST 24 Feb 18 12:31:51 PM PST 24 37731599 ps
T846 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1613678359 Feb 18 12:31:38 PM PST 24 Feb 18 12:31:44 PM PST 24 578817734 ps
T97 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2614304625 Feb 18 12:31:26 PM PST 24 Feb 18 12:31:30 PM PST 24 34893539 ps
T847 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1885201019 Feb 18 12:31:52 PM PST 24 Feb 18 12:31:53 PM PST 24 684550497 ps
T848 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2347433748 Feb 18 12:31:30 PM PST 24 Feb 18 12:31:36 PM PST 24 49368187 ps
T849 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1582269162 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:38 PM PST 24 116337740 ps
T850 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1560204872 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:45 PM PST 24 70445719 ps
T851 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2577265077 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:38 PM PST 24 233049863 ps
T852 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373408680 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 107584743 ps
T853 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4047876252 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 261861837 ps
T854 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114894783 Feb 18 01:55:32 PM PST 24 Feb 18 01:55:37 PM PST 24 138550985 ps
T855 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3157993697 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:47 PM PST 24 54232824 ps
T856 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2131675255 Feb 18 01:55:41 PM PST 24 Feb 18 01:55:47 PM PST 24 289861577 ps
T857 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030215358 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:46 PM PST 24 55661945 ps
T858 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2840011512 Feb 18 01:55:46 PM PST 24 Feb 18 01:55:50 PM PST 24 64107497 ps
T859 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3346491245 Feb 18 01:55:42 PM PST 24 Feb 18 01:55:47 PM PST 24 88530820 ps
T860 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.831897063 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:40 PM PST 24 32307480 ps
T861 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2205924940 Feb 18 01:55:47 PM PST 24 Feb 18 01:55:51 PM PST 24 37997178 ps
T862 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1533375593 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:40 PM PST 24 52612345 ps
T863 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.31778819 Feb 18 01:55:30 PM PST 24 Feb 18 01:55:32 PM PST 24 142366416 ps
T864 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3172908153 Feb 18 01:55:29 PM PST 24 Feb 18 01:55:32 PM PST 24 102446825 ps
T865 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1489608338 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 74743947 ps
T866 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1924814945 Feb 18 01:55:32 PM PST 24 Feb 18 01:55:37 PM PST 24 403353219 ps
T867 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1060543222 Feb 18 01:55:31 PM PST 24 Feb 18 01:55:35 PM PST 24 145333844 ps
T868 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1505697404 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:39 PM PST 24 666526402 ps
T869 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.301883991 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 33314585 ps
T870 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2104919192 Feb 18 01:55:41 PM PST 24 Feb 18 01:55:47 PM PST 24 78148738 ps
T871 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3743260733 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:45 PM PST 24 66284610 ps
T872 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.930890442 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 61227402 ps
T873 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2296896895 Feb 18 01:55:26 PM PST 24 Feb 18 01:55:30 PM PST 24 35867997 ps
T874 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4194787662 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 126961981 ps
T875 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.228872408 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:39 PM PST 24 44963827 ps
T876 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3656985306 Feb 18 01:55:41 PM PST 24 Feb 18 01:55:47 PM PST 24 210905976 ps
T877 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2878679069 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:38 PM PST 24 248089895 ps
T878 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387117271 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 42811876 ps
T879 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2315328476 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:46 PM PST 24 69313887 ps
T880 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2824263211 Feb 18 01:55:44 PM PST 24 Feb 18 01:55:49 PM PST 24 55960742 ps
T881 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4033189410 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:45 PM PST 24 63851068 ps
T882 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77175611 Feb 18 01:55:38 PM PST 24 Feb 18 01:55:44 PM PST 24 46290293 ps
T883 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4102959197 Feb 18 01:55:41 PM PST 24 Feb 18 01:55:47 PM PST 24 71257334 ps
T884 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3896921181 Feb 18 01:55:42 PM PST 24 Feb 18 01:55:47 PM PST 24 162833476 ps
T885 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2785589370 Feb 18 01:55:38 PM PST 24 Feb 18 01:55:45 PM PST 24 106739225 ps
T886 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123559190 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 253220973 ps
T887 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.182865695 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 80985131 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017449644 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 43863027 ps
T889 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1448927448 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:46 PM PST 24 90261720 ps
T890 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1345144813 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 209482483 ps
T891 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476566257 Feb 18 01:55:36 PM PST 24 Feb 18 01:55:43 PM PST 24 54733369 ps
T892 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2118041617 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:39 PM PST 24 33909793 ps
T893 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2871019478 Feb 18 01:55:32 PM PST 24 Feb 18 01:55:37 PM PST 24 145627348 ps
T894 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.481445776 Feb 18 01:55:32 PM PST 24 Feb 18 01:55:36 PM PST 24 34478645 ps
T895 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1829280667 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:46 PM PST 24 136089385 ps
T896 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873560472 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 91671245 ps
T897 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4222564263 Feb 18 01:55:38 PM PST 24 Feb 18 01:55:45 PM PST 24 124208895 ps
T898 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.817372426 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 77495824 ps
T899 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.343215197 Feb 18 01:55:47 PM PST 24 Feb 18 01:55:51 PM PST 24 133294188 ps
T900 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3496899625 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:39 PM PST 24 134116771 ps
T901 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2984758584 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:37 PM PST 24 100844614 ps
T902 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3253960251 Feb 18 01:55:52 PM PST 24 Feb 18 01:55:56 PM PST 24 40294301 ps
T903 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3541915983 Feb 18 01:55:31 PM PST 24 Feb 18 01:55:36 PM PST 24 291653530 ps
T904 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.966343820 Feb 18 01:55:50 PM PST 24 Feb 18 01:55:53 PM PST 24 91432896 ps
T905 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4046442717 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:38 PM PST 24 256201118 ps
T906 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1970449895 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 1021056438 ps
T907 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3627717127 Feb 18 01:55:41 PM PST 24 Feb 18 01:55:47 PM PST 24 456121902 ps
T908 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1819793644 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 67747026 ps
T909 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1531706286 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 427581981 ps
T910 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3187633339 Feb 18 01:55:47 PM PST 24 Feb 18 01:55:50 PM PST 24 156068227 ps
T911 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2513387683 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:38 PM PST 24 269019108 ps
T912 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.880626704 Feb 18 01:55:32 PM PST 24 Feb 18 01:55:37 PM PST 24 44640566 ps
T913 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2119094214 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:45 PM PST 24 444082026 ps
T914 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1103041687 Feb 18 01:55:42 PM PST 24 Feb 18 01:55:48 PM PST 24 79899359 ps
T915 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.183764141 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:45 PM PST 24 39431969 ps
T916 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2122094785 Feb 18 01:55:30 PM PST 24 Feb 18 01:55:32 PM PST 24 50275875 ps
T917 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.829326038 Feb 18 01:55:43 PM PST 24 Feb 18 01:55:49 PM PST 24 58375882 ps
T918 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.542672528 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 248219535 ps
T919 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4191197528 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 65439834 ps
T920 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2015943579 Feb 18 01:55:38 PM PST 24 Feb 18 01:55:44 PM PST 24 41987880 ps
T921 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2587736412 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:43 PM PST 24 123390211 ps
T922 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4026119668 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 611073261 ps
T923 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.807509985 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:46 PM PST 24 79420836 ps
T924 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1654037609 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:46 PM PST 24 46792701 ps
T925 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1087767401 Feb 18 01:55:36 PM PST 24 Feb 18 01:55:43 PM PST 24 1235385783 ps
T926 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1283354113 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:40 PM PST 24 64837763 ps
T927 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2253772324 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 72690451 ps
T928 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1749431784 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:39 PM PST 24 85840523 ps
T929 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4149173622 Feb 18 01:55:34 PM PST 24 Feb 18 01:55:39 PM PST 24 163349738 ps
T930 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3963497982 Feb 18 01:55:31 PM PST 24 Feb 18 01:55:35 PM PST 24 1155691606 ps
T931 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1978297627 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:46 PM PST 24 515772216 ps
T932 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2953902902 Feb 18 01:55:40 PM PST 24 Feb 18 01:55:46 PM PST 24 28566828 ps
T933 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.144078128 Feb 18 01:55:38 PM PST 24 Feb 18 01:55:45 PM PST 24 129992378 ps
T934 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.275467253 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 33693439 ps
T935 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3151818770 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:44 PM PST 24 108970067 ps
T936 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3961120951 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 242326235 ps
T937 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1146745421 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 357147575 ps
T938 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1149213573 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:39 PM PST 24 164506342 ps
T939 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1093876160 Feb 18 01:55:39 PM PST 24 Feb 18 01:55:45 PM PST 24 81408097 ps
T940 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2383464439 Feb 18 01:55:32 PM PST 24 Feb 18 01:55:36 PM PST 24 33948675 ps
T941 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4234318445 Feb 18 01:55:37 PM PST 24 Feb 18 01:55:45 PM PST 24 325380421 ps
T942 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2506540959 Feb 18 01:55:38 PM PST 24 Feb 18 01:55:44 PM PST 24 42801532 ps
T943 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1385138093 Feb 18 01:55:35 PM PST 24 Feb 18 01:55:41 PM PST 24 202843234 ps
T944 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3416664158 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:37 PM PST 24 58656133 ps
T945 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1785871925 Feb 18 01:55:36 PM PST 24 Feb 18 01:55:43 PM PST 24 64478203 ps
T946 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2518305911 Feb 18 01:55:33 PM PST 24 Feb 18 01:55:38 PM PST 24 42610689 ps
T947 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854923627 Feb 18 01:55:41 PM PST 24 Feb 18 01:55:47 PM PST 24 82624302 ps
T948 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.559600291 Feb 18 01:55:30 PM PST 24 Feb 18 01:55:33 PM PST 24 68366086 ps

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3331037104
Short name T30
Test name
Test status
Simulation time 56113456215 ps
CPU time 668.98 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 03:09:18 PM PST 24
Peak memory 198648 kb
Host smart-11ba867c-6a08-4381-a5d8-a7acf438546d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3331037104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3331037104
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.575348322
Short name T121
Test name
Test status
Simulation time 162674465 ps
CPU time 1.91 seconds
Started Feb 18 02:56:52 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 198520 kb
Host smart-692deaeb-ac8c-4a15-b3ea-55404b5e8ba3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575348322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.575348322
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2620813928
Short name T26
Test name
Test status
Simulation time 89882239 ps
CPU time 1.72 seconds
Started Feb 18 02:55:46 PM PST 24
Finished Feb 18 02:55:48 PM PST 24
Peak memory 198488 kb
Host smart-01f8a978-b281-4519-a91f-672dfca71cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620813928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2620813928
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.624625117
Short name T39
Test name
Test status
Simulation time 139976064 ps
CPU time 0.9 seconds
Started Feb 18 02:55:55 PM PST 24
Finished Feb 18 02:55:57 PM PST 24
Peak memory 213772 kb
Host smart-865740c7-fe9d-4a75-8b6f-448387e10bf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624625117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.624625117
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2321605448
Short name T2
Test name
Test status
Simulation time 11250324893 ps
CPU time 134.26 seconds
Started Feb 18 02:58:13 PM PST 24
Finished Feb 18 03:00:41 PM PST 24
Peak memory 198528 kb
Host smart-eacb831b-df00-4295-acac-17bdaf32e074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321605448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2321605448
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1051895628
Short name T85
Test name
Test status
Simulation time 18137848 ps
CPU time 0.8 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 196480 kb
Host smart-1ca89db1-00ab-4649-bc98-7e85e17856dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051895628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1051895628
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.322278980
Short name T44
Test name
Test status
Simulation time 149581149 ps
CPU time 1.35 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198484 kb
Host smart-f4c1aa79-3fa6-4512-82b6-0c5b6b52b24e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322278980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.322278980
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3450577202
Short name T27
Test name
Test status
Simulation time 19041302 ps
CPU time 0.56 seconds
Started Feb 18 02:57:24 PM PST 24
Finished Feb 18 02:57:59 PM PST 24
Peak memory 195292 kb
Host smart-f6a1ac30-93b5-43df-ad17-1322b87de268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450577202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3450577202
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.741791430
Short name T83
Test name
Test status
Simulation time 123153792 ps
CPU time 1.32 seconds
Started Feb 18 12:31:26 PM PST 24
Finished Feb 18 12:31:31 PM PST 24
Peak memory 197292 kb
Host smart-089c8ec3-f1c0-4542-b3e3-3076cc1181e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741791430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.741791430
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1885214543
Short name T101
Test name
Test status
Simulation time 64483512 ps
CPU time 0.62 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 195852 kb
Host smart-921244a6-4029-474d-9d6f-7972319a9525
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885214543 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1885214543
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2702967338
Short name T810
Test name
Test status
Simulation time 197614109 ps
CPU time 0.9 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 197744 kb
Host smart-9fdb3e49-75ed-46b4-ba71-30862c338af2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702967338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2702967338
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3647321746
Short name T51
Test name
Test status
Simulation time 178412497 ps
CPU time 0.88 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:06 PM PST 24
Peak memory 197680 kb
Host smart-d1b0c170-f895-4d76-82b1-67032896837f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647321746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3647321746
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2312366055
Short name T786
Test name
Test status
Simulation time 32251624 ps
CPU time 0.82 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:31:26 PM PST 24
Peak memory 196348 kb
Host smart-4df4b901-628a-4ec1-bdab-2e57dc1dd0e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312366055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2312366055
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3188395613
Short name T824
Test name
Test status
Simulation time 138683721 ps
CPU time 1.56 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 197392 kb
Host smart-9f33dc8e-e4cd-4234-b8b5-2c465e908d36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188395613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3188395613
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.409812333
Short name T740
Test name
Test status
Simulation time 31965527 ps
CPU time 0.68 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:41 PM PST 24
Peak memory 195488 kb
Host smart-90f0b01a-ee8a-45a1-9d49-a4d5c6e12319
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409812333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.409812333
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4162727182
Short name T820
Test name
Test status
Simulation time 128009635 ps
CPU time 2.14 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:31:26 PM PST 24
Peak memory 198540 kb
Host smart-3b550648-4cd4-432b-85cc-95b6f67bf199
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162727182 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.4162727182
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.218368988
Short name T758
Test name
Test status
Simulation time 45802558 ps
CPU time 0.6 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 195652 kb
Host smart-ccafe9c2-e84c-4ea9-95fc-c983c31ff64b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218368988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.218368988
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2717219398
Short name T763
Test name
Test status
Simulation time 48553637 ps
CPU time 0.6 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 194136 kb
Host smart-53d0a711-29d2-41a2-a42f-513fbad8cb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717219398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2717219398
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.205203671
Short name T843
Test name
Test status
Simulation time 424028446 ps
CPU time 3.06 seconds
Started Feb 18 12:31:30 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 198460 kb
Host smart-d8de11a2-5a47-4826-b5fe-ccbf0802aaef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205203671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.205203671
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2801946105
Short name T50
Test name
Test status
Simulation time 98660294 ps
CPU time 1.35 seconds
Started Feb 18 12:31:27 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 198460 kb
Host smart-b4692f54-5a96-478d-813b-8c6a973fa861
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801946105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2801946105
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2614304625
Short name T97
Test name
Test status
Simulation time 34893539 ps
CPU time 0.69 seconds
Started Feb 18 12:31:26 PM PST 24
Finished Feb 18 12:31:30 PM PST 24
Peak memory 194964 kb
Host smart-aa825bf6-29ad-4a3a-9a5b-f5d67befa084
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614304625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2614304625
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.652291589
Short name T88
Test name
Test status
Simulation time 13082216 ps
CPU time 0.61 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:31:40 PM PST 24
Peak memory 195480 kb
Host smart-9762e75f-06bf-47f5-948b-a16e394738a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652291589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.652291589
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1125463830
Short name T760
Test name
Test status
Simulation time 215376122 ps
CPU time 2.09 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 198476 kb
Host smart-e8162ecc-6fe8-44b4-bea7-0f789b1a9974
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125463830 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1125463830
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1133009013
Short name T91
Test name
Test status
Simulation time 37166831 ps
CPU time 0.58 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 195824 kb
Host smart-662aa2cc-b6f5-4f18-97b6-de9e2b1ab62c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133009013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1133009013
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1751526276
Short name T822
Test name
Test status
Simulation time 34208852 ps
CPU time 0.67 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 192128 kb
Host smart-90650e42-458a-447d-8fc4-c9c333fff17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751526276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1751526276
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4178097834
Short name T104
Test name
Test status
Simulation time 20306898 ps
CPU time 0.78 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 197008 kb
Host smart-9c6995ef-7967-44fa-bc63-1d187da10e74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178097834 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4178097834
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1658500487
Short name T819
Test name
Test status
Simulation time 100941661 ps
CPU time 1.46 seconds
Started Feb 18 12:31:41 PM PST 24
Finished Feb 18 12:31:45 PM PST 24
Peak memory 198496 kb
Host smart-41b312a1-9763-456d-9a4e-21a707b1d62b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658500487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1658500487
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3715453528
Short name T43
Test name
Test status
Simulation time 328048113 ps
CPU time 1.07 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:37 PM PST 24
Peak memory 198488 kb
Host smart-e84f72bb-704c-45ca-aaf8-250769a7ce3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715453528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3715453528
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.720689903
Short name T814
Test name
Test status
Simulation time 45993221 ps
CPU time 1.27 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198428 kb
Host smart-c4dd87cc-a6bb-4b4b-9b24-902b322be0b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720689903 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.720689903
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2044821363
Short name T829
Test name
Test status
Simulation time 24012848 ps
CPU time 0.55 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 194476 kb
Host smart-5399ce01-6035-4eab-ab72-5964af399c51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044821363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2044821363
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.49670004
Short name T755
Test name
Test status
Simulation time 54838147 ps
CPU time 0.65 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 194196 kb
Host smart-3ef31d8b-fc03-462a-ba02-f58df1c7bd6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49670004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.49670004
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1521762596
Short name T87
Test name
Test status
Simulation time 16259301 ps
CPU time 0.63 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:41 PM PST 24
Peak memory 194960 kb
Host smart-52801bd5-5fbc-4333-94aa-9c7f5116b9cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521762596 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1521762596
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3132818074
Short name T722
Test name
Test status
Simulation time 216044352 ps
CPU time 2.2 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:44 PM PST 24
Peak memory 198480 kb
Host smart-4c83b15e-1b66-4f0c-a4fa-0d368b53c3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132818074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3132818074
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.103519169
Short name T118
Test name
Test status
Simulation time 47361453 ps
CPU time 0.84 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 198316 kb
Host smart-ea0bbfdd-70d6-4c95-a8d7-394e1212bf0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103519169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.103519169
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.195513841
Short name T789
Test name
Test status
Simulation time 29722261 ps
CPU time 1.56 seconds
Started Feb 18 12:31:41 PM PST 24
Finished Feb 18 12:31:45 PM PST 24
Peak memory 198484 kb
Host smart-dadc9f3e-3e5a-4204-904e-a12a12387063
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195513841 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.195513841
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3720888638
Short name T840
Test name
Test status
Simulation time 32318829 ps
CPU time 0.58 seconds
Started Feb 18 12:31:46 PM PST 24
Finished Feb 18 12:31:48 PM PST 24
Peak memory 194388 kb
Host smart-baa4cc5d-a037-4a93-ab48-725730321c75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720888638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3720888638
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3060733829
Short name T774
Test name
Test status
Simulation time 14847829 ps
CPU time 0.61 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 194144 kb
Host smart-9882a6fe-45e8-4734-8707-8cb1b8db0c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060733829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3060733829
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.189208790
Short name T796
Test name
Test status
Simulation time 180844506 ps
CPU time 0.93 seconds
Started Feb 18 12:31:36 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198040 kb
Host smart-f03b611b-72e5-4552-a66b-c7d0be13d02a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189208790 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.189208790
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1613678359
Short name T846
Test name
Test status
Simulation time 578817734 ps
CPU time 1.91 seconds
Started Feb 18 12:31:38 PM PST 24
Finished Feb 18 12:31:44 PM PST 24
Peak memory 198468 kb
Host smart-9d1011c1-f502-42c0-a02f-763b06cdd289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613678359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1613678359
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4292583711
Short name T37
Test name
Test status
Simulation time 73006514 ps
CPU time 1.07 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 198444 kb
Host smart-537aa0f6-14ed-490e-a67e-fcc9d8b4ca9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292583711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4292583711
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2420819944
Short name T844
Test name
Test status
Simulation time 725894021 ps
CPU time 2.02 seconds
Started Feb 18 12:31:46 PM PST 24
Finished Feb 18 12:31:49 PM PST 24
Peak memory 198520 kb
Host smart-a62bac81-36f2-41db-bae0-e37c09da5266
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420819944 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2420819944
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2616680656
Short name T817
Test name
Test status
Simulation time 55816296 ps
CPU time 0.64 seconds
Started Feb 18 12:31:46 PM PST 24
Finished Feb 18 12:31:48 PM PST 24
Peak memory 195536 kb
Host smart-f002bc14-3a2a-4820-b970-e5b46f51515f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616680656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2616680656
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1357131828
Short name T764
Test name
Test status
Simulation time 50625348 ps
CPU time 0.6 seconds
Started Feb 18 12:31:39 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 194152 kb
Host smart-fec6953e-7283-4d88-900c-be5e1a63a42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357131828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1357131828
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.900661861
Short name T86
Test name
Test status
Simulation time 43320949 ps
CPU time 0.63 seconds
Started Feb 18 12:31:46 PM PST 24
Finished Feb 18 12:31:47 PM PST 24
Peak memory 195008 kb
Host smart-1c864e1d-bce5-43ac-a123-7160a5f8ccde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900661861 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.900661861
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.459960915
Short name T730
Test name
Test status
Simulation time 86383036 ps
CPU time 2.29 seconds
Started Feb 18 12:31:40 PM PST 24
Finished Feb 18 12:31:45 PM PST 24
Peak memory 198540 kb
Host smart-6ddfee07-0681-4350-b860-534049e6b9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459960915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.459960915
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.251422761
Short name T811
Test name
Test status
Simulation time 798091359 ps
CPU time 0.82 seconds
Started Feb 18 12:31:40 PM PST 24
Finished Feb 18 12:31:44 PM PST 24
Peak memory 197432 kb
Host smart-242409d3-af65-4173-b29d-16ae485c0c04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251422761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.251422761
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1946247921
Short name T833
Test name
Test status
Simulation time 53841365 ps
CPU time 1.22 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198516 kb
Host smart-e2a073e8-9552-49d0-9c65-ba4906443b93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946247921 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1946247921
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1171147969
Short name T731
Test name
Test status
Simulation time 43588667 ps
CPU time 0.59 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:41 PM PST 24
Peak memory 195176 kb
Host smart-a092bef5-644b-42bf-952f-4df5a3284c4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171147969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1171147969
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.360575598
Short name T723
Test name
Test status
Simulation time 42425205 ps
CPU time 0.6 seconds
Started Feb 18 12:31:44 PM PST 24
Finished Feb 18 12:31:45 PM PST 24
Peak memory 194204 kb
Host smart-b3d6ba0f-f73b-4f41-87b5-89744caeccad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360575598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.360575598
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1664345304
Short name T102
Test name
Test status
Simulation time 26502476 ps
CPU time 0.62 seconds
Started Feb 18 12:31:48 PM PST 24
Finished Feb 18 12:31:49 PM PST 24
Peak memory 196024 kb
Host smart-19571dbe-23bb-4559-8091-435e64739ffb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664345304 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1664345304
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1592527592
Short name T737
Test name
Test status
Simulation time 1717897518 ps
CPU time 2.2 seconds
Started Feb 18 12:31:43 PM PST 24
Finished Feb 18 12:31:46 PM PST 24
Peak memory 198492 kb
Host smart-16ea3ec5-ac5f-43db-b661-bfaec338ab83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592527592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1592527592
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.800437723
Short name T827
Test name
Test status
Simulation time 64204174 ps
CPU time 1.65 seconds
Started Feb 18 12:31:43 PM PST 24
Finished Feb 18 12:31:46 PM PST 24
Peak memory 198568 kb
Host smart-fa88e81e-5aee-4eb5-99b2-af44e0d4bf87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800437723 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.800437723
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.119234328
Short name T93
Test name
Test status
Simulation time 48561370 ps
CPU time 0.61 seconds
Started Feb 18 12:31:46 PM PST 24
Finished Feb 18 12:31:47 PM PST 24
Peak memory 195056 kb
Host smart-c8b7b562-e7e5-4fb5-889f-eef3116b9860
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119234328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.119234328
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3812166772
Short name T800
Test name
Test status
Simulation time 15098019 ps
CPU time 0.58 seconds
Started Feb 18 12:31:50 PM PST 24
Finished Feb 18 12:31:51 PM PST 24
Peak memory 194256 kb
Host smart-dc14828a-d82d-42be-97a1-dba4ffb66cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812166772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3812166772
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2942366779
Short name T799
Test name
Test status
Simulation time 20624114 ps
CPU time 0.66 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:31:49 PM PST 24
Peak memory 196100 kb
Host smart-6295fa4e-e2b9-443a-ad80-c7f165df647b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942366779 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2942366779
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4239634360
Short name T835
Test name
Test status
Simulation time 21760391 ps
CPU time 0.91 seconds
Started Feb 18 12:31:50 PM PST 24
Finished Feb 18 12:31:52 PM PST 24
Peak memory 198312 kb
Host smart-453c72d8-c7c3-4baf-83aa-68eaba28f306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239634360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4239634360
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4047539229
Short name T823
Test name
Test status
Simulation time 98378421 ps
CPU time 1.45 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:31:49 PM PST 24
Peak memory 198476 kb
Host smart-9836a4b4-c45f-4cc0-9c3f-0e00418474b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047539229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4047539229
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.144812332
Short name T783
Test name
Test status
Simulation time 502025463 ps
CPU time 2.39 seconds
Started Feb 18 12:31:53 PM PST 24
Finished Feb 18 12:31:56 PM PST 24
Peak memory 198536 kb
Host smart-078ee247-c578-4471-ad41-29cbbcd0200f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144812332 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.144812332
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.644221056
Short name T738
Test name
Test status
Simulation time 25460717 ps
CPU time 0.63 seconds
Started Feb 18 12:31:52 PM PST 24
Finished Feb 18 12:31:53 PM PST 24
Peak memory 195328 kb
Host smart-61a7df52-99e1-49d5-8a2b-acb5a586dd23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644221056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.644221056
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1815100329
Short name T845
Test name
Test status
Simulation time 37731599 ps
CPU time 0.58 seconds
Started Feb 18 12:31:50 PM PST 24
Finished Feb 18 12:31:51 PM PST 24
Peak memory 194816 kb
Host smart-4c99f4a9-f2cd-4255-99a7-3b0c6c5f0c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815100329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1815100329
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1392179601
Short name T791
Test name
Test status
Simulation time 33261670 ps
CPU time 0.63 seconds
Started Feb 18 12:31:48 PM PST 24
Finished Feb 18 12:31:49 PM PST 24
Peak memory 195112 kb
Host smart-acfe6d9b-f8ae-496e-93f4-0a55f321278e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392179601 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1392179601
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.54107073
Short name T726
Test name
Test status
Simulation time 47451314 ps
CPU time 1.27 seconds
Started Feb 18 12:31:51 PM PST 24
Finished Feb 18 12:31:53 PM PST 24
Peak memory 198496 kb
Host smart-483b755f-a3c5-450f-b66a-8be8561f7254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54107073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.54107073
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1885201019
Short name T847
Test name
Test status
Simulation time 684550497 ps
CPU time 0.83 seconds
Started Feb 18 12:31:52 PM PST 24
Finished Feb 18 12:31:53 PM PST 24
Peak memory 198268 kb
Host smart-030ec95a-7a23-4375-bbf7-2b9f5e11848a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885201019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1885201019
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3669038025
Short name T837
Test name
Test status
Simulation time 136270864 ps
CPU time 2.76 seconds
Started Feb 18 12:31:53 PM PST 24
Finished Feb 18 12:31:56 PM PST 24
Peak memory 198536 kb
Host smart-76d0ab74-7913-48a4-b98c-f65b413332bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669038025 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3669038025
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.418824047
Short name T724
Test name
Test status
Simulation time 30954811 ps
CPU time 0.58 seconds
Started Feb 18 12:31:54 PM PST 24
Finished Feb 18 12:31:55 PM PST 24
Peak memory 193744 kb
Host smart-490c9b35-efef-4ea4-8731-ba8272927987
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418824047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.418824047
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.55937934
Short name T795
Test name
Test status
Simulation time 19013192 ps
CPU time 0.64 seconds
Started Feb 18 12:31:52 PM PST 24
Finished Feb 18 12:31:54 PM PST 24
Peak memory 194228 kb
Host smart-0e9f1d20-0593-4f79-9af4-77d6deba0e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55937934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.55937934
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.738581689
Short name T832
Test name
Test status
Simulation time 36832117 ps
CPU time 0.84 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:06 PM PST 24
Peak memory 196532 kb
Host smart-7a92425f-d8fa-4e24-a6ad-65366a4b3dd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738581689 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.738581689
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1176058005
Short name T756
Test name
Test status
Simulation time 216656052 ps
CPU time 2.88 seconds
Started Feb 18 12:31:51 PM PST 24
Finished Feb 18 12:31:55 PM PST 24
Peak memory 198456 kb
Host smart-f2d80022-2c33-4aff-b86a-e2e6c9b2c1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176058005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1176058005
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1168431219
Short name T765
Test name
Test status
Simulation time 95086394 ps
CPU time 0.89 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:06 PM PST 24
Peak memory 198240 kb
Host smart-d3e7478a-0de5-45a3-bb0a-d0076bcda313
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168431219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1168431219
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2833016245
Short name T770
Test name
Test status
Simulation time 495673429 ps
CPU time 2.12 seconds
Started Feb 18 12:31:53 PM PST 24
Finished Feb 18 12:31:56 PM PST 24
Peak memory 198540 kb
Host smart-185961ba-11bc-4fca-bdae-a0ec4ea6ba11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833016245 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2833016245
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.796713719
Short name T787
Test name
Test status
Simulation time 42215133 ps
CPU time 0.57 seconds
Started Feb 18 12:31:50 PM PST 24
Finished Feb 18 12:31:51 PM PST 24
Peak memory 195828 kb
Host smart-43f7619f-942e-48fa-8d8f-66a380e1619b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796713719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.796713719
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.486180359
Short name T815
Test name
Test status
Simulation time 135912918 ps
CPU time 0.6 seconds
Started Feb 18 12:31:56 PM PST 24
Finished Feb 18 12:31:58 PM PST 24
Peak memory 194060 kb
Host smart-3a76f961-41e6-46a0-9c12-70afa7cfb7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486180359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.486180359
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3209952526
Short name T99
Test name
Test status
Simulation time 78536956 ps
CPU time 0.75 seconds
Started Feb 18 12:31:56 PM PST 24
Finished Feb 18 12:31:58 PM PST 24
Peak memory 197404 kb
Host smart-4e3ae2a7-5a45-4259-bd3e-2543169cb657
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209952526 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3209952526
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1644651582
Short name T771
Test name
Test status
Simulation time 76398824 ps
CPU time 2.08 seconds
Started Feb 18 12:31:53 PM PST 24
Finished Feb 18 12:31:56 PM PST 24
Peak memory 198460 kb
Host smart-09e0f98f-1a2c-407e-8c35-28b8d2b897a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644651582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1644651582
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.995038601
Short name T38
Test name
Test status
Simulation time 358937907 ps
CPU time 1.25 seconds
Started Feb 18 12:31:52 PM PST 24
Finished Feb 18 12:31:55 PM PST 24
Peak memory 198544 kb
Host smart-a3b65d2f-e549-4b7a-a6eb-4b235776e5f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995038601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.995038601
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2598049825
Short name T838
Test name
Test status
Simulation time 52764269 ps
CPU time 2.65 seconds
Started Feb 18 12:31:57 PM PST 24
Finished Feb 18 12:32:01 PM PST 24
Peak memory 198540 kb
Host smart-020449b7-382c-415f-ba02-8fd2cb1fbe56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598049825 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2598049825
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3206078262
Short name T776
Test name
Test status
Simulation time 14768876 ps
CPU time 0.63 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:06 PM PST 24
Peak memory 194588 kb
Host smart-50456de4-d66a-4373-bd7b-7d34a3be2fe2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206078262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3206078262
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2790104177
Short name T757
Test name
Test status
Simulation time 63406892 ps
CPU time 0.63 seconds
Started Feb 18 12:31:56 PM PST 24
Finished Feb 18 12:31:58 PM PST 24
Peak memory 194848 kb
Host smart-a945de32-8270-4fa2-a8fe-77783dd7ae4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790104177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2790104177
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.544891472
Short name T830
Test name
Test status
Simulation time 19180585 ps
CPU time 0.84 seconds
Started Feb 18 12:31:58 PM PST 24
Finished Feb 18 12:32:00 PM PST 24
Peak memory 197504 kb
Host smart-03c26f78-92d0-44e5-9e4d-8569c2eaf4f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544891472 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.544891472
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1868889540
Short name T744
Test name
Test status
Simulation time 41973134 ps
CPU time 1.22 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:07 PM PST 24
Peak memory 198512 kb
Host smart-4bcb0dea-1ee7-4e10-a14c-0109fece91a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868889540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1868889540
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3674241051
Short name T46
Test name
Test status
Simulation time 41397684 ps
CPU time 0.89 seconds
Started Feb 18 12:31:58 PM PST 24
Finished Feb 18 12:32:01 PM PST 24
Peak memory 198300 kb
Host smart-4f85e2dd-0eb9-4ea6-b719-04f17a8e912e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674241051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3674241051
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3946629800
Short name T836
Test name
Test status
Simulation time 1056194569 ps
CPU time 3.07 seconds
Started Feb 18 12:31:57 PM PST 24
Finished Feb 18 12:32:02 PM PST 24
Peak memory 198516 kb
Host smart-4af2b595-ef78-4dda-a45c-537db91d0573
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946629800 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3946629800
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2937950129
Short name T90
Test name
Test status
Simulation time 26499237 ps
CPU time 0.61 seconds
Started Feb 18 12:31:56 PM PST 24
Finished Feb 18 12:31:58 PM PST 24
Peak memory 194204 kb
Host smart-d0403799-2a9b-43d4-bb14-0488a05d0bdd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937950129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2937950129
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1477800145
Short name T739
Test name
Test status
Simulation time 12552714 ps
CPU time 0.55 seconds
Started Feb 18 12:32:06 PM PST 24
Finished Feb 18 12:32:08 PM PST 24
Peak memory 194796 kb
Host smart-88b7254d-d3c5-45ef-abb2-f62be04d5c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477800145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1477800145
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1936958128
Short name T103
Test name
Test status
Simulation time 55927467 ps
CPU time 0.76 seconds
Started Feb 18 12:31:55 PM PST 24
Finished Feb 18 12:31:57 PM PST 24
Peak memory 197368 kb
Host smart-f79749b0-b34b-466c-a39f-9609cd9b824c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936958128 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1936958128
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2668299544
Short name T804
Test name
Test status
Simulation time 222834843 ps
CPU time 2.98 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:12 PM PST 24
Peak memory 198480 kb
Host smart-012b18d3-75e9-4fee-a32b-dca7a3b4551b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668299544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2668299544
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3273020380
Short name T759
Test name
Test status
Simulation time 221959754 ps
CPU time 2.04 seconds
Started Feb 18 12:31:30 PM PST 24
Finished Feb 18 12:31:37 PM PST 24
Peak memory 197592 kb
Host smart-41b10e04-a9ba-491d-adbb-fdc3a1406243
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273020380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3273020380
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2487211337
Short name T96
Test name
Test status
Simulation time 17896838 ps
CPU time 0.6 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 195208 kb
Host smart-81307188-a455-45d5-a1c9-7574a49253d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487211337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2487211337
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1204169809
Short name T825
Test name
Test status
Simulation time 26596565 ps
CPU time 1.36 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:31:26 PM PST 24
Peak memory 198284 kb
Host smart-e662dfc9-f8fe-44ff-b3de-55b3608a9af2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204169809 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1204169809
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4181606873
Short name T92
Test name
Test status
Simulation time 39212067 ps
CPU time 0.58 seconds
Started Feb 18 12:31:34 PM PST 24
Finished Feb 18 12:31:41 PM PST 24
Peak memory 194988 kb
Host smart-351c64cb-c0c7-4a2a-acdf-4fd88ed5fb9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181606873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.4181606873
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2875174065
Short name T746
Test name
Test status
Simulation time 21374831 ps
CPU time 0.61 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 194148 kb
Host smart-5e9480b9-d8d5-4ebf-8a6c-9e7045250747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875174065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2875174065
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.799153241
Short name T100
Test name
Test status
Simulation time 92271178 ps
CPU time 0.68 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 195320 kb
Host smart-e01b003a-f67e-46aa-9690-88ea230a61bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799153241 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.799153241
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1167714533
Short name T747
Test name
Test status
Simulation time 54983324 ps
CPU time 1.18 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 198460 kb
Host smart-35575e90-2603-48ba-80ce-e519a28d33b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167714533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1167714533
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4227649089
Short name T48
Test name
Test status
Simulation time 71735143 ps
CPU time 1.06 seconds
Started Feb 18 12:31:26 PM PST 24
Finished Feb 18 12:31:31 PM PST 24
Peak memory 198508 kb
Host smart-b5968cd6-cd42-48be-9d63-8a5bfda40ce5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227649089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4227649089
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4190024684
Short name T778
Test name
Test status
Simulation time 17046725 ps
CPU time 0.55 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194052 kb
Host smart-d1799be0-45bd-4a00-bf24-28b814a3e122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190024684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4190024684
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1557733298
Short name T721
Test name
Test status
Simulation time 16020041 ps
CPU time 0.62 seconds
Started Feb 18 12:32:07 PM PST 24
Finished Feb 18 12:32:09 PM PST 24
Peak memory 194888 kb
Host smart-7670285d-0f89-4ca9-a604-b49d1f33dfb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557733298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1557733298
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3862556894
Short name T754
Test name
Test status
Simulation time 43673861 ps
CPU time 0.56 seconds
Started Feb 18 12:32:07 PM PST 24
Finished Feb 18 12:32:09 PM PST 24
Peak memory 194856 kb
Host smart-399f0254-9166-4609-ade8-929a270581f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862556894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3862556894
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.63170283
Short name T816
Test name
Test status
Simulation time 71201025 ps
CPU time 0.64 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:11 PM PST 24
Peak memory 194172 kb
Host smart-dbc32388-7a4c-4fff-aa83-e6f5ad2b87df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63170283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.63170283
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4159455188
Short name T788
Test name
Test status
Simulation time 11032806 ps
CPU time 0.71 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:07 PM PST 24
Peak memory 194880 kb
Host smart-88144563-5c36-45d4-9201-ad444f7ef702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159455188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4159455188
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4043297989
Short name T775
Test name
Test status
Simulation time 15704294 ps
CPU time 0.58 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194176 kb
Host smart-e179c945-2c3d-4bc3-9621-9740eed73f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043297989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4043297989
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1436514765
Short name T841
Test name
Test status
Simulation time 40209234 ps
CPU time 0.59 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194256 kb
Host smart-a7274ed8-5540-40c4-bb8f-caa2ada022ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436514765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1436514765
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.216455455
Short name T780
Test name
Test status
Simulation time 24270599 ps
CPU time 0.61 seconds
Started Feb 18 12:32:13 PM PST 24
Finished Feb 18 12:32:14 PM PST 24
Peak memory 194792 kb
Host smart-0757bbd0-4ec6-41fa-83fd-92aa810f994d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216455455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.216455455
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1242968828
Short name T839
Test name
Test status
Simulation time 14738142 ps
CPU time 0.59 seconds
Started Feb 18 12:32:15 PM PST 24
Finished Feb 18 12:32:16 PM PST 24
Peak memory 194836 kb
Host smart-3ef72eb6-03e5-4835-8094-eca572171e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242968828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1242968828
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4007561692
Short name T818
Test name
Test status
Simulation time 39966180 ps
CPU time 0.55 seconds
Started Feb 18 12:32:17 PM PST 24
Finished Feb 18 12:32:18 PM PST 24
Peak memory 194124 kb
Host smart-bdf0e523-f376-46c4-8920-f64dc9bef157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007561692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4007561692
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1892940313
Short name T84
Test name
Test status
Simulation time 101262259 ps
CPU time 0.86 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 196556 kb
Host smart-6978fc9b-d8fe-42d8-a883-f91788a67a9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892940313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1892940313
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.534769210
Short name T802
Test name
Test status
Simulation time 265088081 ps
CPU time 3.05 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:40 PM PST 24
Peak memory 197624 kb
Host smart-20d404b7-8633-4732-a3a9-ab4b65381617
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534769210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.534769210
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4201265821
Short name T777
Test name
Test status
Simulation time 15473925 ps
CPU time 0.63 seconds
Started Feb 18 12:31:26 PM PST 24
Finished Feb 18 12:31:30 PM PST 24
Peak memory 195376 kb
Host smart-d52705fe-4356-41f7-9da9-116a63bea389
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201265821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4201265821
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.547731838
Short name T790
Test name
Test status
Simulation time 190908396 ps
CPU time 1.12 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:31:35 PM PST 24
Peak memory 198312 kb
Host smart-ec27b47e-9e26-4fc7-9d35-8d91591599e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547731838 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.547731838
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3555670122
Short name T95
Test name
Test status
Simulation time 12785906 ps
CPU time 0.6 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:31:28 PM PST 24
Peak memory 195020 kb
Host smart-7cef9287-e5f9-42cf-aaaf-10260d627321
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555670122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3555670122
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2347433748
Short name T848
Test name
Test status
Simulation time 49368187 ps
CPU time 0.56 seconds
Started Feb 18 12:31:30 PM PST 24
Finished Feb 18 12:31:36 PM PST 24
Peak memory 194220 kb
Host smart-a8bf8801-e803-45d9-9608-3912609a4475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347433748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2347433748
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2854062716
Short name T842
Test name
Test status
Simulation time 15625376 ps
CPU time 0.72 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 197212 kb
Host smart-13713d13-2f1c-4cbc-b4ec-05bccba91733
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854062716 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2854062716
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.740830034
Short name T768
Test name
Test status
Simulation time 35955003 ps
CPU time 1.07 seconds
Started Feb 18 12:35:14 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 196348 kb
Host smart-1f90fcde-28ee-4632-b141-b64563bb9190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740830034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.740830034
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.4037546384
Short name T793
Test name
Test status
Simulation time 172957930 ps
CPU time 1.09 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 198528 kb
Host smart-112d373d-3816-45e3-a2e1-de5ec45f1fab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037546384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.4037546384
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1772259307
Short name T772
Test name
Test status
Simulation time 12510705 ps
CPU time 0.59 seconds
Started Feb 18 12:32:07 PM PST 24
Finished Feb 18 12:32:09 PM PST 24
Peak memory 194168 kb
Host smart-4fecfbef-b0f6-4429-bae0-eb9864bbb07b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772259307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1772259307
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4060409483
Short name T736
Test name
Test status
Simulation time 14083391 ps
CPU time 0.58 seconds
Started Feb 18 12:32:06 PM PST 24
Finished Feb 18 12:32:08 PM PST 24
Peak memory 194828 kb
Host smart-579a1826-c6ea-4a73-92b0-deaa3f3467aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060409483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4060409483
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4287798661
Short name T748
Test name
Test status
Simulation time 38117152 ps
CPU time 0.6 seconds
Started Feb 18 12:32:17 PM PST 24
Finished Feb 18 12:32:18 PM PST 24
Peak memory 194204 kb
Host smart-57139b71-e423-47f0-af05-752e1a932f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287798661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4287798661
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1993846899
Short name T727
Test name
Test status
Simulation time 59944684 ps
CPU time 0.59 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194216 kb
Host smart-57dc243d-6f32-4e0d-a3b8-1447725b3204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993846899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1993846899
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1282228184
Short name T733
Test name
Test status
Simulation time 12626069 ps
CPU time 0.56 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:07 PM PST 24
Peak memory 194152 kb
Host smart-52d384c9-3195-40f3-aec9-c02fe7136794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282228184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1282228184
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.426663141
Short name T808
Test name
Test status
Simulation time 43264090 ps
CPU time 0.6 seconds
Started Feb 18 12:32:13 PM PST 24
Finished Feb 18 12:32:14 PM PST 24
Peak memory 194724 kb
Host smart-8dd99cbe-2a3b-41a9-a284-887e8b5ba5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426663141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.426663141
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2307074406
Short name T743
Test name
Test status
Simulation time 17586782 ps
CPU time 0.63 seconds
Started Feb 18 12:32:09 PM PST 24
Finished Feb 18 12:32:11 PM PST 24
Peak memory 194204 kb
Host smart-f78fc2d0-13d7-420e-bcbd-a756e0ed4766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307074406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2307074406
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.841320661
Short name T801
Test name
Test status
Simulation time 34185454 ps
CPU time 0.61 seconds
Started Feb 18 12:32:05 PM PST 24
Finished Feb 18 12:32:07 PM PST 24
Peak memory 194260 kb
Host smart-aaf1bc89-3800-40fc-8d2a-4180a89c8245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841320661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.841320661
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.4056488276
Short name T750
Test name
Test status
Simulation time 38214960 ps
CPU time 0.56 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194060 kb
Host smart-918114d7-521a-43c0-bda9-33271cc1d392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056488276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.4056488276
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2197102705
Short name T798
Test name
Test status
Simulation time 17722150 ps
CPU time 0.64 seconds
Started Feb 18 12:32:09 PM PST 24
Finished Feb 18 12:32:11 PM PST 24
Peak memory 194188 kb
Host smart-3793c2f9-797b-4dc3-a890-c2c5877fe7a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197102705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2197102705
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3466795404
Short name T826
Test name
Test status
Simulation time 159683667 ps
CPU time 0.76 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:37 PM PST 24
Peak memory 196392 kb
Host smart-028f0d0b-18cf-46c7-8b42-b949d0177fd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466795404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3466795404
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1743314578
Short name T117
Test name
Test status
Simulation time 3379514951 ps
CPU time 2.27 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:31:28 PM PST 24
Peak memory 197852 kb
Host smart-626513e3-51c8-4188-b768-148fab03277b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743314578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1743314578
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1918404205
Short name T89
Test name
Test status
Simulation time 18058000 ps
CPU time 0.6 seconds
Started Feb 18 12:35:27 PM PST 24
Finished Feb 18 12:35:29 PM PST 24
Peak memory 194688 kb
Host smart-4d33b72e-b26f-46fe-b921-84dea363a675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918404205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1918404205
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3066466703
Short name T735
Test name
Test status
Simulation time 141172601 ps
CPU time 2.17 seconds
Started Feb 18 12:31:27 PM PST 24
Finished Feb 18 12:31:34 PM PST 24
Peak memory 198524 kb
Host smart-4b3ad7fa-42f0-4007-a815-305894a3179e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066466703 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3066466703
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2117418901
Short name T94
Test name
Test status
Simulation time 27478711 ps
CPU time 0.59 seconds
Started Feb 18 12:31:28 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 195008 kb
Host smart-74c142ca-12aa-42eb-adc0-1e0a53ea356e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117418901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2117418901
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4034161338
Short name T828
Test name
Test status
Simulation time 54104076 ps
CPU time 0.61 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 194124 kb
Host smart-ea45b04a-d918-41b6-a50a-a868c4ca3ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034161338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4034161338
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4164928096
Short name T805
Test name
Test status
Simulation time 19033932 ps
CPU time 0.83 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 196748 kb
Host smart-c58f63b7-dbba-436e-b803-315c97c5d78f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164928096 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4164928096
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.4076150340
Short name T807
Test name
Test status
Simulation time 446425992 ps
CPU time 1.81 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 198516 kb
Host smart-b74caa94-0a25-4594-a09e-1bd72bfadf8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076150340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.4076150340
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3629530414
Short name T781
Test name
Test status
Simulation time 72556257 ps
CPU time 0.84 seconds
Started Feb 18 12:31:30 PM PST 24
Finished Feb 18 12:31:36 PM PST 24
Peak memory 198308 kb
Host smart-56bbba46-1370-4ff5-a0c1-e5bab3fc6fa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629530414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3629530414
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.858402356
Short name T728
Test name
Test status
Simulation time 26458848 ps
CPU time 0.62 seconds
Started Feb 18 12:32:13 PM PST 24
Finished Feb 18 12:32:14 PM PST 24
Peak memory 194076 kb
Host smart-f66be28e-2c6d-4f27-a3a8-c26ba5ef7df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858402356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.858402356
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2612582591
Short name T792
Test name
Test status
Simulation time 14292625 ps
CPU time 0.6 seconds
Started Feb 18 12:32:13 PM PST 24
Finished Feb 18 12:32:15 PM PST 24
Peak memory 194196 kb
Host smart-e2940cd8-8a7a-4b6f-a455-8455b9fd3702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612582591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2612582591
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.879216804
Short name T752
Test name
Test status
Simulation time 16445862 ps
CPU time 0.64 seconds
Started Feb 18 12:32:07 PM PST 24
Finished Feb 18 12:32:09 PM PST 24
Peak memory 194212 kb
Host smart-b6a28b3d-5abe-4612-a972-540ff9e5ef51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879216804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.879216804
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.524394523
Short name T773
Test name
Test status
Simulation time 13460800 ps
CPU time 0.56 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194120 kb
Host smart-028ebb50-4636-4ebb-91a1-ce776641a373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524394523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.524394523
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4244485936
Short name T797
Test name
Test status
Simulation time 14885443 ps
CPU time 0.6 seconds
Started Feb 18 12:32:08 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 194272 kb
Host smart-3a4a1263-ad37-4b71-bb5a-a0d512ab8ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244485936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4244485936
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2248221419
Short name T834
Test name
Test status
Simulation time 15022238 ps
CPU time 0.59 seconds
Started Feb 18 12:32:13 PM PST 24
Finished Feb 18 12:32:14 PM PST 24
Peak memory 194816 kb
Host smart-6e8c99b8-73d4-4748-9402-7f843c2c58f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248221419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2248221419
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2297022174
Short name T751
Test name
Test status
Simulation time 138891190 ps
CPU time 0.59 seconds
Started Feb 18 12:32:20 PM PST 24
Finished Feb 18 12:32:22 PM PST 24
Peak memory 194160 kb
Host smart-b1d4db5c-01c3-41d5-9ddf-aff58b60e26a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297022174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2297022174
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3047860121
Short name T725
Test name
Test status
Simulation time 55154220 ps
CPU time 0.6 seconds
Started Feb 18 12:32:19 PM PST 24
Finished Feb 18 12:32:21 PM PST 24
Peak memory 194248 kb
Host smart-6c47ee7a-c2bd-431c-8ffb-80cc9c02353f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047860121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3047860121
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2721431948
Short name T732
Test name
Test status
Simulation time 14227180 ps
CPU time 0.6 seconds
Started Feb 18 12:32:18 PM PST 24
Finished Feb 18 12:32:20 PM PST 24
Peak memory 194208 kb
Host smart-daf15d0e-51f4-48b2-9810-0d758ba937bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721431948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2721431948
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1976608090
Short name T742
Test name
Test status
Simulation time 13085541 ps
CPU time 0.6 seconds
Started Feb 18 12:32:19 PM PST 24
Finished Feb 18 12:32:21 PM PST 24
Peak memory 194844 kb
Host smart-01293554-643b-45b4-86e9-2491a91e4f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976608090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1976608090
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.42925102
Short name T779
Test name
Test status
Simulation time 122806301 ps
CPU time 2.44 seconds
Started Feb 18 12:31:26 PM PST 24
Finished Feb 18 12:31:31 PM PST 24
Peak memory 198584 kb
Host smart-d51cc10b-1315-4e20-bb23-bc523d5ee025
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925102 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.42925102
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2861176753
Short name T769
Test name
Test status
Simulation time 118914104 ps
CPU time 0.6 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:37 PM PST 24
Peak memory 196004 kb
Host smart-78e85354-4de8-4b2f-b674-b3e02e378dd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861176753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2861176753
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1834855059
Short name T785
Test name
Test status
Simulation time 48536668 ps
CPU time 0.56 seconds
Started Feb 18 12:31:36 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 194796 kb
Host smart-ba49ae8a-e94c-44af-afa7-eecef257ca7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834855059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1834855059
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3673595106
Short name T812
Test name
Test status
Simulation time 36136681 ps
CPU time 0.95 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:31:25 PM PST 24
Peak memory 197720 kb
Host smart-816b089d-4ae8-45df-8a88-cd5186f2a601
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673595106 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3673595106
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1140214167
Short name T784
Test name
Test status
Simulation time 135650562 ps
CPU time 1.43 seconds
Started Feb 18 12:31:33 PM PST 24
Finished Feb 18 12:31:41 PM PST 24
Peak memory 198592 kb
Host smart-3d4a687f-ab26-4220-90e7-f0a606f13d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140214167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1140214167
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3958438148
Short name T47
Test name
Test status
Simulation time 229880645 ps
CPU time 1.35 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 198492 kb
Host smart-8c87bf0d-decd-4f11-84fe-30f671854e03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958438148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3958438148
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4159234217
Short name T761
Test name
Test status
Simulation time 91047031 ps
CPU time 1.42 seconds
Started Feb 18 12:31:27 PM PST 24
Finished Feb 18 12:31:32 PM PST 24
Peak memory 198488 kb
Host smart-779d4277-707e-4324-8bb6-2ea73b6883ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159234217 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4159234217
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3858440751
Short name T803
Test name
Test status
Simulation time 14364299 ps
CPU time 0.55 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:31:37 PM PST 24
Peak memory 193864 kb
Host smart-ac4eef12-cc31-4d4c-a1f3-590fc05e698d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858440751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3858440751
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2191000801
Short name T745
Test name
Test status
Simulation time 15995667 ps
CPU time 0.59 seconds
Started Feb 18 12:31:28 PM PST 24
Finished Feb 18 12:31:32 PM PST 24
Peak memory 194168 kb
Host smart-ddea582c-3907-4362-abe8-9c4f747db3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191000801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2191000801
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2542504770
Short name T821
Test name
Test status
Simulation time 33544754 ps
CPU time 0.73 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 196424 kb
Host smart-dadb6b74-a63d-4110-97a1-91ab70c5c353
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542504770 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2542504770
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2856582966
Short name T741
Test name
Test status
Simulation time 35035720 ps
CPU time 1.55 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:44 PM PST 24
Peak memory 198512 kb
Host smart-c824212e-474c-4d04-8913-79b86f4f1bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856582966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2856582966
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.973346741
Short name T794
Test name
Test status
Simulation time 258666550 ps
CPU time 2.17 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:44 PM PST 24
Peak memory 198520 kb
Host smart-3ef1d70b-a608-4880-b948-eeb285164911
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973346741 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.973346741
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.519334060
Short name T767
Test name
Test status
Simulation time 43290196 ps
CPU time 0.59 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 195588 kb
Host smart-f96fbe9d-ee2b-4038-b2b0-2bdf6184b3d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519334060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.519334060
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3627632487
Short name T753
Test name
Test status
Simulation time 65441304 ps
CPU time 0.65 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:31:25 PM PST 24
Peak memory 194192 kb
Host smart-d52475d6-b4f3-4e5f-ab8c-798e9f143035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627632487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3627632487
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.55113666
Short name T82
Test name
Test status
Simulation time 145457387 ps
CPU time 0.7 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 195500 kb
Host smart-6a1b09b3-36f2-45ec-8d3a-dc8b398afe97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55113666 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.gpio_same_csr_outstanding.55113666
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3560791357
Short name T762
Test name
Test status
Simulation time 68327658 ps
CPU time 1.82 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198364 kb
Host smart-03e0e168-41b4-4337-8a33-73b95b7eb616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560791357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3560791357
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3117515345
Short name T36
Test name
Test status
Simulation time 143990650 ps
CPU time 0.85 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 198132 kb
Host smart-75fc690a-bed8-4a02-bb76-559d90760742
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117515345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3117515345
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.4215135035
Short name T806
Test name
Test status
Simulation time 31101882 ps
CPU time 1.39 seconds
Started Feb 18 12:31:39 PM PST 24
Finished Feb 18 12:31:44 PM PST 24
Peak memory 198420 kb
Host smart-4a2a7b8d-220f-4210-a3dc-04e786a67d8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215135035 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.4215135035
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3056775819
Short name T749
Test name
Test status
Simulation time 34449444 ps
CPU time 0.56 seconds
Started Feb 18 12:31:34 PM PST 24
Finished Feb 18 12:31:41 PM PST 24
Peak memory 194400 kb
Host smart-bbd3c5ae-e98a-4a5b-985b-79494958b9cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056775819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3056775819
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1876605252
Short name T831
Test name
Test status
Simulation time 49281734 ps
CPU time 0.59 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:31:34 PM PST 24
Peak memory 194872 kb
Host smart-263f1b46-26c7-4c36-a10e-031936fa237c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876605252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1876605252
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3416776432
Short name T813
Test name
Test status
Simulation time 116997932 ps
CPU time 0.64 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:31:34 PM PST 24
Peak memory 195052 kb
Host smart-c77eaeef-970a-4434-a654-03b321c055da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416776432 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3416776432
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2402119758
Short name T809
Test name
Test status
Simulation time 361410288 ps
CPU time 1.86 seconds
Started Feb 18 12:31:36 PM PST 24
Finished Feb 18 12:31:43 PM PST 24
Peak memory 198560 kb
Host smart-61f2007f-c772-4403-83d3-ede88a5a007c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402119758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2402119758
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2930635569
Short name T49
Test name
Test status
Simulation time 271227706 ps
CPU time 1.09 seconds
Started Feb 18 12:31:36 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198512 kb
Host smart-47843e44-7171-49bc-bf0f-e4217c96de07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930635569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2930635569
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1898903126
Short name T766
Test name
Test status
Simulation time 194990761 ps
CPU time 2.59 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:31:37 PM PST 24
Peak memory 198420 kb
Host smart-30a05640-c382-41b9-9035-02b6fce61bd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898903126 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1898903126
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2272052126
Short name T116
Test name
Test status
Simulation time 11402746 ps
CPU time 0.57 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:31:34 PM PST 24
Peak memory 195020 kb
Host smart-a802e10a-2bab-4fb9-af58-bcec091e4f2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272052126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2272052126
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2942013961
Short name T734
Test name
Test status
Simulation time 15479739 ps
CPU time 0.57 seconds
Started Feb 18 12:31:36 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 194952 kb
Host smart-488829b8-68a4-4952-8931-54cefe8dc76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942013961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2942013961
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2351007577
Short name T98
Test name
Test status
Simulation time 31181176 ps
CPU time 0.86 seconds
Started Feb 18 12:31:30 PM PST 24
Finished Feb 18 12:31:35 PM PST 24
Peak memory 197664 kb
Host smart-3396bf4f-55d5-40dd-ae49-dcce1769cfc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351007577 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2351007577
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2900204209
Short name T729
Test name
Test status
Simulation time 131834621 ps
CPU time 0.96 seconds
Started Feb 18 12:31:28 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 198340 kb
Host smart-2e0007e7-52d2-4149-aee7-e8313d37dd94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900204209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2900204209
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2393337785
Short name T782
Test name
Test status
Simulation time 514881808 ps
CPU time 1.39 seconds
Started Feb 18 12:31:35 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 198380 kb
Host smart-c35fc4fc-f1c7-4ebf-a1e4-b6a2f40a562a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393337785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2393337785
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3687322197
Short name T552
Test name
Test status
Simulation time 27224949 ps
CPU time 0.56 seconds
Started Feb 18 02:55:47 PM PST 24
Finished Feb 18 02:55:50 PM PST 24
Peak memory 194280 kb
Host smart-4284e021-eb27-4c33-891d-8446498cd816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687322197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3687322197
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3217912145
Short name T220
Test name
Test status
Simulation time 83528297 ps
CPU time 0.88 seconds
Started Feb 18 02:55:50 PM PST 24
Finished Feb 18 02:55:53 PM PST 24
Peak memory 196868 kb
Host smart-04ef21b9-a742-41c0-9fdc-5785747be329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217912145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3217912145
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3555155758
Short name T215
Test name
Test status
Simulation time 2180203914 ps
CPU time 24.24 seconds
Started Feb 18 02:55:54 PM PST 24
Finished Feb 18 02:56:20 PM PST 24
Peak memory 197380 kb
Host smart-8f2a8c4d-607d-4166-aa98-a9504490031b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555155758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3555155758
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3988470945
Short name T160
Test name
Test status
Simulation time 253191056 ps
CPU time 0.87 seconds
Started Feb 18 02:55:52 PM PST 24
Finished Feb 18 02:55:54 PM PST 24
Peak memory 197168 kb
Host smart-d14d235b-947b-460b-b7ac-155a08c0e974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988470945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3988470945
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.4077201697
Short name T708
Test name
Test status
Simulation time 68230508 ps
CPU time 2.6 seconds
Started Feb 18 02:55:48 PM PST 24
Finished Feb 18 02:55:53 PM PST 24
Peak memory 196732 kb
Host smart-b2fdf1f5-7330-48ca-aca1-7f6b96ff56d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077201697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.4077201697
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.535259775
Short name T75
Test name
Test status
Simulation time 88528349 ps
CPU time 1.83 seconds
Started Feb 18 02:55:48 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 196444 kb
Host smart-7460fb21-401e-41ed-bc71-a7112f0996c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535259775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.535259775
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1831528335
Short name T403
Test name
Test status
Simulation time 233658642 ps
CPU time 1.03 seconds
Started Feb 18 02:55:49 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 196188 kb
Host smart-235069d8-e534-4e69-82d8-945956bb2f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831528335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1831528335
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2286205988
Short name T401
Test name
Test status
Simulation time 115385677 ps
CPU time 1.29 seconds
Started Feb 18 02:55:49 PM PST 24
Finished Feb 18 02:55:53 PM PST 24
Peak memory 197544 kb
Host smart-4308aae6-c8ba-4f01-ba5e-e6a6cf28bb38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286205988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2286205988
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1942585869
Short name T551
Test name
Test status
Simulation time 211101099 ps
CPU time 2.54 seconds
Started Feb 18 02:55:54 PM PST 24
Finished Feb 18 02:55:58 PM PST 24
Peak memory 198424 kb
Host smart-3e00912c-fcd9-461f-a604-bcabcb040a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942585869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1942585869
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2011969779
Short name T54
Test name
Test status
Simulation time 236128446 ps
CPU time 0.92 seconds
Started Feb 18 02:56:00 PM PST 24
Finished Feb 18 02:56:02 PM PST 24
Peak memory 213832 kb
Host smart-74840e68-8547-467b-bfc7-d52dc6461d6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011969779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2011969779
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1467386589
Short name T718
Test name
Test status
Simulation time 168522307 ps
CPU time 1 seconds
Started Feb 18 02:55:52 PM PST 24
Finished Feb 18 02:55:54 PM PST 24
Peak memory 196104 kb
Host smart-cd410d47-4ce9-4b28-bc05-a51c50d9d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467386589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1467386589
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2882271953
Short name T144
Test name
Test status
Simulation time 40347017 ps
CPU time 1.06 seconds
Started Feb 18 02:55:49 PM PST 24
Finished Feb 18 02:55:52 PM PST 24
Peak memory 196964 kb
Host smart-9bc9bd99-bd58-4dd1-8efc-dc2fa096d2fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882271953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2882271953
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2099354734
Short name T632
Test name
Test status
Simulation time 5492786268 ps
CPU time 151.75 seconds
Started Feb 18 02:55:50 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 198556 kb
Host smart-31a43049-18d1-4e2e-8b0f-6d2280b51f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099354734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2099354734
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2898012006
Short name T549
Test name
Test status
Simulation time 13794304 ps
CPU time 0.58 seconds
Started Feb 18 02:55:56 PM PST 24
Finished Feb 18 02:55:59 PM PST 24
Peak memory 195044 kb
Host smart-d4dc9463-37ba-4850-9f0a-d8bf17c4b628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898012006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2898012006
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2489126895
Short name T554
Test name
Test status
Simulation time 36175996 ps
CPU time 0.83 seconds
Started Feb 18 02:55:57 PM PST 24
Finished Feb 18 02:55:59 PM PST 24
Peak memory 195716 kb
Host smart-48911fc6-ec9c-428a-ba2a-3603d1da9690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489126895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2489126895
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.206570901
Short name T418
Test name
Test status
Simulation time 233625901 ps
CPU time 12.29 seconds
Started Feb 18 02:55:57 PM PST 24
Finished Feb 18 02:56:11 PM PST 24
Peak memory 198296 kb
Host smart-00fec55d-052f-40b4-9a8c-dfb5a91dec22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206570901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.206570901
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2795504511
Short name T258
Test name
Test status
Simulation time 76186154 ps
CPU time 0.92 seconds
Started Feb 18 02:55:55 PM PST 24
Finished Feb 18 02:55:58 PM PST 24
Peak memory 197460 kb
Host smart-273b1777-90aa-463d-b0da-cb8d1bf6d4af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795504511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2795504511
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.849397727
Short name T505
Test name
Test status
Simulation time 51907267 ps
CPU time 0.98 seconds
Started Feb 18 02:55:54 PM PST 24
Finished Feb 18 02:55:56 PM PST 24
Peak memory 196516 kb
Host smart-4c7c7e05-ab2b-466a-aa8c-3ecccf21aedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849397727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.849397727
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1793486344
Short name T667
Test name
Test status
Simulation time 76999920 ps
CPU time 3.2 seconds
Started Feb 18 02:55:53 PM PST 24
Finished Feb 18 02:55:58 PM PST 24
Peak memory 198452 kb
Host smart-f4fe1c41-0ee8-4577-8247-87cbaae14259
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793486344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1793486344
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1961383155
Short name T232
Test name
Test status
Simulation time 81870501 ps
CPU time 2.44 seconds
Started Feb 18 02:55:57 PM PST 24
Finished Feb 18 02:56:01 PM PST 24
Peak memory 196936 kb
Host smart-d425643d-24e0-45c0-967c-a499f2dd1115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961383155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1961383155
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3619369481
Short name T659
Test name
Test status
Simulation time 25628846 ps
CPU time 0.88 seconds
Started Feb 18 02:55:56 PM PST 24
Finished Feb 18 02:55:58 PM PST 24
Peak memory 196636 kb
Host smart-c57cf908-5797-4f46-b1df-03c269a0ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619369481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3619369481
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1159936028
Short name T469
Test name
Test status
Simulation time 36917790 ps
CPU time 1.33 seconds
Started Feb 18 02:55:57 PM PST 24
Finished Feb 18 02:56:00 PM PST 24
Peak memory 197224 kb
Host smart-cb6f7d3a-d390-4980-8b5d-da5bbb381495
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159936028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1159936028
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.376066451
Short name T565
Test name
Test status
Simulation time 176894344 ps
CPU time 3.16 seconds
Started Feb 18 02:55:58 PM PST 24
Finished Feb 18 02:56:03 PM PST 24
Peak memory 198388 kb
Host smart-e7dc3142-8a5a-4ece-928c-b71d126f7687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376066451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.376066451
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2558711048
Short name T294
Test name
Test status
Simulation time 122514918 ps
CPU time 1.06 seconds
Started Feb 18 02:55:47 PM PST 24
Finished Feb 18 02:55:50 PM PST 24
Peak memory 196232 kb
Host smart-3d798523-b8e8-4f6d-a895-ad244d564bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558711048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2558711048
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2824744989
Short name T245
Test name
Test status
Simulation time 316889865 ps
CPU time 1.5 seconds
Started Feb 18 02:55:54 PM PST 24
Finished Feb 18 02:55:56 PM PST 24
Peak memory 195988 kb
Host smart-66a8e5f8-8d83-473e-ae34-22bafd62488c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824744989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2824744989
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3166706928
Short name T648
Test name
Test status
Simulation time 5842110819 ps
CPU time 155.36 seconds
Started Feb 18 02:55:54 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 198600 kb
Host smart-6bf0aab9-7e74-4db0-b82e-3b6b9d7e6973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166706928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3166706928
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.21682438
Short name T202
Test name
Test status
Simulation time 17696303 ps
CPU time 0.57 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:56:41 PM PST 24
Peak memory 194316 kb
Host smart-9aaad551-8798-44ca-8d0a-717138268d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21682438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.21682438
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3466973976
Short name T562
Test name
Test status
Simulation time 172644705 ps
CPU time 0.89 seconds
Started Feb 18 02:56:43 PM PST 24
Finished Feb 18 02:56:48 PM PST 24
Peak memory 197504 kb
Host smart-02e4376f-d99f-44ed-95f6-4c078aeaa2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466973976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3466973976
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4041714730
Short name T532
Test name
Test status
Simulation time 776540092 ps
CPU time 26.27 seconds
Started Feb 18 02:56:39 PM PST 24
Finished Feb 18 02:57:10 PM PST 24
Peak memory 197388 kb
Host smart-18aefd02-38d7-4428-bbe1-b9e72f09d593
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041714730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4041714730
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1000016699
Short name T159
Test name
Test status
Simulation time 59597184 ps
CPU time 0.98 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 196432 kb
Host smart-e7d146d6-62d3-4844-973f-4ea6333eb16f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000016699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1000016699
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2804045566
Short name T688
Test name
Test status
Simulation time 44630622 ps
CPU time 1.17 seconds
Started Feb 18 02:56:42 PM PST 24
Finished Feb 18 02:56:48 PM PST 24
Peak memory 196444 kb
Host smart-a10977f7-4afc-440d-8726-8c2e9c1fbd14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804045566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2804045566
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1918708330
Short name T351
Test name
Test status
Simulation time 93514513 ps
CPU time 3.9 seconds
Started Feb 18 02:56:43 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 198460 kb
Host smart-12652b93-be3d-438a-9054-808a87f09423
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918708330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1918708330
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.230752388
Short name T250
Test name
Test status
Simulation time 231445509 ps
CPU time 1.86 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 197668 kb
Host smart-4b4f14a2-b7f9-40ce-b9f1-b56f5bb80aac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230752388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
230752388
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.305056645
Short name T130
Test name
Test status
Simulation time 156405864 ps
CPU time 1.16 seconds
Started Feb 18 02:56:39 PM PST 24
Finished Feb 18 02:56:43 PM PST 24
Peak memory 196564 kb
Host smart-dc5b19f0-55c0-4b89-b09f-d4ac43d13999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305056645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.305056645
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3646630411
Short name T510
Test name
Test status
Simulation time 133197665 ps
CPU time 1.18 seconds
Started Feb 18 02:56:39 PM PST 24
Finished Feb 18 02:56:44 PM PST 24
Peak memory 197276 kb
Host smart-285376a0-fb43-4600-b5f6-f4c38674dcea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646630411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3646630411
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.477360353
Short name T405
Test name
Test status
Simulation time 321429863 ps
CPU time 4.23 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:54 PM PST 24
Peak memory 198396 kb
Host smart-8981d530-f602-4c19-9e64-fabcf719647b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477360353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.477360353
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.786424780
Short name T717
Test name
Test status
Simulation time 394449847 ps
CPU time 1.12 seconds
Started Feb 18 02:56:44 PM PST 24
Finished Feb 18 02:56:49 PM PST 24
Peak memory 195956 kb
Host smart-453d5bc4-90c6-457f-8a35-e1db0e4c4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786424780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.786424780
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.628822780
Short name T422
Test name
Test status
Simulation time 172319052 ps
CPU time 0.96 seconds
Started Feb 18 02:56:38 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 195936 kb
Host smart-6a1a4311-aa7c-4d19-8e8c-58d841a6b7f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628822780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.628822780
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1644411904
Short name T706
Test name
Test status
Simulation time 4306497026 ps
CPU time 46.38 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:57:27 PM PST 24
Peak memory 198580 kb
Host smart-de07c7e1-ab2d-4d04-8677-66fd42a5593f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644411904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1644411904
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.440669459
Short name T585
Test name
Test status
Simulation time 24941781 ps
CPU time 0.57 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 194276 kb
Host smart-13445720-082a-4cd9-a496-99e1e8a2f141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440669459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.440669459
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3933552513
Short name T420
Test name
Test status
Simulation time 129248700 ps
CPU time 0.9 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:50 PM PST 24
Peak memory 196292 kb
Host smart-c6d1a845-e823-4db5-bbf4-04e3aea4243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933552513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3933552513
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.93674421
Short name T569
Test name
Test status
Simulation time 139242254 ps
CPU time 6.77 seconds
Started Feb 18 02:56:40 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 197364 kb
Host smart-191aec6a-be00-4db1-9738-06d9120be3e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93674421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stress
.93674421
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3589835620
Short name T438
Test name
Test status
Simulation time 81255018 ps
CPU time 1.16 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:56:41 PM PST 24
Peak memory 198360 kb
Host smart-25ad2164-2c73-4a21-8d65-ee817c263308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589835620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3589835620
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1788565625
Short name T600
Test name
Test status
Simulation time 85654518 ps
CPU time 1.51 seconds
Started Feb 18 02:56:38 PM PST 24
Finished Feb 18 02:56:43 PM PST 24
Peak memory 198428 kb
Host smart-ec705bd1-b316-453f-8c1b-317800ad28d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788565625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1788565625
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.63506978
Short name T195
Test name
Test status
Simulation time 883496193 ps
CPU time 3.02 seconds
Started Feb 18 02:56:47 PM PST 24
Finished Feb 18 02:56:55 PM PST 24
Peak memory 198512 kb
Host smart-2c4bf4e8-1a06-4a05-98b7-60e9ced17fd6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63506978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_intr_with_filter_rand_intr_event.63506978
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3345648981
Short name T459
Test name
Test status
Simulation time 42940696 ps
CPU time 1.2 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 195952 kb
Host smart-b1206e1a-8b20-44a1-9b59-37b31e1daea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345648981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3345648981
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2906717915
Short name T282
Test name
Test status
Simulation time 82576341 ps
CPU time 0.87 seconds
Started Feb 18 02:56:41 PM PST 24
Finished Feb 18 02:56:47 PM PST 24
Peak memory 197676 kb
Host smart-aab018ec-391f-4ccf-9617-d3913a8cd24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906717915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2906717915
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.509811994
Short name T368
Test name
Test status
Simulation time 87707259 ps
CPU time 0.97 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 197132 kb
Host smart-c6a25a9c-d669-497e-97d8-5dbd6ec8a9f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509811994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.509811994
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.328378346
Short name T6
Test name
Test status
Simulation time 503338568 ps
CPU time 6.21 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 198380 kb
Host smart-72d15a1c-2071-4d7f-83fa-d34bc96379b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328378346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.328378346
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1471752255
Short name T141
Test name
Test status
Simulation time 41853057 ps
CPU time 0.95 seconds
Started Feb 18 02:56:39 PM PST 24
Finished Feb 18 02:56:43 PM PST 24
Peak memory 196000 kb
Host smart-0767710a-c78c-47ea-9df3-3d810aea83a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471752255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1471752255
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4016131582
Short name T347
Test name
Test status
Simulation time 84362967 ps
CPU time 1.45 seconds
Started Feb 18 02:56:39 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 196700 kb
Host smart-be013b47-fc22-4f41-b196-e0baa3425e5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016131582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4016131582
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1398412371
Short name T274
Test name
Test status
Simulation time 54314388628 ps
CPU time 106.61 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:58:37 PM PST 24
Peak memory 198600 kb
Host smart-e38461d2-1781-4ff8-9152-f4ee3e4ce31f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398412371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1398412371
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.421395238
Short name T113
Test name
Test status
Simulation time 114584070674 ps
CPU time 1154.36 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 03:16:06 PM PST 24
Peak memory 198696 kb
Host smart-a50840e9-a2c1-4431-a923-a4b3c044aad0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=421395238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.421395238
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2806595080
Short name T375
Test name
Test status
Simulation time 57121118 ps
CPU time 0.56 seconds
Started Feb 18 02:56:50 PM PST 24
Finished Feb 18 02:56:54 PM PST 24
Peak memory 194284 kb
Host smart-5b45d46f-8cb1-4244-98bd-b23d5e1eb57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806595080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2806595080
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2338719738
Short name T183
Test name
Test status
Simulation time 290248436 ps
CPU time 0.86 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 196820 kb
Host smart-bd87b613-bd03-434a-8325-da381d806315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338719738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2338719738
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1773361465
Short name T151
Test name
Test status
Simulation time 4016148377 ps
CPU time 21.52 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:57:11 PM PST 24
Peak memory 197892 kb
Host smart-32b06d97-929f-4cf0-9f2f-06870ef82d1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773361465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1773361465
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1603347483
Short name T244
Test name
Test status
Simulation time 51025539 ps
CPU time 0.83 seconds
Started Feb 18 02:56:44 PM PST 24
Finished Feb 18 02:56:50 PM PST 24
Peak memory 196188 kb
Host smart-6d1fdf88-daa8-479b-8399-129559cf29a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603347483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1603347483
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.234933065
Short name T571
Test name
Test status
Simulation time 27259270 ps
CPU time 0.72 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 194652 kb
Host smart-6a51223c-5dba-46cb-9ba0-92d41b3db688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234933065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.234933065
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3089013274
Short name T344
Test name
Test status
Simulation time 157665734 ps
CPU time 1.09 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:52 PM PST 24
Peak memory 196628 kb
Host smart-48df5244-fd14-4e31-ad74-a5afdd6eef59
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089013274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3089013274
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3889942927
Short name T409
Test name
Test status
Simulation time 134671194 ps
CPU time 2.15 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:52 PM PST 24
Peak memory 198520 kb
Host smart-29b8c2c6-17dd-4264-b97b-49609d4f0abb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889942927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3889942927
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3003928777
Short name T224
Test name
Test status
Simulation time 45947624 ps
CPU time 1.37 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 197436 kb
Host smart-1cb8d883-abf9-46bb-8453-516824711701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003928777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3003928777
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.466647283
Short name T580
Test name
Test status
Simulation time 56703512 ps
CPU time 0.84 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 196936 kb
Host smart-49fa3cbd-8dda-488e-b393-62c1efaae33b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466647283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.466647283
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2945572628
Short name T482
Test name
Test status
Simulation time 344620154 ps
CPU time 2.55 seconds
Started Feb 18 02:56:49 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 198440 kb
Host smart-a0ca9cd1-7171-4683-abe8-1c1aba8fa5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945572628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2945572628
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1397115932
Short name T251
Test name
Test status
Simulation time 379737209 ps
CPU time 1.49 seconds
Started Feb 18 02:56:45 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 197188 kb
Host smart-db4a4452-66de-4d26-9546-6dcfe5e8ff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397115932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1397115932
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3737743537
Short name T601
Test name
Test status
Simulation time 131654675 ps
CPU time 1.09 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:52 PM PST 24
Peak memory 196152 kb
Host smart-260d0da2-6fe7-4124-aca7-ac0eba9abaf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737743537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3737743537
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2150395090
Short name T313
Test name
Test status
Simulation time 42498306702 ps
CPU time 74.17 seconds
Started Feb 18 02:56:43 PM PST 24
Finished Feb 18 02:58:01 PM PST 24
Peak memory 198564 kb
Host smart-5f19f18c-f4b7-4534-98c9-115342d761ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150395090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2150395090
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1255066473
Short name T599
Test name
Test status
Simulation time 529310744615 ps
CPU time 532.09 seconds
Started Feb 18 02:56:48 PM PST 24
Finished Feb 18 03:05:45 PM PST 24
Peak memory 198728 kb
Host smart-2d0a193b-3243-4480-b729-4cf37563b47a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1255066473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1255066473
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3628511615
Short name T236
Test name
Test status
Simulation time 14324662 ps
CPU time 0.58 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 195012 kb
Host smart-69ee1d77-646e-4ab8-99b6-283861e65eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628511615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3628511615
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1408695030
Short name T683
Test name
Test status
Simulation time 41911366 ps
CPU time 0.63 seconds
Started Feb 18 02:57:02 PM PST 24
Finished Feb 18 02:57:16 PM PST 24
Peak memory 194092 kb
Host smart-2625a9fa-b150-4a39-a2d9-a8c31c1f63cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408695030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1408695030
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.662414863
Short name T524
Test name
Test status
Simulation time 672270144 ps
CPU time 15.2 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 02:57:12 PM PST 24
Peak memory 196952 kb
Host smart-31f1bd25-8aa8-42cf-9a1d-208664000149
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662414863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.662414863
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3417143870
Short name T665
Test name
Test status
Simulation time 32630619 ps
CPU time 0.78 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 196132 kb
Host smart-822f5996-3755-4454-a501-d0553ddf1f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417143870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3417143870
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2572807927
Short name T485
Test name
Test status
Simulation time 130032350 ps
CPU time 0.73 seconds
Started Feb 18 02:56:59 PM PST 24
Finished Feb 18 02:57:02 PM PST 24
Peak memory 196596 kb
Host smart-89687500-8fc7-4094-a41e-82f7ca1de325
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572807927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2572807927
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2090335923
Short name T581
Test name
Test status
Simulation time 111656939 ps
CPU time 1.56 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 02:56:59 PM PST 24
Peak memory 198432 kb
Host smart-e1e25126-3e81-48de-b49e-119e8ecab5d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090335923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2090335923
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4214379016
Short name T264
Test name
Test status
Simulation time 102087760 ps
CPU time 1.59 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 02:56:59 PM PST 24
Peak memory 196356 kb
Host smart-b32ec0d2-6328-4452-a92f-e4868f6e0c7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214379016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4214379016
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2975662439
Short name T410
Test name
Test status
Simulation time 33561300 ps
CPU time 0.73 seconds
Started Feb 18 02:57:02 PM PST 24
Finished Feb 18 02:57:16 PM PST 24
Peak memory 194608 kb
Host smart-d2f5e193-d803-404c-b2dd-dd69d21b1330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975662439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2975662439
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4200734418
Short name T583
Test name
Test status
Simulation time 173809992 ps
CPU time 1.06 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 02:56:57 PM PST 24
Peak memory 196488 kb
Host smart-1114c1a4-90ad-490b-92df-89e1c93d7137
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200734418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.4200734418
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.789851071
Short name T390
Test name
Test status
Simulation time 627478397 ps
CPU time 4.76 seconds
Started Feb 18 02:56:51 PM PST 24
Finished Feb 18 02:56:59 PM PST 24
Peak memory 198372 kb
Host smart-101e1310-0ff0-4827-8d11-2e8a95ff842d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789851071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.789851071
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.234039396
Short name T336
Test name
Test status
Simulation time 20340572 ps
CPU time 0.68 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:51 PM PST 24
Peak memory 194524 kb
Host smart-7e8fffd6-ed55-4155-b82f-f2649bb48e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234039396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.234039396
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1908389180
Short name T534
Test name
Test status
Simulation time 435761476 ps
CPU time 1.43 seconds
Started Feb 18 02:56:46 PM PST 24
Finished Feb 18 02:56:52 PM PST 24
Peak memory 197152 kb
Host smart-206d48ef-324c-441a-9e37-b46c80c1d441
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908389180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1908389180
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.521721001
Short name T536
Test name
Test status
Simulation time 33768195786 ps
CPU time 88.46 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 198580 kb
Host smart-4334464c-2258-4ddd-a882-2339b4233609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521721001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.521721001
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2969702035
Short name T408
Test name
Test status
Simulation time 59040074013 ps
CPU time 628.04 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 03:07:25 PM PST 24
Peak memory 198648 kb
Host smart-1b3bf956-991a-4d38-a090-7c0f08284a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2969702035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2969702035
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4042997144
Short name T462
Test name
Test status
Simulation time 14728038 ps
CPU time 0.6 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:12 PM PST 24
Peak memory 194292 kb
Host smart-8592a7e3-6bd5-485e-8d71-180398f288be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042997144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4042997144
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.599113774
Short name T455
Test name
Test status
Simulation time 22521287 ps
CPU time 0.77 seconds
Started Feb 18 02:56:55 PM PST 24
Finished Feb 18 02:56:59 PM PST 24
Peak memory 195700 kb
Host smart-31fe947c-4026-42b0-92cc-1d28cb37ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599113774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.599113774
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1734117651
Short name T625
Test name
Test status
Simulation time 3347186229 ps
CPU time 17.26 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:57:13 PM PST 24
Peak memory 198524 kb
Host smart-a8a3fa71-9353-4f2b-8294-32e7e87a4d8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734117651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1734117651
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2392472962
Short name T539
Test name
Test status
Simulation time 91740470 ps
CPU time 0.92 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 02:56:58 PM PST 24
Peak memory 197480 kb
Host smart-b996d0dc-008b-47f5-9e72-e1244de4eb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392472962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2392472962
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1490726821
Short name T149
Test name
Test status
Simulation time 41939397 ps
CPU time 0.77 seconds
Started Feb 18 02:56:58 PM PST 24
Finished Feb 18 02:57:01 PM PST 24
Peak memory 195896 kb
Host smart-ad6d9fd6-b898-4678-b7df-3aba6194b681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490726821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1490726821
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.82558095
Short name T553
Test name
Test status
Simulation time 29776666 ps
CPU time 1.11 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 195952 kb
Host smart-5ba3e90f-0438-40b2-add8-0599ea086328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82558095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.82558095
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2707111725
Short name T644
Test name
Test status
Simulation time 32585717 ps
CPU time 1.15 seconds
Started Feb 18 02:56:56 PM PST 24
Finished Feb 18 02:56:59 PM PST 24
Peak memory 198480 kb
Host smart-3efac462-b89e-48f0-a0b1-148b5df211fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707111725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2707111725
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4256690018
Short name T73
Test name
Test status
Simulation time 134949567 ps
CPU time 0.92 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 196288 kb
Host smart-276a252e-a48f-4d6e-b24b-69008193e2a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256690018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4256690018
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3441061214
Short name T381
Test name
Test status
Simulation time 244908460 ps
CPU time 4.23 seconds
Started Feb 18 02:56:55 PM PST 24
Finished Feb 18 02:57:02 PM PST 24
Peak memory 198432 kb
Host smart-86269642-d444-4220-b8e3-5460648c7b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441061214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3441061214
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2562808187
Short name T154
Test name
Test status
Simulation time 141514885 ps
CPU time 1.15 seconds
Started Feb 18 02:56:53 PM PST 24
Finished Feb 18 02:56:56 PM PST 24
Peak memory 195968 kb
Host smart-a3e6d7c2-6b20-4eb4-bbbe-8463daf782ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562808187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2562808187
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1632842520
Short name T273
Test name
Test status
Simulation time 84876579 ps
CPU time 1.38 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 02:56:59 PM PST 24
Peak memory 198416 kb
Host smart-c7439fd0-b463-45f4-99ec-9d9e3074bea1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632842520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1632842520
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.4208381493
Short name T176
Test name
Test status
Simulation time 13834539355 ps
CPU time 193.52 seconds
Started Feb 18 02:56:54 PM PST 24
Finished Feb 18 03:00:10 PM PST 24
Peak memory 198552 kb
Host smart-e1d0bc24-9b48-42f0-ba39-b0814b183a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208381493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.4208381493
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1072006603
Short name T293
Test name
Test status
Simulation time 14129807 ps
CPU time 0.63 seconds
Started Feb 18 02:56:59 PM PST 24
Finished Feb 18 02:57:02 PM PST 24
Peak memory 194300 kb
Host smart-4dd525ba-d01a-4ef7-8e0b-d0a25e854552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072006603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1072006603
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1508350270
Short name T382
Test name
Test status
Simulation time 212987750 ps
CPU time 0.78 seconds
Started Feb 18 02:57:06 PM PST 24
Finished Feb 18 02:57:20 PM PST 24
Peak memory 195784 kb
Host smart-d0e7f615-1bbe-4cf7-9c6b-81d075e47f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508350270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1508350270
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2744914061
Short name T24
Test name
Test status
Simulation time 925203545 ps
CPU time 7.4 seconds
Started Feb 18 02:57:02 PM PST 24
Finished Feb 18 02:57:22 PM PST 24
Peak memory 198452 kb
Host smart-9fe62d9a-d5a9-4c5b-942d-1d8ff0569efd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744914061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2744914061
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3751092695
Short name T530
Test name
Test status
Simulation time 162000714 ps
CPU time 0.77 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:57:25 PM PST 24
Peak memory 195140 kb
Host smart-d6c92de2-8623-49ee-9891-23cc6743d846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751092695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3751092695
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1972763532
Short name T327
Test name
Test status
Simulation time 171790673 ps
CPU time 0.99 seconds
Started Feb 18 02:57:03 PM PST 24
Finished Feb 18 02:57:18 PM PST 24
Peak memory 196940 kb
Host smart-4c013308-b58a-4793-9a99-7c429fd728a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972763532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1972763532
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2517264535
Short name T165
Test name
Test status
Simulation time 75949974 ps
CPU time 0.88 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:57:25 PM PST 24
Peak memory 196584 kb
Host smart-39b1ee5b-e956-43d0-879a-322c2dd58e96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517264535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2517264535
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1434768920
Short name T395
Test name
Test status
Simulation time 203280797 ps
CPU time 2.42 seconds
Started Feb 18 02:57:02 PM PST 24
Finished Feb 18 02:57:17 PM PST 24
Peak memory 196408 kb
Host smart-b150a516-9a8e-4e53-b44f-37a930079c91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434768920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1434768920
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.506989169
Short name T340
Test name
Test status
Simulation time 30904597 ps
CPU time 1.09 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:09 PM PST 24
Peak memory 196472 kb
Host smart-3f390b3c-6465-4f34-ac71-236d61841f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506989169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.506989169
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3673105304
Short name T497
Test name
Test status
Simulation time 149668284 ps
CPU time 1 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:08 PM PST 24
Peak memory 196492 kb
Host smart-9dc5746e-44c0-4e0e-a034-ebddbde693c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673105304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3673105304
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.667834770
Short name T5
Test name
Test status
Simulation time 1415663494 ps
CPU time 7.11 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:21 PM PST 24
Peak memory 198400 kb
Host smart-f6c07ace-0c45-4fc6-9d43-4719631cfc8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667834770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.667834770
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3212623336
Short name T630
Test name
Test status
Simulation time 287828826 ps
CPU time 0.86 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:57:25 PM PST 24
Peak memory 195784 kb
Host smart-06c1f5db-5c4a-49d3-8e7f-268d01537535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212623336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3212623336
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.159287272
Short name T132
Test name
Test status
Simulation time 131124724 ps
CPU time 1.21 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:57:25 PM PST 24
Peak memory 196208 kb
Host smart-cd8b1f16-2a95-4a33-92b1-fab4adb8814b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159287272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.159287272
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2461709409
Short name T646
Test name
Test status
Simulation time 4472031563 ps
CPU time 114.09 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 198580 kb
Host smart-2a5ddd8d-22b3-49ff-a21b-a6633804e062
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461709409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2461709409
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.285980054
Short name T341
Test name
Test status
Simulation time 15071627 ps
CPU time 0.59 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:57:40 PM PST 24
Peak memory 195292 kb
Host smart-3c4f2476-4268-431d-9777-bc7e669fe0e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285980054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.285980054
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3925759189
Short name T45
Test name
Test status
Simulation time 45852007 ps
CPU time 0.82 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:57:25 PM PST 24
Peak memory 195632 kb
Host smart-8908eabf-8887-4181-bcd0-0040fb04d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925759189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3925759189
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4134930518
Short name T163
Test name
Test status
Simulation time 1687045940 ps
CPU time 11.02 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:58:01 PM PST 24
Peak memory 197268 kb
Host smart-3eb7886d-caaf-414c-8e8e-feca0a013d2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134930518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4134930518
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3658554539
Short name T358
Test name
Test status
Simulation time 38368514 ps
CPU time 0.64 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 194732 kb
Host smart-3ec41385-81f7-44a9-ba6f-7c06075e801d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658554539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3658554539
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3177558465
Short name T269
Test name
Test status
Simulation time 46723653 ps
CPU time 1.45 seconds
Started Feb 18 02:57:08 PM PST 24
Finished Feb 18 02:57:26 PM PST 24
Peak memory 198416 kb
Host smart-adf923ac-c0be-4b28-9c25-4aafddb4f5a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177558465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3177558465
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3440431822
Short name T267
Test name
Test status
Simulation time 343873738 ps
CPU time 3.49 seconds
Started Feb 18 02:57:19 PM PST 24
Finished Feb 18 02:57:55 PM PST 24
Peak memory 198556 kb
Host smart-8037d66b-f817-4269-a085-bc1ee4f4261c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440431822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3440431822
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.101455866
Short name T444
Test name
Test status
Simulation time 36055313 ps
CPU time 1.05 seconds
Started Feb 18 02:57:03 PM PST 24
Finished Feb 18 02:57:18 PM PST 24
Peak memory 195892 kb
Host smart-e20a8e31-4cfe-4c3a-bab0-f54c71279a83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101455866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
101455866
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.849338180
Short name T235
Test name
Test status
Simulation time 40135796 ps
CPU time 1.12 seconds
Started Feb 18 02:57:00 PM PST 24
Finished Feb 18 02:57:03 PM PST 24
Peak memory 197104 kb
Host smart-32e16cfa-f301-4deb-94f7-5cdf966fbe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849338180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.849338180
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3168657717
Short name T464
Test name
Test status
Simulation time 52699184 ps
CPU time 1.17 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:12 PM PST 24
Peak memory 197204 kb
Host smart-4ed45bdf-b6a1-4a7e-aca2-0e2dca77ae73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168657717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3168657717
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2215190605
Short name T119
Test name
Test status
Simulation time 1840877492 ps
CPU time 1.88 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:52 PM PST 24
Peak memory 198416 kb
Host smart-7677382d-d625-4232-95b7-e1384780c1bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215190605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2215190605
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2223326999
Short name T249
Test name
Test status
Simulation time 207186780 ps
CPU time 1.13 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:11 PM PST 24
Peak memory 196180 kb
Host smart-b41f8398-cbc6-464a-a142-d0fc23b1a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223326999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2223326999
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3073842451
Short name T18
Test name
Test status
Simulation time 48511817 ps
CPU time 1.31 seconds
Started Feb 18 02:57:01 PM PST 24
Finished Feb 18 02:57:09 PM PST 24
Peak memory 196668 kb
Host smart-7a517bd7-a103-4662-aa8e-aafd9a555b42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073842451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3073842451
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1434815728
Short name T80
Test name
Test status
Simulation time 10010265594 ps
CPU time 41.16 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:58:31 PM PST 24
Peak memory 198608 kb
Host smart-5c4b2a69-7843-401e-80a2-e0b929a0fa19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434815728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1434815728
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.859641526
Short name T67
Test name
Test status
Simulation time 59119704314 ps
CPU time 481.03 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 03:05:51 PM PST 24
Peak memory 198684 kb
Host smart-fe9d8f36-c5c7-453b-8787-fc84e41fdc29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=859641526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.859641526
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3767824967
Short name T256
Test name
Test status
Simulation time 12824890 ps
CPU time 0.55 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:56 PM PST 24
Peak memory 194268 kb
Host smart-1f8c4979-d738-409d-837f-40aea27f9cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767824967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3767824967
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1573276709
Short name T466
Test name
Test status
Simulation time 22477463 ps
CPU time 0.78 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:57:40 PM PST 24
Peak memory 196412 kb
Host smart-42c8fe4b-34e6-41ec-ae71-73f953ccdd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573276709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1573276709
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4146304942
Short name T182
Test name
Test status
Simulation time 1023752591 ps
CPU time 26.45 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:58:08 PM PST 24
Peak memory 198448 kb
Host smart-45d63eab-bf18-461d-90fe-c879c3aabd72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146304942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4146304942
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3702060828
Short name T372
Test name
Test status
Simulation time 108049764 ps
CPU time 0.97 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:49 PM PST 24
Peak memory 197560 kb
Host smart-c2bfa1c8-605b-43bd-bfbe-e32cc0027439
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702060828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3702060828
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3875196191
Short name T609
Test name
Test status
Simulation time 48015852 ps
CPU time 0.85 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 197600 kb
Host smart-df847ea6-90e9-49d4-ab44-f4becfe13dc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875196191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3875196191
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.706666754
Short name T335
Test name
Test status
Simulation time 87677331 ps
CPU time 3.3 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:54 PM PST 24
Peak memory 198496 kb
Host smart-818b453d-bb97-428c-862b-2cf87b51470b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706666754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.706666754
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2783936660
Short name T199
Test name
Test status
Simulation time 311353786 ps
CPU time 2.59 seconds
Started Feb 18 02:57:13 PM PST 24
Finished Feb 18 02:57:41 PM PST 24
Peak memory 196284 kb
Host smart-b88d8399-400f-4650-8ffb-fa928e28ac81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783936660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2783936660
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.199806465
Short name T184
Test name
Test status
Simulation time 170730599 ps
CPU time 0.87 seconds
Started Feb 18 02:57:19 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 196408 kb
Host smart-5c5eca36-a6d9-4041-9c3d-c2d8d8564cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199806465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.199806465
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2315258256
Short name T709
Test name
Test status
Simulation time 40911992 ps
CPU time 0.99 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:57:44 PM PST 24
Peak memory 196256 kb
Host smart-149f2ae6-f693-4ea6-aac7-f7d89b9afe04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315258256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2315258256
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.198060402
Short name T451
Test name
Test status
Simulation time 749938128 ps
CPU time 3.2 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:57:44 PM PST 24
Peak memory 198412 kb
Host smart-8fec047f-8538-403e-b466-cedaa20050a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198060402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.198060402
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.757754743
Short name T450
Test name
Test status
Simulation time 161072966 ps
CPU time 0.95 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:58 PM PST 24
Peak memory 196200 kb
Host smart-8ea8e243-9959-4a11-b449-8d763aef0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757754743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.757754743
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.625774416
Short name T13
Test name
Test status
Simulation time 93926247 ps
CPU time 0.94 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196956 kb
Host smart-e35e3c12-2a1c-4ed2-a7d6-89cf53fdfb6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625774416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.625774416
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1437996876
Short name T477
Test name
Test status
Simulation time 6172554409 ps
CPU time 87.67 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 198576 kb
Host smart-4f8fa60c-a968-404c-878c-9134204a5c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437996876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1437996876
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2157524437
Short name T21
Test name
Test status
Simulation time 76838418 ps
CPU time 0.54 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:57:46 PM PST 24
Peak memory 194992 kb
Host smart-3ff79fb5-9154-4ae9-98f2-bed818d5b2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157524437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2157524437
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3964564497
Short name T460
Test name
Test status
Simulation time 42112606 ps
CPU time 0.93 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:57:44 PM PST 24
Peak memory 196404 kb
Host smart-053c0f44-3e8e-4114-b7db-b1d18c18c8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964564497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3964564497
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2796290440
Short name T595
Test name
Test status
Simulation time 916042668 ps
CPU time 26.23 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:58:16 PM PST 24
Peak memory 196000 kb
Host smart-0d2a093c-1639-4d24-8948-152321012bc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796290440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2796290440
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.672023950
Short name T547
Test name
Test status
Simulation time 281609463 ps
CPU time 0.98 seconds
Started Feb 18 02:57:13 PM PST 24
Finished Feb 18 02:57:39 PM PST 24
Peak memory 198456 kb
Host smart-6776fee5-45b6-44ce-a18b-e396220cdc77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672023950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.672023950
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1673062484
Short name T11
Test name
Test status
Simulation time 603169336 ps
CPU time 1.13 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 196184 kb
Host smart-965f54d7-a5b8-4636-a891-6c0ffac8cd7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673062484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1673062484
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2945534729
Short name T243
Test name
Test status
Simulation time 79661978 ps
CPU time 3.06 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 198472 kb
Host smart-576aa1ab-bf69-4041-aa93-338afca2034c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945534729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2945534729
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3330455279
Short name T309
Test name
Test status
Simulation time 307658367 ps
CPU time 1.05 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:50 PM PST 24
Peak memory 196776 kb
Host smart-37bc7cc7-47f8-4ccd-b40d-c0a9b014f822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330455279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3330455279
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1142444368
Short name T606
Test name
Test status
Simulation time 79553999 ps
CPU time 0.83 seconds
Started Feb 18 02:57:18 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 196548 kb
Host smart-3bc6b62b-4186-4ae5-853f-4d4777497859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142444368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1142444368
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2905790131
Short name T568
Test name
Test status
Simulation time 33488854 ps
CPU time 1.29 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 198524 kb
Host smart-7c3c21dc-5719-4606-9a91-8239357001e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905790131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2905790131
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1075223723
Short name T166
Test name
Test status
Simulation time 197954822 ps
CPU time 2.56 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:58:01 PM PST 24
Peak memory 198372 kb
Host smart-3d027aee-fd29-4694-bb7a-109d3f048513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075223723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1075223723
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3101294490
Short name T190
Test name
Test status
Simulation time 186138783 ps
CPU time 1.21 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:57:59 PM PST 24
Peak memory 196244 kb
Host smart-7dbf0ce5-1c2f-40c5-81f9-0deb61f03982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101294490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3101294490
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2158149041
Short name T695
Test name
Test status
Simulation time 63095257 ps
CPU time 1.2 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 196980 kb
Host smart-bda3fc0a-15f4-4761-a73e-b1851c15f609
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158149041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2158149041
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3959265168
Short name T588
Test name
Test status
Simulation time 40067129427 ps
CPU time 114.25 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:59:35 PM PST 24
Peak memory 198552 kb
Host smart-4605c1d1-3e77-48c8-b5fa-5b01ab21df62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959265168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3959265168
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3624297432
Short name T71
Test name
Test status
Simulation time 79451624044 ps
CPU time 294.9 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 03:02:40 PM PST 24
Peak memory 206868 kb
Host smart-8915091f-9fae-42b0-ba6a-e6cd71a409b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3624297432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3624297432
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2902982689
Short name T385
Test name
Test status
Simulation time 49122288 ps
CPU time 0.58 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 194316 kb
Host smart-f865af6b-0a86-4f2f-9d7c-774e9355ddca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902982689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2902982689
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.798940044
Short name T559
Test name
Test status
Simulation time 24604257 ps
CPU time 0.87 seconds
Started Feb 18 02:57:20 PM PST 24
Finished Feb 18 02:57:55 PM PST 24
Peak memory 196632 kb
Host smart-3af350be-f427-4dd2-8be9-ac64040a3982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798940044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.798940044
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4157504394
Short name T619
Test name
Test status
Simulation time 236185544 ps
CPU time 6.66 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:57:49 PM PST 24
Peak memory 197192 kb
Host smart-5f92c1fc-9a0b-41d6-8109-db58451558f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157504394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4157504394
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2203026050
Short name T412
Test name
Test status
Simulation time 25056122 ps
CPU time 0.66 seconds
Started Feb 18 02:57:20 PM PST 24
Finished Feb 18 02:57:55 PM PST 24
Peak memory 194832 kb
Host smart-e08d1bca-bd35-4e8e-9a86-a9bf09683ae0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203026050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2203026050
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3245140366
Short name T290
Test name
Test status
Simulation time 44163004 ps
CPU time 1.32 seconds
Started Feb 18 02:57:18 PM PST 24
Finished Feb 18 02:57:52 PM PST 24
Peak memory 198452 kb
Host smart-b71824a3-3def-4763-af8f-7c8a5d3435d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245140366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3245140366
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4031159472
Short name T217
Test name
Test status
Simulation time 321003846 ps
CPU time 3.43 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:59 PM PST 24
Peak memory 198476 kb
Host smart-3a0a4414-39dd-4b1b-87bb-877a93b0d22c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031159472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4031159472
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.582321565
Short name T593
Test name
Test status
Simulation time 156474153 ps
CPU time 2.86 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:05 PM PST 24
Peak memory 196296 kb
Host smart-7e9a2f80-873d-4c82-9265-715f3253da92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582321565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
582321565
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3813573180
Short name T148
Test name
Test status
Simulation time 43033614 ps
CPU time 0.96 seconds
Started Feb 18 02:57:13 PM PST 24
Finished Feb 18 02:57:39 PM PST 24
Peak memory 197148 kb
Host smart-81a68af1-f002-425d-bcd8-aa7730bcd348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813573180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3813573180
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3911775684
Short name T544
Test name
Test status
Simulation time 28987130 ps
CPU time 0.65 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:49 PM PST 24
Peak memory 194672 kb
Host smart-22e50f92-b8c3-403a-b55d-0f9bc032921e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911775684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3911775684
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.446152072
Short name T303
Test name
Test status
Simulation time 132820462 ps
CPU time 1.7 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:57:50 PM PST 24
Peak memory 198400 kb
Host smart-8f22a64d-2b7e-43ea-a5b5-7fe4b38ab6ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446152072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.446152072
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2099649300
Short name T605
Test name
Test status
Simulation time 35469073 ps
CPU time 0.85 seconds
Started Feb 18 02:57:19 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 195744 kb
Host smart-55714380-86d1-4524-9ada-fb76286f6a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099649300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2099649300
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1206481533
Short name T276
Test name
Test status
Simulation time 397676006 ps
CPU time 1.67 seconds
Started Feb 18 02:57:13 PM PST 24
Finished Feb 18 02:57:40 PM PST 24
Peak memory 197004 kb
Host smart-418b1bbd-658c-4f79-a213-7437f70fd704
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206481533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1206481533
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.503820267
Short name T329
Test name
Test status
Simulation time 25890118186 ps
CPU time 77.05 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 198504 kb
Host smart-d75924f0-3d93-440e-b168-10bc605c777a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503820267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.503820267
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2443037808
Short name T284
Test name
Test status
Simulation time 18531518 ps
CPU time 0.57 seconds
Started Feb 18 02:55:59 PM PST 24
Finished Feb 18 02:56:01 PM PST 24
Peak memory 195324 kb
Host smart-e2992ce5-e65f-43e1-a621-97275188b782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443037808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2443037808
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.90398332
Short name T693
Test name
Test status
Simulation time 790026133 ps
CPU time 1.03 seconds
Started Feb 18 02:56:00 PM PST 24
Finished Feb 18 02:56:02 PM PST 24
Peak memory 197184 kb
Host smart-dfbc88e0-68ee-4574-b7ae-c3e5c36eae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90398332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.90398332
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3850904719
Short name T305
Test name
Test status
Simulation time 159274562 ps
CPU time 8.34 seconds
Started Feb 18 02:55:58 PM PST 24
Finished Feb 18 02:56:07 PM PST 24
Peak memory 195988 kb
Host smart-881bbcca-511f-4f70-84d5-f24baac0cbb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850904719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3850904719
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3691282096
Short name T671
Test name
Test status
Simulation time 64071930 ps
CPU time 0.92 seconds
Started Feb 18 02:56:00 PM PST 24
Finished Feb 18 02:56:02 PM PST 24
Peak memory 197372 kb
Host smart-8c96f49a-15d9-4ddc-be03-a8d807eca5af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691282096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3691282096
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3727988082
Short name T171
Test name
Test status
Simulation time 120178806 ps
CPU time 1.14 seconds
Started Feb 18 02:56:02 PM PST 24
Finished Feb 18 02:56:05 PM PST 24
Peak memory 196348 kb
Host smart-11e4e2bc-da16-4324-a908-4960fcbde5ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727988082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3727988082
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3897692673
Short name T227
Test name
Test status
Simulation time 447793914 ps
CPU time 1.93 seconds
Started Feb 18 02:56:06 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 198388 kb
Host smart-4d7e3ad0-6ff0-40b1-839c-f007a39ec307
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897692673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3897692673
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1174147210
Short name T169
Test name
Test status
Simulation time 141938302 ps
CPU time 3.02 seconds
Started Feb 18 02:55:59 PM PST 24
Finished Feb 18 02:56:03 PM PST 24
Peak memory 197400 kb
Host smart-cfc8dfc4-e5c7-46ea-8572-3e7a144bdbeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174147210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1174147210
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1424354774
Short name T426
Test name
Test status
Simulation time 20747194 ps
CPU time 0.81 seconds
Started Feb 18 02:55:54 PM PST 24
Finished Feb 18 02:55:56 PM PST 24
Peak memory 196576 kb
Host smart-d981b357-0f3d-48e6-8a74-2ca991e1b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424354774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1424354774
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1638537323
Short name T416
Test name
Test status
Simulation time 84875158 ps
CPU time 0.88 seconds
Started Feb 18 02:56:02 PM PST 24
Finished Feb 18 02:56:04 PM PST 24
Peak memory 196400 kb
Host smart-f0fceb62-bf7b-412c-8123-10eff16b6eeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638537323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1638537323
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3160524763
Short name T495
Test name
Test status
Simulation time 111626680 ps
CPU time 5.18 seconds
Started Feb 18 02:56:00 PM PST 24
Finished Feb 18 02:56:07 PM PST 24
Peak memory 198428 kb
Host smart-e8b749d2-40d6-411e-8757-0a3f748e8b5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160524763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3160524763
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.346148548
Short name T40
Test name
Test status
Simulation time 229507294 ps
CPU time 0.83 seconds
Started Feb 18 02:55:58 PM PST 24
Finished Feb 18 02:56:00 PM PST 24
Peak memory 213764 kb
Host smart-1a741eee-32d6-493f-addf-1719b2e6f61c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346148548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.346148548
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.738231232
Short name T157
Test name
Test status
Simulation time 89098747 ps
CPU time 0.96 seconds
Started Feb 18 02:55:55 PM PST 24
Finished Feb 18 02:55:57 PM PST 24
Peak memory 196652 kb
Host smart-96ab1992-d78c-48de-97ba-47cf5e7fadab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738231232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.738231232
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2080107354
Short name T527
Test name
Test status
Simulation time 486060455 ps
CPU time 1.08 seconds
Started Feb 18 02:55:56 PM PST 24
Finished Feb 18 02:55:58 PM PST 24
Peak memory 196952 kb
Host smart-142335bd-d4ce-4ebc-b75c-e8707398b3cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080107354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2080107354
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1935774899
Short name T307
Test name
Test status
Simulation time 49674824179 ps
CPU time 140.39 seconds
Started Feb 18 02:56:05 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 198564 kb
Host smart-d9131e39-a6fc-4dea-bea8-9f4ee202af2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935774899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1935774899
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3884115497
Short name T115
Test name
Test status
Simulation time 203363327764 ps
CPU time 615.6 seconds
Started Feb 18 02:56:01 PM PST 24
Finished Feb 18 03:06:18 PM PST 24
Peak memory 198672 kb
Host smart-afcfc91e-a8ac-4b3c-b1a8-dc55a3bd2aee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3884115497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3884115497
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2338324203
Short name T322
Test name
Test status
Simulation time 29338926 ps
CPU time 0.57 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:58 PM PST 24
Peak memory 194468 kb
Host smart-b686d0e7-6f3b-4d8a-a1ef-9f9d6580da6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338324203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2338324203
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.274011645
Short name T626
Test name
Test status
Simulation time 26776492 ps
CPU time 0.86 seconds
Started Feb 18 02:57:19 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 195816 kb
Host smart-fa20240f-2a7c-4b69-8edd-53d0b9832411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274011645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.274011645
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.465062089
Short name T476
Test name
Test status
Simulation time 304482632 ps
CPU time 15.97 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:57:55 PM PST 24
Peak memory 197184 kb
Host smart-7a2f3e46-843d-4f6d-b5fc-1043605e4ce0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465062089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.465062089
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.119444200
Short name T20
Test name
Test status
Simulation time 39837257 ps
CPU time 0.77 seconds
Started Feb 18 02:57:21 PM PST 24
Finished Feb 18 02:57:55 PM PST 24
Peak memory 195124 kb
Host smart-6b71bd89-5b90-4140-869d-455c013197e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119444200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.119444200
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.24056056
Short name T509
Test name
Test status
Simulation time 748813477 ps
CPU time 1.32 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:52 PM PST 24
Peak memory 197656 kb
Host smart-92a7db21-de97-46a1-b6d3-b6318ed6eb49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24056056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.24056056
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3359103543
Short name T499
Test name
Test status
Simulation time 267443494 ps
CPU time 2 seconds
Started Feb 18 02:57:15 PM PST 24
Finished Feb 18 02:57:52 PM PST 24
Peak memory 198524 kb
Host smart-1fb4b5d3-d3d3-43e8-b1dc-4b7781e248c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359103543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3359103543
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.78028626
Short name T17
Test name
Test status
Simulation time 40989241 ps
CPU time 1.4 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 197120 kb
Host smart-8f220ef2-dc9c-4c19-a7f7-a326d2aeba2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78028626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.78028626
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2410169024
Short name T676
Test name
Test status
Simulation time 180156763 ps
CPU time 1.16 seconds
Started Feb 18 02:57:19 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 196288 kb
Host smart-2308ffda-dc01-4300-b06a-d92643112eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410169024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2410169024
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2399947451
Short name T346
Test name
Test status
Simulation time 156502387 ps
CPU time 1.09 seconds
Started Feb 18 02:57:14 PM PST 24
Finished Feb 18 02:57:42 PM PST 24
Peak memory 197160 kb
Host smart-7c8947be-c69c-48d1-bb9a-d01cd0458686
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399947451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2399947451
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.442739938
Short name T640
Test name
Test status
Simulation time 1361920211 ps
CPU time 4.96 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:53 PM PST 24
Peak memory 198416 kb
Host smart-3e34d5cc-2160-437f-8604-99958b5381c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442739938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.442739938
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2749500650
Short name T393
Test name
Test status
Simulation time 126878042 ps
CPU time 0.81 seconds
Started Feb 18 02:57:17 PM PST 24
Finished Feb 18 02:57:49 PM PST 24
Peak memory 195692 kb
Host smart-c8d4493c-d690-4916-9826-c91b18ad6f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749500650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2749500650
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2054127937
Short name T123
Test name
Test status
Simulation time 58375203 ps
CPU time 1.19 seconds
Started Feb 18 02:57:16 PM PST 24
Finished Feb 18 02:57:51 PM PST 24
Peak memory 196032 kb
Host smart-aba78478-b4bf-4f99-b1b3-32c5560db7ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054127937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2054127937
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2413728062
Short name T59
Test name
Test status
Simulation time 1615903524 ps
CPU time 35.94 seconds
Started Feb 18 02:57:21 PM PST 24
Finished Feb 18 02:58:31 PM PST 24
Peak memory 198548 kb
Host smart-2d4b94ce-c032-4397-914d-13109ea98d76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413728062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2413728062
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.616932217
Short name T311
Test name
Test status
Simulation time 50367436118 ps
CPU time 792.17 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 03:11:10 PM PST 24
Peak memory 198676 kb
Host smart-8bf13933-9037-496f-96bb-6b69b11c0562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=616932217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.616932217
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3955291274
Short name T511
Test name
Test status
Simulation time 13542266 ps
CPU time 0.6 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:57:59 PM PST 24
Peak memory 194280 kb
Host smart-3c64fc32-b44d-456a-b212-335ce2c154f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955291274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3955291274
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3953781483
Short name T575
Test name
Test status
Simulation time 153594785 ps
CPU time 0.91 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 196976 kb
Host smart-d095a992-319c-4568-91d9-c43e32c20a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953781483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3953781483
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2126976319
Short name T618
Test name
Test status
Simulation time 279708162 ps
CPU time 9.53 seconds
Started Feb 18 02:57:21 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 197324 kb
Host smart-d8430044-e716-4e66-9e85-fcbbb469f9c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126976319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2126976319
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2939634019
Short name T109
Test name
Test status
Simulation time 71339040 ps
CPU time 0.97 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:57:58 PM PST 24
Peak memory 198268 kb
Host smart-77782cc0-afe1-4f2e-87ff-e8608e090e36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939634019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2939634019
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.736723299
Short name T379
Test name
Test status
Simulation time 88650507 ps
CPU time 0.7 seconds
Started Feb 18 02:57:25 PM PST 24
Finished Feb 18 02:58:00 PM PST 24
Peak memory 195520 kb
Host smart-bb6c5cc1-9ee6-4975-bcb8-2c3fe074bf5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736723299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.736723299
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.711302234
Short name T407
Test name
Test status
Simulation time 234307757 ps
CPU time 2.22 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:58:00 PM PST 24
Peak memory 196748 kb
Host smart-873b24d5-ec55-429b-bfe8-d449a0b13ec9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711302234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.711302234
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2301228806
Short name T124
Test name
Test status
Simulation time 58705237 ps
CPU time 1.53 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:58 PM PST 24
Peak memory 196164 kb
Host smart-3d6ad8d0-6724-4a69-b24d-75c3e7a38ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301228806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2301228806
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2449000754
Short name T167
Test name
Test status
Simulation time 106364126 ps
CPU time 1.24 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 197540 kb
Host smart-13bd1c6b-3897-4e17-a07b-3091ed411779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449000754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2449000754
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3511080827
Short name T684
Test name
Test status
Simulation time 112362245 ps
CPU time 1.34 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 197724 kb
Host smart-737e5ba8-7a60-4840-b8e4-1f7feef91ffa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511080827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3511080827
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2843755348
Short name T239
Test name
Test status
Simulation time 1354882182 ps
CPU time 5.67 seconds
Started Feb 18 02:57:24 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 198404 kb
Host smart-5755592d-8639-4c9f-ad3a-0265b0591b54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843755348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2843755348
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1185451876
Short name T332
Test name
Test status
Simulation time 410659660 ps
CPU time 1.01 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 196240 kb
Host smart-66e09e62-4602-4707-b8f5-b8754e058ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185451876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1185451876
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.893796048
Short name T185
Test name
Test status
Simulation time 54469578 ps
CPU time 1.46 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 197232 kb
Host smart-6c755eb1-1fc6-4f04-956b-8f64b80dadf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893796048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.893796048
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1295582092
Short name T578
Test name
Test status
Simulation time 2202634873 ps
CPU time 25.42 seconds
Started Feb 18 02:57:20 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 198540 kb
Host smart-007fdbcd-4c29-4241-939f-17a33de44f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295582092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1295582092
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3212669257
Short name T702
Test name
Test status
Simulation time 47449591 ps
CPU time 0.99 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196880 kb
Host smart-3e2e8a28-841d-455c-809b-53158fb1ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212669257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3212669257
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4274967111
Short name T221
Test name
Test status
Simulation time 467180195 ps
CPU time 23.5 seconds
Started Feb 18 02:57:23 PM PST 24
Finished Feb 18 02:58:22 PM PST 24
Peak memory 197228 kb
Host smart-62ace743-2645-4263-9758-7489d85d34ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274967111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4274967111
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1804340324
Short name T172
Test name
Test status
Simulation time 543898195 ps
CPU time 0.93 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 198284 kb
Host smart-0e77a8fb-a46a-475a-b75b-d3aa3f21aa9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804340324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1804340324
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.737425149
Short name T262
Test name
Test status
Simulation time 117912488 ps
CPU time 0.78 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 195980 kb
Host smart-e5ed7f8f-e9ae-4622-86e4-dfe97b63c844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737425149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.737425149
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2917013294
Short name T19
Test name
Test status
Simulation time 72252248 ps
CPU time 2.84 seconds
Started Feb 18 02:57:21 PM PST 24
Finished Feb 18 02:57:58 PM PST 24
Peak memory 198488 kb
Host smart-bd1dd467-ae12-403b-9a9e-ee0828187e04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917013294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2917013294
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.528173139
Short name T701
Test name
Test status
Simulation time 184463166 ps
CPU time 3.12 seconds
Started Feb 18 02:57:20 PM PST 24
Finished Feb 18 02:57:58 PM PST 24
Peak memory 196248 kb
Host smart-d12f5be5-928a-450f-aa47-82e3a92df0cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528173139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
528173139
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1949522210
Short name T170
Test name
Test status
Simulation time 35892393 ps
CPU time 1.26 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 197412 kb
Host smart-0a6cee31-1cd4-47ee-9905-fe067464af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949522210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1949522210
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3763013068
Short name T12
Test name
Test status
Simulation time 43325496 ps
CPU time 0.84 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 195628 kb
Host smart-e2fde3df-70ee-4585-a1f2-52036300d756
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763013068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3763013068
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3171748324
Short name T331
Test name
Test status
Simulation time 190247356 ps
CPU time 4.84 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:07 PM PST 24
Peak memory 198504 kb
Host smart-df5e2bad-4b87-4202-b4d5-534cbf315e5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171748324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3171748324
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2386717687
Short name T481
Test name
Test status
Simulation time 85984838 ps
CPU time 1.34 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:57:57 PM PST 24
Peak memory 197008 kb
Host smart-031782a7-4085-433b-975d-4be0ffa9d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386717687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2386717687
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2104440000
Short name T523
Test name
Test status
Simulation time 174093082 ps
CPU time 1.12 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196884 kb
Host smart-f40b3f14-8782-41ec-b931-a8022605e3ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104440000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2104440000
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.720705153
Short name T7
Test name
Test status
Simulation time 5843708295 ps
CPU time 61.89 seconds
Started Feb 18 02:57:22 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 198536 kb
Host smart-5ce9b7f0-2f3c-4ec6-88a9-6b9cae4478d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720705153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.720705153
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1398623234
Short name T364
Test name
Test status
Simulation time 20004422 ps
CPU time 0.6 seconds
Started Feb 18 02:57:30 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 194300 kb
Host smart-5540836e-3f64-4e20-ad68-cdcd991a557f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398623234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1398623234
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.201162274
Short name T433
Test name
Test status
Simulation time 23712615 ps
CPU time 0.71 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 02:58:06 PM PST 24
Peak memory 194636 kb
Host smart-ceeba817-57b3-41cb-9dbe-136b4a83c299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201162274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.201162274
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4286369516
Short name T128
Test name
Test status
Simulation time 350325643 ps
CPU time 12.31 seconds
Started Feb 18 02:57:30 PM PST 24
Finished Feb 18 02:58:16 PM PST 24
Peak memory 197128 kb
Host smart-3af34aef-fa47-4e7d-979a-1b770bd20e08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286369516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4286369516
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1120583870
Short name T348
Test name
Test status
Simulation time 57086568 ps
CPU time 0.9 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196372 kb
Host smart-55b60374-c8d3-402c-baa1-bed1ef1ce051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120583870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1120583870
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1549990437
Short name T28
Test name
Test status
Simulation time 59104344 ps
CPU time 0.7 seconds
Started Feb 18 02:57:29 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 194640 kb
Host smart-eea9c1aa-46ac-486b-a4e6-e180cf54dd90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549990437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1549990437
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3794034543
Short name T442
Test name
Test status
Simulation time 974099131 ps
CPU time 2.33 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 198520 kb
Host smart-86d19197-cc96-4aaa-905c-6ecedf118c9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794034543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3794034543
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3851215297
Short name T147
Test name
Test status
Simulation time 78068148 ps
CPU time 1.12 seconds
Started Feb 18 02:57:31 PM PST 24
Finished Feb 18 02:58:05 PM PST 24
Peak memory 196148 kb
Host smart-f4bb75ad-a266-4070-a5a5-08e101836ef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851215297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3851215297
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2616867826
Short name T203
Test name
Test status
Simulation time 451276325 ps
CPU time 0.83 seconds
Started Feb 18 02:57:29 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 195844 kb
Host smart-885e5e54-d1fa-491b-8204-b1e7bf2a72ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616867826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2616867826
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1694772749
Short name T191
Test name
Test status
Simulation time 67694094 ps
CPU time 1.28 seconds
Started Feb 18 02:57:37 PM PST 24
Finished Feb 18 02:58:10 PM PST 24
Peak memory 197540 kb
Host smart-b4734514-f289-4d21-9b8c-3fbdf531bd8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694772749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1694772749
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2341698543
Short name T649
Test name
Test status
Simulation time 80862535 ps
CPU time 1.41 seconds
Started Feb 18 02:57:31 PM PST 24
Finished Feb 18 02:58:06 PM PST 24
Peak memory 198376 kb
Host smart-b210798d-ce2e-49c8-8fa5-9e30870d28d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341698543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2341698543
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2369656688
Short name T189
Test name
Test status
Simulation time 44339370 ps
CPU time 1.3 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 197040 kb
Host smart-cc1e9639-c596-4fbd-a2f3-c3756cff3ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369656688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2369656688
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1203462343
Short name T563
Test name
Test status
Simulation time 206057937 ps
CPU time 1.55 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 197180 kb
Host smart-4f7778f9-0e3b-4d37-8010-238047f58b1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203462343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1203462343
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.592311296
Short name T320
Test name
Test status
Simulation time 910438950 ps
CPU time 9.92 seconds
Started Feb 18 02:57:26 PM PST 24
Finished Feb 18 02:58:12 PM PST 24
Peak memory 198524 kb
Host smart-44d59d2e-9579-4bc0-b199-1c75edbe74ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592311296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.592311296
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4114386056
Short name T70
Test name
Test status
Simulation time 72906925824 ps
CPU time 1565.36 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 03:24:11 PM PST 24
Peak memory 198696 kb
Host smart-0a89d7f5-47b0-4da8-8403-c6473bd0c7d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4114386056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4114386056
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3173373902
Short name T206
Test name
Test status
Simulation time 92517176 ps
CPU time 0.54 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 194988 kb
Host smart-e0ab903c-6d0d-4f12-afb9-11bb9475bbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173373902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3173373902
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.24155851
Short name T664
Test name
Test status
Simulation time 36774865 ps
CPU time 0.74 seconds
Started Feb 18 02:57:29 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 194616 kb
Host smart-87172c8d-bd35-4ca3-ac44-c8239bce0dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24155851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.24155851
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3438850919
Short name T362
Test name
Test status
Simulation time 4726737143 ps
CPU time 24.1 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 197088 kb
Host smart-84fcec5f-9df1-4c8a-b681-1935093060ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438850919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3438850919
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.842513627
Short name T211
Test name
Test status
Simulation time 23793677 ps
CPU time 0.62 seconds
Started Feb 18 02:57:32 PM PST 24
Finished Feb 18 02:58:05 PM PST 24
Peak memory 194744 kb
Host smart-4c11a820-f0dd-44d8-b3cb-4df104e10623
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842513627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.842513627
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.4272473622
Short name T537
Test name
Test status
Simulation time 165407793 ps
CPU time 1.4 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 198504 kb
Host smart-0c190401-8bf7-4dc5-bfc4-5c2b81ee7158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272473622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.4272473622
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2256110316
Short name T716
Test name
Test status
Simulation time 104845667 ps
CPU time 3.6 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:06 PM PST 24
Peak memory 198456 kb
Host smart-ae158b9c-32bb-4d97-a3f2-96df14db3d0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256110316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2256110316
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3475776060
Short name T34
Test name
Test status
Simulation time 272981802 ps
CPU time 2.41 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 197532 kb
Host smart-cf56abc2-00be-4141-9c00-b8e02fdd2ef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475776060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3475776060
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1110066921
Short name T219
Test name
Test status
Simulation time 54470165 ps
CPU time 1.23 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 197332 kb
Host smart-499e5e46-4366-4390-a476-f120cfeae0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110066921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1110066921
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1946188944
Short name T231
Test name
Test status
Simulation time 21402125 ps
CPU time 0.83 seconds
Started Feb 18 02:57:31 PM PST 24
Finished Feb 18 02:58:05 PM PST 24
Peak memory 197128 kb
Host smart-5c53dad3-e209-4514-a0b7-3889e6fa26fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946188944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1946188944
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3908837765
Short name T194
Test name
Test status
Simulation time 139106633 ps
CPU time 2.58 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:05 PM PST 24
Peak memory 198428 kb
Host smart-86a840a8-4538-427d-853a-d0fde096f3f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908837765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3908837765
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1863117891
Short name T367
Test name
Test status
Simulation time 86593075 ps
CPU time 0.75 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 196328 kb
Host smart-8687fc50-048b-4063-a249-b5d98b69f449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863117891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1863117891
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3267445248
Short name T242
Test name
Test status
Simulation time 48626513 ps
CPU time 0.91 seconds
Started Feb 18 02:57:30 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 196996 kb
Host smart-249f9a1b-7fbb-404e-bf5a-56b5c2de04c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267445248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3267445248
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2695420320
Short name T328
Test name
Test status
Simulation time 90407936829 ps
CPU time 127.3 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 03:00:13 PM PST 24
Peak memory 198620 kb
Host smart-f0c6a2e9-8ab3-464f-a361-e6862a471f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695420320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2695420320
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3250256077
Short name T388
Test name
Test status
Simulation time 1134364939393 ps
CPU time 1537.46 seconds
Started Feb 18 02:57:31 PM PST 24
Finished Feb 18 03:23:42 PM PST 24
Peak memory 198676 kb
Host smart-7f6fc75f-d06e-4561-9ece-25043625677c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3250256077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3250256077
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1096320470
Short name T57
Test name
Test status
Simulation time 90500294 ps
CPU time 0.57 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 02:58:06 PM PST 24
Peak memory 194324 kb
Host smart-f01421d8-0893-4b2b-928c-821f54b524f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096320470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1096320470
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2023988919
Short name T582
Test name
Test status
Simulation time 87335691 ps
CPU time 0.86 seconds
Started Feb 18 02:57:29 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 196424 kb
Host smart-f6980f8a-9d51-4ea5-949a-abab41791668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023988919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2023988919
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.287556830
Short name T111
Test name
Test status
Simulation time 516579627 ps
CPU time 18.28 seconds
Started Feb 18 02:57:30 PM PST 24
Finished Feb 18 02:58:22 PM PST 24
Peak memory 197356 kb
Host smart-0456e35c-0379-40c9-abfa-5057be3d63de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287556830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.287556830
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3954001025
Short name T458
Test name
Test status
Simulation time 422244611 ps
CPU time 0.81 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196256 kb
Host smart-e040e0c0-6293-48bb-90c4-7102cb005e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954001025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3954001025
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.345532888
Short name T472
Test name
Test status
Simulation time 99383162 ps
CPU time 1.44 seconds
Started Feb 18 02:57:29 PM PST 24
Finished Feb 18 02:58:04 PM PST 24
Peak memory 197000 kb
Host smart-3c31575f-e92a-40e8-af1d-c4df4a343bd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345532888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.345532888
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1486016593
Short name T681
Test name
Test status
Simulation time 25265039 ps
CPU time 1.12 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196584 kb
Host smart-23269ab2-5243-4ef7-93b3-545eaa7c4c4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486016593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1486016593
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1417280715
Short name T400
Test name
Test status
Simulation time 64164908 ps
CPU time 1.82 seconds
Started Feb 18 02:57:32 PM PST 24
Finished Feb 18 02:58:07 PM PST 24
Peak memory 197120 kb
Host smart-9878af3e-df93-4fe1-89a8-1409fdde1432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417280715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1417280715
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2536627229
Short name T278
Test name
Test status
Simulation time 66872429 ps
CPU time 0.88 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196988 kb
Host smart-677eafa8-f325-45f1-8a2e-baff42e0ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536627229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2536627229
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2180180270
Short name T566
Test name
Test status
Simulation time 203645855 ps
CPU time 1.15 seconds
Started Feb 18 02:57:28 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196512 kb
Host smart-022ca7b6-7d05-4100-bed9-10f106621ff4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180180270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2180180270
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2969825502
Short name T492
Test name
Test status
Simulation time 350796465 ps
CPU time 5.65 seconds
Started Feb 18 02:57:32 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 198348 kb
Host smart-59465bd2-870d-4367-8cfe-9afb36d5afb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969825502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2969825502
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1718881858
Short name T122
Test name
Test status
Simulation time 133029729 ps
CPU time 0.96 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196296 kb
Host smart-2c3e46ac-dece-4654-9732-e6f9534390f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718881858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1718881858
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.132609381
Short name T257
Test name
Test status
Simulation time 157081061 ps
CPU time 0.95 seconds
Started Feb 18 02:57:27 PM PST 24
Finished Feb 18 02:58:03 PM PST 24
Peak memory 196848 kb
Host smart-213afc85-4a2f-493e-b5cb-e7deeeaa636e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132609381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.132609381
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.589613010
Short name T439
Test name
Test status
Simulation time 2848104625 ps
CPU time 41.98 seconds
Started Feb 18 02:57:30 PM PST 24
Finished Feb 18 02:58:45 PM PST 24
Peak memory 198564 kb
Host smart-c3984ab6-88c7-4557-90ac-acdd843b05dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589613010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.589613010
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1629843933
Short name T69
Test name
Test status
Simulation time 80976715053 ps
CPU time 1562.25 seconds
Started Feb 18 02:57:32 PM PST 24
Finished Feb 18 03:24:08 PM PST 24
Peak memory 198596 kb
Host smart-bf617a00-12e2-4561-ae26-d6336c9fe11f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1629843933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1629843933
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.832198794
Short name T15
Test name
Test status
Simulation time 37834780 ps
CPU time 0.58 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:08 PM PST 24
Peak memory 195016 kb
Host smart-b046a5be-8cb0-43da-bffa-70b53d888bd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832198794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.832198794
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1235453032
Short name T246
Test name
Test status
Simulation time 42276180 ps
CPU time 0.68 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 194504 kb
Host smart-f6723203-7647-46a7-aa56-9b61408fccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235453032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1235453032
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1039980242
Short name T355
Test name
Test status
Simulation time 748830023 ps
CPU time 19.67 seconds
Started Feb 18 02:57:34 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 195980 kb
Host smart-c69f695a-d5d9-40a2-b87b-4ce4b09f72e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039980242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1039980242
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.88321682
Short name T591
Test name
Test status
Simulation time 123227590 ps
CPU time 0.97 seconds
Started Feb 18 02:57:34 PM PST 24
Finished Feb 18 02:58:07 PM PST 24
Peak memory 198228 kb
Host smart-cf2b530e-a93b-42c7-8092-530cc35e153a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88321682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.88321682
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1508389414
Short name T145
Test name
Test status
Simulation time 56733476 ps
CPU time 1.03 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 197284 kb
Host smart-4756ac4f-5e60-40d2-9405-c404042d81e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508389414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1508389414
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3651587982
Short name T228
Test name
Test status
Simulation time 109172184 ps
CPU time 2.04 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:10 PM PST 24
Peak memory 198456 kb
Host smart-1ad60cd9-a90e-494b-a9bd-904c12755160
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651587982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3651587982
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3884011079
Short name T406
Test name
Test status
Simulation time 94871980 ps
CPU time 2.67 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 198480 kb
Host smart-7e6532af-3b00-4e58-af8a-b21f85d08db8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884011079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3884011079
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3318824095
Short name T558
Test name
Test status
Simulation time 106490764 ps
CPU time 0.77 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 195716 kb
Host smart-830fcf52-5261-46ac-8504-8e061bef78b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318824095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3318824095
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.11655977
Short name T186
Test name
Test status
Simulation time 57564212 ps
CPU time 1.18 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 02:58:07 PM PST 24
Peak memory 198452 kb
Host smart-d566f858-0321-4819-a160-a1b4beea3247
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup_
pulldown.11655977
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3586142150
Short name T610
Test name
Test status
Simulation time 52217496 ps
CPU time 2.31 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 198404 kb
Host smart-376c833b-d766-4341-bf54-b4dcf7b5123a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586142150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3586142150
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.426040907
Short name T383
Test name
Test status
Simulation time 197526640 ps
CPU time 1.29 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 197124 kb
Host smart-9e8c1d80-5af7-456b-839a-719f629bd282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426040907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.426040907
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2352455749
Short name T650
Test name
Test status
Simulation time 110840301 ps
CPU time 0.81 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 195696 kb
Host smart-019907ae-12e8-476b-9c1e-eb27ab1a6b9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352455749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2352455749
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1585163064
Short name T463
Test name
Test status
Simulation time 4860216190 ps
CPU time 96.64 seconds
Started Feb 18 02:57:34 PM PST 24
Finished Feb 18 02:59:43 PM PST 24
Peak memory 198532 kb
Host smart-7e629ac6-7834-48ef-aea2-47fb3a33b7a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585163064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1585163064
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.459307503
Short name T446
Test name
Test status
Simulation time 30970374 ps
CPU time 0.56 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:08 PM PST 24
Peak memory 193172 kb
Host smart-c82c4e8a-14a7-48c3-840f-41962ef8e18a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459307503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.459307503
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.752818183
Short name T107
Test name
Test status
Simulation time 171047194 ps
CPU time 0.9 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 197676 kb
Host smart-b3d548bc-7472-435b-aa1a-dde32e373715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752818183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.752818183
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.4242193818
Short name T268
Test name
Test status
Simulation time 1312854772 ps
CPU time 17.76 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:25 PM PST 24
Peak memory 197364 kb
Host smart-28e690e4-65e5-498d-a2d3-0b83ed928656
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242193818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.4242193818
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.417054065
Short name T429
Test name
Test status
Simulation time 357005869 ps
CPU time 0.76 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 195200 kb
Host smart-3c4d1a08-6136-4ba7-b6ad-652d2f6fea2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417054065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.417054065
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.866522360
Short name T421
Test name
Test status
Simulation time 291161470 ps
CPU time 1.19 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 196252 kb
Host smart-874de8ee-948f-4ed0-becb-5a7ecfcd1be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866522360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.866522360
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1738716574
Short name T471
Test name
Test status
Simulation time 84652485 ps
CPU time 2.37 seconds
Started Feb 18 02:57:38 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 198408 kb
Host smart-e3ba4fc2-c6fc-4b35-b82e-25656de837d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738716574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1738716574
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.659994143
Short name T281
Test name
Test status
Simulation time 373692469 ps
CPU time 1.77 seconds
Started Feb 18 02:57:34 PM PST 24
Finished Feb 18 02:58:08 PM PST 24
Peak memory 196540 kb
Host smart-03c4017a-05ca-4a19-9228-60dc5e078259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659994143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
659994143
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2046963344
Short name T396
Test name
Test status
Simulation time 351002548 ps
CPU time 1.25 seconds
Started Feb 18 02:57:36 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 197044 kb
Host smart-b5326579-3612-4c92-ade5-5c37e209cfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046963344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2046963344
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3222024744
Short name T703
Test name
Test status
Simulation time 36054016 ps
CPU time 0.96 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 02:58:07 PM PST 24
Peak memory 196436 kb
Host smart-80d16816-8d3d-46b8-b31a-8ae800899d8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222024744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3222024744
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2762263007
Short name T596
Test name
Test status
Simulation time 297140032 ps
CPU time 3.53 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 198432 kb
Host smart-febf46b2-66d1-41cb-9be1-15725ee7f1ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762263007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2762263007
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2686410099
Short name T127
Test name
Test status
Simulation time 183221372 ps
CPU time 1.07 seconds
Started Feb 18 02:57:33 PM PST 24
Finished Feb 18 02:58:07 PM PST 24
Peak memory 196856 kb
Host smart-1e437153-65ab-4fdf-8b3a-76e1e99d54df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686410099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2686410099
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.591567923
Short name T377
Test name
Test status
Simulation time 35932879 ps
CPU time 0.81 seconds
Started Feb 18 02:57:35 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 196408 kb
Host smart-8c1975e2-c55b-4125-ab6a-ba0e6d0431ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591567923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.591567923
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1431224234
Short name T138
Test name
Test status
Simulation time 10158465846 ps
CPU time 138.79 seconds
Started Feb 18 02:57:31 PM PST 24
Finished Feb 18 03:00:23 PM PST 24
Peak memory 198564 kb
Host smart-ca684598-d853-4fca-a06f-34f86687d09b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431224234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1431224234
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2555169441
Short name T475
Test name
Test status
Simulation time 158837471143 ps
CPU time 1283.27 seconds
Started Feb 18 02:57:40 PM PST 24
Finished Feb 18 03:19:34 PM PST 24
Peak memory 198708 kb
Host smart-7c024bb5-d661-4033-9ef5-29c1d548d04b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2555169441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2555169441
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1568415134
Short name T611
Test name
Test status
Simulation time 12184264 ps
CPU time 0.56 seconds
Started Feb 18 02:57:43 PM PST 24
Finished Feb 18 02:58:13 PM PST 24
Peak memory 193180 kb
Host smart-80e88a5e-7fbe-4c1f-b55d-99a648dc8083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568415134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1568415134
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2155098396
Short name T55
Test name
Test status
Simulation time 35896251 ps
CPU time 0.85 seconds
Started Feb 18 02:57:39 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 196944 kb
Host smart-6ad46a06-7d2f-4cbc-b397-5ad9f87a5980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155098396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2155098396
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3366397288
Short name T440
Test name
Test status
Simulation time 1450663552 ps
CPU time 6.98 seconds
Started Feb 18 02:57:40 PM PST 24
Finished Feb 18 02:58:19 PM PST 24
Peak memory 197232 kb
Host smart-686eb677-5461-4829-9d88-b6692aaab60e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366397288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3366397288
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.246810146
Short name T345
Test name
Test status
Simulation time 244719640 ps
CPU time 0.88 seconds
Started Feb 18 02:57:43 PM PST 24
Finished Feb 18 02:58:14 PM PST 24
Peak memory 196372 kb
Host smart-4b7ea977-3c38-48c5-b77a-c73655945364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246810146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.246810146
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2279233358
Short name T402
Test name
Test status
Simulation time 45916861 ps
CPU time 1.27 seconds
Started Feb 18 02:57:39 PM PST 24
Finished Feb 18 02:58:12 PM PST 24
Peak memory 196572 kb
Host smart-9a928859-7104-44cd-8e02-243543ec16f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279233358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2279233358
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1778367855
Short name T419
Test name
Test status
Simulation time 56197237 ps
CPU time 2.08 seconds
Started Feb 18 02:57:38 PM PST 24
Finished Feb 18 02:58:12 PM PST 24
Peak memory 198444 kb
Host smart-b46d5724-e057-42bd-ab5f-812de49ccd20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778367855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1778367855
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1176079495
Short name T291
Test name
Test status
Simulation time 867860465 ps
CPU time 3.37 seconds
Started Feb 18 02:57:40 PM PST 24
Finished Feb 18 02:58:15 PM PST 24
Peak memory 197428 kb
Host smart-dbcfe85f-52c7-49f1-8e97-08892d0d061a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176079495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1176079495
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.193260666
Short name T685
Test name
Test status
Simulation time 63110324 ps
CPU time 0.85 seconds
Started Feb 18 02:57:40 PM PST 24
Finished Feb 18 02:58:12 PM PST 24
Peak memory 197852 kb
Host smart-978567cb-cd41-4f06-9ac2-47e766275441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193260666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.193260666
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.634025959
Short name T662
Test name
Test status
Simulation time 32913204 ps
CPU time 0.74 seconds
Started Feb 18 02:57:39 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 196560 kb
Host smart-9225ba20-baf5-4fa0-8872-efe42b304337
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634025959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.634025959
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2300756689
Short name T363
Test name
Test status
Simulation time 749403558 ps
CPU time 2.88 seconds
Started Feb 18 02:57:42 PM PST 24
Finished Feb 18 02:58:15 PM PST 24
Peak memory 198444 kb
Host smart-4a26448b-66ec-49f1-bab4-e505e7236512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300756689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2300756689
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1999263037
Short name T586
Test name
Test status
Simulation time 69278522 ps
CPU time 1.3 seconds
Started Feb 18 02:57:40 PM PST 24
Finished Feb 18 02:58:12 PM PST 24
Peak memory 196280 kb
Host smart-75abb9fe-d465-4137-897c-a5bfda0e7361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999263037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1999263037
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3852853595
Short name T266
Test name
Test status
Simulation time 183967130 ps
CPU time 1.39 seconds
Started Feb 18 02:57:38 PM PST 24
Finished Feb 18 02:58:11 PM PST 24
Peak memory 197236 kb
Host smart-c6c626af-bcde-45a2-bff8-eeb1b2bfb031
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852853595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3852853595
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1035170478
Short name T238
Test name
Test status
Simulation time 7298458283 ps
CPU time 128.04 seconds
Started Feb 18 02:57:39 PM PST 24
Finished Feb 18 03:00:18 PM PST 24
Peak memory 198576 kb
Host smart-1c4d7805-397b-4b3d-a93e-a52de87b96d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035170478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1035170478
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3103558255
Short name T146
Test name
Test status
Simulation time 73707551 ps
CPU time 0.57 seconds
Started Feb 18 02:57:50 PM PST 24
Finished Feb 18 02:58:16 PM PST 24
Peak memory 194256 kb
Host smart-c184361c-78a5-4cbd-857d-2c397c0e7e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103558255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3103558255
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2028082281
Short name T237
Test name
Test status
Simulation time 234856248 ps
CPU time 1 seconds
Started Feb 18 02:57:56 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 196940 kb
Host smart-be304f03-be30-4c93-a62d-a853701ba284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028082281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2028082281
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2210226520
Short name T414
Test name
Test status
Simulation time 2934578885 ps
CPU time 23.03 seconds
Started Feb 18 02:57:53 PM PST 24
Finished Feb 18 02:58:41 PM PST 24
Peak memory 198496 kb
Host smart-a642f6b6-31fd-4db2-9450-ff42bcb1a4ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210226520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2210226520
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2325173493
Short name T473
Test name
Test status
Simulation time 77674439 ps
CPU time 1.05 seconds
Started Feb 18 02:57:56 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 197616 kb
Host smart-ded9ed49-28a6-48bf-9831-3f94059e8dde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325173493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2325173493
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1896813109
Short name T452
Test name
Test status
Simulation time 28892064 ps
CPU time 0.88 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:26 PM PST 24
Peak memory 197140 kb
Host smart-b403c0bb-0f62-4a39-94f2-61225519f156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896813109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1896813109
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4123725906
Short name T699
Test name
Test status
Simulation time 680007422 ps
CPU time 3.64 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:29 PM PST 24
Peak memory 198480 kb
Host smart-d39738e5-c96c-4004-bc68-9ee60f774dbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123725906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4123725906
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2954187496
Short name T478
Test name
Test status
Simulation time 42683410 ps
CPU time 1.16 seconds
Started Feb 18 02:58:14 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 196160 kb
Host smart-069da516-a65a-4465-a9b4-a930c56e3cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954187496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2954187496
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3965596796
Short name T306
Test name
Test status
Simulation time 87755326 ps
CPU time 0.78 seconds
Started Feb 18 02:57:51 PM PST 24
Finished Feb 18 02:58:17 PM PST 24
Peak memory 196608 kb
Host smart-61a7be34-93d1-43e0-aa69-ee865942757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965596796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3965596796
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2794427359
Short name T174
Test name
Test status
Simulation time 49028801 ps
CPU time 1.17 seconds
Started Feb 18 02:57:52 PM PST 24
Finished Feb 18 02:58:18 PM PST 24
Peak memory 196196 kb
Host smart-5542fd2e-67a5-4199-a979-bcfe0afbc4ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794427359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2794427359
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4254220696
Short name T175
Test name
Test status
Simulation time 65588296 ps
CPU time 3.18 seconds
Started Feb 18 02:57:54 PM PST 24
Finished Feb 18 02:58:21 PM PST 24
Peak memory 198412 kb
Host smart-c298934e-08f0-4929-82e4-65d8cdba81bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254220696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4254220696
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1342500498
Short name T112
Test name
Test status
Simulation time 75481334 ps
CPU time 1.25 seconds
Started Feb 18 02:57:39 PM PST 24
Finished Feb 18 02:58:12 PM PST 24
Peak memory 198436 kb
Host smart-7b38ad6a-5ea1-4ee1-a00a-101c32af984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342500498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1342500498
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1759623636
Short name T594
Test name
Test status
Simulation time 133449144 ps
CPU time 0.82 seconds
Started Feb 18 02:57:44 PM PST 24
Finished Feb 18 02:58:14 PM PST 24
Peak memory 196480 kb
Host smart-937f4c20-075d-42f0-8f80-35326f6961a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759623636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1759623636
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.855464696
Short name T214
Test name
Test status
Simulation time 6050503737 ps
CPU time 155.29 seconds
Started Feb 18 02:57:53 PM PST 24
Finished Feb 18 03:00:53 PM PST 24
Peak memory 198564 kb
Host smart-fd9db94f-7a0b-4200-820e-7341dd88cc15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855464696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.855464696
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2237907017
Short name T423
Test name
Test status
Simulation time 80713144801 ps
CPU time 1239.31 seconds
Started Feb 18 02:57:56 PM PST 24
Finished Feb 18 03:18:58 PM PST 24
Peak memory 198680 kb
Host smart-57499893-0f7a-4c23-9939-6b0421607be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2237907017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2237907017
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2844791650
Short name T277
Test name
Test status
Simulation time 38655994 ps
CPU time 0.62 seconds
Started Feb 18 02:56:06 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 194440 kb
Host smart-e0fcc193-5bb0-454a-803c-787beb860acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844791650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2844791650
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.678362300
Short name T286
Test name
Test status
Simulation time 30291491 ps
CPU time 0.91 seconds
Started Feb 18 02:56:16 PM PST 24
Finished Feb 18 02:56:19 PM PST 24
Peak memory 197468 kb
Host smart-fa9b36ff-3e7a-4816-9039-183dc16bcd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678362300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.678362300
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.207108660
Short name T324
Test name
Test status
Simulation time 576232933 ps
CPU time 7.6 seconds
Started Feb 18 02:56:06 PM PST 24
Finished Feb 18 02:56:15 PM PST 24
Peak memory 197532 kb
Host smart-0ce47cb7-2fa4-4fd7-ab60-8fd9187a5ca3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207108660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.207108660
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4017222202
Short name T678
Test name
Test status
Simulation time 60243344 ps
CPU time 0.89 seconds
Started Feb 18 02:56:07 PM PST 24
Finished Feb 18 02:56:10 PM PST 24
Peak memory 197212 kb
Host smart-6c7ecb9b-3849-4d5f-a1c0-4d21e0e5a850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017222202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4017222202
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3548090251
Short name T508
Test name
Test status
Simulation time 36164269 ps
CPU time 0.67 seconds
Started Feb 18 02:56:06 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 194616 kb
Host smart-63e966ff-369e-4970-8382-0e5efebabdb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548090251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3548090251
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.307798026
Short name T254
Test name
Test status
Simulation time 37781975 ps
CPU time 1.42 seconds
Started Feb 18 02:56:06 PM PST 24
Finished Feb 18 02:56:09 PM PST 24
Peak memory 196900 kb
Host smart-641937ae-79c7-4f3a-8519-d19fc1260cb6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307798026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.307798026
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3365207901
Short name T209
Test name
Test status
Simulation time 95461638 ps
CPU time 2.2 seconds
Started Feb 18 02:56:11 PM PST 24
Finished Feb 18 02:56:15 PM PST 24
Peak memory 197636 kb
Host smart-436b2df3-4531-491e-beb0-1f99b561384e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365207901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3365207901
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4254817045
Short name T259
Test name
Test status
Simulation time 60421183 ps
CPU time 1.23 seconds
Started Feb 18 02:56:05 PM PST 24
Finished Feb 18 02:56:08 PM PST 24
Peak memory 197412 kb
Host smart-c5a2889f-c528-4a40-9b96-3bdc5702bac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254817045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4254817045
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3950229316
Short name T672
Test name
Test status
Simulation time 46048633 ps
CPU time 0.92 seconds
Started Feb 18 02:56:16 PM PST 24
Finished Feb 18 02:56:19 PM PST 24
Peak memory 197708 kb
Host smart-f080f711-f834-4c59-b6fa-12e2bf2e2b0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950229316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3950229316
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.83513223
Short name T230
Test name
Test status
Simulation time 462192609 ps
CPU time 4.19 seconds
Started Feb 18 02:56:16 PM PST 24
Finished Feb 18 02:56:22 PM PST 24
Peak memory 198380 kb
Host smart-ef6038b6-29c7-4a67-9aec-0205728f90a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83513223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rando
m_long_reg_writes_reg_reads.83513223
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4288804767
Short name T53
Test name
Test status
Simulation time 229635774 ps
CPU time 0.86 seconds
Started Feb 18 02:56:15 PM PST 24
Finished Feb 18 02:56:18 PM PST 24
Peak memory 213768 kb
Host smart-ba744d42-344f-41e7-96b1-3cb10595bb9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288804767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4288804767
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2144145397
Short name T627
Test name
Test status
Simulation time 37646475 ps
CPU time 1.16 seconds
Started Feb 18 02:55:59 PM PST 24
Finished Feb 18 02:56:01 PM PST 24
Peak memory 196068 kb
Host smart-3fa6510d-e25a-4dbd-81ac-4af9fcbf8766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144145397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2144145397
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1132094589
Short name T380
Test name
Test status
Simulation time 92198213 ps
CPU time 1.14 seconds
Started Feb 18 02:56:01 PM PST 24
Finished Feb 18 02:56:03 PM PST 24
Peak memory 196080 kb
Host smart-c064f10f-0dfb-405a-bd77-f939f8a0fb84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132094589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1132094589
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.650036295
Short name T430
Test name
Test status
Simulation time 52496877544 ps
CPU time 138.14 seconds
Started Feb 18 02:56:04 PM PST 24
Finished Feb 18 02:58:23 PM PST 24
Peak memory 198568 kb
Host smart-9609cbe2-48d5-4521-ad4d-cb61e879102a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650036295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.650036295
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3561182788
Short name T560
Test name
Test status
Simulation time 15173585 ps
CPU time 0.58 seconds
Started Feb 18 02:58:08 PM PST 24
Finished Feb 18 02:58:25 PM PST 24
Peak memory 194304 kb
Host smart-79f18645-0e82-4c13-9ce9-d34efc0e2a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561182788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3561182788
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1734024457
Short name T308
Test name
Test status
Simulation time 23805196 ps
CPU time 0.7 seconds
Started Feb 18 02:57:57 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 194452 kb
Host smart-6bf5ff4e-a89c-4c1d-a03a-99aa114ef44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734024457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1734024457
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3413928997
Short name T150
Test name
Test status
Simulation time 320570832 ps
CPU time 8.56 seconds
Started Feb 18 02:57:55 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 197444 kb
Host smart-12de60b3-795b-4849-be02-147070fc3e6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413928997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3413928997
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1333973688
Short name T338
Test name
Test status
Simulation time 94120561 ps
CPU time 0.83 seconds
Started Feb 18 02:58:10 PM PST 24
Finished Feb 18 02:58:26 PM PST 24
Peak memory 196400 kb
Host smart-ab056099-72c2-4c0f-94ab-82b6c86e1d3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333973688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1333973688
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3388638294
Short name T428
Test name
Test status
Simulation time 49845708 ps
CPU time 1.31 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 197508 kb
Host smart-7273ec99-4441-4ace-9adc-6cb8a7a076a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388638294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3388638294
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.209597796
Short name T162
Test name
Test status
Simulation time 56702752 ps
CPU time 2.31 seconds
Started Feb 18 02:58:03 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 198536 kb
Host smart-d3f50ea4-7bd5-4225-838d-bd30ed16ff0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209597796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.209597796
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1442801913
Short name T516
Test name
Test status
Simulation time 120188795 ps
CPU time 2.33 seconds
Started Feb 18 02:57:56 PM PST 24
Finished Feb 18 02:58:21 PM PST 24
Peak memory 196292 kb
Host smart-a79e64e5-bcd0-4974-8a31-40d5a9828284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442801913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1442801913
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3952538806
Short name T694
Test name
Test status
Simulation time 108020835 ps
CPU time 1.15 seconds
Started Feb 18 02:57:54 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 196928 kb
Host smart-c0333017-8d03-4137-9286-99aabf847e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952538806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3952538806
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3535672150
Short name T567
Test name
Test status
Simulation time 63272400 ps
CPU time 1.2 seconds
Started Feb 18 02:57:51 PM PST 24
Finished Feb 18 02:58:17 PM PST 24
Peak memory 197496 kb
Host smart-f179237a-0db9-4c1f-9aee-18c655354b91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535672150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3535672150
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.209137813
Short name T465
Test name
Test status
Simulation time 286422611 ps
CPU time 4.69 seconds
Started Feb 18 02:58:02 PM PST 24
Finished Feb 18 02:58:26 PM PST 24
Peak memory 198312 kb
Host smart-2a431ae9-c4f5-427e-9a88-f8d5ff052643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209137813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.209137813
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3676927605
Short name T180
Test name
Test status
Simulation time 43468679 ps
CPU time 1.28 seconds
Started Feb 18 02:58:10 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 196164 kb
Host smart-1280019f-2261-4d60-b5b4-735396fffeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676927605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3676927605
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2847494384
Short name T652
Test name
Test status
Simulation time 71845269 ps
CPU time 0.81 seconds
Started Feb 18 02:57:50 PM PST 24
Finished Feb 18 02:58:17 PM PST 24
Peak memory 195720 kb
Host smart-3167dde1-11e9-4ed9-9006-06cef82a807c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847494384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2847494384
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3116219780
Short name T323
Test name
Test status
Simulation time 15404081546 ps
CPU time 102.67 seconds
Started Feb 18 02:58:10 PM PST 24
Finished Feb 18 03:00:08 PM PST 24
Peak memory 198624 kb
Host smart-7035b360-94c8-4fd5-899f-eb5d95ea2708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116219780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3116219780
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1678540709
Short name T208
Test name
Test status
Simulation time 61778322 ps
CPU time 0.59 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:26 PM PST 24
Peak memory 194300 kb
Host smart-7b42acfb-b83a-4d83-a2fb-c9ca6ddf7cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678540709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1678540709
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3998834875
Short name T543
Test name
Test status
Simulation time 371095651 ps
CPU time 0.84 seconds
Started Feb 18 02:57:55 PM PST 24
Finished Feb 18 02:58:19 PM PST 24
Peak memory 195780 kb
Host smart-a3872cfb-5382-4e50-ae24-9d7d62feb32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998834875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3998834875
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.503845272
Short name T500
Test name
Test status
Simulation time 3227985962 ps
CPU time 23.89 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:49 PM PST 24
Peak memory 197476 kb
Host smart-67c096d8-f723-4fd2-9193-8f008069d3aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503845272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.503845272
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1239925908
Short name T177
Test name
Test status
Simulation time 112978608 ps
CPU time 0.8 seconds
Started Feb 18 02:58:04 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 196868 kb
Host smart-2ff83a97-5fe9-41cf-9503-f6fde76d988e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239925908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1239925908
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.534270845
Short name T620
Test name
Test status
Simulation time 413493084 ps
CPU time 0.82 seconds
Started Feb 18 02:57:56 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 196712 kb
Host smart-955ab51f-1f35-44eb-a94e-f14e968f0438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534270845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.534270845
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.697407704
Short name T501
Test name
Test status
Simulation time 151515678 ps
CPU time 2.57 seconds
Started Feb 18 02:58:03 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 196892 kb
Host smart-0bc37260-a080-4d77-b21b-7b9dbffd1d42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697407704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.697407704
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.598240368
Short name T296
Test name
Test status
Simulation time 119040760 ps
CPU time 3.66 seconds
Started Feb 18 02:57:58 PM PST 24
Finished Feb 18 02:58:23 PM PST 24
Peak memory 198476 kb
Host smart-ecc533c3-80ec-417f-81ce-b0fd075f0007
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598240368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
598240368
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1194340492
Short name T133
Test name
Test status
Simulation time 76303948 ps
CPU time 1.24 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 196992 kb
Host smart-19751b62-b2b0-47e3-87c1-2d40eed97322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194340492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1194340492
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.152246264
Short name T317
Test name
Test status
Simulation time 27893240 ps
CPU time 1.08 seconds
Started Feb 18 02:57:56 PM PST 24
Finished Feb 18 02:58:20 PM PST 24
Peak memory 197104 kb
Host smart-8283c280-ac93-4380-8f72-97d24d0d1d31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152246264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.152246264
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2081673952
Short name T275
Test name
Test status
Simulation time 348937476 ps
CPU time 6.06 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:32 PM PST 24
Peak memory 198420 kb
Host smart-646b24e3-9415-40dd-8e2d-d1cae38e1036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081673952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2081673952
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3741835043
Short name T248
Test name
Test status
Simulation time 48027717 ps
CPU time 1.41 seconds
Started Feb 18 02:57:58 PM PST 24
Finished Feb 18 02:58:21 PM PST 24
Peak memory 198480 kb
Host smart-fd32e2a7-3bdc-4378-9109-da455daf5590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741835043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3741835043
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1956155390
Short name T461
Test name
Test status
Simulation time 42987358 ps
CPU time 0.96 seconds
Started Feb 18 02:57:53 PM PST 24
Finished Feb 18 02:58:18 PM PST 24
Peak memory 197600 kb
Host smart-61b3ba71-61a2-4459-b97b-3dfbe9cd6433
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956155390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1956155390
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3880186444
Short name T68
Test name
Test status
Simulation time 30409069756 ps
CPU time 485.71 seconds
Started Feb 18 02:58:15 PM PST 24
Finished Feb 18 03:06:34 PM PST 24
Peak memory 198716 kb
Host smart-5926a9fd-c3e0-402a-af42-b10e8d98f155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3880186444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3880186444
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.423082907
Short name T241
Test name
Test status
Simulation time 12037101 ps
CPU time 0.59 seconds
Started Feb 18 02:58:16 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 194356 kb
Host smart-3f4b7e34-c696-48d1-bbbc-0675a8e907c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423082907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.423082907
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4132864866
Short name T126
Test name
Test status
Simulation time 24902357 ps
CPU time 0.86 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 195812 kb
Host smart-d97e9cba-9823-4447-9c15-6d2d6b8b4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132864866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4132864866
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2654349972
Short name T229
Test name
Test status
Simulation time 274585712 ps
CPU time 10.38 seconds
Started Feb 18 02:58:13 PM PST 24
Finished Feb 18 02:58:37 PM PST 24
Peak memory 195956 kb
Host smart-0413c623-f3ac-4b7d-9c81-9f9c398e94c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654349972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2654349972
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.568519375
Short name T334
Test name
Test status
Simulation time 46656583 ps
CPU time 0.83 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:26 PM PST 24
Peak memory 197036 kb
Host smart-9cfe2d8a-23d9-4319-950e-e6efee4c9f60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568519375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.568519375
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2171551064
Short name T288
Test name
Test status
Simulation time 23964623 ps
CPU time 0.74 seconds
Started Feb 18 02:58:03 PM PST 24
Finished Feb 18 02:58:23 PM PST 24
Peak memory 195900 kb
Host smart-23dc2f75-bbc8-41e0-a112-11848a809fe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171551064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2171551064
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1133396395
Short name T52
Test name
Test status
Simulation time 89233617 ps
CPU time 3.03 seconds
Started Feb 18 02:58:01 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 198536 kb
Host smart-0f517432-6d80-457c-97f2-21f822afa92f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133396395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1133396395
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2244072518
Short name T136
Test name
Test status
Simulation time 240800273 ps
CPU time 2.21 seconds
Started Feb 18 02:58:10 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 197648 kb
Host smart-2b2ee0bb-a51e-47b2-aeb3-92f945dd6c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244072518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2244072518
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3160153696
Short name T447
Test name
Test status
Simulation time 41967429 ps
CPU time 0.84 seconds
Started Feb 18 02:58:06 PM PST 24
Finished Feb 18 02:58:24 PM PST 24
Peak memory 196256 kb
Host smart-2a16f291-614e-4da8-a78b-a048d21a3541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160153696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3160153696
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2247772115
Short name T77
Test name
Test status
Simulation time 137811490 ps
CPU time 0.95 seconds
Started Feb 18 02:58:00 PM PST 24
Finished Feb 18 02:58:21 PM PST 24
Peak memory 196948 kb
Host smart-22dba2eb-c9e3-44f6-a69c-c35cafadc708
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247772115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2247772115
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1351868745
Short name T489
Test name
Test status
Simulation time 573203198 ps
CPU time 5.25 seconds
Started Feb 18 02:58:03 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 198416 kb
Host smart-fce7ddbd-d50c-4b52-acc4-4ccc1e50dfe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351868745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1351868745
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2289436992
Short name T108
Test name
Test status
Simulation time 116978389 ps
CPU time 1.06 seconds
Started Feb 18 02:58:14 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 196068 kb
Host smart-51cafa4b-3448-47f9-aec8-994bee267ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289436992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2289436992
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1609791038
Short name T415
Test name
Test status
Simulation time 60850985 ps
CPU time 0.75 seconds
Started Feb 18 02:58:01 PM PST 24
Finished Feb 18 02:58:22 PM PST 24
Peak memory 195660 kb
Host smart-6a09c5e3-bd1a-40ea-a796-89b821c0c6d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609791038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1609791038
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1289235745
Short name T8
Test name
Test status
Simulation time 10248796199 ps
CPU time 29.04 seconds
Started Feb 18 02:58:08 PM PST 24
Finished Feb 18 02:58:54 PM PST 24
Peak memory 198576 kb
Host smart-d46a5e80-af93-43eb-a91c-792932b1eac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289235745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1289235745
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.850027200
Short name T234
Test name
Test status
Simulation time 43653509 ps
CPU time 0.58 seconds
Started Feb 18 02:58:16 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 194312 kb
Host smart-8d168cc8-1558-4678-b279-1447e9070853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850027200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.850027200
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.45607157
Short name T670
Test name
Test status
Simulation time 41098177 ps
CPU time 0.95 seconds
Started Feb 18 02:58:08 PM PST 24
Finished Feb 18 02:58:25 PM PST 24
Peak memory 196788 kb
Host smart-cc05be50-6687-4cb5-b1e5-b9de506192c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45607157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.45607157
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3523816986
Short name T56
Test name
Test status
Simulation time 273289933 ps
CPU time 4.68 seconds
Started Feb 18 02:58:22 PM PST 24
Finished Feb 18 02:58:38 PM PST 24
Peak memory 196424 kb
Host smart-6e0e7d75-7704-4947-8b1d-f1f02fb6900e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523816986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3523816986
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2683318633
Short name T106
Test name
Test status
Simulation time 53984675 ps
CPU time 0.84 seconds
Started Feb 18 02:58:22 PM PST 24
Finished Feb 18 02:58:34 PM PST 24
Peak memory 196380 kb
Host smart-6a4dc9e8-33f4-4609-bd33-f2b4b2234e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683318633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2683318633
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4201643935
Short name T152
Test name
Test status
Simulation time 38947956 ps
CPU time 0.85 seconds
Started Feb 18 02:58:16 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 195996 kb
Host smart-8f35b4f4-3eb6-440d-8b17-9ef116a861f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201643935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4201643935
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1018400480
Short name T370
Test name
Test status
Simulation time 79273071 ps
CPU time 3.55 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 198552 kb
Host smart-58d48749-0082-4444-9044-0e9d988f6ad6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018400480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1018400480
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.399262496
Short name T233
Test name
Test status
Simulation time 621255366 ps
CPU time 2.72 seconds
Started Feb 18 02:58:09 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 197660 kb
Host smart-c134cc28-0ab0-4a9d-9262-2e34ed4dde30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399262496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
399262496
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.939353353
Short name T526
Test name
Test status
Simulation time 44971029 ps
CPU time 0.72 seconds
Started Feb 18 02:58:15 PM PST 24
Finished Feb 18 02:58:29 PM PST 24
Peak memory 195688 kb
Host smart-0adddef6-8993-409e-acf1-a52d4a91dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939353353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.939353353
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1671353479
Short name T616
Test name
Test status
Simulation time 71576417 ps
CPU time 0.81 seconds
Started Feb 18 02:58:07 PM PST 24
Finished Feb 18 02:58:25 PM PST 24
Peak memory 195880 kb
Host smart-89ca7f1a-e6fb-4494-b99f-def23ec9613a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671353479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1671353479
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.4186011122
Short name T533
Test name
Test status
Simulation time 330590360 ps
CPU time 1.8 seconds
Started Feb 18 02:58:13 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 198436 kb
Host smart-72901ffd-f5e9-4f8e-84de-5b321bcec682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186011122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.4186011122
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2979618254
Short name T651
Test name
Test status
Simulation time 52159802 ps
CPU time 1.08 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 196696 kb
Host smart-b44e839b-f0ea-4194-b957-dd8614ea4c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979618254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2979618254
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3937906186
Short name T448
Test name
Test status
Simulation time 70309614 ps
CPU time 0.75 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:27 PM PST 24
Peak memory 194584 kb
Host smart-a663833a-0a9b-4707-a52b-cf2f169c2cb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937906186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3937906186
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.438615442
Short name T187
Test name
Test status
Simulation time 7228902069 ps
CPU time 60.67 seconds
Started Feb 18 02:58:15 PM PST 24
Finished Feb 18 02:59:30 PM PST 24
Peak memory 198584 kb
Host smart-41100295-fc5b-4e13-a008-9fae864231d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438615442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.438615442
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1950436143
Short name T453
Test name
Test status
Simulation time 99644199002 ps
CPU time 647.05 seconds
Started Feb 18 02:58:22 PM PST 24
Finished Feb 18 03:09:20 PM PST 24
Peak memory 198704 kb
Host smart-92ed4166-d068-4b98-aeef-efd6dde2af86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1950436143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1950436143
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3942612280
Short name T361
Test name
Test status
Simulation time 14401515 ps
CPU time 0.58 seconds
Started Feb 18 02:58:22 PM PST 24
Finished Feb 18 02:58:34 PM PST 24
Peak memory 194292 kb
Host smart-768739ff-20a9-463f-8337-69f544b72d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942612280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3942612280
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3367932377
Short name T622
Test name
Test status
Simulation time 33295912 ps
CPU time 0.95 seconds
Started Feb 18 02:58:22 PM PST 24
Finished Feb 18 02:58:34 PM PST 24
Peak memory 196140 kb
Host smart-12053e5e-59dd-40e8-bed4-2ea323ccb786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367932377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3367932377
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1120108674
Short name T720
Test name
Test status
Simulation time 2455031991 ps
CPU time 20.16 seconds
Started Feb 18 02:58:12 PM PST 24
Finished Feb 18 02:58:46 PM PST 24
Peak memory 197336 kb
Host smart-11196b1a-5513-4514-af62-61b01c878e86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120108674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1120108674
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2268226172
Short name T614
Test name
Test status
Simulation time 86364996 ps
CPU time 0.83 seconds
Started Feb 18 02:58:15 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 196996 kb
Host smart-7c4370f4-e2ad-4892-893a-dc6e7b5a2222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268226172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2268226172
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1087664085
Short name T272
Test name
Test status
Simulation time 18836980 ps
CPU time 0.7 seconds
Started Feb 18 02:58:14 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 195808 kb
Host smart-e411c6f3-f9a1-487f-807d-28e3e95071b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087664085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1087664085
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3055837392
Short name T520
Test name
Test status
Simulation time 276059392 ps
CPU time 1.91 seconds
Started Feb 18 02:58:13 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 198388 kb
Host smart-ffa43cee-45c8-4c4d-837a-5b6c6c3e987d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055837392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3055837392
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1928937991
Short name T61
Test name
Test status
Simulation time 75445812 ps
CPU time 1.39 seconds
Started Feb 18 02:58:17 PM PST 24
Finished Feb 18 02:58:31 PM PST 24
Peak memory 196188 kb
Host smart-523e1722-887a-4653-9b71-9f3c877d4389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928937991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1928937991
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.907267593
Short name T557
Test name
Test status
Simulation time 72506951 ps
CPU time 0.88 seconds
Started Feb 18 02:58:16 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 196844 kb
Host smart-f5ea9441-f7cc-42c0-b6a3-a99f318e09d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907267593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.907267593
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1870611074
Short name T378
Test name
Test status
Simulation time 42459397 ps
CPU time 1.03 seconds
Started Feb 18 02:58:16 PM PST 24
Finished Feb 18 02:58:31 PM PST 24
Peak memory 196408 kb
Host smart-9fb3e3a3-bd5e-4795-8190-70dc95140921
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870611074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1870611074
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1012875430
Short name T289
Test name
Test status
Simulation time 1975052871 ps
CPU time 6.34 seconds
Started Feb 18 02:58:14 PM PST 24
Finished Feb 18 02:58:34 PM PST 24
Peak memory 198384 kb
Host smart-2a812311-795b-4207-85c3-75a6f31edc02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012875430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1012875430
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3193731661
Short name T623
Test name
Test status
Simulation time 42948277 ps
CPU time 1.15 seconds
Started Feb 18 02:58:13 PM PST 24
Finished Feb 18 02:58:28 PM PST 24
Peak memory 196772 kb
Host smart-f9c8fb4b-4778-459e-8817-4b4376796fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193731661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3193731661
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3021462273
Short name T140
Test name
Test status
Simulation time 58822021 ps
CPU time 1.15 seconds
Started Feb 18 02:58:16 PM PST 24
Finished Feb 18 02:58:30 PM PST 24
Peak memory 195936 kb
Host smart-71336554-6342-4557-ad7a-8002245386a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021462273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3021462273
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1542670604
Short name T417
Test name
Test status
Simulation time 17002801100 ps
CPU time 222.86 seconds
Started Feb 18 02:58:22 PM PST 24
Finished Feb 18 03:02:16 PM PST 24
Peak memory 198548 kb
Host smart-259a97ab-dabf-47b9-bacd-3faca21d6567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542670604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1542670604
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.423245334
Short name T42
Test name
Test status
Simulation time 13132268 ps
CPU time 0.6 seconds
Started Feb 18 02:58:30 PM PST 24
Finished Feb 18 02:58:41 PM PST 24
Peak memory 194288 kb
Host smart-a77199fb-28d4-4aa9-8f3a-a93aac7ee44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423245334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.423245334
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1525595207
Short name T155
Test name
Test status
Simulation time 33413138 ps
CPU time 0.68 seconds
Started Feb 18 02:58:21 PM PST 24
Finished Feb 18 02:58:33 PM PST 24
Peak memory 194264 kb
Host smart-d9b926c1-7805-45a6-9004-bfeea09c5c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525595207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1525595207
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3362789809
Short name T590
Test name
Test status
Simulation time 556381750 ps
CPU time 28.87 seconds
Started Feb 18 02:58:19 PM PST 24
Finished Feb 18 02:59:00 PM PST 24
Peak memory 198464 kb
Host smart-1de79821-58c4-4537-b0bb-3d2f2310daf3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362789809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3362789809
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3463184106
Short name T263
Test name
Test status
Simulation time 144703122 ps
CPU time 0.82 seconds
Started Feb 18 02:58:27 PM PST 24
Finished Feb 18 02:58:39 PM PST 24
Peak memory 197056 kb
Host smart-c7debd8f-abd9-4617-b495-0831d20ca476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463184106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3463184106
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2549831455
Short name T424
Test name
Test status
Simulation time 70802263 ps
CPU time 1.27 seconds
Started Feb 18 02:58:23 PM PST 24
Finished Feb 18 02:58:36 PM PST 24
Peak memory 196436 kb
Host smart-60ddfd57-3e1c-444c-9d1d-24dcfc4ef9ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549831455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2549831455
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.428299525
Short name T359
Test name
Test status
Simulation time 52816612 ps
CPU time 2.14 seconds
Started Feb 18 02:58:20 PM PST 24
Finished Feb 18 02:58:34 PM PST 24
Peak memory 196736 kb
Host smart-b29ce3a2-e4b4-451d-8d95-23d30e0bd079
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428299525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.428299525
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.995940440
Short name T62
Test name
Test status
Simulation time 90412374 ps
CPU time 1.45 seconds
Started Feb 18 02:58:19 PM PST 24
Finished Feb 18 02:58:32 PM PST 24
Peak memory 197856 kb
Host smart-a95c3d3b-fef5-4be1-a633-ef2b8bf53d48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995940440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
995940440
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.589326777
Short name T188
Test name
Test status
Simulation time 58558103 ps
CPU time 1.24 seconds
Started Feb 18 02:58:19 PM PST 24
Finished Feb 18 02:58:32 PM PST 24
Peak memory 198468 kb
Host smart-3107bbe3-edae-4007-ad2d-1f288ccc7402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589326777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.589326777
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1964910141
Short name T612
Test name
Test status
Simulation time 20576609 ps
CPU time 0.81 seconds
Started Feb 18 02:58:20 PM PST 24
Finished Feb 18 02:58:33 PM PST 24
Peak memory 195804 kb
Host smart-f51331cb-4d76-4b80-8269-86eac0d5036a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964910141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1964910141
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2172481736
Short name T181
Test name
Test status
Simulation time 237117826 ps
CPU time 5.63 seconds
Started Feb 18 02:58:19 PM PST 24
Finished Feb 18 02:58:37 PM PST 24
Peak memory 198412 kb
Host smart-b7007e63-ead1-4b02-b5e5-c16135de5c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172481736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2172481736
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.284550654
Short name T491
Test name
Test status
Simulation time 510320218 ps
CPU time 0.93 seconds
Started Feb 18 02:58:20 PM PST 24
Finished Feb 18 02:58:33 PM PST 24
Peak memory 195804 kb
Host smart-b66671e0-feb6-4205-a139-c6fae6f2884b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284550654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.284550654
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2453435398
Short name T502
Test name
Test status
Simulation time 561337156 ps
CPU time 0.91 seconds
Started Feb 18 02:58:19 PM PST 24
Finished Feb 18 02:58:32 PM PST 24
Peak memory 196816 kb
Host smart-c884187f-1659-46e4-a6a6-d6af6033fe7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453435398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2453435398
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.83495652
Short name T603
Test name
Test status
Simulation time 48769650598 ps
CPU time 213.63 seconds
Started Feb 18 02:58:33 PM PST 24
Finished Feb 18 03:02:17 PM PST 24
Peak memory 198572 kb
Host smart-142fa7ab-c48b-4968-8689-dc5a06d34a8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83495652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gp
io_stress_all.83495652
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2783190288
Short name T35
Test name
Test status
Simulation time 64052880134 ps
CPU time 1081.78 seconds
Started Feb 18 02:58:28 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 198668 kb
Host smart-8e3a5350-6d97-41bf-8af8-3e50e63b4eb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2783190288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2783190288
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3703509063
Short name T512
Test name
Test status
Simulation time 23042110 ps
CPU time 0.59 seconds
Started Feb 18 02:58:33 PM PST 24
Finished Feb 18 02:58:44 PM PST 24
Peak memory 194316 kb
Host smart-63e49af7-dcb6-4026-9818-0bfd50a52eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703509063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3703509063
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.75670091
Short name T490
Test name
Test status
Simulation time 61219934 ps
CPU time 0.82 seconds
Started Feb 18 02:58:31 PM PST 24
Finished Feb 18 02:58:42 PM PST 24
Peak memory 195644 kb
Host smart-612fdf4a-113b-49c5-8143-0bc9efb30ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75670091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.75670091
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1899361932
Short name T597
Test name
Test status
Simulation time 880879987 ps
CPU time 6.33 seconds
Started Feb 18 02:58:30 PM PST 24
Finished Feb 18 02:58:47 PM PST 24
Peak memory 197388 kb
Host smart-eb8e701b-f455-4622-a60c-16c154d5d267
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899361932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1899361932
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2632312557
Short name T493
Test name
Test status
Simulation time 103239504 ps
CPU time 0.84 seconds
Started Feb 18 02:58:30 PM PST 24
Finished Feb 18 02:58:41 PM PST 24
Peak memory 196200 kb
Host smart-658985d4-59d1-48a4-9812-4cea57db9151
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632312557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2632312557
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.617982578
Short name T637
Test name
Test status
Simulation time 155942413 ps
CPU time 0.88 seconds
Started Feb 18 02:58:30 PM PST 24
Finished Feb 18 02:58:41 PM PST 24
Peak memory 196024 kb
Host smart-c9553bfb-5deb-4295-9c88-dcf3e1d0c5fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617982578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.617982578
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1455707840
Short name T210
Test name
Test status
Simulation time 249679390 ps
CPU time 2.53 seconds
Started Feb 18 02:58:30 PM PST 24
Finished Feb 18 02:58:43 PM PST 24
Peak memory 196744 kb
Host smart-5cfbdf4f-67b3-4107-ad8e-b8e8ea8f4252
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455707840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1455707840
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3901059136
Short name T161
Test name
Test status
Simulation time 294407850 ps
CPU time 1.49 seconds
Started Feb 18 02:58:28 PM PST 24
Finished Feb 18 02:58:41 PM PST 24
Peak memory 197064 kb
Host smart-ec682eba-7298-49ed-b873-7498105e2cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901059136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3901059136
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3846702102
Short name T515
Test name
Test status
Simulation time 216201035 ps
CPU time 1.14 seconds
Started Feb 18 02:58:29 PM PST 24
Finished Feb 18 02:58:41 PM PST 24
Peak memory 196568 kb
Host smart-c673b678-9d9b-4051-a5ab-3aab9eebd2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846702102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3846702102
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4174196938
Short name T456
Test name
Test status
Simulation time 55595543 ps
CPU time 1.12 seconds
Started Feb 18 02:58:31 PM PST 24
Finished Feb 18 02:58:42 PM PST 24
Peak memory 196984 kb
Host smart-aa945a4e-5e60-4948-9fd8-8d7d36a338c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174196938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4174196938
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1968826456
Short name T454
Test name
Test status
Simulation time 89555833 ps
CPU time 4.13 seconds
Started Feb 18 02:58:29 PM PST 24
Finished Feb 18 02:58:44 PM PST 24
Peak memory 198324 kb
Host smart-7bda564b-22da-4f9d-8ee8-ff89b37c273c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968826456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1968826456
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3445458466
Short name T142
Test name
Test status
Simulation time 42677716 ps
CPU time 1.24 seconds
Started Feb 18 02:58:28 PM PST 24
Finished Feb 18 02:58:40 PM PST 24
Peak memory 198424 kb
Host smart-93f8b4e3-e716-4316-bd6f-7d638b2a2131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445458466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3445458466
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.934371900
Short name T519
Test name
Test status
Simulation time 591514080 ps
CPU time 1.39 seconds
Started Feb 18 02:58:30 PM PST 24
Finished Feb 18 02:58:42 PM PST 24
Peak memory 196124 kb
Host smart-15dec7a4-b985-49d4-abce-627fdc194331
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934371900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.934371900
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3921658791
Short name T697
Test name
Test status
Simulation time 2557935291 ps
CPU time 34.32 seconds
Started Feb 18 02:58:34 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 198592 kb
Host smart-263526a1-17af-4e9e-9234-b335ec3a8d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921658791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3921658791
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2343110713
Short name T114
Test name
Test status
Simulation time 48800656982 ps
CPU time 780.86 seconds
Started Feb 18 02:58:29 PM PST 24
Finished Feb 18 03:11:41 PM PST 24
Peak memory 198728 kb
Host smart-b1fd7b07-dda9-4ed7-8c8c-e503cb9e9870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2343110713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2343110713
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1751760367
Short name T474
Test name
Test status
Simulation time 11095402 ps
CPU time 0.63 seconds
Started Feb 18 02:58:31 PM PST 24
Finished Feb 18 02:58:42 PM PST 24
Peak memory 194992 kb
Host smart-85d035df-4f2d-49c6-b4ac-2bcc71b82d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751760367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1751760367
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2462203431
Short name T550
Test name
Test status
Simulation time 130216988 ps
CPU time 0.72 seconds
Started Feb 18 02:58:36 PM PST 24
Finished Feb 18 02:58:47 PM PST 24
Peak memory 194620 kb
Host smart-6f073153-534a-4f33-9d9d-ce7c23cd6b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462203431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2462203431
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3751224762
Short name T636
Test name
Test status
Simulation time 748451888 ps
CPU time 10.85 seconds
Started Feb 18 02:58:32 PM PST 24
Finished Feb 18 02:58:53 PM PST 24
Peak memory 197436 kb
Host smart-099f96a1-0df6-4a9e-b49d-eb3b348cbc94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751224762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3751224762
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.898153088
Short name T179
Test name
Test status
Simulation time 110235386 ps
CPU time 0.94 seconds
Started Feb 18 02:58:31 PM PST 24
Finished Feb 18 02:58:42 PM PST 24
Peak memory 196304 kb
Host smart-126e33da-8e6f-4c42-99ad-952824957342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898153088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.898153088
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3321433078
Short name T673
Test name
Test status
Simulation time 185822373 ps
CPU time 0.86 seconds
Started Feb 18 02:58:33 PM PST 24
Finished Feb 18 02:58:45 PM PST 24
Peak memory 196064 kb
Host smart-244a3484-bcd9-47fe-b756-4d6ab58f6001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321433078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3321433078
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3234304064
Short name T353
Test name
Test status
Simulation time 128038057 ps
CPU time 2.75 seconds
Started Feb 18 02:58:40 PM PST 24
Finished Feb 18 02:58:52 PM PST 24
Peak memory 196864 kb
Host smart-090ed1c2-5689-448e-838e-98df45c72efa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234304064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3234304064
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1612827484
Short name T691
Test name
Test status
Simulation time 430129713 ps
CPU time 3.42 seconds
Started Feb 18 02:58:42 PM PST 24
Finished Feb 18 02:58:55 PM PST 24
Peak memory 197532 kb
Host smart-1e0c0d94-e95e-4584-9116-3a8be5c8d300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612827484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1612827484
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.246747580
Short name T483
Test name
Test status
Simulation time 15418023 ps
CPU time 0.72 seconds
Started Feb 18 02:58:42 PM PST 24
Finished Feb 18 02:58:52 PM PST 24
Peak memory 195820 kb
Host smart-aa290c64-e003-4df4-a8ec-6ae5cd602a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246747580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.246747580
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2126297728
Short name T129
Test name
Test status
Simulation time 135271717 ps
CPU time 1.36 seconds
Started Feb 18 02:58:32 PM PST 24
Finished Feb 18 02:58:44 PM PST 24
Peak memory 197540 kb
Host smart-cfbae84a-d500-48da-b348-8df1724172c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126297728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2126297728
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3137406096
Short name T63
Test name
Test status
Simulation time 404026917 ps
CPU time 3.31 seconds
Started Feb 18 02:58:42 PM PST 24
Finished Feb 18 02:58:55 PM PST 24
Peak memory 198404 kb
Host smart-e3abf8b1-0fa7-4f23-981d-38dbace0ade9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137406096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3137406096
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1697104177
Short name T193
Test name
Test status
Simulation time 119126926 ps
CPU time 0.82 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:01 PM PST 24
Peak memory 195708 kb
Host smart-e83d6014-ff6a-4555-98c6-54f45942d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697104177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1697104177
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1554104551
Short name T535
Test name
Test status
Simulation time 51389863 ps
CPU time 1.22 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:57 PM PST 24
Peak memory 198108 kb
Host smart-3b74e1e1-4278-4b4b-af3b-5ff5692bcc3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554104551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1554104551
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3699691005
Short name T663
Test name
Test status
Simulation time 16656563394 ps
CPU time 33.25 seconds
Started Feb 18 02:58:44 PM PST 24
Finished Feb 18 02:59:27 PM PST 24
Peak memory 198576 kb
Host smart-c9d04b84-0396-496e-b7f0-32c810a2ac3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699691005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3699691005
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2913651156
Short name T3
Test name
Test status
Simulation time 120813844076 ps
CPU time 312.16 seconds
Started Feb 18 02:58:44 PM PST 24
Finished Feb 18 03:04:06 PM PST 24
Peak memory 198704 kb
Host smart-c2fbe636-2632-4e8e-983b-163c0e8dfcd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2913651156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2913651156
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2242638397
Short name T299
Test name
Test status
Simulation time 13023521 ps
CPU time 0.61 seconds
Started Feb 18 02:58:44 PM PST 24
Finished Feb 18 02:58:55 PM PST 24
Peak memory 194344 kb
Host smart-f61f3000-6d16-4b71-a483-61e5cac9f9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242638397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2242638397
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1832018535
Short name T449
Test name
Test status
Simulation time 251614621 ps
CPU time 0.65 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:01 PM PST 24
Peak memory 194400 kb
Host smart-dbd550ab-be72-4e5c-a729-bb7ffeded8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832018535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1832018535
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1645938630
Short name T634
Test name
Test status
Simulation time 2394130884 ps
CPU time 16.83 seconds
Started Feb 18 02:58:32 PM PST 24
Finished Feb 18 02:59:00 PM PST 24
Peak memory 197336 kb
Host smart-edc2162d-ff5a-4dbf-9385-cb0f5d712220
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645938630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1645938630
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2257790136
Short name T658
Test name
Test status
Simulation time 82005058 ps
CPU time 1.13 seconds
Started Feb 18 02:58:36 PM PST 24
Finished Feb 18 02:58:47 PM PST 24
Peak memory 198492 kb
Host smart-b26e3168-7324-486a-85e5-2654b8846e96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257790136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2257790136
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3175546163
Short name T704
Test name
Test status
Simulation time 210561711 ps
CPU time 1.16 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:57 PM PST 24
Peak memory 196344 kb
Host smart-677f7300-8bc3-4a50-88d6-627d1e42fda1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175546163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3175546163
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.940535217
Short name T158
Test name
Test status
Simulation time 29188691 ps
CPU time 1.13 seconds
Started Feb 18 02:58:36 PM PST 24
Finished Feb 18 02:58:47 PM PST 24
Peak memory 198312 kb
Host smart-7628b24c-223f-440b-9e79-65ac72b72fb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940535217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.940535217
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2734629181
Short name T143
Test name
Test status
Simulation time 227751013 ps
CPU time 3.55 seconds
Started Feb 18 02:58:41 PM PST 24
Finished Feb 18 02:58:54 PM PST 24
Peak memory 196988 kb
Host smart-d4408ffc-aa89-4995-a364-91d121a14f92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734629181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2734629181
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2821138920
Short name T587
Test name
Test status
Simulation time 33109407 ps
CPU time 0.84 seconds
Started Feb 18 02:58:34 PM PST 24
Finished Feb 18 02:58:45 PM PST 24
Peak memory 197740 kb
Host smart-e60e05ab-fb71-4311-a10b-52afd4f7289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821138920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2821138920
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.916053399
Short name T285
Test name
Test status
Simulation time 32852600 ps
CPU time 0.8 seconds
Started Feb 18 02:58:41 PM PST 24
Finished Feb 18 02:58:52 PM PST 24
Peak memory 195828 kb
Host smart-54f3a1ee-83b8-44fc-9fac-2e136ee75915
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916053399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.916053399
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1573165119
Short name T10
Test name
Test status
Simulation time 1613377783 ps
CPU time 4.94 seconds
Started Feb 18 02:58:44 PM PST 24
Finished Feb 18 02:58:58 PM PST 24
Peak memory 198420 kb
Host smart-74676e08-626b-4f9d-b2e3-7550600d589d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573165119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1573165119
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1765531911
Short name T602
Test name
Test status
Simulation time 106411441 ps
CPU time 0.86 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 196328 kb
Host smart-4669201e-b04f-40a2-bd86-f54052b7b4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765531911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1765531911
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3510494388
Short name T629
Test name
Test status
Simulation time 54477688 ps
CPU time 1.44 seconds
Started Feb 18 02:58:32 PM PST 24
Finished Feb 18 02:58:45 PM PST 24
Peak memory 198440 kb
Host smart-005b6e13-e5af-47a1-a2f4-837101e392f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510494388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3510494388
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3123101684
Short name T432
Test name
Test status
Simulation time 31528885104 ps
CPU time 90.61 seconds
Started Feb 18 02:58:32 PM PST 24
Finished Feb 18 03:00:14 PM PST 24
Peak memory 198520 kb
Host smart-32216b4d-684c-435d-9a6d-7e7f823333fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123101684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3123101684
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1102491335
Short name T666
Test name
Test status
Simulation time 42407563 ps
CPU time 0.56 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:05 PM PST 24
Peak memory 194460 kb
Host smart-2fb166af-f991-4a19-a077-c2b9142a0e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102491335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1102491335
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1169952982
Short name T484
Test name
Test status
Simulation time 176492671 ps
CPU time 0.82 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:02 PM PST 24
Peak memory 195856 kb
Host smart-c109aa64-7a51-4193-b8d2-df0566ecb1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169952982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1169952982
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1530569511
Short name T698
Test name
Test status
Simulation time 345650416 ps
CPU time 18.21 seconds
Started Feb 18 02:58:42 PM PST 24
Finished Feb 18 02:59:10 PM PST 24
Peak memory 198440 kb
Host smart-05c3d31d-7a74-4d1a-97bf-e0803697f16c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530569511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1530569511
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3556323603
Short name T78
Test name
Test status
Simulation time 62017164 ps
CPU time 1 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:56 PM PST 24
Peak memory 196764 kb
Host smart-a2400ec5-2c32-499f-8c3c-263896427ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556323603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3556323603
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1126235688
Short name T486
Test name
Test status
Simulation time 53183267 ps
CPU time 1.35 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:17 PM PST 24
Peak memory 197632 kb
Host smart-6c975ce1-c94c-4130-81b1-948847a54fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126235688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1126235688
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3090413743
Short name T300
Test name
Test status
Simulation time 166241617 ps
CPU time 2.03 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:04 PM PST 24
Peak memory 198532 kb
Host smart-10d06143-7c46-46ea-a707-01f16c0b18f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090413743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3090413743
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1165368893
Short name T399
Test name
Test status
Simulation time 66471201 ps
CPU time 1.55 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 196476 kb
Host smart-2006cbfd-8f19-49db-946a-9f1580a76d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165368893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1165368893
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2153478384
Short name T457
Test name
Test status
Simulation time 21844424 ps
CPU time 0.92 seconds
Started Feb 18 02:58:36 PM PST 24
Finished Feb 18 02:58:47 PM PST 24
Peak memory 196272 kb
Host smart-3b2dd394-6e7a-4efb-971f-d0da46a51d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153478384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2153478384
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2869535860
Short name T391
Test name
Test status
Simulation time 302918628 ps
CPU time 1.26 seconds
Started Feb 18 02:58:32 PM PST 24
Finished Feb 18 02:58:43 PM PST 24
Peak memory 198508 kb
Host smart-e97ef5f9-d9fc-4560-b7a6-39cab07c82b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869535860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2869535860
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1236526330
Short name T4
Test name
Test status
Simulation time 873591036 ps
CPU time 3.62 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:03 PM PST 24
Peak memory 198420 kb
Host smart-18528625-364e-4cd3-8331-c8a9ad03c57f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236526330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1236526330
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2124470329
Short name T333
Test name
Test status
Simulation time 82636469 ps
CPU time 1.61 seconds
Started Feb 18 02:58:44 PM PST 24
Finished Feb 18 02:58:55 PM PST 24
Peak memory 197180 kb
Host smart-42b7b710-f4a4-4660-97ab-a587961b2680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124470329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2124470329
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.600967309
Short name T522
Test name
Test status
Simulation time 121485902 ps
CPU time 1.15 seconds
Started Feb 18 02:58:43 PM PST 24
Finished Feb 18 02:58:54 PM PST 24
Peak memory 196172 kb
Host smart-346ec071-0d4a-4ef7-84b0-5b80f4a83d78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600967309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.600967309
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.874827641
Short name T638
Test name
Test status
Simulation time 60370260602 ps
CPU time 214.98 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 03:02:30 PM PST 24
Peak memory 198592 kb
Host smart-8cb3a308-0412-485a-a69f-0fa9ce35ce32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874827641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.874827641
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4103357135
Short name T639
Test name
Test status
Simulation time 308730601080 ps
CPU time 1630.9 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 03:26:08 PM PST 24
Peak memory 198644 kb
Host smart-f11521c5-d806-427d-aa7c-8bb19263c16a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4103357135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4103357135
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2486294290
Short name T503
Test name
Test status
Simulation time 35525165 ps
CPU time 0.57 seconds
Started Feb 18 02:56:15 PM PST 24
Finished Feb 18 02:56:18 PM PST 24
Peak memory 193880 kb
Host smart-bbe030bb-3ba0-4fba-bb30-9175da66370e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486294290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2486294290
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.790694590
Short name T222
Test name
Test status
Simulation time 19299990 ps
CPU time 0.79 seconds
Started Feb 18 02:56:15 PM PST 24
Finished Feb 18 02:56:18 PM PST 24
Peak memory 195348 kb
Host smart-ff4b9f7c-cb17-4d3e-8cb2-0c74b7afed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790694590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.790694590
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.334542116
Short name T216
Test name
Test status
Simulation time 374050527 ps
CPU time 12.19 seconds
Started Feb 18 02:56:18 PM PST 24
Finished Feb 18 02:56:33 PM PST 24
Peak memory 198468 kb
Host smart-cc4b8555-4d4a-4e0d-a2d7-84599c0fe7e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334542116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.334542116
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1554464364
Short name T270
Test name
Test status
Simulation time 36456666 ps
CPU time 0.8 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 196960 kb
Host smart-7249869d-0755-4591-bd24-579a0e1044cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554464364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1554464364
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1455779218
Short name T712
Test name
Test status
Simulation time 345880245 ps
CPU time 1.45 seconds
Started Feb 18 02:56:15 PM PST 24
Finished Feb 18 02:56:18 PM PST 24
Peak memory 197584 kb
Host smart-ac5056a1-94d8-49ec-92f5-73672ed97674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455779218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1455779218
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.4289703049
Short name T615
Test name
Test status
Simulation time 258575229 ps
CPU time 2.99 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:29 PM PST 24
Peak memory 198448 kb
Host smart-a4981e08-3ea8-4c98-8361-65b1dff2c27c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289703049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.4289703049
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.397539698
Short name T297
Test name
Test status
Simulation time 332528827 ps
CPU time 1.98 seconds
Started Feb 18 02:56:21 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 196296 kb
Host smart-0f2caea3-e75d-47ba-8f46-9f2a46891d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397539698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.397539698
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1480380498
Short name T570
Test name
Test status
Simulation time 34824328 ps
CPU time 0.99 seconds
Started Feb 18 02:56:14 PM PST 24
Finished Feb 18 02:56:17 PM PST 24
Peak memory 196392 kb
Host smart-96109723-7f4d-4b00-a714-1af19c9b3e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480380498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1480380498
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2824869266
Short name T354
Test name
Test status
Simulation time 17513364 ps
CPU time 0.79 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 196552 kb
Host smart-a7ceae0d-6b31-4dca-9439-08403c0f2333
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824869266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2824869266
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2195823378
Short name T696
Test name
Test status
Simulation time 3004071085 ps
CPU time 3.62 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 198488 kb
Host smart-08b66d48-35d4-447a-a0e7-2915d85addc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195823378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2195823378
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.446096280
Short name T41
Test name
Test status
Simulation time 76134760 ps
CPU time 0.84 seconds
Started Feb 18 02:56:19 PM PST 24
Finished Feb 18 02:56:23 PM PST 24
Peak memory 213752 kb
Host smart-c4c1539b-c79f-4e1c-986f-533c65474647
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446096280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.446096280
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1941196886
Short name T413
Test name
Test status
Simulation time 337776405 ps
CPU time 1.19 seconds
Started Feb 18 02:56:04 PM PST 24
Finished Feb 18 02:56:07 PM PST 24
Peak memory 196684 kb
Host smart-062bf292-73d2-4b05-911d-cf72d9aa2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941196886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1941196886
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1106997022
Short name T507
Test name
Test status
Simulation time 57056537 ps
CPU time 0.98 seconds
Started Feb 18 02:56:16 PM PST 24
Finished Feb 18 02:56:20 PM PST 24
Peak memory 197596 kb
Host smart-5f681771-dd47-456d-a423-24a6ebc01d88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106997022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1106997022
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1362947370
Short name T487
Test name
Test status
Simulation time 31439731328 ps
CPU time 229.03 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 03:00:13 PM PST 24
Peak memory 198572 kb
Host smart-0439014d-a18a-4229-8402-c3a65efdcf52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362947370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1362947370
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1081726750
Short name T631
Test name
Test status
Simulation time 4275168125 ps
CPU time 73.71 seconds
Started Feb 18 02:56:21 PM PST 24
Finished Feb 18 02:57:39 PM PST 24
Peak memory 198604 kb
Host smart-cd6dfe08-26a6-4bf6-b579-f97cf8e9c673
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1081726750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1081726750
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.253258051
Short name T528
Test name
Test status
Simulation time 19100696 ps
CPU time 0.59 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:56 PM PST 24
Peak memory 194464 kb
Host smart-924ac6b8-d1f8-4f02-b4f9-36289e1cab8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253258051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.253258051
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1511779853
Short name T200
Test name
Test status
Simulation time 17129544 ps
CPU time 0.7 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 194548 kb
Host smart-74465154-251a-413a-bcb1-fdcaf43a9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511779853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1511779853
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1308378159
Short name T555
Test name
Test status
Simulation time 125168599 ps
CPU time 4.22 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:09 PM PST 24
Peak memory 195920 kb
Host smart-4d222541-6527-4ca0-b3aa-c1227c338083
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308378159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1308378159
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3875213975
Short name T247
Test name
Test status
Simulation time 318758809 ps
CPU time 0.99 seconds
Started Feb 18 02:58:43 PM PST 24
Finished Feb 18 02:58:54 PM PST 24
Peak memory 197008 kb
Host smart-39be8689-56c8-436f-80a6-7360567f9804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875213975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3875213975
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3337583513
Short name T628
Test name
Test status
Simulation time 453891661 ps
CPU time 0.96 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:13 PM PST 24
Peak memory 196172 kb
Host smart-9ed98465-3066-4b57-af1f-9c758c2622c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337583513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3337583513
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4049187453
Short name T680
Test name
Test status
Simulation time 26272029 ps
CPU time 1.19 seconds
Started Feb 18 02:58:42 PM PST 24
Finished Feb 18 02:58:53 PM PST 24
Peak memory 197464 kb
Host smart-d63ab9ba-6a2b-452e-b721-517c43ff082a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049187453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4049187453
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.931885919
Short name T425
Test name
Test status
Simulation time 82021206 ps
CPU time 2.67 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:12 PM PST 24
Peak memory 197660 kb
Host smart-d8740c8c-4cc2-4489-a90c-3a5766d664db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931885919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
931885919
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.294029893
Short name T374
Test name
Test status
Simulation time 119550723 ps
CPU time 0.72 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 195868 kb
Host smart-d4d3bd23-7a06-401c-b76e-8c27ccd11ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294029893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.294029893
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1431112819
Short name T538
Test name
Test status
Simulation time 54977898 ps
CPU time 1.29 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:57 PM PST 24
Peak memory 197460 kb
Host smart-97dc4d18-0daa-4c81-b3fd-cefe9d1c876e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431112819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1431112819
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4002158017
Short name T343
Test name
Test status
Simulation time 426488818 ps
CPU time 5.18 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:07 PM PST 24
Peak memory 198416 kb
Host smart-ae6a496f-ca32-48c3-b4de-85858c511a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002158017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4002158017
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.245502435
Short name T655
Test name
Test status
Simulation time 90873487 ps
CPU time 1.11 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:56 PM PST 24
Peak memory 196192 kb
Host smart-a2871a3e-2271-4b3b-9ba2-412bb9974ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245502435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.245502435
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1947604519
Short name T60
Test name
Test status
Simulation time 108396560 ps
CPU time 0.94 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 196536 kb
Host smart-7b85c225-5ee6-4f5b-b0dc-8ca75f185690
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947604519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1947604519
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1579231681
Short name T105
Test name
Test status
Simulation time 5143093262 ps
CPU time 29.01 seconds
Started Feb 18 02:58:39 PM PST 24
Finished Feb 18 02:59:17 PM PST 24
Peak memory 198604 kb
Host smart-f6b7862d-ff44-4fb2-908a-368ed1fee618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579231681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1579231681
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.972039809
Short name T389
Test name
Test status
Simulation time 306616481871 ps
CPU time 1926.1 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 03:31:01 PM PST 24
Peak memory 198636 kb
Host smart-6bd660f5-149b-4bb2-832a-99efd2df5fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=972039809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.972039809
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.733638646
Short name T295
Test name
Test status
Simulation time 23326300 ps
CPU time 0.61 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:56 PM PST 24
Peak memory 194512 kb
Host smart-6b2a18ba-134a-4b2c-b27b-99de96e21349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733638646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.733638646
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2428174999
Short name T506
Test name
Test status
Simulation time 21213884 ps
CPU time 0.66 seconds
Started Feb 18 02:58:42 PM PST 24
Finished Feb 18 02:58:52 PM PST 24
Peak memory 194364 kb
Host smart-0870fe54-342e-4ee1-a5c1-b7821fd00831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428174999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2428174999
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.236664978
Short name T253
Test name
Test status
Simulation time 307911965 ps
CPU time 4.92 seconds
Started Feb 18 02:58:51 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 195952 kb
Host smart-ecc55789-8959-4e3b-a7a3-b277234160dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236664978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.236664978
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1826580442
Short name T441
Test name
Test status
Simulation time 100618649 ps
CPU time 0.86 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:58 PM PST 24
Peak memory 196992 kb
Host smart-10fac3db-2094-4c0f-be0a-c02361e48bcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826580442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1826580442
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2421532969
Short name T540
Test name
Test status
Simulation time 79357350 ps
CPU time 0.67 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 195448 kb
Host smart-b595bd5c-ac17-4b52-ba35-2ac851c5f5d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421532969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2421532969
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1794849088
Short name T467
Test name
Test status
Simulation time 43295864 ps
CPU time 1.74 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:01 PM PST 24
Peak memory 197160 kb
Host smart-8522ee43-f1e5-4fda-a856-445b48fca755
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794849088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1794849088
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2437462505
Short name T710
Test name
Test status
Simulation time 98680913 ps
CPU time 2.14 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:07 PM PST 24
Peak memory 196192 kb
Host smart-557828d0-d324-4f6f-80c0-f86f02f45736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437462505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2437462505
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1729052666
Short name T226
Test name
Test status
Simulation time 79654401 ps
CPU time 0.87 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 196316 kb
Host smart-ee147468-3c7d-4b47-bddd-cbfbd0aafb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729052666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1729052666
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3006718925
Short name T178
Test name
Test status
Simulation time 85827242 ps
CPU time 0.79 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 195968 kb
Host smart-60b3cc91-7921-42f8-8a2b-7809942c4795
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006718925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3006718925
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2429978006
Short name T384
Test name
Test status
Simulation time 181475611 ps
CPU time 2.31 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 198396 kb
Host smart-b21a69f6-38b1-4e2b-aea2-dfe125e8ed7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429978006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2429978006
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3748676551
Short name T287
Test name
Test status
Simulation time 209315847 ps
CPU time 1.48 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:58 PM PST 24
Peak memory 197212 kb
Host smart-ca1371f9-8823-4359-bac3-ada20bf4e747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748676551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3748676551
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.751058331
Short name T326
Test name
Test status
Simulation time 100283308 ps
CPU time 1.06 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:03 PM PST 24
Peak memory 195660 kb
Host smart-93cf4154-ae14-4fe1-9cef-8ff80665b5ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751058331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.751058331
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1887633728
Short name T584
Test name
Test status
Simulation time 6331213581 ps
CPU time 45.05 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:50 PM PST 24
Peak memory 198544 kb
Host smart-b5d95533-1bba-4745-8919-867c0f3df42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887633728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1887633728
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1215740141
Short name T349
Test name
Test status
Simulation time 188018725885 ps
CPU time 877.78 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 03:13:34 PM PST 24
Peak memory 198720 kb
Host smart-966c29b1-c480-4db4-b426-1cf481f00f49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1215740141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1215740141
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1030861272
Short name T707
Test name
Test status
Simulation time 20160078 ps
CPU time 0.58 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:00 PM PST 24
Peak memory 194304 kb
Host smart-b8d77d46-f92a-485b-9fc0-2c18e08f1aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030861272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1030861272
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3947359306
Short name T301
Test name
Test status
Simulation time 18314117 ps
CPU time 0.76 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:56 PM PST 24
Peak memory 194608 kb
Host smart-f6b91758-1d8b-4b38-8db7-0dd1f9be3e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947359306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3947359306
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3908166118
Short name T392
Test name
Test status
Simulation time 719963298 ps
CPU time 5.07 seconds
Started Feb 18 02:58:49 PM PST 24
Finished Feb 18 02:59:08 PM PST 24
Peak memory 197416 kb
Host smart-0ca0b5e3-7882-4a26-a838-9417299733af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908166118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3908166118
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3455255904
Short name T660
Test name
Test status
Simulation time 58813644 ps
CPU time 0.62 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:05 PM PST 24
Peak memory 194828 kb
Host smart-19a6256a-b000-48c8-9a19-b08efc31e4b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455255904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3455255904
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3364798123
Short name T654
Test name
Test status
Simulation time 132687787 ps
CPU time 0.9 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:03 PM PST 24
Peak memory 196640 kb
Host smart-76af824e-5bca-4486-b91e-540d156f992d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364798123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3364798123
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3758455581
Short name T319
Test name
Test status
Simulation time 301724548 ps
CPU time 3.63 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:09 PM PST 24
Peak memory 198512 kb
Host smart-6755c675-3d08-4a2f-9f4e-d317e2abf2c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758455581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3758455581
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2898486767
Short name T545
Test name
Test status
Simulation time 396461187 ps
CPU time 1.51 seconds
Started Feb 18 02:58:49 PM PST 24
Finished Feb 18 02:59:05 PM PST 24
Peak memory 196536 kb
Host smart-1d0b9181-09b1-4ddc-877b-d083293590b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898486767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2898486767
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2763732443
Short name T201
Test name
Test status
Simulation time 53047373 ps
CPU time 0.86 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:57 PM PST 24
Peak memory 195932 kb
Host smart-72b3a25a-7a66-4d55-bfbe-6dc98b67601e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763732443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2763732443
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1115762490
Short name T292
Test name
Test status
Simulation time 67164527 ps
CPU time 0.94 seconds
Started Feb 18 02:58:49 PM PST 24
Finished Feb 18 02:59:04 PM PST 24
Peak memory 196380 kb
Host smart-417e43f6-3365-47cf-8e42-c38115d097ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115762490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1115762490
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4194830962
Short name T546
Test name
Test status
Simulation time 222099969 ps
CPU time 4.37 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:05 PM PST 24
Peak memory 198456 kb
Host smart-dd80d861-b76c-45b3-bd0c-2e56fa9cea40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194830962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4194830962
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.806075469
Short name T556
Test name
Test status
Simulation time 458515616 ps
CPU time 0.97 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 196076 kb
Host smart-5e05401e-e0b4-474d-b7ec-d5055cdaaa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806075469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.806075469
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1569755885
Short name T613
Test name
Test status
Simulation time 85089168 ps
CPU time 1.2 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:02 PM PST 24
Peak memory 196104 kb
Host smart-6f82ad31-4ec1-40be-9c0c-1ddafbc2c4ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569755885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1569755885
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.4128165294
Short name T153
Test name
Test status
Simulation time 7451990782 ps
CPU time 104.1 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 03:00:40 PM PST 24
Peak memory 198620 kb
Host smart-43c4b13b-e9f4-4967-b387-dfa277b7c4b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128165294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.4128165294
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2415921819
Short name T302
Test name
Test status
Simulation time 196755812047 ps
CPU time 658.54 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 03:10:01 PM PST 24
Peak memory 206924 kb
Host smart-9ea87f4a-a120-45f0-aa8a-e7014e88ec49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2415921819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2415921819
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3492744828
Short name T679
Test name
Test status
Simulation time 45326443 ps
CPU time 0.58 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 194308 kb
Host smart-43e20788-556b-46ab-9142-92c886a1c10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492744828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3492744828
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4133382517
Short name T689
Test name
Test status
Simulation time 22238750 ps
CPU time 0.76 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:01 PM PST 24
Peak memory 195772 kb
Host smart-521907a0-12f6-467a-8408-037b18457bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133382517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4133382517
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3670545858
Short name T321
Test name
Test status
Simulation time 437380064 ps
CPU time 24.09 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:24 PM PST 24
Peak memory 198448 kb
Host smart-8c92c0be-569d-434a-a02c-aa147482c62f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670545858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3670545858
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1511447926
Short name T572
Test name
Test status
Simulation time 286377701 ps
CPU time 0.76 seconds
Started Feb 18 02:58:51 PM PST 24
Finished Feb 18 02:59:09 PM PST 24
Peak memory 196248 kb
Host smart-f06eff32-a3f9-4daa-9295-c5ee50ddca17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511447926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1511447926
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2008738950
Short name T205
Test name
Test status
Simulation time 98234191 ps
CPU time 1.01 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:00 PM PST 24
Peak memory 196872 kb
Host smart-d06f832b-3369-4a67-aafc-ee8bd2104e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008738950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2008738950
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1390181306
Short name T223
Test name
Test status
Simulation time 331918391 ps
CPU time 3.52 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:02 PM PST 24
Peak memory 198504 kb
Host smart-43469ff9-7a9b-4430-9f46-d01970522089
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390181306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1390181306
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2513159758
Short name T33
Test name
Test status
Simulation time 513598211 ps
CPU time 2.8 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:08 PM PST 24
Peak memory 196252 kb
Host smart-8b5cb973-cf7d-4583-8b0e-0398a737a73f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513159758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2513159758
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3611397083
Short name T411
Test name
Test status
Simulation time 107740572 ps
CPU time 1.12 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 197444 kb
Host smart-37a076bd-4c1f-4767-a89c-0603ad73e112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611397083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3611397083
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3897036525
Short name T261
Test name
Test status
Simulation time 65299846 ps
CPU time 1.25 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:57 PM PST 24
Peak memory 197428 kb
Host smart-edcb0088-d7cf-4f71-b38b-5a690a3f58a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897036525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3897036525
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.465615844
Short name T318
Test name
Test status
Simulation time 181018218 ps
CPU time 4.23 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 198448 kb
Host smart-b8d25ad0-e5c8-45b4-8642-a55762fd5e6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465615844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.465615844
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2933156348
Short name T134
Test name
Test status
Simulation time 253596457 ps
CPU time 0.88 seconds
Started Feb 18 02:58:47 PM PST 24
Finished Feb 18 02:59:01 PM PST 24
Peak memory 196568 kb
Host smart-7f161f81-adc4-4a66-a1aa-31f6c4b29465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933156348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2933156348
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.4094653376
Short name T682
Test name
Test status
Simulation time 47902026 ps
CPU time 1.09 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 02:58:57 PM PST 24
Peak memory 195920 kb
Host smart-a9ac30a7-37b1-4b05-af2d-10a831fe324f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094653376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.4094653376
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.634028852
Short name T643
Test name
Test status
Simulation time 22905907576 ps
CPU time 151.25 seconds
Started Feb 18 02:58:52 PM PST 24
Finished Feb 18 03:01:40 PM PST 24
Peak memory 198568 kb
Host smart-d5e7b3ea-1af8-4175-ae6e-0856173943f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634028852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.634028852
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1484640352
Short name T64
Test name
Test status
Simulation time 651335334286 ps
CPU time 2531.98 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 03:41:07 PM PST 24
Peak memory 198672 kb
Host smart-a1834563-1a72-4c28-843f-7f413db0778f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1484640352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1484640352
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2161213450
Short name T139
Test name
Test status
Simulation time 47828670 ps
CPU time 0.59 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 194480 kb
Host smart-e3e1c01c-04d9-4a2a-90b9-45a66b0e3287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161213450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2161213450
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.776111198
Short name T513
Test name
Test status
Simulation time 101265059 ps
CPU time 0.81 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 195692 kb
Host smart-d8a480d9-ca85-4cf3-97e1-352585079b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776111198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.776111198
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.483218437
Short name T366
Test name
Test status
Simulation time 991239397 ps
CPU time 25.27 seconds
Started Feb 18 02:58:52 PM PST 24
Finished Feb 18 02:59:35 PM PST 24
Peak memory 197416 kb
Host smart-7f6c8699-7ae8-407e-b0d1-d1e2695b6583
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483218437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.483218437
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1911075982
Short name T29
Test name
Test status
Simulation time 189730178 ps
CPU time 0.79 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:06 PM PST 24
Peak memory 196840 kb
Host smart-909d511d-315d-4739-b6a4-ff27102f0d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911075982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1911075982
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4251280770
Short name T577
Test name
Test status
Simulation time 108094470 ps
CPU time 0.94 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:16 PM PST 24
Peak memory 196248 kb
Host smart-c0ace118-cae8-46ad-9fc0-8923fd6fae79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251280770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4251280770
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2929563552
Short name T573
Test name
Test status
Simulation time 205129935 ps
CPU time 1.96 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:59 PM PST 24
Peak memory 198436 kb
Host smart-2575caea-12c4-4f54-8a14-03e709042e94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929563552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2929563552
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1820664211
Short name T488
Test name
Test status
Simulation time 55342598 ps
CPU time 1.26 seconds
Started Feb 18 02:58:53 PM PST 24
Finished Feb 18 02:59:12 PM PST 24
Peak memory 195952 kb
Host smart-7a561902-e416-4b84-a300-3e7b3061c4ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820664211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1820664211
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1072661883
Short name T316
Test name
Test status
Simulation time 116634868 ps
CPU time 0.88 seconds
Started Feb 18 02:58:57 PM PST 24
Finished Feb 18 02:59:16 PM PST 24
Peak memory 196444 kb
Host smart-740288fa-80ca-41c2-a6f9-d8060df150f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072661883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1072661883
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.493810303
Short name T387
Test name
Test status
Simulation time 412573539 ps
CPU time 1.24 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:17 PM PST 24
Peak memory 197468 kb
Host smart-3f8c7a1e-befb-4e86-91f9-33da0b8ef60c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493810303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.493810303
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.421316688
Short name T719
Test name
Test status
Simulation time 72377964 ps
CPU time 3.49 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:04 PM PST 24
Peak memory 198416 kb
Host smart-4b271130-9ecf-4cc6-82be-e3691b9521df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421316688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.421316688
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2732064126
Short name T521
Test name
Test status
Simulation time 301398499 ps
CPU time 0.81 seconds
Started Feb 18 02:58:46 PM PST 24
Finished Feb 18 02:58:58 PM PST 24
Peak memory 196380 kb
Host smart-72e034da-ae89-409b-ade5-746f5d99b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732064126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2732064126
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2131739017
Short name T356
Test name
Test status
Simulation time 260949085 ps
CPU time 1.33 seconds
Started Feb 18 02:58:49 PM PST 24
Finished Feb 18 02:59:04 PM PST 24
Peak memory 198436 kb
Host smart-22408469-2982-4d55-87de-eccf7505bbd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131739017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2131739017
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3260993932
Short name T529
Test name
Test status
Simulation time 26331254117 ps
CPU time 183.01 seconds
Started Feb 18 02:58:45 PM PST 24
Finished Feb 18 03:01:59 PM PST 24
Peak memory 198576 kb
Host smart-ae871f11-a2dc-4330-b0b1-a2cf091ad866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260993932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3260993932
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1264360109
Short name T635
Test name
Test status
Simulation time 27648116 ps
CPU time 0.58 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:16 PM PST 24
Peak memory 194228 kb
Host smart-94f5d2fd-deea-43d9-a183-e2b868d1c59f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264360109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1264360109
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1825237251
Short name T337
Test name
Test status
Simulation time 155462179 ps
CPU time 0.88 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:13 PM PST 24
Peak memory 195648 kb
Host smart-da63367c-5568-4899-a9c6-fe8366477cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825237251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1825237251
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1522123364
Short name T156
Test name
Test status
Simulation time 1003064163 ps
CPU time 25.69 seconds
Started Feb 18 02:58:59 PM PST 24
Finished Feb 18 02:59:42 PM PST 24
Peak memory 197144 kb
Host smart-1963f6ac-307e-4e3f-95bb-029745934842
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522123364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1522123364
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4001167679
Short name T690
Test name
Test status
Simulation time 82786381 ps
CPU time 0.79 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 196208 kb
Host smart-f68f85f5-0f8d-40f5-b3a4-709a32163fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001167679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4001167679
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.595550377
Short name T398
Test name
Test status
Simulation time 30631458 ps
CPU time 0.74 seconds
Started Feb 18 02:58:57 PM PST 24
Finished Feb 18 02:59:16 PM PST 24
Peak memory 195420 kb
Host smart-6830e449-42e0-466d-b484-4470b15c39d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595550377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.595550377
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1434849846
Short name T445
Test name
Test status
Simulation time 315732590 ps
CPU time 3.02 seconds
Started Feb 18 02:58:51 PM PST 24
Finished Feb 18 02:59:11 PM PST 24
Peak memory 198508 kb
Host smart-118d3e17-ba3b-4fea-8a67-8c1e0b0d4106
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434849846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1434849846
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2984344521
Short name T692
Test name
Test status
Simulation time 191073866 ps
CPU time 2.1 seconds
Started Feb 18 02:59:01 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 196952 kb
Host smart-6aaeceb3-a601-41b3-9121-b05831b9eb74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984344521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2984344521
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2860884028
Short name T22
Test name
Test status
Simulation time 45703613 ps
CPU time 0.93 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:13 PM PST 24
Peak memory 196448 kb
Host smart-1592c401-1950-4108-b77c-693c8e065d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860884028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2860884028
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2316973030
Short name T645
Test name
Test status
Simulation time 211990594 ps
CPU time 1.29 seconds
Started Feb 18 02:58:51 PM PST 24
Finished Feb 18 02:59:09 PM PST 24
Peak memory 197296 kb
Host smart-be187d59-e131-457b-885f-413739007bf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316973030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2316973030
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3623112472
Short name T325
Test name
Test status
Simulation time 711358179 ps
CPU time 4.93 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 198100 kb
Host smart-8873156b-d87d-45f2-a5ec-83f6fd321a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623112472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3623112472
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2132555336
Short name T110
Test name
Test status
Simulation time 27126054 ps
CPU time 0.79 seconds
Started Feb 18 02:58:49 PM PST 24
Finished Feb 18 02:59:04 PM PST 24
Peak memory 195568 kb
Host smart-25ba19b9-6684-4fd7-99b7-ee2b68464f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132555336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2132555336
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3109340190
Short name T255
Test name
Test status
Simulation time 159287075 ps
CPU time 1.17 seconds
Started Feb 18 02:58:48 PM PST 24
Finished Feb 18 02:59:02 PM PST 24
Peak memory 195940 kb
Host smart-818f77c2-d2be-4d10-a440-9fa760bab75b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109340190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3109340190
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2272526727
Short name T561
Test name
Test status
Simulation time 27518538676 ps
CPU time 198.05 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 03:02:35 PM PST 24
Peak memory 198532 kb
Host smart-f67e70d0-a99a-490e-8f3c-e04c456109e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272526727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2272526727
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2417713575
Short name T66
Test name
Test status
Simulation time 672124971230 ps
CPU time 2233.39 seconds
Started Feb 18 02:58:52 PM PST 24
Finished Feb 18 03:36:23 PM PST 24
Peak memory 198692 kb
Host smart-27472265-759f-4688-9dc2-68426dad873c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2417713575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2417713575
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1290954868
Short name T517
Test name
Test status
Simulation time 20407912 ps
CPU time 0.6 seconds
Started Feb 18 02:59:02 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 194964 kb
Host smart-e1993439-148c-4716-94a3-1fbc3344dc9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290954868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1290954868
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3870475000
Short name T642
Test name
Test status
Simulation time 29652451 ps
CPU time 0.78 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:12 PM PST 24
Peak memory 196308 kb
Host smart-c0f78323-5ade-4b49-b789-975568a3836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870475000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3870475000
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1252829841
Short name T504
Test name
Test status
Simulation time 559919059 ps
CPU time 7.8 seconds
Started Feb 18 02:59:01 PM PST 24
Finished Feb 18 02:59:25 PM PST 24
Peak memory 198008 kb
Host smart-22ff3f9c-5c0b-4cea-99ce-2eff2df86c4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252829841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1252829841
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3311779551
Short name T641
Test name
Test status
Simulation time 161889730 ps
CPU time 0.83 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:13 PM PST 24
Peak memory 196180 kb
Host smart-918dc17b-0852-4f95-9960-65e461b363cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311779551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3311779551
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3537732620
Short name T310
Test name
Test status
Simulation time 84469696 ps
CPU time 1.32 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 196688 kb
Host smart-3ed75d56-8360-4870-abe7-699bce229d29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537732620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3537732620
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1524392272
Short name T120
Test name
Test status
Simulation time 265950856 ps
CPU time 3.13 seconds
Started Feb 18 02:59:02 PM PST 24
Finished Feb 18 02:59:22 PM PST 24
Peak memory 198496 kb
Host smart-c627d51a-dfa8-42b9-8406-29a2fe126356
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524392272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1524392272
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.466097500
Short name T283
Test name
Test status
Simulation time 93279527 ps
CPU time 2.86 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 197736 kb
Host smart-27682249-aec2-4cfa-8ba3-0eb677e78415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466097500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
466097500
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1118276295
Short name T656
Test name
Test status
Simulation time 108004298 ps
CPU time 0.82 seconds
Started Feb 18 02:58:57 PM PST 24
Finished Feb 18 02:59:16 PM PST 24
Peak memory 196480 kb
Host smart-bb87b4d2-a922-4741-9e9c-d08dabc25116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118276295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1118276295
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1773399947
Short name T443
Test name
Test status
Simulation time 46601351 ps
CPU time 1.03 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:13 PM PST 24
Peak memory 196232 kb
Host smart-2853b095-2788-47db-a0b6-44d28a748de9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773399947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1773399947
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.203044447
Short name T74
Test name
Test status
Simulation time 115199497 ps
CPU time 4.93 seconds
Started Feb 18 02:58:52 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 198424 kb
Host smart-2269e04a-6c63-4f4a-a6ca-9cf4a9846f76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203044447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.203044447
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3088028621
Short name T705
Test name
Test status
Simulation time 93570350 ps
CPU time 1.46 seconds
Started Feb 18 02:58:59 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 197236 kb
Host smart-83c47b2a-4642-4804-abb8-ef17fac35008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088028621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3088028621
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4105450351
Short name T531
Test name
Test status
Simulation time 78785960 ps
CPU time 1.34 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 197220 kb
Host smart-c1bcb647-4874-4358-83b4-57d566ddbaa9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105450351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4105450351
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1533913097
Short name T373
Test name
Test status
Simulation time 13880064200 ps
CPU time 204.11 seconds
Started Feb 18 02:59:02 PM PST 24
Finished Feb 18 03:02:43 PM PST 24
Peak memory 198536 kb
Host smart-95a54a1b-bddb-4475-9577-64adfd28d1bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533913097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1533913097
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3921657153
Short name T608
Test name
Test status
Simulation time 42053010036 ps
CPU time 1336.74 seconds
Started Feb 18 02:58:57 PM PST 24
Finished Feb 18 03:21:32 PM PST 24
Peak memory 198672 kb
Host smart-aaa1031a-8f3e-437b-a35d-c2612506b507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3921657153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3921657153
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3503856868
Short name T394
Test name
Test status
Simulation time 10722893 ps
CPU time 0.6 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:17 PM PST 24
Peak memory 194284 kb
Host smart-9abeb61e-9d5d-45cb-ae3c-9834f6c2cb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503856868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3503856868
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2693482533
Short name T173
Test name
Test status
Simulation time 29628583 ps
CPU time 0.77 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 195612 kb
Host smart-159bfd8d-3bb8-49e8-b742-c0a16e97b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693482533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2693482533
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2553569321
Short name T72
Test name
Test status
Simulation time 1209954334 ps
CPU time 17.55 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:29 PM PST 24
Peak memory 197304 kb
Host smart-cb3a8201-4f8a-477b-99b1-9ee601586004
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553569321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2553569321
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3758519944
Short name T196
Test name
Test status
Simulation time 431888293 ps
CPU time 0.92 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:12 PM PST 24
Peak memory 197004 kb
Host smart-fc4c669e-e867-4cc0-ae8f-b7cf924da9aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758519944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3758519944
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3112264521
Short name T260
Test name
Test status
Simulation time 241656269 ps
CPU time 1.35 seconds
Started Feb 18 02:59:01 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 197284 kb
Host smart-4fd146fc-2012-4098-a547-e3a589aa27d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112264521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3112264521
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.479427970
Short name T514
Test name
Test status
Simulation time 32971200 ps
CPU time 0.9 seconds
Started Feb 18 02:58:50 PM PST 24
Finished Feb 18 02:59:07 PM PST 24
Peak memory 197364 kb
Host smart-27b2d1ec-c600-4d74-b0c0-b40d960e77aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479427970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.479427970
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.497410436
Short name T360
Test name
Test status
Simulation time 99650958 ps
CPU time 1.62 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 197052 kb
Host smart-8f194b63-acb8-4dd4-b982-344ddfcb3095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497410436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
497410436
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1264427209
Short name T204
Test name
Test status
Simulation time 115217659 ps
CPU time 1.28 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 197324 kb
Host smart-f4c0d5df-de80-4d4c-b5b4-a1b39bdd9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264427209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1264427209
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.265116878
Short name T657
Test name
Test status
Simulation time 26453611 ps
CPU time 0.65 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 194672 kb
Host smart-b3df4523-d1cd-488c-bc30-d5108dcd4a92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265116878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.265116878
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1986598013
Short name T9
Test name
Test status
Simulation time 2203993143 ps
CPU time 6.41 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 198524 kb
Host smart-ef939bb0-0dae-4ab2-a07c-0c7715cfedc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986598013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1986598013
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4116870470
Short name T621
Test name
Test status
Simulation time 294294177 ps
CPU time 1.39 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:14 PM PST 24
Peak memory 197172 kb
Host smart-36c7ee0e-dd51-4bf7-b6c2-d80e3b0f2528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116870470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4116870470
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1312164180
Short name T653
Test name
Test status
Simulation time 58612683 ps
CPU time 1.69 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 196944 kb
Host smart-527ac340-c630-4235-830d-633447d2f7d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312164180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1312164180
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3846855790
Short name T137
Test name
Test status
Simulation time 8344498616 ps
CPU time 43.4 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 02:59:57 PM PST 24
Peak memory 198576 kb
Host smart-1159f38e-331a-494f-adc7-5cc1fb5de8b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846855790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3846855790
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1223445377
Short name T365
Test name
Test status
Simulation time 19587560 ps
CPU time 0.58 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 194988 kb
Host smart-1326c2c8-e135-41a3-ae3b-29f105ff7cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223445377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1223445377
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4129041229
Short name T198
Test name
Test status
Simulation time 44208503 ps
CPU time 0.73 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 195240 kb
Host smart-924b7d77-e5c1-47ec-bc0a-232472dbcfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129041229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4129041229
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.466934208
Short name T496
Test name
Test status
Simulation time 439336533 ps
CPU time 7.31 seconds
Started Feb 18 02:59:04 PM PST 24
Finished Feb 18 02:59:29 PM PST 24
Peak memory 197396 kb
Host smart-7afca994-d80a-469e-a6c8-c253857c271b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466934208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.466934208
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2956394873
Short name T404
Test name
Test status
Simulation time 199494816 ps
CPU time 0.82 seconds
Started Feb 18 02:59:02 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 196348 kb
Host smart-6806efbd-0f36-452c-8751-19a181292bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956394873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2956394873
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2974253428
Short name T711
Test name
Test status
Simulation time 71808641 ps
CPU time 1.16 seconds
Started Feb 18 02:59:01 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 196592 kb
Host smart-e91e6748-13d2-41ea-a645-6e2fe08aa8a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974253428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2974253428
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.519130705
Short name T525
Test name
Test status
Simulation time 551046134 ps
CPU time 3.7 seconds
Started Feb 18 02:59:02 PM PST 24
Finished Feb 18 02:59:23 PM PST 24
Peak memory 198520 kb
Host smart-c2914c27-c24c-4d67-a0ac-ca3be0a14e8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519130705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.519130705
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3488957641
Short name T207
Test name
Test status
Simulation time 390883602 ps
CPU time 1.56 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 196904 kb
Host smart-b11e030e-9603-4e87-908e-413e3c02a803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488957641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3488957641
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1493377777
Short name T397
Test name
Test status
Simulation time 123137356 ps
CPU time 1.37 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 198480 kb
Host smart-337777a7-3194-48b7-be8f-b619fabc6708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493377777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1493377777
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3210648612
Short name T576
Test name
Test status
Simulation time 140445914 ps
CPU time 0.92 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:12 PM PST 24
Peak memory 197140 kb
Host smart-a0bd8691-108b-4bc2-97a4-0f7120254902
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210648612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3210648612
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.345911520
Short name T574
Test name
Test status
Simulation time 1255548440 ps
CPU time 5.9 seconds
Started Feb 18 02:58:55 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 198468 kb
Host smart-2017b66a-e807-41b8-bacf-75ba6b5d5404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345911520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.345911520
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4113869729
Short name T58
Test name
Test status
Simulation time 40386941 ps
CPU time 1.22 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 195908 kb
Host smart-156acf52-876b-42ab-ba01-03137746441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113869729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4113869729
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3543544844
Short name T315
Test name
Test status
Simulation time 37092624 ps
CPU time 0.94 seconds
Started Feb 18 02:58:54 PM PST 24
Finished Feb 18 02:59:12 PM PST 24
Peak memory 196208 kb
Host smart-fa8ce58e-cb3b-4b3b-baf9-30a1922b3ad0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543544844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3543544844
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.174879788
Short name T675
Test name
Test status
Simulation time 44471813259 ps
CPU time 88.09 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 03:00:42 PM PST 24
Peak memory 198476 kb
Host smart-6f025847-bbec-4995-ae61-28d3b4402f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174879788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.174879788
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3806068502
Short name T668
Test name
Test status
Simulation time 22872816 ps
CPU time 0.56 seconds
Started Feb 18 02:59:03 PM PST 24
Finished Feb 18 02:59:22 PM PST 24
Peak memory 194260 kb
Host smart-e2154d6b-7fbe-4379-b52a-19634a9e7d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806068502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3806068502
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3209975487
Short name T541
Test name
Test status
Simulation time 26005489 ps
CPU time 0.71 seconds
Started Feb 18 02:59:03 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 195580 kb
Host smart-2e6a9227-271a-4216-885f-955b573041e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209975487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3209975487
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1533081618
Short name T713
Test name
Test status
Simulation time 505455132 ps
CPU time 26.09 seconds
Started Feb 18 02:58:57 PM PST 24
Finished Feb 18 02:59:41 PM PST 24
Peak memory 197312 kb
Host smart-ac5dbf6b-af98-4394-b0e8-b44acdf7d7ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533081618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1533081618
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1476923182
Short name T592
Test name
Test status
Simulation time 26573327 ps
CPU time 0.64 seconds
Started Feb 18 02:59:03 PM PST 24
Finished Feb 18 02:59:21 PM PST 24
Peak memory 194928 kb
Host smart-a6fe6c44-f361-4841-b4d0-4af6836621c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476923182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1476923182
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3933135983
Short name T498
Test name
Test status
Simulation time 175974590 ps
CPU time 1.47 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 198508 kb
Host smart-8e02a859-5bc6-41e4-b126-72b0a0491836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933135983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3933135983
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1027411109
Short name T314
Test name
Test status
Simulation time 311923999 ps
CPU time 3.63 seconds
Started Feb 18 02:58:58 PM PST 24
Finished Feb 18 02:59:20 PM PST 24
Peak memory 198428 kb
Host smart-a62d40de-74b0-44a9-83c1-f1e7acd7fa0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027411109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1027411109
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2526384279
Short name T687
Test name
Test status
Simulation time 456466379 ps
CPU time 3.43 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 198480 kb
Host smart-bd193185-ad09-466b-bb09-78c27750aa94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526384279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2526384279
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1067940905
Short name T435
Test name
Test status
Simulation time 206985535 ps
CPU time 1.28 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 02:59:15 PM PST 24
Peak memory 197404 kb
Host smart-84fe3ee5-6d70-445f-8934-6fed38141c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067940905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1067940905
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3738539558
Short name T14
Test name
Test status
Simulation time 48021014 ps
CPU time 1.16 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 02:59:16 PM PST 24
Peak memory 197172 kb
Host smart-7efe3c73-d813-4206-bbbb-825bd137c2d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738539558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3738539558
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2259294756
Short name T352
Test name
Test status
Simulation time 558961049 ps
CPU time 5.35 seconds
Started Feb 18 02:59:00 PM PST 24
Finished Feb 18 02:59:22 PM PST 24
Peak memory 198412 kb
Host smart-b370f5ee-1db6-4477-a16a-1a2b1836ebb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259294756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2259294756
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.181932512
Short name T280
Test name
Test status
Simulation time 41756291 ps
CPU time 1.13 seconds
Started Feb 18 02:59:01 PM PST 24
Finished Feb 18 02:59:19 PM PST 24
Peak memory 196156 kb
Host smart-02d82a89-d236-402f-8f99-3227c447ac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181932512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.181932512
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2045690341
Short name T674
Test name
Test status
Simulation time 522077973 ps
CPU time 1.21 seconds
Started Feb 18 02:58:59 PM PST 24
Finished Feb 18 02:59:18 PM PST 24
Peak memory 197184 kb
Host smart-edc4586e-f315-470f-b71a-cac36c1657be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045690341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2045690341
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3695988481
Short name T1
Test name
Test status
Simulation time 21198640627 ps
CPU time 84.14 seconds
Started Feb 18 02:58:56 PM PST 24
Finished Feb 18 03:00:38 PM PST 24
Peak memory 198556 kb
Host smart-21ad7e28-3ecf-49e5-b70f-f39443bef629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695988481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3695988481
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.954079688
Short name T81
Test name
Test status
Simulation time 119561859737 ps
CPU time 1407.01 seconds
Started Feb 18 02:59:01 PM PST 24
Finished Feb 18 03:22:45 PM PST 24
Peak memory 198728 kb
Host smart-00f3e4ab-4fa4-4407-9f8f-5febc2a69f76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=954079688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.954079688
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2773682872
Short name T437
Test name
Test status
Simulation time 21885460 ps
CPU time 0.64 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 02:56:23 PM PST 24
Peak memory 195184 kb
Host smart-1ebefd39-3570-4584-9e75-39a906f40f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773682872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2773682872
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3284318953
Short name T135
Test name
Test status
Simulation time 138014899 ps
CPU time 0.65 seconds
Started Feb 18 02:56:14 PM PST 24
Finished Feb 18 02:56:16 PM PST 24
Peak memory 195148 kb
Host smart-8722065f-5d0e-414c-a868-e73ad3dc6082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284318953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3284318953
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1931839513
Short name T357
Test name
Test status
Simulation time 291971076 ps
CPU time 8.13 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 02:56:31 PM PST 24
Peak memory 197336 kb
Host smart-b3fa6840-44cb-45c7-abe0-84ab32fd712d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931839513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1931839513
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.231117036
Short name T342
Test name
Test status
Simulation time 101782837 ps
CPU time 1.11 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 196828 kb
Host smart-6f886345-4d2d-49a8-a5c4-1840283815bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231117036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.231117036
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1561333320
Short name T434
Test name
Test status
Simulation time 154542149 ps
CPU time 1.03 seconds
Started Feb 18 02:56:15 PM PST 24
Finished Feb 18 02:56:17 PM PST 24
Peak memory 196228 kb
Host smart-997934c5-2184-4b27-bd33-a88f228424b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561333320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1561333320
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1539360226
Short name T677
Test name
Test status
Simulation time 314271854 ps
CPU time 2.1 seconds
Started Feb 18 02:56:21 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 198468 kb
Host smart-707ef0ee-ef6a-4251-97d7-e58b043a02a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539360226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1539360226
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.448276897
Short name T192
Test name
Test status
Simulation time 340662980 ps
CPU time 2.56 seconds
Started Feb 18 02:56:17 PM PST 24
Finished Feb 18 02:56:23 PM PST 24
Peak memory 196288 kb
Host smart-b511a754-49e5-4040-912f-3e72ea0bf09d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448276897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.448276897
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3141172390
Short name T23
Test name
Test status
Simulation time 23284538 ps
CPU time 0.65 seconds
Started Feb 18 02:56:21 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 194720 kb
Host smart-4b81c2e2-7f43-4633-adf8-ad269ff1a949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141172390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3141172390
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3638578116
Short name T252
Test name
Test status
Simulation time 483784429 ps
CPU time 1.4 seconds
Started Feb 18 02:56:15 PM PST 24
Finished Feb 18 02:56:19 PM PST 24
Peak memory 197552 kb
Host smart-0c11f4dd-fa97-4298-ab4e-33b34235a569
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638578116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3638578116
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.204525862
Short name T468
Test name
Test status
Simulation time 523920058 ps
CPU time 4.74 seconds
Started Feb 18 02:56:23 PM PST 24
Finished Feb 18 02:56:32 PM PST 24
Peak memory 198408 kb
Host smart-d1eb60dd-c54d-44d4-b1f0-40560e3a6c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204525862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.204525862
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1859244524
Short name T330
Test name
Test status
Simulation time 161667848 ps
CPU time 1.15 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 195960 kb
Host smart-47f48c9a-d1d7-4a4e-8898-c554ab4e0366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859244524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1859244524
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3210408043
Short name T312
Test name
Test status
Simulation time 60855447 ps
CPU time 1.21 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 02:56:25 PM PST 24
Peak memory 198416 kb
Host smart-ccdfa94d-efa7-44c7-8312-a1792cc8714b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210408043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3210408043
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3753714780
Short name T669
Test name
Test status
Simulation time 2285613964 ps
CPU time 30.91 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:58 PM PST 24
Peak memory 198612 kb
Host smart-872c92be-64cb-46d6-865a-54e4d32cf043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753714780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3753714780
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1565355988
Short name T715
Test name
Test status
Simulation time 11412325 ps
CPU time 0.59 seconds
Started Feb 18 02:56:26 PM PST 24
Finished Feb 18 02:56:31 PM PST 24
Peak memory 194280 kb
Host smart-a672490e-dc64-4e61-9e46-e2afba6d5040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565355988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1565355988
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2293236977
Short name T339
Test name
Test status
Simulation time 28240029 ps
CPU time 0.63 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 02:56:24 PM PST 24
Peak memory 194284 kb
Host smart-c6ce902e-3a12-4c5c-9938-050bca388ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293236977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2293236977
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1341060856
Short name T197
Test name
Test status
Simulation time 1299532750 ps
CPU time 8.44 seconds
Started Feb 18 02:56:38 PM PST 24
Finished Feb 18 02:56:50 PM PST 24
Peak memory 198400 kb
Host smart-e7b2af5a-1d7c-4c3e-9292-64dca53d8102
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341060856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1341060856
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2971096625
Short name T494
Test name
Test status
Simulation time 111362477 ps
CPU time 0.69 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:39 PM PST 24
Peak memory 195100 kb
Host smart-412b6881-2d21-44dd-907a-53bc1f6f2152
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971096625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2971096625
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4072238491
Short name T431
Test name
Test status
Simulation time 49498503 ps
CPU time 0.69 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:27 PM PST 24
Peak memory 194880 kb
Host smart-d8e5241e-56c0-45a1-8c03-554c752d0fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072238491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4072238491
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3941410909
Short name T589
Test name
Test status
Simulation time 226734022 ps
CPU time 1.84 seconds
Started Feb 18 02:56:35 PM PST 24
Finished Feb 18 02:56:41 PM PST 24
Peak memory 197168 kb
Host smart-eace7544-ffeb-42e3-83d2-185819d3bf2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941410909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3941410909
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3090086928
Short name T371
Test name
Test status
Simulation time 158850033 ps
CPU time 3.28 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:41 PM PST 24
Peak memory 197612 kb
Host smart-85557e02-42c3-4315-9276-fff373db010e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090086928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3090086928
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3111097260
Short name T436
Test name
Test status
Simulation time 90234569 ps
CPU time 1.11 seconds
Started Feb 18 02:56:21 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 197096 kb
Host smart-dc0400ef-64bf-4632-8a04-ab44f72bb0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111097260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3111097260
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.911305215
Short name T386
Test name
Test status
Simulation time 33661080 ps
CPU time 1.26 seconds
Started Feb 18 02:56:20 PM PST 24
Finished Feb 18 02:56:26 PM PST 24
Peak memory 197512 kb
Host smart-f31a2345-4e79-44f2-8d29-172ff063ddd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911305215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.911305215
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.306689750
Short name T350
Test name
Test status
Simulation time 275533545 ps
CPU time 1.95 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 198416 kb
Host smart-c23248d6-a9a9-4765-b628-2f6d7d326048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306689750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.306689750
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.478355333
Short name T479
Test name
Test status
Simulation time 49134627 ps
CPU time 1.22 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:28 PM PST 24
Peak memory 196236 kb
Host smart-68ad8990-d7eb-4d0c-969b-76563d5f223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478355333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.478355333
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.837000489
Short name T271
Test name
Test status
Simulation time 267482429 ps
CPU time 1.17 seconds
Started Feb 18 02:56:22 PM PST 24
Finished Feb 18 02:56:28 PM PST 24
Peak memory 196096 kb
Host smart-7a189eee-c372-4b69-a5f5-81d74c5f9776
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837000489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.837000489
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1703084988
Short name T470
Test name
Test status
Simulation time 55643313725 ps
CPU time 169.66 seconds
Started Feb 18 02:56:31 PM PST 24
Finished Feb 18 02:59:24 PM PST 24
Peak memory 198508 kb
Host smart-62f21dea-381f-4581-bf35-aabfd844748c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703084988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1703084988
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1318672052
Short name T279
Test name
Test status
Simulation time 24463124 ps
CPU time 0.57 seconds
Started Feb 18 02:56:36 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 194984 kb
Host smart-79b274a4-0ee0-4361-b27a-f5de8dfea6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318672052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1318672052
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1234077629
Short name T168
Test name
Test status
Simulation time 198225589 ps
CPU time 0.77 seconds
Started Feb 18 02:56:25 PM PST 24
Finished Feb 18 02:56:31 PM PST 24
Peak memory 195688 kb
Host smart-2d1ccbc0-910c-4fb3-ace3-6809dc267f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234077629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1234077629
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2177223611
Short name T265
Test name
Test status
Simulation time 968209826 ps
CPU time 24.24 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:57:04 PM PST 24
Peak memory 196004 kb
Host smart-7298d5ec-031e-47ca-8c43-f06839903bd8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177223611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2177223611
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.389074894
Short name T617
Test name
Test status
Simulation time 61821780 ps
CPU time 0.7 seconds
Started Feb 18 02:56:32 PM PST 24
Finished Feb 18 02:56:36 PM PST 24
Peak memory 195176 kb
Host smart-4629fb4d-b4ae-43a0-b805-44d907414f7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389074894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.389074894
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.494507101
Short name T218
Test name
Test status
Simulation time 129884143 ps
CPU time 1.28 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 196380 kb
Host smart-00fdcb83-cb1f-413c-856b-aa10b087fa33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494507101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.494507101
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2260243079
Short name T213
Test name
Test status
Simulation time 79093632 ps
CPU time 3.29 seconds
Started Feb 18 02:56:38 PM PST 24
Finished Feb 18 02:56:44 PM PST 24
Peak memory 198560 kb
Host smart-67ee3cdd-c90c-4f53-8347-e89887b75132
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260243079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2260243079
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4068394818
Short name T164
Test name
Test status
Simulation time 87384764 ps
CPU time 1.98 seconds
Started Feb 18 02:56:36 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 196404 kb
Host smart-7ae98e5b-0301-4e9e-950a-5ea0ee63b4b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068394818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4068394818
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2527403086
Short name T518
Test name
Test status
Simulation time 58412781 ps
CPU time 0.77 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:37 PM PST 24
Peak memory 195960 kb
Host smart-0a422a34-4287-4290-b150-4b20981f1476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527403086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2527403086
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1784570166
Short name T76
Test name
Test status
Simulation time 153230791 ps
CPU time 1 seconds
Started Feb 18 02:56:30 PM PST 24
Finished Feb 18 02:56:33 PM PST 24
Peak memory 197152 kb
Host smart-a85b4d3f-bbc9-42c4-b7f2-98c82227e685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784570166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1784570166
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.93977648
Short name T298
Test name
Test status
Simulation time 1008473671 ps
CPU time 2.95 seconds
Started Feb 18 02:56:35 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 198460 kb
Host smart-d9635b2a-711d-4481-a7a4-59352e77efd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93977648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rando
m_long_reg_writes_reg_reads.93977648
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2807306818
Short name T225
Test name
Test status
Simulation time 180609220 ps
CPU time 1.15 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 196616 kb
Host smart-4a99d187-b8aa-44ff-aa58-51bbdd0fd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807306818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2807306818
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3164418904
Short name T32
Test name
Test status
Simulation time 112720926 ps
CPU time 0.95 seconds
Started Feb 18 02:56:30 PM PST 24
Finished Feb 18 02:56:34 PM PST 24
Peak memory 195956 kb
Host smart-906a8d26-1d22-4d2c-9fd8-be8b658c74ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164418904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3164418904
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.234722876
Short name T686
Test name
Test status
Simulation time 58879487818 ps
CPU time 215.72 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 03:00:12 PM PST 24
Peak memory 198588 kb
Host smart-bbd7453a-950a-45d1-af1c-e57ca84c919b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234722876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.234722876
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2483694114
Short name T65
Test name
Test status
Simulation time 182793155996 ps
CPU time 715.92 seconds
Started Feb 18 02:56:31 PM PST 24
Finished Feb 18 03:08:30 PM PST 24
Peak memory 198676 kb
Host smart-81c350a5-d020-4a5a-931b-e5e08d4cfb17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2483694114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2483694114
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.663749042
Short name T16
Test name
Test status
Simulation time 81782512 ps
CPU time 0.58 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:39 PM PST 24
Peak memory 194296 kb
Host smart-da560370-8b88-49ec-85be-f36def41cf8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663749042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.663749042
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.876176874
Short name T548
Test name
Test status
Simulation time 102071997 ps
CPU time 0.86 seconds
Started Feb 18 02:56:38 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 196920 kb
Host smart-965b8119-b119-47d2-85b0-4d012e4074d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876176874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.876176874
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1201337423
Short name T212
Test name
Test status
Simulation time 2012915801 ps
CPU time 18.05 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:57 PM PST 24
Peak memory 198472 kb
Host smart-488ae49d-d468-41ea-af11-b6a6cb3d2263
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201337423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1201337423
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3491746147
Short name T304
Test name
Test status
Simulation time 58845038 ps
CPU time 0.72 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 195820 kb
Host smart-243bbd19-841a-41e1-acb3-71f783411710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491746147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3491746147
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3706226766
Short name T633
Test name
Test status
Simulation time 67212952 ps
CPU time 0.85 seconds
Started Feb 18 02:56:32 PM PST 24
Finished Feb 18 02:56:35 PM PST 24
Peak memory 196592 kb
Host smart-8969b9b5-c4a9-40da-8623-0ae3c2c4be84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706226766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3706226766
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2736732220
Short name T624
Test name
Test status
Simulation time 694654114 ps
CPU time 2.37 seconds
Started Feb 18 02:56:31 PM PST 24
Finished Feb 18 02:56:37 PM PST 24
Peak memory 198452 kb
Host smart-bb99ae61-7da1-4e48-8442-00ba1db241b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736732220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2736732220
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4278795371
Short name T25
Test name
Test status
Simulation time 225948780 ps
CPU time 1.42 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:56:42 PM PST 24
Peak memory 197336 kb
Host smart-39f8f7ab-6fdc-4da3-b3c8-4d8048c7905e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278795371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4278795371
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.246789283
Short name T542
Test name
Test status
Simulation time 349710594 ps
CPU time 0.71 seconds
Started Feb 18 02:56:35 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 195932 kb
Host smart-a5c2a685-fccd-42d0-8e5d-434be555e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246789283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.246789283
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2622042069
Short name T564
Test name
Test status
Simulation time 50024648 ps
CPU time 1.19 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 196272 kb
Host smart-69240b82-8e2e-4127-b260-593cc8ffd04d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622042069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2622042069
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1807066490
Short name T427
Test name
Test status
Simulation time 310179319 ps
CPU time 2.83 seconds
Started Feb 18 02:56:34 PM PST 24
Finished Feb 18 02:56:41 PM PST 24
Peak memory 198240 kb
Host smart-38a22a7f-ea6c-4ecd-80ea-75311a180516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807066490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1807066490
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.344986611
Short name T647
Test name
Test status
Simulation time 373580387 ps
CPU time 0.89 seconds
Started Feb 18 02:56:36 PM PST 24
Finished Feb 18 02:56:40 PM PST 24
Peak memory 196104 kb
Host smart-39c9d1cd-b71d-425f-b223-b314f74febb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344986611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.344986611
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.4094619573
Short name T480
Test name
Test status
Simulation time 45300358 ps
CPU time 1.17 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:37 PM PST 24
Peak memory 196216 kb
Host smart-aea605ab-831a-4c19-a530-bad20feaa8e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094619573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.4094619573
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1216240040
Short name T604
Test name
Test status
Simulation time 18371952647 ps
CPU time 118.81 seconds
Started Feb 18 02:56:31 PM PST 24
Finished Feb 18 02:58:33 PM PST 24
Peak memory 198556 kb
Host smart-04155724-79b8-4c62-aa42-1a69b2a8fe79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216240040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1216240040
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2979948119
Short name T579
Test name
Test status
Simulation time 43279101 ps
CPU time 0.59 seconds
Started Feb 18 02:56:41 PM PST 24
Finished Feb 18 02:56:47 PM PST 24
Peak memory 194284 kb
Host smart-91a22493-ada1-4b8d-ba1f-cbaf19aa5041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979948119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2979948119
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3961642354
Short name T369
Test name
Test status
Simulation time 130348375 ps
CPU time 0.94 seconds
Started Feb 18 02:56:35 PM PST 24
Finished Feb 18 02:56:39 PM PST 24
Peak memory 196924 kb
Host smart-151ace8a-31f1-499c-839c-dca11124ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961642354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3961642354
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1663976015
Short name T131
Test name
Test status
Simulation time 1920303724 ps
CPU time 17.29 seconds
Started Feb 18 02:56:44 PM PST 24
Finished Feb 18 02:57:05 PM PST 24
Peak memory 195960 kb
Host smart-20e0f942-56ca-484e-9aa7-32a0f18e3c50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663976015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1663976015
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2148015889
Short name T598
Test name
Test status
Simulation time 63587249 ps
CPU time 0.95 seconds
Started Feb 18 02:56:41 PM PST 24
Finished Feb 18 02:56:46 PM PST 24
Peak memory 198112 kb
Host smart-f8bdb397-7284-411c-a1f2-1395d75e5abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148015889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2148015889
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3531407239
Short name T240
Test name
Test status
Simulation time 108989897 ps
CPU time 1.57 seconds
Started Feb 18 02:56:41 PM PST 24
Finished Feb 18 02:56:48 PM PST 24
Peak memory 197404 kb
Host smart-c3823c3e-2491-47c3-a6a4-8b7009367282
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531407239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3531407239
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.15976620
Short name T376
Test name
Test status
Simulation time 34819766 ps
CPU time 1.51 seconds
Started Feb 18 02:56:39 PM PST 24
Finished Feb 18 02:56:45 PM PST 24
Peak memory 197224 kb
Host smart-6fb97140-ee1a-46ef-828a-8cb03bd89580
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15976620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.gpio_intr_with_filter_rand_intr_event.15976620
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3143681115
Short name T125
Test name
Test status
Simulation time 83146835 ps
CPU time 1.89 seconds
Started Feb 18 02:56:41 PM PST 24
Finished Feb 18 02:56:48 PM PST 24
Peak memory 197280 kb
Host smart-207b0a33-5ced-4f44-b5e3-6312b53f28e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143681115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3143681115
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.613684100
Short name T661
Test name
Test status
Simulation time 60114589 ps
CPU time 1.18 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 196236 kb
Host smart-aea841b4-f742-4596-95ea-268f58e96907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613684100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.613684100
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.104655755
Short name T31
Test name
Test status
Simulation time 111937133 ps
CPU time 1.05 seconds
Started Feb 18 02:56:32 PM PST 24
Finished Feb 18 02:56:37 PM PST 24
Peak memory 196556 kb
Host smart-ecd01d8a-0618-4a54-a636-289aa1044b59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104655755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.104655755
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.901375269
Short name T607
Test name
Test status
Simulation time 1410309533 ps
CPU time 6.69 seconds
Started Feb 18 02:56:37 PM PST 24
Finished Feb 18 02:56:47 PM PST 24
Peak memory 198524 kb
Host smart-c027381e-202d-4df9-b508-f740eab184b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901375269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.901375269
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1387622477
Short name T700
Test name
Test status
Simulation time 63229163 ps
CPU time 1.01 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 195980 kb
Host smart-c3cbd4e5-a8f9-473b-85ef-ce7bf25f5f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387622477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1387622477
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.673949401
Short name T714
Test name
Test status
Simulation time 781878895 ps
CPU time 1.24 seconds
Started Feb 18 02:56:33 PM PST 24
Finished Feb 18 02:56:38 PM PST 24
Peak memory 196652 kb
Host smart-9f78c130-bb39-444f-bbca-309234d705f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673949401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.673949401
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.4204291631
Short name T79
Test name
Test status
Simulation time 34494777762 ps
CPU time 84.45 seconds
Started Feb 18 02:56:40 PM PST 24
Finished Feb 18 02:58:09 PM PST 24
Peak memory 198568 kb
Host smart-1004c5dc-97cf-43c9-a716-966d6ec279a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204291631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.4204291631
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3541915983
Short name T903
Test name
Test status
Simulation time 291653530 ps
CPU time 1.47 seconds
Started Feb 18 01:55:31 PM PST 24
Finished Feb 18 01:55:36 PM PST 24
Peak memory 196784 kb
Host smart-50da1135-96c8-4c4b-95ed-135881e99adb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3541915983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3541915983
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2296896895
Short name T873
Test name
Test status
Simulation time 35867997 ps
CPU time 1.08 seconds
Started Feb 18 01:55:26 PM PST 24
Finished Feb 18 01:55:30 PM PST 24
Peak memory 197192 kb
Host smart-ab67f265-b51a-4603-8eb1-fdd1d0ec8119
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296896895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2296896895
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1582269162
Short name T849
Test name
Test status
Simulation time 116337740 ps
CPU time 1.07 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:38 PM PST 24
Peak memory 195948 kb
Host smart-be914430-600c-42eb-9f22-1131bde4e78e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1582269162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1582269162
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1970449895
Short name T906
Test name
Test status
Simulation time 1021056438 ps
CPU time 1.22 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 197012 kb
Host smart-73098bb5-ee29-4b75-b1dc-6cfa66de48c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970449895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1970449895
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1149213573
Short name T938
Test name
Test status
Simulation time 164506342 ps
CPU time 1.21 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 195988 kb
Host smart-c2bb8b09-c15b-4070-9a76-4e4727f19456
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1149213573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1149213573
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3961120951
Short name T936
Test name
Test status
Simulation time 242326235 ps
CPU time 1 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 195904 kb
Host smart-51c28df8-b864-4185-bc3d-6a71dac06b4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961120951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3961120951
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3496899625
Short name T900
Test name
Test status
Simulation time 134116771 ps
CPU time 1.06 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 197200 kb
Host smart-568f0a78-621c-4999-82ac-81f3b41f8863
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3496899625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3496899625
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4046442717
Short name T905
Test name
Test status
Simulation time 256201118 ps
CPU time 1.21 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:38 PM PST 24
Peak memory 196920 kb
Host smart-8af43de1-4ecd-439c-bd70-cc4bb0396afc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046442717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4046442717
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1924814945
Short name T866
Test name
Test status
Simulation time 403353219 ps
CPU time 1.06 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 196732 kb
Host smart-fd1ec6dd-1a9b-416d-874c-831de92e82ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1924814945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1924814945
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2118041617
Short name T892
Test name
Test status
Simulation time 33909793 ps
CPU time 0.82 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 196408 kb
Host smart-c316d9ff-d34c-461f-951e-9a60f69ae21f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118041617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2118041617
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.4026119668
Short name T922
Test name
Test status
Simulation time 611073261 ps
CPU time 1.46 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 197200 kb
Host smart-1997f964-b7bb-4fbd-8bf2-0ad74dbec06e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4026119668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.4026119668
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2383464439
Short name T940
Test name
Test status
Simulation time 33948675 ps
CPU time 1.04 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:36 PM PST 24
Peak memory 196984 kb
Host smart-73f5dad4-f3da-4280-8fed-6a30f0108916
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383464439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2383464439
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1531706286
Short name T909
Test name
Test status
Simulation time 427581981 ps
CPU time 1.5 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 196020 kb
Host smart-72f62614-1829-455d-81ea-0e0a5c3be962
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1531706286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1531706286
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2017449644
Short name T888
Test name
Test status
Simulation time 43863027 ps
CPU time 1.21 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 197148 kb
Host smart-6d1319f2-d756-4fd9-b002-39425a99c141
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017449644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2017449644
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2513387683
Short name T911
Test name
Test status
Simulation time 269019108 ps
CPU time 1.37 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:38 PM PST 24
Peak memory 197084 kb
Host smart-90795128-f402-47f1-bca0-7642cbe6753a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2513387683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2513387683
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3151818770
Short name T935
Test name
Test status
Simulation time 108970067 ps
CPU time 0.96 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 196852 kb
Host smart-5887af51-2919-46aa-87fc-301eb41a911a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151818770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3151818770
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2122094785
Short name T916
Test name
Test status
Simulation time 50275875 ps
CPU time 0.76 seconds
Started Feb 18 01:55:30 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 195644 kb
Host smart-23412fb8-c4c6-4fa7-ae6a-36b9a5e9d657
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2122094785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2122094785
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1448927448
Short name T889
Test name
Test status
Simulation time 90261720 ps
CPU time 1.32 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 198408 kb
Host smart-a7cd83a1-ec49-44c6-9de8-f66183c6677a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448927448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1448927448
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1345144813
Short name T890
Test name
Test status
Simulation time 209482483 ps
CPU time 1.05 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 198324 kb
Host smart-076d7de8-c5c4-4f6e-89e2-5b101e91cf9b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1345144813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1345144813
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2119094214
Short name T913
Test name
Test status
Simulation time 444082026 ps
CPU time 1.35 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 197316 kb
Host smart-2d5c4212-e807-4593-95ed-ea9c296e100c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119094214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2119094214
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2315328476
Short name T879
Test name
Test status
Simulation time 69313887 ps
CPU time 0.83 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 195396 kb
Host smart-5c49b160-fbb3-4ffa-b93e-c39d5bf37d21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2315328476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2315328476
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.807509985
Short name T923
Test name
Test status
Simulation time 79420836 ps
CPU time 1.18 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 196836 kb
Host smart-fc8fa72f-7f21-41ed-b8d4-745b297c04fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807509985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.807509985
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2871019478
Short name T893
Test name
Test status
Simulation time 145627348 ps
CPU time 1.27 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 196992 kb
Host smart-28551cac-6a2d-4a34-b3e3-7385d331fb21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2871019478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2871019478
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3157993697
Short name T855
Test name
Test status
Simulation time 54232824 ps
CPU time 1.46 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 197180 kb
Host smart-7236654f-c062-4f8a-873f-0123422c88d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157993697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3157993697
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4047876252
Short name T853
Test name
Test status
Simulation time 261861837 ps
CPU time 1.14 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 196844 kb
Host smart-037f5f06-6232-4a64-ba61-457e1a4fe71c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4047876252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4047876252
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.228872408
Short name T875
Test name
Test status
Simulation time 44963827 ps
CPU time 0.95 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 196012 kb
Host smart-299ba23c-f2c7-4403-9dd1-015cf7487c69
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228872408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.228872408
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1829280667
Short name T895
Test name
Test status
Simulation time 136089385 ps
CPU time 1.3 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 197120 kb
Host smart-701fe276-c616-4f7a-9311-b1e82486e5f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1829280667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1829280667
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1087767401
Short name T925
Test name
Test status
Simulation time 1235385783 ps
CPU time 1.17 seconds
Started Feb 18 01:55:36 PM PST 24
Finished Feb 18 01:55:43 PM PST 24
Peak memory 197020 kb
Host smart-6f4ab67c-332f-4ab9-b643-f7a1fd5ff732
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087767401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1087767401
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1146745421
Short name T937
Test name
Test status
Simulation time 357147575 ps
CPU time 1.57 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 197252 kb
Host smart-3972f733-e200-4258-98bb-5896e78a1a2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1146745421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1146745421
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387117271
Short name T878
Test name
Test status
Simulation time 42811876 ps
CPU time 1.31 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 196344 kb
Host smart-eed26742-1861-488f-a8ff-b20a8a91a892
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387117271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.387117271
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2518305911
Short name T946
Test name
Test status
Simulation time 42610689 ps
CPU time 1.31 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:38 PM PST 24
Peak memory 198068 kb
Host smart-268ad812-32f4-405f-bf1b-9dfcb4017a3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2518305911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2518305911
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476566257
Short name T891
Test name
Test status
Simulation time 54733369 ps
CPU time 1.14 seconds
Started Feb 18 01:55:36 PM PST 24
Finished Feb 18 01:55:43 PM PST 24
Peak memory 196800 kb
Host smart-5811d525-1757-49ff-917e-e09314809ebe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476566257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3476566257
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.182865695
Short name T887
Test name
Test status
Simulation time 80985131 ps
CPU time 1.63 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 198384 kb
Host smart-3f0a09f0-6b4a-4b5a-8f68-a468bf0fcf23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=182865695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.182865695
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1978297627
Short name T931
Test name
Test status
Simulation time 515772216 ps
CPU time 1.4 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 196688 kb
Host smart-c5d205b6-6b69-4207-8a71-51c178ce0460
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978297627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1978297627
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1060543222
Short name T867
Test name
Test status
Simulation time 145333844 ps
CPU time 1.45 seconds
Started Feb 18 01:55:31 PM PST 24
Finished Feb 18 01:55:35 PM PST 24
Peak memory 196748 kb
Host smart-159bfc5c-e468-4160-b4c4-87137186eb13
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1060543222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1060543222
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3627717127
Short name T907
Test name
Test status
Simulation time 456121902 ps
CPU time 1.16 seconds
Started Feb 18 01:55:41 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 197000 kb
Host smart-c551a6c6-ba69-4749-b788-9770fb1220b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627717127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3627717127
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1283354113
Short name T926
Test name
Test status
Simulation time 64837763 ps
CPU time 1.17 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 196020 kb
Host smart-7892db2c-9ce5-42a8-8611-a95098f2ef21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1283354113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1283354113
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373408680
Short name T852
Test name
Test status
Simulation time 107584743 ps
CPU time 1.33 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 197192 kb
Host smart-4dfe1a09-4d9d-48b0-ad17-1039356050dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373408680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3373408680
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2587736412
Short name T921
Test name
Test status
Simulation time 123390211 ps
CPU time 0.82 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:43 PM PST 24
Peak memory 195492 kb
Host smart-a8fa9c0f-805e-4269-b99e-c18a8a2f59b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2587736412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2587736412
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2253772324
Short name T927
Test name
Test status
Simulation time 72690451 ps
CPU time 1.12 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 197060 kb
Host smart-afb90513-8440-4e7d-b518-58751b1d67a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253772324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2253772324
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1093876160
Short name T939
Test name
Test status
Simulation time 81408097 ps
CPU time 0.95 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 196844 kb
Host smart-d8acf293-98cf-4e28-8266-fd31f7e6b54b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1093876160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1093876160
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3416664158
Short name T944
Test name
Test status
Simulation time 58656133 ps
CPU time 1.09 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 197076 kb
Host smart-74916555-eabe-4851-8d69-c1a9ccc498e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416664158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3416664158
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.880626704
Short name T912
Test name
Test status
Simulation time 44640566 ps
CPU time 1.08 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 197036 kb
Host smart-93a6a77d-5b2c-4a2e-a38b-376691576c77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=880626704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.880626704
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114894783
Short name T854
Test name
Test status
Simulation time 138550985 ps
CPU time 1.41 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 198436 kb
Host smart-c23f4d5d-d5d1-43d7-91d0-a3c5b3cd262b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114894783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1114894783
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.183764141
Short name T915
Test name
Test status
Simulation time 39431969 ps
CPU time 1.26 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 198412 kb
Host smart-971df566-7a63-443a-9ba1-7484ee37c37b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=183764141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.183764141
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123559190
Short name T886
Test name
Test status
Simulation time 253220973 ps
CPU time 1.18 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 198400 kb
Host smart-29f53c97-0722-4382-a4ca-3c7106b00a1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123559190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2123559190
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1749431784
Short name T928
Test name
Test status
Simulation time 85840523 ps
CPU time 0.87 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 197688 kb
Host smart-a3e18f9d-25fb-4b96-8b1e-cd4d3976c3ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1749431784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1749431784
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.481445776
Short name T894
Test name
Test status
Simulation time 34478645 ps
CPU time 0.97 seconds
Started Feb 18 01:55:32 PM PST 24
Finished Feb 18 01:55:36 PM PST 24
Peak memory 196728 kb
Host smart-118a3d4b-dad8-45cd-a0f0-097117886bcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481445776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.481445776
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4149173622
Short name T929
Test name
Test status
Simulation time 163349738 ps
CPU time 1.01 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 196828 kb
Host smart-40d1e7b4-f599-4975-a73a-be57fef513bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4149173622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4149173622
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1785871925
Short name T945
Test name
Test status
Simulation time 64478203 ps
CPU time 0.96 seconds
Started Feb 18 01:55:36 PM PST 24
Finished Feb 18 01:55:43 PM PST 24
Peak memory 198236 kb
Host smart-91825a5c-f89d-4245-92ed-0cfeb7119363
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785871925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1785871925
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4222564263
Short name T897
Test name
Test status
Simulation time 124208895 ps
CPU time 1.33 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 197188 kb
Host smart-dfbedeb0-20fe-4796-aa61-21ecd3969161
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4222564263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4222564263
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.854923627
Short name T947
Test name
Test status
Simulation time 82624302 ps
CPU time 1.27 seconds
Started Feb 18 01:55:41 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 197132 kb
Host smart-ca6df616-ae99-4dd9-8eac-e952e6d13399
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854923627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.854923627
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1819793644
Short name T908
Test name
Test status
Simulation time 67747026 ps
CPU time 1.24 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 198416 kb
Host smart-b7841688-5275-4f05-954f-aeb83c52f9d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1819793644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1819793644
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1654037609
Short name T924
Test name
Test status
Simulation time 46792701 ps
CPU time 1.01 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 196724 kb
Host smart-2b824913-d97c-4500-b8c7-bcc339ca87b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654037609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1654037609
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.144078128
Short name T933
Test name
Test status
Simulation time 129992378 ps
CPU time 1.37 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 196924 kb
Host smart-b6d34ca3-116d-4e3f-bfa5-31e804517761
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=144078128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.144078128
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.77175611
Short name T882
Test name
Test status
Simulation time 46290293 ps
CPU time 1.05 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 198380 kb
Host smart-5a525c76-570b-46b7-8dff-18013e7837e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77175611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.77175611
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4194787662
Short name T874
Test name
Test status
Simulation time 126961981 ps
CPU time 1.21 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 197204 kb
Host smart-9e3ac4f7-8839-4771-89ac-7eaa8c812b33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4194787662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4194787662
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.301883991
Short name T869
Test name
Test status
Simulation time 33314585 ps
CPU time 0.97 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 196952 kb
Host smart-77139747-5df4-4317-beed-84ce3801d0e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301883991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.301883991
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2785589370
Short name T885
Test name
Test status
Simulation time 106739225 ps
CPU time 1.16 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 196908 kb
Host smart-59b80259-c398-4495-a0a6-142ecb148847
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2785589370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2785589370
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1385138093
Short name T943
Test name
Test status
Simulation time 202843234 ps
CPU time 1.12 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 197196 kb
Host smart-697f2afe-0e4d-491e-b25d-6eada4e3f84b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385138093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1385138093
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4191197528
Short name T919
Test name
Test status
Simulation time 65439834 ps
CPU time 1.36 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 197052 kb
Host smart-06bfab2f-401c-45f0-8a77-77d7957c14e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4191197528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.4191197528
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030215358
Short name T857
Test name
Test status
Simulation time 55661945 ps
CPU time 1.19 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 195904 kb
Host smart-1d3e2e98-2db0-4705-af10-1fd98cd4758c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030215358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4030215358
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1489608338
Short name T865
Test name
Test status
Simulation time 74743947 ps
CPU time 1.06 seconds
Started Feb 18 01:55:34 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 196160 kb
Host smart-0b5e63f5-4fb8-4e84-bc32-e54149b795c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1489608338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1489608338
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4234318445
Short name T941
Test name
Test status
Simulation time 325380421 ps
CPU time 1.5 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 198388 kb
Host smart-20f97425-04b0-4342-958f-1f13f5bbd43a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234318445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4234318445
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3896921181
Short name T884
Test name
Test status
Simulation time 162833476 ps
CPU time 0.75 seconds
Started Feb 18 01:55:42 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 194692 kb
Host smart-d9ec763e-b3a8-41d9-a1ec-f1fc80888029
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3896921181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3896921181
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873560472
Short name T896
Test name
Test status
Simulation time 91671245 ps
CPU time 0.94 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 196928 kb
Host smart-2f4a160f-548b-4cd9-8cb7-0ef5573f6682
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873560472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1873560472
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.817372426
Short name T898
Test name
Test status
Simulation time 77495824 ps
CPU time 0.88 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 195772 kb
Host smart-3891af5c-f344-4a2f-bacd-615bc5227e4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=817372426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.817372426
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2953902902
Short name T932
Test name
Test status
Simulation time 28566828 ps
CPU time 0.92 seconds
Started Feb 18 01:55:40 PM PST 24
Finished Feb 18 01:55:46 PM PST 24
Peak memory 196900 kb
Host smart-a04ad126-29c8-4882-a4b0-327207ff9d39
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953902902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2953902902
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.559600291
Short name T948
Test name
Test status
Simulation time 68366086 ps
CPU time 1.29 seconds
Started Feb 18 01:55:30 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 196912 kb
Host smart-1fa1cc48-c676-4cb6-8307-bd59f2876afe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=559600291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.559600291
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1505697404
Short name T868
Test name
Test status
Simulation time 666526402 ps
CPU time 1.12 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:39 PM PST 24
Peak memory 196976 kb
Host smart-8fbbd641-94f7-4d52-a391-5bbb75990693
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505697404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1505697404
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1560204872
Short name T850
Test name
Test status
Simulation time 70445719 ps
CPU time 1.23 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 198336 kb
Host smart-c1f3d420-2994-41a3-aade-fb58296d78ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1560204872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1560204872
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4102959197
Short name T883
Test name
Test status
Simulation time 71257334 ps
CPU time 1.17 seconds
Started Feb 18 01:55:41 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 196204 kb
Host smart-b29d1e8d-11d1-4b2d-b1f8-8f8b893d3fb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102959197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4102959197
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.930890442
Short name T872
Test name
Test status
Simulation time 61227402 ps
CPU time 0.94 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 196724 kb
Host smart-158f5b36-1753-4828-bce9-4ee5529ccdf0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=930890442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.930890442
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4033189410
Short name T881
Test name
Test status
Simulation time 63851068 ps
CPU time 0.88 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 196332 kb
Host smart-280cda64-3764-4bca-b1b1-61308be38911
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033189410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4033189410
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1103041687
Short name T914
Test name
Test status
Simulation time 79899359 ps
CPU time 1.3 seconds
Started Feb 18 01:55:42 PM PST 24
Finished Feb 18 01:55:48 PM PST 24
Peak memory 198360 kb
Host smart-45cb58ac-d9d7-439a-a127-60f69e90d70e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103041687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1103041687
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3346491245
Short name T859
Test name
Test status
Simulation time 88530820 ps
CPU time 1.03 seconds
Started Feb 18 01:55:42 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 198360 kb
Host smart-0247d7a8-9415-40a4-9c5a-d90bcc449298
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346491245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3346491245
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.275467253
Short name T934
Test name
Test status
Simulation time 33693439 ps
CPU time 0.93 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 195676 kb
Host smart-41152942-4398-4847-a582-d13b1104c56d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=275467253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.275467253
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.542672528
Short name T918
Test name
Test status
Simulation time 248219535 ps
CPU time 1.08 seconds
Started Feb 18 01:55:37 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 196208 kb
Host smart-81e757dc-6fb2-4aa7-83c7-e8ae4ccec236
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542672528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.542672528
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3743260733
Short name T871
Test name
Test status
Simulation time 66284610 ps
CPU time 1.2 seconds
Started Feb 18 01:55:39 PM PST 24
Finished Feb 18 01:55:45 PM PST 24
Peak memory 198404 kb
Host smart-043b5ee5-d258-4812-a481-4aa443c78ead
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3743260733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3743260733
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2506540959
Short name T942
Test name
Test status
Simulation time 42801532 ps
CPU time 0.99 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 196876 kb
Host smart-4043e805-b34a-4bfe-acc6-4cd9e6fd0a03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506540959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2506540959
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2015943579
Short name T920
Test name
Test status
Simulation time 41987880 ps
CPU time 1.38 seconds
Started Feb 18 01:55:38 PM PST 24
Finished Feb 18 01:55:44 PM PST 24
Peak memory 196824 kb
Host smart-16e448d7-21fd-46c7-86cc-fa508338d074
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2015943579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2015943579
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2104919192
Short name T870
Test name
Test status
Simulation time 78148738 ps
CPU time 1.33 seconds
Started Feb 18 01:55:41 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 197296 kb
Host smart-6c292b65-868a-4d69-adb4-e144dd6a094f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104919192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2104919192
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.343215197
Short name T899
Test name
Test status
Simulation time 133294188 ps
CPU time 1.7 seconds
Started Feb 18 01:55:47 PM PST 24
Finished Feb 18 01:55:51 PM PST 24
Peak memory 197276 kb
Host smart-b4fb27c9-d85c-4e67-a01b-e2e732662b8d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=343215197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.343215197
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2824263211
Short name T880
Test name
Test status
Simulation time 55960742 ps
CPU time 1.16 seconds
Started Feb 18 01:55:44 PM PST 24
Finished Feb 18 01:55:49 PM PST 24
Peak memory 197264 kb
Host smart-368de214-308b-464f-ad6b-0c144efcb0e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824263211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2824263211
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2840011512
Short name T858
Test name
Test status
Simulation time 64107497 ps
CPU time 1.19 seconds
Started Feb 18 01:55:46 PM PST 24
Finished Feb 18 01:55:50 PM PST 24
Peak memory 196224 kb
Host smart-10cb0d11-f2cc-47f5-89ff-b91e55f76ef7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2840011512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2840011512
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.966343820
Short name T904
Test name
Test status
Simulation time 91432896 ps
CPU time 0.88 seconds
Started Feb 18 01:55:50 PM PST 24
Finished Feb 18 01:55:53 PM PST 24
Peak memory 195676 kb
Host smart-b91ea5b0-999c-4dae-aec6-d50bb9828742
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966343820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.966343820
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3253960251
Short name T902
Test name
Test status
Simulation time 40294301 ps
CPU time 0.99 seconds
Started Feb 18 01:55:52 PM PST 24
Finished Feb 18 01:55:56 PM PST 24
Peak memory 196868 kb
Host smart-f0966ce4-995b-4d21-83e4-a60448eec2ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3253960251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3253960251
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.829326038
Short name T917
Test name
Test status
Simulation time 58375882 ps
CPU time 1.14 seconds
Started Feb 18 01:55:43 PM PST 24
Finished Feb 18 01:55:49 PM PST 24
Peak memory 196056 kb
Host smart-15b3c4b4-45e6-4e01-a116-1d325df20422
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829326038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.829326038
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3187633339
Short name T910
Test name
Test status
Simulation time 156068227 ps
CPU time 1.16 seconds
Started Feb 18 01:55:47 PM PST 24
Finished Feb 18 01:55:50 PM PST 24
Peak memory 196116 kb
Host smart-c7d70b7d-1a57-4e32-ab50-72bed9883196
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3187633339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3187633339
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2205924940
Short name T861
Test name
Test status
Simulation time 37997178 ps
CPU time 1.19 seconds
Started Feb 18 01:55:47 PM PST 24
Finished Feb 18 01:55:51 PM PST 24
Peak memory 197036 kb
Host smart-54569654-ac49-4e6a-9d15-ce09331a4a57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205924940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2205924940
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1533375593
Short name T862
Test name
Test status
Simulation time 52612345 ps
CPU time 1.45 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 197052 kb
Host smart-7ac0b493-27eb-4630-b5fb-211eb31135b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1533375593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1533375593
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3172908153
Short name T864
Test name
Test status
Simulation time 102446825 ps
CPU time 1.49 seconds
Started Feb 18 01:55:29 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 197008 kb
Host smart-c9072a32-48cf-4e3b-85c0-62f5c3ded813
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172908153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3172908153
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.31778819
Short name T863
Test name
Test status
Simulation time 142366416 ps
CPU time 0.92 seconds
Started Feb 18 01:55:30 PM PST 24
Finished Feb 18 01:55:32 PM PST 24
Peak memory 197388 kb
Host smart-282ef814-dced-4bc9-8ff5-c9eadabb144f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=31778819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.31778819
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3963497982
Short name T930
Test name
Test status
Simulation time 1155691606 ps
CPU time 1.36 seconds
Started Feb 18 01:55:31 PM PST 24
Finished Feb 18 01:55:35 PM PST 24
Peak memory 196796 kb
Host smart-4c6b4113-9361-48a8-9a61-82d042faff74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963497982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3963497982
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2878679069
Short name T877
Test name
Test status
Simulation time 248089895 ps
CPU time 1.47 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:38 PM PST 24
Peak memory 197012 kb
Host smart-e43dc4d3-306e-4511-9509-0bee7fd23a02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2878679069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2878679069
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2577265077
Short name T851
Test name
Test status
Simulation time 233049863 ps
CPU time 1.23 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:38 PM PST 24
Peak memory 196192 kb
Host smart-0f9239be-f905-4f7c-9039-7722b6cef04d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577265077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2577265077
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2131675255
Short name T856
Test name
Test status
Simulation time 289861577 ps
CPU time 1.41 seconds
Started Feb 18 01:55:41 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 198376 kb
Host smart-1eac62f8-a49b-43df-aa48-77fcdafa2ae2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2131675255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2131675255
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.831897063
Short name T860
Test name
Test status
Simulation time 32307480 ps
CPU time 1.1 seconds
Started Feb 18 01:55:35 PM PST 24
Finished Feb 18 01:55:40 PM PST 24
Peak memory 195984 kb
Host smart-56946a94-7693-4f7c-b11e-f3e7c3033150
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831897063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.831897063
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2984758584
Short name T901
Test name
Test status
Simulation time 100844614 ps
CPU time 1.16 seconds
Started Feb 18 01:55:33 PM PST 24
Finished Feb 18 01:55:37 PM PST 24
Peak memory 198296 kb
Host smart-a0bce297-ee32-44b1-b5e1-5ba35301b63d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2984758584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2984758584
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3656985306
Short name T876
Test name
Test status
Simulation time 210905976 ps
CPU time 0.92 seconds
Started Feb 18 01:55:41 PM PST 24
Finished Feb 18 01:55:47 PM PST 24
Peak memory 196588 kb
Host smart-79d4deb4-0d43-47dd-ba28-99e2bce4e168
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656985306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3656985306
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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