Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4545113	1			T20	1		T21	1		T22	1
all_pins[1]	4545113	1			T20	1		T21	1		T22	1
all_pins[2]	4545113	1			T20	1		T21	1		T22	1
all_pins[3]	4545113	1			T20	1		T21	1		T22	1
all_pins[4]	4545113	1			T20	1		T21	1		T22	1
all_pins[5]	4545113	1			T20	1		T21	1		T22	1
all_pins[6]	4545113	1			T20	1		T21	1		T22	1
all_pins[7]	4545113	1			T20	1		T21	1		T22	1
all_pins[8]	4545113	1			T20	1		T21	1		T22	1
all_pins[9]	4545113	1			T20	1		T21	1		T22	1
all_pins[10]	4545113	1			T20	1		T21	1		T22	1
all_pins[11]	4545113	1			T20	1		T21	1		T22	1
all_pins[12]	4545113	1			T20	1		T21	1		T22	1
all_pins[13]	4545113	1			T20	1		T21	1		T22	1
all_pins[14]	4545113	1			T20	1		T21	1		T22	1
all_pins[15]	4545113	1			T20	1		T21	1		T22	1
all_pins[16]	4545113	1			T20	1		T21	1		T22	1
all_pins[17]	4545113	1			T20	1		T21	1		T22	1
all_pins[18]	4545113	1			T20	1		T21	1		T22	1
all_pins[19]	4545113	1			T20	1		T21	1		T22	1
all_pins[20]	4545113	1			T20	1		T21	1		T22	1
all_pins[21]	4545113	1			T20	1		T21	1		T22	1
all_pins[22]	4545113	1			T20	1		T21	1		T22	1
all_pins[23]	4545113	1			T20	1		T21	1		T22	1
all_pins[24]	4545113	1			T20	1		T21	1		T22	1
all_pins[25]	4545113	1			T20	1		T21	1		T22	1
all_pins[26]	4545113	1			T20	1		T21	1		T22	1
all_pins[27]	4545113	1			T20	1		T21	1		T22	1
all_pins[28]	4545113	1			T20	1		T21	1		T22	1
all_pins[29]	4545113	1			T20	1		T21	1		T22	1
all_pins[30]	4545113	1			T20	1		T21	1		T22	1
all_pins[31]	4545113	1			T20	1		T21	1		T22	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	90305064	1			T20	32		T21	32		T22	32
values[0x1]	55138552	1			T23	17217		T24	709		T26	1261
transitions[0x0=>0x1]	33028276	1			T23	10228		T24	363		T26	633
transitions[0x1=>0x0]	33028133	1			T23	10227		T24	362		T26	632

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2816463	1			T20	1		T21	1		T22	1
all_pins[0]	values[0x1]	1728650	1			T23	541		T24	21		T26	47
all_pins[0]	transitions[0x0=>0x1]	1073876	1			T23	320		T24	13		T26	22
all_pins[0]	transitions[0x1=>0x0]	1066215	1			T23	363		T24	9		T26	17
all_pins[1]	values[0x0]	2819304	1			T20	1		T21	1		T22	1
all_pins[1]	values[0x1]	1725809	1			T23	499		T24	24		T26	39
all_pins[1]	transitions[0x0=>0x1]	1028199	1			T23	284		T24	14		T26	16
all_pins[1]	transitions[0x1=>0x0]	1031040	1			T23	326		T24	11		T26	24
all_pins[2]	values[0x0]	2820884	1			T20	1		T21	1		T22	1
all_pins[2]	values[0x1]	1724229	1			T23	428		T24	27		T26	40
all_pins[2]	transitions[0x0=>0x1]	1030654	1			T23	251		T24	16		T26	23
all_pins[2]	transitions[0x1=>0x0]	1032234	1			T23	322		T24	13		T26	22
all_pins[3]	values[0x0]	2830826	1			T20	1		T21	1		T22	1
all_pins[3]	values[0x1]	1714287	1			T23	557		T24	18		T26	39
all_pins[3]	transitions[0x0=>0x1]	1025605	1			T23	355		T24	8		T26	20
all_pins[3]	transitions[0x1=>0x0]	1035547	1			T23	226		T24	17		T26	21
all_pins[4]	values[0x0]	2822351	1			T20	1		T21	1		T22	1
all_pins[4]	values[0x1]	1722762	1			T23	594		T24	24		T26	38
all_pins[4]	transitions[0x0=>0x1]	1034404	1			T23	368		T24	14		T26	19
all_pins[4]	transitions[0x1=>0x0]	1025929	1			T23	331		T24	8		T26	20
all_pins[5]	values[0x0]	2822439	1			T20	1		T21	1		T22	1
all_pins[5]	values[0x1]	1722674	1			T23	610		T24	24		T26	38
all_pins[5]	transitions[0x0=>0x1]	1029773	1			T23	292		T24	13		T26	19
all_pins[5]	transitions[0x1=>0x0]	1029861	1			T23	276		T24	13		T26	19
all_pins[6]	values[0x0]	2819958	1			T20	1		T21	1		T22	1
all_pins[6]	values[0x1]	1725155	1			T23	489		T24	27		T26	43
all_pins[6]	transitions[0x0=>0x1]	1032869	1			T23	242		T24	13		T26	17
all_pins[6]	transitions[0x1=>0x0]	1030388	1			T23	363		T24	10		T26	12
all_pins[7]	values[0x0]	2823521	1			T20	1		T21	1		T22	1
all_pins[7]	values[0x1]	1721592	1			T23	544		T24	23		T26	37
all_pins[7]	transitions[0x0=>0x1]	1027977	1			T23	352		T24	11		T26	16
all_pins[7]	transitions[0x1=>0x0]	1031540	1			T23	297		T24	15		T26	22
all_pins[8]	values[0x0]	2821728	1			T20	1		T21	1		T22	1
all_pins[8]	values[0x1]	1723385	1			T23	617		T24	26		T26	45
all_pins[8]	transitions[0x0=>0x1]	1031969	1			T23	364		T24	12		T26	24
all_pins[8]	transitions[0x1=>0x0]	1030176	1			T23	291		T24	9		T26	16
all_pins[9]	values[0x0]	2825451	1			T20	1		T21	1		T22	1
all_pins[9]	values[0x1]	1719662	1			T23	505		T24	25		T26	39
all_pins[9]	transitions[0x0=>0x1]	1028348	1			T23	292		T24	9		T26	15
all_pins[9]	transitions[0x1=>0x0]	1032071	1			T23	404		T24	10		T26	21
all_pins[10]	values[0x0]	2825924	1			T20	1		T21	1		T22	1
all_pins[10]	values[0x1]	1719189	1			T23	586		T24	17		T26	39
all_pins[10]	transitions[0x0=>0x1]	1030988	1			T23	342		T24	6		T26	23
all_pins[10]	transitions[0x1=>0x0]	1031461	1			T23	261		T24	14		T26	23
all_pins[11]	values[0x0]	2820063	1			T20	1		T21	1		T22	1
all_pins[11]	values[0x1]	1725050	1			T23	542		T24	19		T26	43
all_pins[11]	transitions[0x0=>0x1]	1031777	1			T23	285		T24	10		T26	21
all_pins[11]	transitions[0x1=>0x0]	1025916	1			T23	329		T24	8		T26	17
all_pins[12]	values[0x0]	2821848	1			T20	1		T21	1		T22	1
all_pins[12]	values[0x1]	1723265	1			T23	497		T24	18		T26	35
all_pins[12]	transitions[0x0=>0x1]	1029060	1			T23	287		T24	13		T26	10
all_pins[12]	transitions[0x1=>0x0]	1030845	1			T23	332		T24	14		T26	18
all_pins[13]	values[0x0]	2824652	1			T20	1		T21	1		T22	1
all_pins[13]	values[0x1]	1720461	1			T23	591		T24	23		T26	40
all_pins[13]	transitions[0x0=>0x1]	1027109	1			T23	354		T24	14		T26	25
all_pins[13]	transitions[0x1=>0x0]	1029913	1			T23	260		T24	9		T26	20
all_pins[14]	values[0x0]	2824504	1			T20	1		T21	1		T22	1
all_pins[14]	values[0x1]	1720609	1			T23	497		T24	23		T26	41
all_pins[14]	transitions[0x0=>0x1]	1029957	1			T23	270		T24	10		T26	22
all_pins[14]	transitions[0x1=>0x0]	1029809	1			T23	364		T24	10		T26	21
all_pins[15]	values[0x0]	2824351	1			T20	1		T21	1		T22	1
all_pins[15]	values[0x1]	1720762	1			T23	646		T24	26		T26	44
all_pins[15]	transitions[0x0=>0x1]	1032185	1			T23	416		T24	14		T26	18
all_pins[15]	transitions[0x1=>0x0]	1032032	1			T23	267		T24	11		T26	15
all_pins[16]	values[0x0]	2821031	1			T20	1		T21	1		T22	1
all_pins[16]	values[0x1]	1724082	1			T23	440		T24	26		T26	40
all_pins[16]	transitions[0x0=>0x1]	1033365	1			T23	307		T24	10		T26	19
all_pins[16]	transitions[0x1=>0x0]	1030045	1			T23	513		T24	10		T26	23
all_pins[17]	values[0x0]	2823925	1			T20	1		T21	1		T22	1
all_pins[17]	values[0x1]	1721188	1			T23	571		T24	26		T26	38
all_pins[17]	transitions[0x0=>0x1]	1027910	1			T23	335		T24	13		T26	19
all_pins[17]	transitions[0x1=>0x0]	1030804	1			T23	204		T24	13		T26	21
all_pins[18]	values[0x0]	2820266	1			T20	1		T21	1		T22	1
all_pins[18]	values[0x1]	1724847	1			T23	600		T24	19		T26	38
all_pins[18]	transitions[0x0=>0x1]	1034855	1			T23	360		T24	8		T26	19
all_pins[18]	transitions[0x1=>0x0]	1031196	1			T23	331		T24	15		T26	19
all_pins[19]	values[0x0]	2817614	1			T20	1		T21	1		T22	1
all_pins[19]	values[0x1]	1727499	1			T23	470		T24	26		T26	39
all_pins[19]	transitions[0x0=>0x1]	1034546	1			T23	265		T24	15		T26	20
all_pins[19]	transitions[0x1=>0x0]	1031894	1			T23	395		T24	8		T26	19
all_pins[20]	values[0x0]	2825417	1			T20	1		T21	1		T22	1
all_pins[20]	values[0x1]	1719696	1			T23	734		T24	24		T26	39
all_pins[20]	transitions[0x0=>0x1]	1028006	1			T23	490		T24	9		T26	19
all_pins[20]	transitions[0x1=>0x0]	1035809	1			T23	226		T24	11		T26	19
all_pins[21]	values[0x0]	2823287	1			T20	1		T21	1		T22	1
all_pins[21]	values[0x1]	1721826	1			T23	549		T24	24		T26	42
all_pins[21]	transitions[0x0=>0x1]	1030365	1			T23	248		T24	11		T26	20
all_pins[21]	transitions[0x1=>0x0]	1028235	1			T23	433		T24	11		T26	17
all_pins[22]	values[0x0]	2818718	1			T20	1		T21	1		T22	1
all_pins[22]	values[0x1]	1726395	1			T23	584		T24	19		T26	29
all_pins[22]	transitions[0x0=>0x1]	1035243	1			T23	333		T24	8		T26	10
all_pins[22]	transitions[0x1=>0x0]	1030674	1			T23	298		T24	13		T26	23
all_pins[23]	values[0x0]	2819242	1			T20	1		T21	1		T22	1
all_pins[23]	values[0x1]	1725871	1			T23	507		T24	24		T26	31
all_pins[23]	transitions[0x0=>0x1]	1032864	1			T23	279		T24	17		T26	25
all_pins[23]	transitions[0x1=>0x0]	1033388	1			T23	356		T24	12		T26	23
all_pins[24]	values[0x0]	2823931	1			T20	1		T21	1		T22	1
all_pins[24]	values[0x1]	1721182	1			T23	531		T24	25		T26	37
all_pins[24]	transitions[0x0=>0x1]	1029418	1			T23	322		T24	12		T26	26
all_pins[24]	transitions[0x1=>0x0]	1034107	1			T23	298		T24	11		T26	20
all_pins[25]	values[0x0]	2824876	1			T20	1		T21	1		T22	1
all_pins[25]	values[0x1]	1720237	1			T23	556		T24	20		T26	42
all_pins[25]	transitions[0x0=>0x1]	1029570	1			T23	308		T24	6		T26	23
all_pins[25]	transitions[0x1=>0x0]	1030515	1			T23	283		T24	11		T26	18
all_pins[26]	values[0x0]	2818675	1			T20	1		T21	1		T22	1
all_pins[26]	values[0x1]	1726438	1			T23	549		T24	26		T26	38
all_pins[26]	transitions[0x0=>0x1]	1034861	1			T23	284		T24	13		T26	20
all_pins[26]	transitions[0x1=>0x0]	1028660	1			T23	291		T24	7		T26	24
all_pins[27]	values[0x0]	2816827	1			T20	1		T21	1		T22	1
all_pins[27]	values[0x1]	1728286	1			T23	424		T24	17		T26	45
all_pins[27]	transitions[0x0=>0x1]	1032825	1			T23	313		T24	8		T26	21
all_pins[27]	transitions[0x1=>0x0]	1030977	1			T23	438		T24	17		T26	14
all_pins[28]	values[0x0]	2824832	1			T20	1		T21	1		T22	1
all_pins[28]	values[0x1]	1720281	1			T23	387		T24	18		T26	38
all_pins[28]	transitions[0x0=>0x1]	1027888	1			T23	205		T24	10		T26	13
all_pins[28]	transitions[0x1=>0x0]	1035893	1			T23	242		T24	9		T26	20
all_pins[29]	values[0x0]	2817340	1			T20	1		T21	1		T22	1
all_pins[29]	values[0x1]	1727773	1			T23	384		T24	16		T26	38
all_pins[29]	transitions[0x0=>0x1]	1032696	1			T23	272		T24	9		T26	19
all_pins[29]	transitions[0x1=>0x0]	1025204	1			T23	275		T24	11		T26	19
all_pins[30]	values[0x0]	2820835	1			T20	1		T21	1		T22	1
all_pins[30]	values[0x1]	1724278	1			T23	603		T24	16		T26	37
all_pins[30]	transitions[0x0=>0x1]	1028515	1			T23	510		T24	10		T26	23
all_pins[30]	transitions[0x1=>0x0]	1032010	1			T23	291		T24	10		T26	24
all_pins[31]	values[0x0]	2823981	1			T20	1		T21	1		T22	1
all_pins[31]	values[0x1]	1721132	1			T23	585		T24	18		T26	43
all_pins[31]	transitions[0x0=>0x1]	1030599	1			T23	323		T24	14		T26	27
all_pins[31]	transitions[0x1=>0x0]	1033745	1			T23	341		T24	12		T26	21